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Xilinx-HLS

Vivado High-Level Synthesis (HLS) is a design framework that enables C/C++ based IP design with integrated RTL co-simulation and AXI interface synthesis. It provides optimized libraries to accelerate design processes and was first utilized in Xilinx Video IPs starting from version 2015.3, including a Video Subsystem and Test Pattern Generator. The framework emphasizes design flexibility, performance optimization, and efficient resource utilization in algorithmic designs.

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yehia.mahmoud02
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7 views

Xilinx-HLS

Vivado High-Level Synthesis (HLS) is a design framework that enables C/C++ based IP design with integrated RTL co-simulation and AXI interface synthesis. It provides optimized libraries to accelerate design processes and was first utilized in Xilinx Video IPs starting from version 2015.3, including a Video Subsystem and Test Pattern Generator. The framework emphasizes design flexibility, performance optimization, and efficient resource utilization in algorithmic designs.

Uploaded by

yehia.mahmoud02
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
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Vivado High-Level Synthesis

Duncan Mackay, Xilinx


Vivado HLS
Framework for C-based IP Design

© Copyright 2015 Xilinx


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Agenda

• Overview of Vivado HLS

• Xilinx Video IP with HLS

• Summary / Q&A

© Copyright 2015 Xilinx


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Vivado HLS

 C based code brings design flexibility


– HLS puts few restrictions in C semantics
– Optimized design likely to involve paying attention to coding style

 Common Tips and Tricks


– Follow good methodology principles (see UltraFast methodology)
– Refine code to meet design goals
– Use pre-optimized libraries

© Copyright 2015 Xilinx


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Vivado HLS: Framework for C based IP Design

Vivado 2015.3: 1st Xilinx HLS IPs


– Video Subsystem and pattern generator
C/C++ to optimized RTL IP

C to hand-coded quality RTL


– In weeks not months…
Accelerated verification
– Over 100X over RTL
Ideal for algorithmic designs
– Excels at math (floating / fixed point)
– Video, DSP…

© Copyright 2015 Xilinx


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Vivado HLS: System IP Integration Flow
C-based IP Creation System Integration

C, C++, SystemC

Libraries Vivado IP Integrator


Arbitrary Precision
Video
Math
Linear algebra
IP Catalog
LogiCore IP Vivado RTL
FFT, FIR
DSP

VHDL or Verilog

System Generator for DSP

Vivado HLS Integrates into System Flows

© Copyright 2015 Xilinx


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Design Decisions

Decisions made by designer Decisions made by the tool


 Functionality  State Machine
– As implicit state machine – Structure, encoding
 Performance  Pipelining
– Latency, throughput – Pipeline, registers allocation
 Interfaces  Scheduling
 Storage architecture – Memory I/O
– Interface I/O
– Memories, registers banks etc…
 Partitioning into modules
 Design Exploration

© Copyright 2015 Xilinx


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Differences with RTL

 Code is untimed (C/C++)

 Loops are folded by default

 Pragmas play a crucial role in HLS for throughput

 Design control is added by HLS as a state machine

 RAMs are auto-generated based on arrays

 Simulation is tightly integrated

 Extensive architecture exploration

 Support for floating point

© Copyright 2015 Xilinx


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The 5 UltraFast Steps

Simulate Design • Validate

Synthesize Design • Baseline

• Define interfaces (and data packing)


1: Add Initial Directives
• Define loop trip counts

2: Pipeline • Pipeline and Dataflow

• Partition memories and ports


3: Improve Pipelining
• Remove false dependencies

4: Improve Area • Optionally recover resources through sharing

5: Reduce Latency • Tweak operator sharing and constraints

5 Steps to UltraFast Design Methodology

© Copyright 2015 Xilinx


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Agenda

• Overview of Vivado HLS

• Xilinx Video IP with HLS

• Summary / Q&A

© Copyright 2015 Xilinx


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Xilinx Video IP – Reference Design

• Design Features • Video processing features


– 4K UHD 60fps on input and o/p – Motion adaptive de-interlacer
– Dynamic configuration thru SW driver – Color space converter and Chroma resampler
– HDMI 2.0 TX and RX – 6-tap polyphase scaler up 4K
– Runs on KC705 and TB-FMCH-HDMI4k – Zoom of user defined window
– 4-pixel/clock processing – Frame rate conversion

MIG + External Memory MicroBlaze

AXI-MM AXI-Lite

AXI Interconnect AXI Interconnect


AXI-MM AXI-MM AXI-Lite

VDMA Deinterlacer V-Scaler H-Scaler CSC 422-444 420-422 Letterboxing

AXI-S AXI-S AXI-S AXI-S AXI-S AXI-S AXI-S AXI-S


AXI-S AXI-S
HDMI RX AXI-S Router HDMI TX

Video Processing SubSystem – Full System

© Copyright 2015 Xilinx


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Xilinx Video IP – Leverages IP Integrator

• Hierarchical IP
– Processing blocks designed in C
– Connectivity based on AXI4
– AXI4 IPs

HLS Blocks

Video Processing Subsystem – Scaler

© Copyright 2015 Xilinx


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Xilinx Video IP – Flow and Methodology

 Algorithm development
– Can start in Matlab 5% 5%
C simulation
 Write algorithm in C++ C/RTL co-simulation
90% HW validation
– Float to fixed point conversions
C simulation
 Run initial evaluations…
 Port to Vivado HLS Verification tests (as a percentage)
– Leverage hls_video.h library
– Add line buffers, pixel kernels, etc…
– Evaluate resources and performance
 Optimize to architecture
– Tune precisions to optimal number of DSP blocks

© Copyright 2015 Xilinx


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Full Design – Results
LUTs FFs
Function Block
(in 1000s) (in 1000s)
HDMI Rx 6.5 9
HDMI Tx 6 9
HDMI GT 1 2
Memory Interface 18 16 Video processing using ASSPs
MicroBlaze 3 3
Patter Generator (optional) 2.5 2.5
Video Subsystem 27 33.5
Total ( 1-ch 4K video 61 73
system)*
Resources available in 101 202
Kintex 160T
*Resource estimates Video processing using FPGAs

 Cost effective implementation


– Low cost per channel
– Reduced BOM by integrating interface and video functions
 Multiple ASSP to one FPGA with on-chip HDMI decoding

© Copyright 2015 Xilinx


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Agenda

• Overview of Vivado HLS

• Xilinx Video IP with HLS

• Summary / Q&A

© Copyright 2015 Xilinx


.
Summary

 Vivado HLS is a complete design framework


– C/C++ with integrated RTL co-simulation
– AXI interface synthesis
 Libraries help speedup design
– Optimized data structures

 Xilinx IP Video IPs use HLS starting in 2015.3


– Video Subsystem (IP catalog, also available as a reference design)
– Video Test Pattern Generator (IP catalog)
 New HDMI IP in 2015.3

© Copyright 2015 Xilinx


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