COURSE OUTLINE

DIGITAL LOGIC AND DESIGN

Department of Computer Science

Code: CS 121
Credit Hours: 3+1
Category: Major
Course: Digital Logic Design Spring 2023
Code: CS 121
Credit Hours: 3+1
Pre-Requisite: None
Instructor: Arfa Dilawari
Lab Instructor: Attiya Khan

Course Outline

Course Description
Digital Logic is the basis of electronic systems, such as computers and cell phones. Digital Logic
is rooted in binary code, a series of zeroes and ones each having an opposite value. It facilitates
the design of electronic circuits that convey information, including logic gates. Digital Logic
Design is used to develop hardware, such as circuit boards and microchip processors. This
hardware processes input, system protocol and other data in computers, navigational systems, cell
phones or other high-tech systems.

Digital Logic Design is the fundamental course in Computer Science. This course will provide the
essential background needed to understand how digital systems work. It focuses on the principles
and practices of digital circuit design. The objective of the course is to explain how digital circuit
of large complexity can be built in a methodological way, starting from Boolean logic and applying
a set of rigorous techniques.

This course introduces students to the basic concepts of digital systems, including analysis and
design. Both combinational and sequential logic will be covered. Students will gain experience
with several levels of digital systems, from simple logic circuits to programmable logic devices
and hardware description language. This course will stress on fundamentals of digital circuit
designing. We will pay particular attention to design principles and techniques, timing analysis,
and finite state machines. The concepts covering in this class are needed in other courses in
Computer Science. It is imperative that these concepts are well understood.

Numerous examples and case studies will be used to illustrate the concepts presented in the
lectures. The students will apply their knowledge in the labs by building increasingly more
complex digital logic circuits.
Course Objectives
1. Acquire knowledge related to the concepts, tools and techniques for the design of digital
electronic circuits.
2. Demonstrate the skills to design and analyze both combinational and sequential circuits
using a variety of techniques.
3. Apply the acquired knowledge to simulate and implement small-scale digital circuits
4. Understand the relationship between abstract logic characterizations and practical
electrical implementations.

Course Learning Outcomes

By the end of this course the students will be able to:
1. Apply knowledge of mathematics, science, and engineering
2. Design and conduct experiments, as well as to analyze and interpret data
3. Design a system, component, or process to meet desired needs within realistic constraints
4. Realize complex logic functions utilizing programmable logic.
5. Identify, formulate, and solve engineering problems.
6. Use the techniques, skills, and modern engineering tools necessary for engineering
practice

Recommended Book
1. Digital Design 5th Edition, by Morris Mano and Michael D. Ciletti
https://www.portcity.edu.bd/files/636444791235373856_Digitallogicdesign.pdf

2. Digital Fundamentals, 11th Ed., by T. Floyd, Prentice Hall

https://bpcbirgunj.edu.np/wp-content/uploads/2019/10/DIGITAL_ELECTRONICS-by-
Flyod.pdf

Reference Book
1. Digital Logic Design by Mansaf Alam and Bashir Alam
Published in October 2015
https://www.researchgate.net/publication/282979377_Digital_Logic_Design

Lecture Schedule and Duration

Lectures will be held as per the College time table for Spring 2023.

Teaching Methodology
1. Delivering lectures with the help of lecture slides and explaining each slide
2. Using white board in lectures to explain diagrams and solving problems
3. Sharing online resources and videos for better understanding.
4. Quizzes: Quizzes will be conducted to access the learning of students during the live
session.
5. Presentations/Project: Each group will be assigned topics related to the course for
presentations/project
Class Policies
1. Attendance & Absences: Students are expected to attend and sit through the entire class
meetings. A student shall be marked absent if she leaves the class during the lecture. If a
student is absent for more than six lecture-hours she will be withdrawn from the course.
2. Assessment Completion & Late Work: Late Assessment submission is not allowed,
unless permission is granted by the instructor prior to the deadline. All Course elements
including assignments, tests, examinations and presentations must be fulfilled to pass the
course.
3. Conduct Code: Cheating and plagiarism will not be tolerated. They will result in no credit
for the assignment or examination and may lead to disciplinary actions.

Tests/Quiz schedule
Short tests which would emphasize application as well as knowledge, will be administered at
regular intervals. MCQs and problems will be included in these tests. They will be taken according
to the following schedule to check concepts and problem-solving abilities of students.

Tentative Tests Schedule:

 Pre Mid Test 1: Feb 6 - Feb 24, 2023
 Pre Mid Test 2: Mar 06 - Mar 17, 2023
 Post Mid Test 1: May 1 - May 19, 2023

Rubrics for Quiz

● Correct logic: 50% marks
● Correct circuit diagram: 25% marks
● Correct equations and truth table: 25% marks

Assignments
Two assignments will be given to reflect on the information covered and show the understanding
of the students.

Submission Dates for Assignments

● Assignment 1(Pre-Mid): Feb 6 - Mar 10, 2023

● Assignment 2(Pre-Mid): Feb 27 - Mar 03, 2023
● Assignment 1(Post-Mid): May 8 - May 12, 2023

Rubric for Assignment

● Correct logic: 50% marks

● Correct circuit diagram: 25% marks
● Correct equations: 25% marks
Assessment Instruments with Weights

Student’s performance will be evaluated through the following criteria:

Assignments 15%
Quizzes 15%
Lab 5%
Midterm 25%
Presentations/Projects 10%
Final 30%
Course Content and Weekly Schedule (Theory)
Pre-Mid Weekly Schedule

Week 1 January 23 – 27, 2023 Introduction to digital and computer systems and
Chapter 1,Moris Mano information representation.
Number Systems, their conversion and Arithmetic

Week 2 January 30 – 03, 2023 Standard Codes (BCD, Excess-3, 8421,2421,24-2-1,

Chapter 1,Moris Mano Gray, ASCII)
Error detecting codes
Complements (r’s and (r-1)’s)
Subtraction using Complements
Representing of Signed Numbers

Week 3 February 6 – 10, 2023 Logic Gates and Truth Tables

Chapter 2, Morris Mano Boolean Algebra
Chapter 3, Floyd

Week 4 February 13 – 17, 2023 Minterms and Maxterms

Chapter 4, Floyd Representation of Boolean function in Canonical
Form(Sum of Minterms and Product of Maxterms)
Standard Form(SOP’s and POS’s)

Week 5 February 20 – 24, 2023 Karnaugh Map Logic Simplification tool

Chapter 4, Floyd Problem Solving session
Pre Mid Test 1

Week 6 February 27 – March 3, 2023 NAND & NOR as Universal Gates

Chapter 4, Morris Mano
Combinational circuits analysis and design
Half Adders and Full Adders

Week 7 March 06 – 10, 2023 Binary Adders

Half Subtractor, Full-Subtractor
Adder Subtractor Circuit
Pre Mid Test 2

Week 8 Mar 13 - Mar 17, 2023 Revision

Week 9 and 10
Exam Week Mar 20 - Mar 31, 2023 Midterm Exams
 Post Midterm Weekly Schedule

Week 1 April 11 – 14, 2023 Decoders and Encoders in detail

Chapter 4, Morris Mano Binary Multiplier
Decimal Adder

Week 2* April 17 – 21, 2023 MUX

Comparators

Week 3* April 24 – 28, 2023 ROM

Chapter 5, Morris Mano Synchronous Sequential Logic
NAND Latch & D Flip Flop ,JK and T Flip flops
Analysis of Flip flops

Week 4* May 2 – 5, 2023 Analysis of Flip flops

Practice Questions

Week 5: May 8 – 12, 2023 Up/Down Counter

Chapter 6, Morris Mano Ripple Counter

Week 6: May 15 – 19, 2023 Registers

Types of Registers
Post Mid Test 1

Week 7: May 22 – May 26, 2023 Presentations/Projects

Week 8: May 22 – May 26, 2023 Revision

Week 9: May 29 – June 7, 2023 FINALS

Lab Component
Hardware Labs have been designed to familiarize students with the Combinational Digital Logic
Design. Since hardware is required to carry out experiments and lab access is not possible in the
prevailing situation, so the post-midterm lab sessions shall be utilized to give additional in-class
challenges.

Course Content and Weekly Schedule (Lab)

Week 1 + 2 Introduction
Explaining Lab rules
Implementation of Digital Logic Gates using ICs
 Week 3 +4 Implementation of simple circuits

Week 5 Implementation of Half Adders

Week 6 Implementation of Full Adder

Week 7 Lab Test

Week 8 Implementation of Half Subtractor and Full

Subtractor
Week 9 + 10 Implementation of 2x4 and 3 x 8 decoders

Week 11 Building 3 x 8 decoder using two 2 x 4 decoders

Week 12 Lab Test

Week 13 +14 Implementation of Encoder and MUX

Week 15 + 16 Revision

Rubric for Project Presentation

Criteria Excellent Acceptable Less than Acceptable

Content Student effective use of Minimum level of Less than minimum level of
Knowledge understanding and knowledge effective use of effective use of understanding
of information understanding and and knowledge of information
knowledge of
information 1
3
2
Slides As per given format Minimum level Less than minimum level
Formation 2 1 0.5
Clarity Effective coherence Satisfactory Less than satisfactory
2 1 0.5
Presentation Effective use of presentation Minimum level Less than minimum level
Skills skills
3 1 0.5
Group Well-coordinated Minimum level of No coordination at all
Coordination presentation coordination
2 1 0
Handling Q/A All questions are correctly 50% of the questions are Less than 50% of the questions
session answered correctly answered correctly answered
1.5 0.5
3