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MS_Second_Exam_logic_Design_2018_1

The document outlines the marking scheme for the Logic Circuits exam (630211) at Philadelphia University, detailing the structure of the exam and the distribution of marks across four compulsory questions. It includes multiple-choice questions related to Boolean functions, encoders, and circuit analysis. The exam is coordinated by Dr. Qadri Hamarsheh and is weighted at 20% of the module total.

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11 views

MS_Second_Exam_logic_Design_2018_1

The document outlines the marking scheme for the Logic Circuits exam (630211) at Philadelphia University, detailing the structure of the exam and the distribution of marks across four compulsory questions. It includes multiple-choice questions related to Boolean functions, encoders, and circuit analysis. The exam is coordinated by Dr. Qadri Hamarsheh and is weighted at 20% of the module total.

Uploaded by

fakhar_fast
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Philadelphia University

Faculty of Engineering

Marking Scheme

Exam Paper
BSc CE

Logic Circuits (630211)

Second Exam First semester Date 23/12/2018


Section 1
Weighting 20% of the module total

Lecturer: Dr. Qadri Hamarsheh


Coordinator: Dr. Qadri Hamarsheh
Internal Examiner: Eng. Anis Nazer
Marking Scheme
Logic Circuits (630211)
The presented exam questions are organized to overcome course material through 4 questions.
The all questions are compulsory requested to be answered.
Marking Assignments
Question 1 Multiple Choice (6 marks)
1) The Boolean function F with don't-care conditions are represented in the K-map for four-variables as
shown below, the simplification of the function F in sum-of-products form is:
CD
AB 00 01 11 10

a) ̅𝑫 + 𝑨
𝑨 ̅𝑩 + 𝑩𝑫 + 𝑪̅𝑫 00 0 1 1 0

b) ̅ ̅ ̅
𝑨𝑫 + 𝑨𝑩 + 𝑪𝑫 + 𝑨𝑩 ̅𝑫
̅𝑪 01 X 1 1 X
c) ̅𝑫 + 𝑩𝑫 + 𝑪
𝑨 ̅𝑫
11
d) ̅𝑩
𝑨 ̅𝑫 + 𝑨
̅𝑩 + 𝑩𝑫 + 𝑨𝑩 ̅𝑫
̅𝑪 X X 1 0

10 0 1 0 0

2) The simplified expression of half adder carry is


a) 𝐜 = 𝐱𝐲 + 𝐱 b) 𝐜 = 𝐱𝐲
c) 𝐜 = 𝐱𝐲 + 𝐲 d) 𝐜=𝐲+𝐱
3) How many select lines will a 16 to 1 multiplexer will have:
a) 4 b) 3
c) 5 d) 6
4) Decoder with enable input can be used as:
a) Encoder b) Multiplexer
c) XOR d) Demultiplexer
5) The following circuit is a _________.

a) 2-4 decoder with active low enable and active low outputs
b) 2-4 decoder with active low enable and active high outputs
c) 2-4 decoder with active high enable and active low outputs
d) 2-4 decoder with active high enable and active high outputs
6) The logic realized by the circuit shown in figure is

a) 𝐅 = 𝐁 ⊕ 𝐂 b) 𝐅 = ̅̅̅̅̅̅̅̅̅̅
𝐁 ⊕ 𝐂
c) 𝐅 = 𝐀 ⊕ 𝐂 d) 𝐅 = ̅̅̅̅̅̅̅̅̅̅
𝐀 ⊕ 𝐂
Question 2: (5 marks)
a) (2.5 marks)
Solution

b) (2.5 marks)
Solution
An encoder is a digital circuit that performs the inverse operation of a decoder. An
encoder has 𝟐𝒏 (or fewer) input lines and 𝒏 output lines.

Inputs Outputs

𝑫𝟎 𝑫𝟏 𝑫𝟐 𝑫𝟑 𝑫𝟒 𝑫𝟓 𝑫𝟔 𝑫𝟕 𝑿 𝒀 𝒁

1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 0 0 1 0 0 0 0 0 1 1

0 0 0 0 1 0 0 0 1 0 0

0 0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 0 1 1 1 1

𝑿 = 𝑫𝟒 + 𝑫𝟓 + 𝑫𝟔 + 𝑫𝟕
𝒀 = 𝑫𝟐 + 𝑫𝟑 + 𝑫𝟔 + 𝑫𝟕
𝒁 = 𝑫𝟏 + 𝑫𝟑 + 𝑫𝟓 + 𝑫𝟕
D0 D1 D2 D3 D4 D5 D6 D7

X
Question 3: (6 marks)
a) (3 marks)
Solution
𝐅𝟏 = 𝐱’𝐲’𝐳’ + 𝐱𝐳(𝐲 + 𝐲’) = 𝐱’𝐲’𝐳’ + 𝐱𝐲𝐳 + 𝐱𝐲’𝐳 = 𝚺𝐦(𝟎, 𝟓, 𝟕)
𝐅𝟐 = 𝚺𝐦(𝟐, 𝟑, 𝟒)
𝐅𝟑 = 𝚺𝐦(𝟏, 𝟔, 𝟕)

b) (3 marks)
Solution
Question 4: (3 marks)
Solution

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