Dhirubhai Ambani Institute of Information

and Communication Technology Introduction

Hardware Modeling Devices/Platform
EL203: Embedded Hardware Design Bread board

Printed Circuit Board

Field Programmable Gate Array (FPGA) Microprocessor and Microcontrollers (8051, ATMega

Development Boards -- Arduino, Rapberry Pi, etc.

Programmable Devices (PROM, PAL, PLA, CPLD, FPGA)

Dr. Yash Agrawal
Associate Professor, Application Specific Integrated Circuit
DA-IICT, Gandhinagar

Dr. Yash Agrawal @ DA-IICT Gandhinagar 2

Technology Advancement and Need of advanced

Embedded SSI, MSI, Embedded VLSI, Embedded

Systems

Connecting
LSI, VLSI Systems ULSI
Again Integrating
Systems
Why FPGA...?
discrete active Integrated Embedding and discrete Further
and passive Circuit (IC) Connecting Components of Embedding of
Components, Several ICS, Embedded Systems can be
Integrating Systems to develop
transistor on Components, made to get
millions of Sensors and entire System or advanced
PCB, Bread
board Transistors Actuators Network on a
Applications
Chip

Printed Circuit Board (PCB), Integrated Internet of Things (IOT) System-on-Chip (SoC)
Bread board Circuit (IC) Cyber Physical Systems Network-on-Chip (NoC)

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Field Programmable Gate Array (FPGA) Package Marking

A field-programmable gate array (FPGA) is a logic device that

contains a two-dimensional array of generic logic cells and
programmable switches.

Fig: Spartan-3E QFP Package Marking Example.

Fig: Conceptual structure of an FPGA device. Fig: Spartan-3E BGA Package Marking Example.

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Ordering Information Spartan 3E Architecture Overview

Spartan-3E family architecture consists of five fundamental

programmable functional elements:

Configurable Logic Blocks (CLBs)

Input/Output Blocks (IOBs)

Block RAM

Multiple Blocks
Digital Clock Manager (DCM) Blocks

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Spartan 3E Architecture Overview IOBs Organized into Banks

Fig: Spartan-3E Family Architecture. Fig: Spartan-3E I/O Banks (top view).

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Configurable Logic Block (CLB) and Slice Resources Summary of Spartan-3E FPGA Attributes

Table: Spartan-3E FPGA Attributes

Fig: CLB Locations.

Table: Spartan-3E CLB Resources

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Slice Overview Digital Clock Managers (DCMs)

Fig: Arrangement of Slices within the CLB.

Fig: DCM Functional Blocks and Associated Signals.

Fig: Resources in Slice.

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Clocking Infrastructure Clocking Infrastructure

Each Spartan-3E FPGA has:

16 Global Clock inputs (GCLK0 through GCLK15) located

along the top and bottom edges of the FPGA.

8 Right-Half Clock inputs (RHCLK0 through RHCLK7) located

along the right edge.

8 Left-Half Clock inputs (LHCLK0 through LHCLK7) located

along the left edge.

Fig: Spartan-3E Internal Quadrant-Based Clock Network (Electrical Connectivity View).

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FG320: 320-ball Fine-Pitch Ball Grid Array Spartan 3E FPGA Board

Fig: FT320 Package Footprint (top view).

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Spartan 3E Features/Specifications Spartan 3E Features/Specifications

The key features of the Spartan-3E Starter Kit board are: The key features of the Spartan-3E Starter Kit board are:

-3E FPGA -line, 16-character LCD screen

-macrocell XC2C64A CoolRunner

-I/O pins
-pin FBGA package

-pin RS-232 ports (DTE- and DCE-style)

Mbit Platform Flash configuration PROM -board USB-based FPGA/CPLD download/debug interface
MByte (512 Mbit) of DDR SDRAM, x16 data interface, 100+ MHz Digilent 6-pin expansion connectors
MByte (128 Mbit) of parallel NOR Flash (Intel StrataFlash)
-1 1-wire serial EEPROM for bitstream copy protection
MicroBlaze code storage/shadowing
Mbits of SPI serial Flash (STMicro)

-pin DIP socket for auxiliary clock oscillator

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Spartan 3E Features/Specifications Components/Parts of different Company assembled in Spartan 3E board

The key features of the Spartan-3E Starter Kit board are: Linear Technology for the SPI-compatible A/D and D/A converters, the
programmable pre-amplifier, and the power regulators for the non-FPGA
-output, SPI-based Digital-to-Analog Converter (DAC) Components
-input, SPI-based Analog-to-Digital Converter (ADC) with programmable-gain pre-
Intel Corporation for the 128 Mbit StrataFlash memory
amplifier
Micron Technology, Inc. for the 32M x 16 DDR SDRAM
ChipScope SoftTouch debugging port
-encoder with push-button shaft SMSC for the 10/100 Ethernet PHY
STMicroelectronics for the 16M x 1 SPI serial Flash PROM
-button switches
Texas Instruments Incorporated for the three-rail TPS75003 regulator
-encoder with push-button shaft supplying most of the FPGA supply voltages
-button switches Xilinx, Inc. Configuration Solutions Division for the XCF04S Platform
Flash PROM and their support for the embedded USB programmer
Xilinx, Inc. for the XC2C64A CoolRunner -II CPLD
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I/O Capabilities I/O Capabilities

Table: Single-Ended IOSTANDARD Bank Compatibility

The Spartan-3E FPGA SelectIO interface supports many popular
single-ended and differential standards
Spartan-3E FPGAs support the following single-ended standards:
3.3V low-voltage TTL (LVTTL)
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V, 1.5V, or 1.2V
3V PCI at 33 MHz, and in some devices, 66 MHz
HSTL I and III at 1.8V, commonly used in memory applications
SSTL I at 1.8V and 2.5V, commonly used for memory applications

Spartan-3E FPGAs support the following differential standards:

LVDS
Bus LVDS
mini-LVDS
RSDS
Differential HSTL (1.8V, Types I and III)
Differential SSTL (2.5V and 1.8V, Type I)
2.5V LVPECL inputs

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Slew Rate Control Drive Strength

Drive Strength
Slew Rate
Each LVCMOS and LVTTL output additionally supports up to six
Each IOB has a slew-rate control that sets the output switching edge- different drive current strengths as shown in Table.
rate for LVCMOS and LVTTL outputs.
Table: Programmable Output Drive Current

The SLEW attribute controls the slew rate and can either be set to
SLOW (default) or FAST.

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Drive Strength

Each LVCMOS & LVTTL output additionally support upto Six

different drive current strength.

The drive attribute is set to desired drive strength: 2, 4, 6, 8, 12,

16.
Switches/Buttons
Unless and otherwise mentioned, default for LVCMOS and
LVTTL is drive strength 12mA and Slow Slew rate.

High output current drive strength and Fast O/P Slew rate
generally result in fastest I/O performance.

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On Board Switches on Spartan 3E Board On Board Switches - Switch, Buttons and Knob

Slide Switches
There are three types of on-board switches:

Slide Switch (4 Nos.) 3.3V

Push Button Switch (4 Nos.)

Fig: User Constraint File (UCF )
Rotary Push Button Switch (1 No.) 0V
for Slide Switches.

Fig: Four Slide Switches.

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On Board Switches - Switch, Buttons and Knob On Board Switches - Switch, Buttons and Knob

Push-Button Switches Rotary Push-Button Switch The Rotary Push-Button Switch

integrates two different function:
Rotating shaft produces values
whenever the shaft turns.
Push-button switch
Fig: Push-Button requires an internal Pull-
Down resistor in FPGA Input pin.
The Rotary Push-Button Switch
produces three outputs:
Two Shaft encoder outputs
ROT_A
ROT_B

Fig: Four Push-Button switches surrounded Fig: Rotary Push Button switch at the center of The center push-button switch output
Rotary Push Button switch. Fig: User Constraint File (UCF ) for Four Push-Button switches. ROT_CENTER
Push-Button switches.

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On Board Switches - Switch, Buttons and Knob On Board Switches - Switch, Buttons and Knob

Rotary Push-Button Switch Rotary Push-Button Switch

Rotary Switch-Button when Rotary Push-Button Switch when
Not Pressed Not rotating (Detent), both switch closed

Rotary Push-Button Switch when

Rotary Switch-Button when
rotating Right, Switch A opens while B closes
Pressed

Rotary Push-Button Switch when

rotating Left, Switch A closes while B opens

Active Pull-down resistor is used for

Fig: Push-Button circuitry in Rotary Push- Push button operation Fig: Rotary shaft encoder circuitry in Rotary
Button switch. Push-Button switch.
Active Pull-up resistor is used for Rotary operation

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On Board Switches - Switch, Buttons and Knob

Rotary Push-Button Switch

Fig: Outputs from Rotary Shaft Encoder may include Mechanical Chatter.
On-board Displays

Fig: UCF constraints for Rotary Push-button Switch.

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On Board Displays on Spartan 3E Board On Board Display LEDs

LEDS

There are two types of on-board displays:

LED (8 Nos.)

LCD (1 No.)
Fig: UCF constraints for Eight
Discrete LEDs.

Fig: Eight Discrete LEDs.

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On Board Display LEDs On Board Display LCD

Liquid Crystal Display (LCD) I. FPGA LCD Interface

The Spartan-3E FPGA Starter Kit features a 16x2 LCD with 5x8 pixel
matrix (per character). Table: Character LCD Interface Signal

The character is represented as the ASCII value.

Fig: FPGA LCD Interface. 1st

Fig: Liquid Crystal Display (LCD). 2nd 3rd

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On Board Display LCD

II. LCD UCF

Clock
Fig: UCF constraints for the Character LCD.

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On-board Clock Sources/Inputs On-board Clock Sources/Inputs

The Spartan-3E FPGA Board supports three primary clock

input sources:

50 MHz On-Board Oscillator

SMA Clock Input or Output connector

Fig: Available Clock Inputs.

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On-board Clock Sources/Inputs On-board Clock Sources/Inputs

50 MHz On-Board Oscillator Clock Connections

- The board includes a 50 MHz oscillator with a 40% to 60% output duty cycle.
- Each of the clock inputs connect directly to a global buffer input in I/O Bank
- The oscillator is accurate to 2500 Hz or 50 ppm.
0, along the top of the FPGA.

SMA Clock Input or Output connector - As shown in Table below, each of the clock inputs also optimally connects to
an associated DCM.
- Clocks can be supplied off-board via an SMA-style connector.
- The FPGA can also generate a single-ended clock output or other high-speed Table: Clock Inputs and Associated Global Buffers and DCM
signal on the SMA clock connector for an external device.

- The provided 8-pin socket accepts clock oscillators that fit the 8-pin DIP footprint.
- Use this socket if the FPGA application requires a frequency other than 50 MHz.
- Alternatively, use the Digital Clock Manager (DCM) to generate or
synthesize other frequencies from the on-board 50 MHz oscillator.

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On-board Clock Sources/Inputs On-board Clock Sources/Inputs

UCF Constraints UCF Constraints
The clock input sources require two different types of constraints:
The clock input sources require two different types of constraints:
1) The location constraints define the I/O pin assignments and
I/O standards. 2) The period constraints define the clock period and
consequently the clock frequency and the duty cycle of the
- UCF constraints for the three clock input sources, including the I/O pin incoming clock signal.
assignment and the I/O standard used. The settings assume that jumper JP9
is set for 3.3V. - The Xilinx ISE® development software uses timing-driven logic
- If JP9 is set for 2.5V, adjust the IOSTANDARD settings accordingly. placement and routing. Set the clock PERIOD constraint as appropriate.

Fig: UCF Clock Period Constraint.

Fig: UCF constraints for Clock Sources.

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On-board Clock Sources/Inputs

Voltage Control

- The voltage for all I/O pins in FPGA I/O Bank 0 is controlled by jumper JP9.
FPGA Configuration
- Consequently, these clock resources are also controlled by jumper JP9. Options
By default, JP9 is set for 3.3V. The on-board oscillator is a 3.3V device and might
not perform as expected when jumper JP9 is set for 2.5V.

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FPGA Configuration Options FPGA Configuration Options

Table: Spartan-3E Configuration Mode Options and Pin Settings
The configuration data is stored externally in a PROM or some other
non-volatile medium, either on or off the board. After applying power, the
configuration data is written to the FPGA using any of seven different modes:

-standard SPI serial Flash

-standard x8 or x8/x16 parallel NOR Flash

Furthermore, Spartan-3E FPGAs support MultiBoot configuration, allowing two or more FPGA
configuration bitstreams to be stored in a single parallel NOR Flash.
The FPGA application controls which configuration to load next and when to load it.

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Configuration Bitstream Image Sizes FPGA Configuration Options

The Spartan®-3E FPGA Starter Kit board supports a variety of

Table: Number of Bits to Program a Spartan-3E FPGA (Uncompressed Bitstreams)
FPGA configuration options:
Download FPGA designs directly to the Spartan-3E FPGA via JTAG, using the onboard USB
interface. The on-board USB-JTAG logic also provides in-system programming for the on-
board Platform Flash PROM and the Xilinx XC2C64A CPLD.
SPI serial Flash and StrataFlash programming are performed separately.

Program the on-board 4 Mbit Xilinx XCF04S serial Platform Flash PROM, then configure
the FPGA from the image stored in the Platform Flash PROM using Master Serial mode.

Program the on-board 16 Mbit ST Microelectronics SPI serial Flash PROM, then configure
the FPGA from the image stored in the SPI serial Flash PROM using SPI mode.

Program the on-board 128 Mbit Intel StrataFlash parallel NOR Flash PROM, then
configure the FPGA from the image stored in the Flash PROM using BPI Up or BPI Down
configuration modes. Further, an FPGA application can dynamically load two different FPGA
configurations using the Spartan-3E MultiBoot mode. See the Spartan-3E data sheet
(DS312) for additional details on the MultiBoot feature.

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FPGA Configuration Options FPGA Configuration Options

Fig: Spartan 3E FPGA Configuration Options.

Fig: Detailed Configuration Options.

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FPGA Configuration Options
Configuration Mode Jumpers
Table: Spartan-3E Configuration Mode Jumper Settings (J30)

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