electronics

Article
A High Efficiency Linear Power Supply with Pure Sine Wave
for High Voltage Test
Baichao Chen, Wei Gao *, Yaojun Chen, Cuihua Tian , Yuxiong Zhou and Gang Xue

School of Electrical Engineering and Automation, Wuhan University, Wuhan 430072, China;
[email protected] (B.C.); [email protected] (Y.C.); [email protected] (C.T.); [email protected] (Y.Z.);
[email protected] (G.X.)
* Correspondence: [email protected]; Tel.: +86-1562-325-5726

Abstract: The input part of the high-voltage test power supply is usually composed of switching
devices; however, the pulse-type periodic interference caused by the switching devices makes the
monitoring of the test power supply partial discharge more difficult. Therefore, this paper proposes
a high-efficiency and distortion-free linear power supply based on piecewise-linearization with all
N-type transistor. Under the same DC input, multiple power transistors are connected to different
taps of the same transformer. By controlling the period of linear conduction of each power transistor
in turn, we ensure that the power transistor works on the linear side (biased towards saturation)
to reduce its conduction voltage drop and the output realizes sinusoidal piecewise linearization,
so that the converter can greatly improve the system efficiency. After that, from the perspective of
the lowest sum of the transistor loss, an optimization method for the design of the multi-winding
transformer ratio at each stage is proposed. Finally, a power supply prototype based on four-piece
linear converter with an output voltage of 220 V was built. The experimental efficiency reaches
87.03%, and, additionally, if the linear amplification is divided into more sections, the efficiency can
be further improved.



Keywords: power conversion; high voltage test supply; high efficiency; power loss



Citation: Chen, B.; Gao, W.; Chen, Y.;

Tian, C.; Zhou, Y.; Xue, G. A High
Efficiency Linear Power Supply with
1. Introduction
Pure Sine Wave for High Voltage Test.
Electronics 2021, 10, 18. The construction of Ultra-High Voltage (UHV) power grids is inseparable from UHV
https://dx.doi.org/10.3390/ electrical equipment, which must undergo various insulation detection tests before being
electronics10010018 put into operation in the grid system. To successfully carry out various high-voltage tests of
electrical equipment, high-voltage test power supplies are required to supply high-voltage.
Received: 31 October 2020 Determining the insulation status of the test power supply and accurately pre-warning the
Accepted: 22 December 2020 insulation failure can effectively improve the safety and stability of its operation, and it is
Published: 24 December 2020 necessary to carry out the partial discharge test [1].
One of the types of high-voltage test power supplies is power transformers, among
Publisher’s Note: MDPI stays neu- which step-up transformers are often used as intermediate transformers to match the
tral with regard to jurisdictional claims voltage of the power supply and the voltage required for the test. At present, power
in published maps and institutional electronic switching devices are widely used to generate high-power sine waves as the
affiliations. energy source input of the high-voltage test power supply, but at the same time, the use of
switching devices will also increase the difficulty of measuring the partial discharge of the
transformer. When the switching device is turned on or off, it will emit a pulse interfer-
Copyright: © 2020 by the authors. Li-
ence signal. If the interference cannot be effectively suppressed, this pulse-type periodic
censee MDPI, Basel, Switzerland. This interference makes the signal-to-noise ratio and sensitivity of the online detection low,
article is an open access article distributed so it is impossible to effectively and accurately perform real-time partial discharge online
under the terms and conditions of the monitoring. The commonly used methods of partial discharge interference suppression can
Creative Commons Attribution (CC BY) improve the accuracy of measurement to a certain extent, but if the pulse-shaped periodic
license (https://creativecommons.org/ interference caused by switching devices is fundamentally avoided, the problem of difficult
licenses/by/4.0/). partial discharge detection can be solved. There is no pulse signal when the input power

Electronics 2021, 10, 18. https://dx.doi.org/10.3390/electronics10010018 https://www.mdpi.com/journal/electronics

Electronics 2021, 10, 18 2 of 16

supply based on the mechanism of the analog amplifier works, and the power device
works in a linear state. Traditional linear power converters have the advantages of smooth
output waveforms, close to standard sine waves, fast dynamic response characteristics and
wide frequency bandwidth, but serious power consumption problems have become the
technical bottleneck for their application in high power occasion [2,3].
Currently, the efficiency of linear amplifiers is mainly improved by switch-linearity
hybrid power converter. Jin et al. [4–6] improve the efficiency and response speed of
communication power by introducing a switching link in the linear amplifier. The linear
amplifier compensates the waveform, and the switching link bears most of the power
output. Qianzhi et al. [7,8] use the output of a switching circuit as the power supply for
a linear amplifier. Both track the same reference signal source, and the output takes into
account the characteristics of excellent waves and high efficiency. Liu et al. [9] combines
a multilevel switch converter structure with a linear amplifier circuit, and it achieves the
optimal performance of fast reference tracking and linear regulation efficiency, which
enables the RF power amplifier circuit to achieve both linearity and efficiency in modern
communication systems. This type of converter improves the accuracy of the output voltage
waveform, but still has electromagnetic compatibility problems caused by switching noise.
Fujita et al. [10] proposes a diode-clamped high-efficiency linear amplifier topology,
which uses a lower DC level to supply power when the output voltage is low. As the
output voltage increases, the DC power supply automatically switches to a higher level. By
reducing the difference between the output voltage and the DC power supply level, thereby
it obviously improves the efficiency. Fujita et al. References [11,12] apply this amplifier to
motor speed control and transmission systems, and good results can be achieved. However,
the circuit structure is relatively complicated, and the utilization ratio of the semiconductor
is low. The topology uses transistors in series and the P-type transistors must be used,
which limits the further improvement of efficiency. Due to the capacity of the P-type
transistor, the further increase of its output power is limited. The main way to improve
the efficiency of linear power supplies is to reduce the transistor voltage drop. The above
literatures have adopted different forms, some by introducing switching links, some by
changing the form of input power supply, and some by using special topology to directly
reduce the voltage drop.
The research on large-power linear converter is mainly a dual-supply complementary
symmetrical power amplifier circuit, and that technology is quite mature. It is generally
composed of a triode or field-effect transistor circuit, and is difficult to achieve high power
output due to the circuit structure, P-type transistor parameters and low efficiency. To this
end, researchers have proposed a bridge structure with complementary symmetrical paral-
lel outputs composed of a large number of triodes [13,14]. The current output capability of
the power amplifier is increased by increasing the number of triodes, but the size of the
device becomes larger and the heat dissipation design is more complicated.
In order to pursue the characteristics of high-power output, conventional linear power
devices such as BJT and MOSFET have been difficult to meet the demand. This paper
intends to use Insulated Gate Bipolar Transistor (IGBT) as the power transistor. IGBT
selection is not necessary, because on the one hand it can achieve linear operation, while on
the other hand it can provide high voltage and large capacity [15,16]. Figure 1 shows the
output characteristics of the IGBT. The area below the brown curve is the linear working
workspace of the IGBT. When vGE < 9 V, the saturation voltage drop vCE is about 2.5 V.
When the IGBT works in this nearby area, it not only retains the linear amplification
characteristics, but also reduces the transistor consumption to the greatest extent. Based
on this, the paper proposes a single-stage linear converter topology based on an all-N
transistor, which achieves higher voltage and larger power output.
Electronics 2021,2021,
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18 PEER REVIEW 3 of 16

Linear
amplification
workspace

· · · · · · · · · ·

Figure 1.1.Output
Figure Outputcharacteristic of theof
characteristic Insulated Gate Bipolar
the Insulated GateTransistor Transistor (IGBT).
Bipolar(IGBT).
This paper presents a high-efficiency and distortion-free converter based on piecewise-
This paper
linearization with presents
all N-type atransistors
high-efficiency
(HDCPLN), andwhich
distortion-free
can be applied converter
to a linear based on
wise-linearization
power supply. The linear withvoltage
all N-type transistors
drop of (HDCPLN),
the novel topology which
can also can betoapplied
be reduced the to
greatest extent without switching the converter part, and the power
power supply. The linear voltage drop of the novel topology can also be reduced conversion efficiency
can be improved. There is no need for the structure of multiple triodes in parallel, and
greatest extent without switching the converter part, and the power conversion eff
a relatively simple structure can achieve greater power output. Based on a single-stage
can beconverter
linear improved. There
topology is all-N
with no need for the
transistors, structure
multiple poweroftransistors
multiplearetriodes
connectedin paralle
relatively
to differentsimple structure
taps of the can achieve
same transformer. By greater
controllingpower output.
the linear Based angle
conduction on a ofsingle-st
each power transistor in turn, the conduction transistor voltage drop
ear converter topology with all-N transistors, multiple power transistors are conneis reduced, so that
the converter
different tapscan
ofgreatly improve
the same the system efficiency.
transformer. In addition,
By controlling the third
the linear part of this angle
conduction
paper proposes an optimization method for the design of the multi-winding transformer
power transistor in turn, the conduction transistor voltage drop is reduced, so t
ratio at each stage from the perspective of the lowest sum of the transistor loss. Finally,
converter can greatly
the experimental improve
results of the system
a power supply efficiency.
prototype based on Intheaddition,
principle ofthe third part of
four-piece
per proposes
linear converter an optimization method for the design of the multi-winding trans
are given.
ratio at each stage from the perspective of the lowest sum of the transistor loss. F
2. Single-Stage Linear Converter Based on All-N Transistor
the
2.1. experimental results
Single-Stage Linear Power of a power
Converter supply prototype based on the principle of fou
Topology
linear A converter
single-stageare given.
linear converter topology with all-N transistor is shown in Figure 2.
When the control signal vs. is a standard sine, T1 and T10 work complementarily and
2.symmetrically.
Single-Stage and Tf0 are
Tf Linear Converter Basedfeedback,
used for energy on All-NandTransistor
their control signals are the
0
same as T1 and T1 . The difference from the traditional Class-B power amplifier is that it is
2.1. Single-Stage Linear Power Converter Topology
powered by the same DC power supply and is controlled by two voltage signals with a
phaseAdifference of 180◦linear
single-stage converter
. The circuit uses thetopology
same type with all-N
of power transistor
transistor is shown in Fi
and integrates
’
the primary
When output through
the control signal vs.a double winding transformer,
is a standard thereby
sine, T 1 and T1work the secondary side
complementarily an
outputs a complete positive
’ and negative half-cycle voltage waveform.
metrically. Tf and Tf are used for energy feedback, and their control signals are th
’
as T1 and T1. The difference from the traditional Class-B power amplifier is that it
ered by the same DC power supply and is controlled by two voltage signals with
difference of 180°. The circuit uses the same type of power transistor and integra
primary output through a double winding transformer, thereby the secondary si
puts a complete positive and negative half-cycle voltage waveform.
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Figure2.2.AAsingle-stage
Figure single-stagelinear
linearconverter
convertertopology
topologywith
withall-N
all-Ntransistor.
transistor.(a)
(a)Control
Controlsignal
signaljudgment
judg-
Figure
ment 2. A single-stage
circuit. Main linear
(b)circuit circuitconverter
topology.topology with all-N transistor. (a) Control signal judg-
circuit. (b) Main topology.
ment circuit. (b) Main circuit topology.
Theconverter
The converterhas
hasfour
fourworking
workingphasesphasesin inaacycle,
cycle,and
andthetheconduction
conductionofofthe
thepower
power
The converter has four working phases in a cycle, and the conduction of the power
transistorare
transistor areshown
shownin inTable
Table1.1.Figure
Figure33shows
showsthethecontrol
controlsignals
signalsand
andsystem
systemoutput
output
transistor are shown in Table 1. Figure 3 shows the control0’ signals and system output
waveforms.The
waveforms. Thesolid
solidlines
linesofofvs.
vs.andand−−v are actual
vss are actualTT11 and
and ’TT1 driving
drivingwaveforms,
waveforms,andandthe
the
waveforms. The solid lines of vs.0 ’ and −vs are actual T1 and T1 1driving waveforms, and the
dottedlines
dotted linesare
areactual
actualTTf fand
andT’ Tf f driving
drivingwaveforms.
waveforms.
dotted lines are actual Tf and Tf driving waveforms.
Table1.1.Conduction
Table Conductionofoftransistor.
transistor.
Table 1. Conduction of transistor.
LoadVoltage
Load Voltage and Current Relationship Linearly Conducting Transistor
Load Voltage andandCurrent
Current Relationship
Relationship Linearly
Linearly Conducting
Conducting ’
Transistor
Transistor
Positive voltage and negative current (phase 1) 0’ fT
Positivevoltage
Positive voltage and
andnegative
negativecurrent
current(phase 1) 1)
(phase TTff
Positivevoltage
Positive voltage and positive current (phase
2) 2)2) T1
Positive voltage and
andpositive
positivecurrent (phase
current (phase TT
11
Negativevoltage
Negative voltage and
and positive
positive current
current (phase(phase
3) 3) Tf T f
Negative voltage and positive current (phase 3) Tf ’
Negativevoltage
Negative voltage and
and negative
negative current
current (phase
(phase 4) 4) T10 ’ T1
Negative voltage and negative current (phase 4) T1

Figure 3. Input and output waveform diagram.

Figure
Figure3.3.Input
Inputand
andoutput
outputwaveform
waveformdiagram.
diagram.
2.2. Working Principle
2.2.Working
2.2. WorkingPrinciple
Principle
When the driving signals vs, −vs are sine waves with equal amplitude and 180° phase
Whenthe
When thedriving
drivingsignals −svare
signals vvss, ,−v s are sinewaves
sine waveswith withequal
equalamplitude
amplitudeand 180◦phase
and180° phase
difference, and
difference,and
andthethe circuit
thecircuit works
circuitworks in a
worksininaastablestable state,
stablestate, it is known
state,ititisisknown
knownfromfrom Table
fromTable 1 that
Table11that the
thatthe output
theoutput
output
difference,
ofthe
thepower
powerconverter
converterhas has44working
workingphases.
phases.TheThecurrent
currentpath
pathinineach
eachworking
workingstage
stage is
of the power converter has 4 working phases. The current path in each working stage isis
of
shown in Figure
shownininFigure 4.
Figure4.4.
shown
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Figure4.4. Decomposition of
Figure of working
workingprocess
processofofpower
powerconverter. (a)(a)
converter. Positive voltage,
Positive negative
voltage, negative
current. (b) Positive voltage, positive current. (c) Negative voltage, positive current. (d)Negative
current. (b) Positive voltage, positive current. (c) Negative voltage, positive current. (d) Negative
voltage,negative
voltage, negativecurrent.
current.

’
(1) When
(1) Whenthe theloadloadvoltage
voltageisispositive
positiveand andthe thecurrent
currentisisnegative,
negative,only onlythe theTTf0 f works,
works,and and
the current
current path pathisisshown
shownininFigure Figure4a. 4a.Load
Loadvoltage
voltagecommutates,
commutates,and andTT 0 ’
without
the 1 1without
’
driving signal
driving signal is is in
in the off state. The The input
inputsignal
signal−v −svis
s isconnected
connected toto thethe gate gate of of
Tf ,
0 ’
isf0 linearly
Tand Tf T
f , and is linearly conductive.
conductive. T1 and
T1 and Tf areTf cut
are off
cutwithout
off without a current
a currentpath.path. The nega- The
tive half-cycle
negative half-cyclewaveform
waveform of -vsof when−vs thewhen load thecurrent is negative
load current is obtained
is negative is obtainedwithout
without
distortion distortion on the primary
on the primary windingwinding Np2, AllNthe p2 ,“·”
Allare “·” are positive,
thepositive, and the and loadthe RL load
bears
Rpositive
L bears positive voltage (N
voltage (Ns/Np2)·−vss through /N p2 ) ·− v
the through the transformer
s transformer coupling. coupling.
(2) When
(2) Whenthe theloadloadvoltage
voltageisispositive
positiveand andthe thecurrent
currentisispositive,
positive,only onlythe theT1Tworks,
1 works,and and
the current
the current path is shown shown in inFigure
Figure4b. 4b.Load Load current
current commutes,
commutes, and andthethe driving driving sig-
signals
nals vs.vs. is greater
is greater than
than zero zero potential
potential and and connected
connected to tothethe gate
gate ofof T 1T. 1T.f Tisf inis inthetheoff
’ 0 ’ 0
off
state state
duedue to the
to the opposite
opposite voltage
voltage and andT1 T is linearly
is1 linearly conductive.
conductive. T1 T and
1 and T f T aref arecut cut
off
off without a current path. The positive half-cycle waveform
without a current path. The positive half-cycle waveform of −vs whens the load current of − v when the load
current
is positive is positive
is obtainedis obtained
without withoutdistortion distortion on the primary
on the primary winding windingN p1, All the Np1“·” , All
are
the “·” areand
positive, positive,
the loadandRtheL bears RL bearsvoltage
loadpositive positive (Nvoltage
s/Np1)·vs(N s /Np1 )·the
through vs through
transformer the
transformer
coupling. coupling.
(3)
(3) When
Whenthe theloadloadvoltage
voltageisisnegative
negativeand andthe thecurrent
currentisispositive,
positive,only onlythe theTT f works,
f works,and and
the current path is shown in Figure 4c. Load
the current path is shown in Figure 4c. Load voltage commutes, and T1 without voltage commutes, and T 1 without driv-
driving
ing signal signalis inisthe
in the
off off state.
state. TheThe inputinput signal
signal vs.vs.
is is connected
connected totothe thegate
gateofofTT , andTf
f, fand
0 0
Tisf is linearly
linearly conductive.
conductive. T1 T
’
and1 and Tf T
’
f are
are cutcutoffoff without
without a current
a current path.path.
TheThe negativenegative half-
half-cycle
cycle waveform waveform of vs.of vs. the
when when load the load current
current is positiveis positive
is obtained is obtained
without distortion without
distortion
on the primary on thewinding
primary winding
Np2, All the Np2“·”, Allarethe “·” are negative,
negative, and the load and the load Rnegative
RL bears L bears
negative voltage (N s /N ) · v s through
voltage (Ns/Np1)·vs through the transformer coupling.
p1 the transformer coupling.
Electronics 2021, 10, 18 6 of 16

(4) When the load voltage is negative and the current is negative, only the T10 works,
and the current path is shown in Figure 4d. Load current commutes, and the driving
signals −vs is greater than zero potential and connected to the gate of T10 . Tf0 is in the
off state due to the opposite voltage and T10 is linearly conductive. T1 and Tf are cut
off without a current path. The positive half-cycle waveform of −vs when the load
current is negative is obtained without distortion on the primary winding Np2 , All
the “·” are positive, and the load RL bears negative voltage (Ns /Np2 )·−vs through
the transformer coupling.
In order to obtain the expected output and avoid the occurrence of bias magnetism,
generally take Np1 = Np2 = Np , and the output voltage vo

Ns
vo = × vs (1)
Np

The transformer is amplitude-second balance throughout the process, and the system
reaches a stable state. However, due to the inherent shortcomings of push-pull linear power
amplification, the ideal efficiency of A single-stage linear converter with all-N transistor is
only 78.5% [17], which limits its application range.

3. HDCPLN Circuit Topology and Principle

3.1. Reasons for Improving HDCPLN Efficiency
Although the single-stage converter structure proposed above avoids the P-type
transistor, it still belongs to the traditional class-B power amplifier in essence and the
efficiency is still very low. Therefore, the idea of piecewise linearization is proposed
in this paper. At each stage, different power transistors are controlled to be turned on
linearly, so that the working transistor withstands very low voltage drop, which can greatly
reduce losses.
On the basis of the structure proposed in the previous section, a multistage converter
topology is proposed to achieve an all-N transistor high-efficiency converter. The two-stage
circuit structure is taken as an example to explain the principle of HDCPLN efficiency
improvement and the circuit working process.
The multistage signal sources are connected to the gates of the corresponding tran-
sistors via the on-off control circuit shown in Figure 5a according to the transformer ratio
relationship. Figure 5b is the main circuit topology of the two-stage HDCPLN. On the basis
of the single-stage linear converter structure, another input branch is added. Figure 5c
shows the detailed control circuit block diagram. The multi-stage low-voltage signals
are first amplified to the preset value, and then compared with each threshold potential.
Then the signals are connected to the gates of the multi-stage power transistors to control
its linear conduction. The low-voltage DC voltage is input through the collector, and the
target waveform is finally output on the secondary side of the transformer.
As shown in Figure 5d, vs1 and vs2 are multistage driving signal sources, which input
through the gates of T1 , T2 , and Tf respectively (the same can be seen, −vs1 , −vs2 input
through T10 , T20 and Tf0 ), where the dotted line indicates that the signal has not passed
through the control circuit, the brown part is the actual driving waveform and the primary
winding voltage is equal to the driving voltage. vo is the final output voltage waveform of
the secondary side of the transformer, io is the load current, and the DC voltage is E. It can
be known that the commutation angles of the two-stage linear converter are respectively θ,
π − θ, π + θ, and 2π − θ.
During the period from 0 to θ, the T1 conducts linearly and the voltage drop is kept
to a minimum among all transistors, and the other transistors are in a natural cutoff state.
When the instantaneous voltage value of T1 emitter reaches E, it automatically cut off.
From θ to π − θ, T2 automatically turns on when it meets the optimal turn-on condition,
and then iterates back and forth. The timing relationship of the linear turn-on is shown
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in TTable
Table 2. 2. T and T2 conduct
1 and T2 1conduct
linearly in within
steps within the positive
half half cycle of the output
0 linearly
0 in steps the positive cycle of the output
current. Similarly,
’ ’ T1 , T2 conduct linearly in steps within the negative half cycle.
current. Similarly, T1, T2 conduct linearly in steps within the negative half cycle.

Figure 5. Operating principle of two-stage HDCPLN. (a) Control signal judgment circuit. (b) Main
Figure 5. Operating principle of two-stage HDCPLN. (a) Control signal judgment circuit. (b) Main
circuit topology. (c) Control structure diagram. (d) Work process. (e) Traditional amplifier work
circuit topology. (c) Control structure diagram. (d) Work process. (e) Traditional amplifier work
process.
process.
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Table 2. Timing list of transistor turn-on linearly.

Table 2. Timing list of transistor turn-on linearly.
Linear Conduction Angle Interval Transistor Voltage Drop
0~θInterval
Linear Conduction Angle Transistor T1 E-vDrop
Voltage s1msinθ

0~θ θ~π − θ T1 T2 E−vE-v s2msinθ

s1m sinθ
θ~π − θΠ − θ~π T2 T1 E-v
E−vs2ms1m
sinθsinθ
Π − θ~ππ~π + θ T1 ’
T1 E−E-(-v
vs1m sinθ
s1msinθ)
π~π +πθ+ θ~2π − θ T10 ’
T2 E−(− vs1ms2m
E-(-v sinθ)
sinθ)
π + θ~2π − θ T20 ’ E−(−vs2m sinθ)
2π − θ~2π T1 E-(-vs1msinθ)
2π − θ~2π T10 E−(−vs1m sinθ)
Figure 5e is a schematic diagram of the traditional power amplifier operation. The
shaded part5eisisthe
Figure transistor diagram
a schematic voltage drop,
of theand the integral
traditional withamplifier
power the current is the transis-
operation. The
shaded part is the transistor voltage drop, and the integral with the current is theistransistor
tor loss. In the positive and negative half cycles of the output current, the loss borne by
the same
loss. In the transistor
positive andrespectively. HDCPLN
negative half cycles ofalways controls
the output the voltage
current, the loss drop to abylower
is borne the
value, and the total power consumption is distributed to different transistors,
same transistor respectively. HDCPLN always controls the voltage drop to a lower value, which can
improve the working efficiency to a certain extent.
and the total power consumption is distributed to different transistors, which can improve
the working efficiency to a certain extent.
3.2. HDCPLN Topology
3.2. HDCPLN
The methodTopology
of piecewise-linearization can improve the working efficiency as much
The method
as possible underofthe
piecewise-linearization
premise of transmitting can improve
the inputthe workingwith
waveform efficiency as muchThe
high fidelity. as
possible under the premise of transmitting the input waveform with high fidelity.
idea of this method is that multiple transistors are linearly conducted in a hierarchical The idea
ofmanner,
this method is that
and only multiple
one transistors
transistor is on at are
anylinearly
time andconducted in drop
its voltage a hierarchical
is minimal. manner,
Based
and onlyprinciple,
on this one transistor is on atof
the topology any time andisits
HDCPLN voltage
shown drop is6.minimal.
in Figure Based
The n-stage HDCPLNon thisis
principle, the topology
mainly composed of HDCPLN
of 2n-stage signalissources,
shown in Figure 6. The n-stage HDCPLN
piecewise-linearization is mainly
control module, and
composed
n parallel of 2n-stage signal
single-stage linearsources, piecewise-linearization
converters control
based on all-N transistor module,
and and n parallel
multi-winding trans-
single-stage
former. linear converters based on all-N transistor and multi-winding transformer.

Figure6.6.Circuit
Figure Circuittopology
topologyofofHDCPLN.
HDCPLN.

Theprimary
The primaryside
sideofofthe
themulti-winding
multi-windingtransformer
transformerhas has2n 2nwindings
windingswithwithconsistent
consistent
directions,and
directions, and they are connected
connectedendendtotoend.
end. Each
Each connection
connection point is used
point as theastap
is used theof
theof
tap primary winding,
the primary and the
winding, center
and tap of the
the center tap primary windingwinding
of the primary is used as the potential
is used as the
referencereference
potential point of point
the power
of theinput
power oninput
that side.
on thatTheside.
number of single-stage
The number linear convert-
of single-stage linear
ers is the same
converters is theas the as
same number of tapsofoftaps
the number the of
multi-winding
the multi-winding transformer. It can be
transformer. known
It can be
known
from thefrom the winding
winding relationship
relationship that
that the the(1,taps
taps (1,n)
2, ..., . . . , n)the
2, above above thetap
center center
andtap
theand
taps
Electronics 2021, 10, 18 9 of 16

the taps (1’, 2’, . . . , n’) are mutually different ends. During a cycle of output current, the
transistor connected to the upper tap and the transistor connected to the lower tap are
alternately conductive to form a push-pull circuit. The transistors connected to the taps
with the same name end conduct linearly in stage in a half cycle of the output current, so as
to ensure that the primary output voltage and the DC voltage E always maintain a small
difference. By reducing the voltage drop during the linear conduction of the transistors
at each stage, the loss during the energy transmission is reduced. The function of the
piecewise-linearization control module is to change the point in time when the signal
source at each stage is connected to the gate of the transistor.
Let the turns of the primary winding in circuit from stage 1 to stage n be Np11 , Np12 ,
. . . Np1i , . . . Np1n ; Np21 , Np22 , . . . Np2i , . . . Np2n (Np1i = Np2i = Npi , i = 1, 2, . . . , n), the
turns of the secondary winding is Ns , then the transformation ratio ki is:

Ns
ki = (i = 1, 2, . . . , n) (2)
Npi

The multistage sine wave signal sources are vsi (i = 1, 2, . . . , n). The multi-winding
transformer superimposes the waveform of the output voltage on the primary side through
different transformation ratios, thereby high voltage sine wave output from the secondary
side of the transformer, vsi needs to satisfy the following equation:

vs1 × k1 = vs2 × k2 = · · · vsi × ki · · · = vsn × kn (3)

In the conduction control module, vsi needs to be greater than the comparison potential
Ui so that it can be added to the gate of the corresponding IGBT. The setting of Ui directly
determines the turn-on time of the IGBT in the number i converter. To ensure that each
transistor can switch linearly on and off according to the timing, the expression of Ui is
shown in Equation (4), where U1 = 0 V.

k (i−1)
Ui = × E (i = 2, . . . , n) (4)
ki

The output voltage vo is:

vo = vsi × ki (5)
According to Figure 5b, the commutation time of the HDCPLN can be obtained (ωtj (j
= 1, 2, . . . , 4 × (n −1)) as shown in Equations (6)–(8)).

Vsim π
ωtj = arcsin( ) (0 < ωtj < ; i = j = 1, 2, · · · (n − 1)) (6)
E 2

ωtj = π − ωt(n−1−j) (j = n, · · · , 2(n − 1)) (7)

ωtj = π + ωt(j−2(n−1)) (j = 2(n − 1) + 1, · · · , 4(n − 1)) (8)

4. Efficiency Analysis and Optimization of HDCPLN

When HDCPLN is piecewise linearly conductive, the voltage drop and loss of the
transistor can be further obtained in the case of obtaining the on-time period in each stage
power converter. When the DC supply voltage E is constant, if the linear conduction angle
of each transistor is infinitely small, the IGBT conduction voltage drop approaches the
critical value of the linear working area. The consumption is almost negligible, then the
efficiency of HDCPLN can be approximately equal to 1. The way for the linear conduction
time to be infinitely small is to increase the number of stages to infinite, which is obviously
impossible to achieve. It is only possible to use the HDCPLN structure with a limited
number of stages to obtain higher efficiency. This section takes pure resistive load as an
Electronics 2021, 10, 18 10 of 16

example, calculates the working efficiency of HDCPLN, and optimizes the efficiency with
the ratio ki of the multi-winding transformer as a variable.

4.1. Efficiency Calculation of HDCPLN

If the time function of the target output voltage vo is known to be f (t) and the cycle
is T, the relationship f (t) = −f (t + 0.5 × T) is satisfied, the load is RL , and the DC supply
voltage is E. The ratio of a multi-winding transformer can be expressed as:

k 1 , 0 < t ≤ t1


..





 .
ki (t) = k i , t i−1 < t ≤ t i (9)

 ..
.




k n , t n−1 < t ≤ t n


Then the multistage driving signal sources vsi (i = 1, 2 , . . . , n) are respectively:

f( t )
vsi = (10)
ki

In addition, Equations (9) and (10) satisfy the following relationship:

f( t i )
=E (11)
ki

The current i of the number i transistor when it is turned on linearly is:

f (t)
ii = k i io = k i × (12)
RL

In Equation (12), io represents the current on the load.

The total output power of HDCPLN is Po .
Z T
1 f (t)
Po = f (t) × d(t) (13)
T 0 RL

Furthermore, the transistor losses PTi and PT 0 of each stage can be obtained.
i

1 T f (t)
Z
PTi = ( E − f (t)) × ki d(t) (14)
T 0 RL

Since the conduction state of Ti0 in the negative half cycle of the output current is
exactly the same as Ti , PTi is equal to PT0 , then the total loss PT is:
i

n
PT = 2 × ∑ PTi (15)
i =1

Then the theoretical working efficiency of HDCPLN can be found.

Po
η= (16)
PT + Po

4.2. Ratio Optimal Design

The expected output voltage waveform is the standard sine of the amplitude V om . Set
the transformer ratio ki as the variable. With the maximum efficiency of HDCPLN as the
Electronics 2021, 10, 18 11 of 16

goal, the optimal objective function under theoretical conditions can be obtained according
to Equation (16).

Po
 max η = PT + Po =

1 Vom 2



2 RL


 n
 
R ωt 2
 Vom sin(ωt)
 2× ∑ π1 ωt(ii−1) (E− Vom + 12 Vom


ki sin ( ωt ))× k i RL d ( ωt ) RL
i =1
(17)
 s.t. Vkom sin(ωti ) = Eωt0 = 0 ωtn = π2 i ∈ [1, 2, · · · n]

 i







 kn E = Vom
ki−1 <ki


In the Equation (17): the first and second constraints are equality constraints, and
the upper and lower limits of the integral and the value of the number n ratio kn of the
transformer are given when solving the loss at each stage; The third is the ratio constraint
between the primary and secondary windings at all stages.
Set the amplitude of the output voltage V om equal to 310 V and the DC voltage E to 50 V.
In the Matlab software environment, set different transformer winding numbers (i = 2, 3, . . .
. . . ) in turn, and use genetic algorithm programming to solve the multivariate optimization
problem of formula 17 with a single objective in consideration of constraints which include
equal constraints and unequal constraints [18–20]. We can obtain the design strategy and
corresponding optimal efficiency. As shown in Table 3, the efficiency of HDCPLN increases
as the number of transformer ratios increases. The conventional design of multi-winding
transformer ratio refers to that the voltages of the primary side tap are distributed at equal
interval. Compared with the efficiency with the conventional transformer ratio design,
the optimized results are significantly improved. The optimized three-segment power
converter can reach the efficiency level of the conventional four-segment conversion. The
efficiency of a four-stage HDCPLN using an optimized transformation ratio distribution
can reach 91.49%, which is a 12.95% improvement over traditional class-B amplifiers.

Table 3. Transformer ratio design strategy and optimal efficiency.

Optimized Ratio Efficiency with Optimal

Number of Ratios
Distribution Conventional Design/% Efficiency/%
1 6.20 78.54 78.54
2 6.20, 4.38 84.18 85.91
3 6.20, 5.10, 3.51 87.76 89.41
4 6.20, 5.44, 4.38, 2.99 89.69 91.49

In addition, if you want to further improve the working efficiency, you can increase
the number of the windings and use more power converters in parallel. Analysis shows
that variation of HDCPLN working efficiency with the number of transformation ratios
is shown in Figure 7. It is necessary to make a trade-off between design cost and work
efficiency. Although the efficiency increases with the increase in the number of power
converters, the cost will undoubtedly increase as a result. This will also have some effects,
such as the design cost and difficulty of multi-winding transformers, the cost of power
transistors and the layout of radiators, the design of multiple independent control signals,
and the internal layout design of the power supply. From Figure 7, it is easy to know
that when the number of converters increases to a certain value, and the cost increases in
proportion, but the efficiency increase is no longer obvious. When 8-stage converters are
connected in parallel, a very high theoretical efficiency (95.24%) has been reached. After
calculation analysis and comprehensive consideration, this is the best choice for large-scale
applications of the novel linear power supply.
 Electronics2021,
Electronics 2021,10,
10,18
x FOR PEER REVIEW 12of
12 of16
17

Figure 7.
Figure 7. Variation
Variationof
ofHDCPLN
HDCPLNworking
workingefficiency
efficiencywith
withthe
thenumber
numberof
oftransformation
transformationratios.
ratios.

5.
5. Experimental
Experimental Verification
Verification
In
In order
ordertotoverify
verifythe thecorrectness
correctness ofof theoretical
theoretical research,
research, a four-stage
a four-stage HDCPLN
HDCPLN experi-
ex-
mental prototype
perimental is designed
prototype and built
is designed and in thisinpaper.
built FigureFigure
this paper. 8 is a photo
8 is a of the experimental
photo of the exper-
platform, and the circuit
imental platform, and theparameters are shown in
circuit parameters areTable
shown4. Figure 9 shows
in Table the experimental
4. Figure 9 shows the
results of the output voltage and current waveforms. The
experimental results of the output voltage and current waveforms. The peak peak value of the load voltage
value of theis
310 V and the average power is 1 kW. Analysis of the data in Figure
load voltage is 310 V and the average power is 1 kW. Analysis of the data in Figure 9a 9a shows that the total
harmonic
shows thatdistortion coefficientdistortion
the total harmonic (THD) ofcoefficient
the load voltage
(THD) and current
of the are lessand
load voltage than 1.5%,
current
which
are lessachieves high-fidelity
than 1.5%, which achievespowerhigh-fidelity
amplification. In Figure
power 9b, ii represents
amplification. In Figure the9b,
current
ii rep-
flowing through
resents the theflowing
current center tap of thethe
through primary
centerside
tap of
of the
the multi-winding
primary side oftransformer.
the multi-wind- It is
aing
continuous DC waveform, which is consistent with the theoretical
transformer. It is a continuous DC waveform, which is consistent with the theoretical analysis. Figure 9c
shows the results obtained from the no-load test. i and i 0 represent the excitation’ current
analysis. Figure 9c shows the0 results obtained fromf the no-load f test. if and if represent the
flowing through
excitation currentthe Tf andthrough
flowing Tf branches the Toff and
the transformer.
’
Tf branches of the transformer.
Figures 10 and 11 show the waveforms of the current and the output voltage of the
0
primary sideparameters
Table 4. The of the four-stage HDCPLN. experimental prototype. ioi and ioi represent
of 4-stage HDCPLN
the current flowing through the i-th power branch when the load current is positive and
negative. voi and voi Parameter
0 respectively represent the output voltage of the i-th Value stage power
First-stage ratio k
converter on the primary side when the load current is positive and negative.
1 1.79 It can be
seen from Figure 10 that Second-stage
the outputratio k2 of the primary side of each stage
voltage 2.99 of the power
converter satisfies theThird-stage ratio k3
turns ratio relationship between the windings. It superimposes 4.61 the
waveforms output onFourth-stage
Electronics 2021, 10, x FOR PEER REVIEW the secondaryratio sidekin 4 sections to accurately output the 6.00expected 13 load
of 17
voltage. Load RL/Ω 48.6
DC supply voltage E/V 53.2
First-stage drive signal vs1/V ±178.6sin(wt)
Second-stage drive signal vs2/V ±109.1sin(wt)
Third-stage drive signal vs3/V ±72.2 sin(wt)
Fourth-stage drive signal vs4/V ±56.4sin(wt)
Transistor (IGBT) model FF200R12KT4
Control triode PNP model 2SA1413

Figure
Figure 8.8.Experiment
Experimentplatform.
platform.
Electronics 2021, 10, 18 13 of 16

Electronics 2021, 10, x FOR PEER REVIEW 13 of 17

Table 4. The parameters of 4-stage HDCPLN.

Parameter Value
First-stage ratio k1 1.79
Second-stage ratio k2 2.99
Third-stage ratio k3 4.61
Fourth-stage ratio k4 6.00
Load RL /Ω 48.6
DC supply voltage E/V 53.2
First-stage drive signal vs1 /V ±178.6sin(wt)
Second-stage drive signal vs2 /V ±109.1sin(wt)
Third-stage drive signal vs3 /V ±72.2 sin(wt)
Fourth-stage drive signal vs4 /V ±56.4sin(wt)
Transistor (IGBT) model FF200R12KT4
Control triode PNP model 2SA1413
Figure 8. Experiment platform.

Figure 9. Output waveform of 4-stage HDCPLN. (a) Load voltage and current waveform. (b) Primary and secondary total
Figure 9. Output
current.waveform of 4-stage HDCPLN.
current.(a) Load voltage and current waveform. (b) Primary and secondary total
Electronics 2021,(c)
10,No-load voltage,
x FOR PEER excitation
REVIEW 14 of 17
current. (c) No-load voltage, excitation current.
Figures 10 and 11 show the waveforms of the current and the output voltage of the
’
primary side of the four-stage HDCPLN experimental prototype. ioi and ioi represent the
current flowing through the i-th power branch when the load current is positive and neg-
’
ative. voi and voi respectively represent the output voltage of the i-th stage power converter
on the primary side when the load current is positive and negative. It can be seen from
Figure 10 that the output voltage of the primary side of each stage of the power converter
satisfies the turns ratio relationship between the windings. It superimposes the wave-
forms output on the secondary side in sections to accurately output the expected load
voltage.

Figure 10.and
Figure 10. Voltage Voltage and current
current of each of tap
eachof
taptransformer
of transformerprimary
primary winding.
winding. (a) (a)
FirstFirst
stagestage
voltage and current.
voltage and (b) Second-(b) Second-
current.
stage voltage and current. (c) Third-stage voltage and current. (d) Fourth-stage voltage and current.
stage voltage and current. (c) Third-stage voltage and current. (d) Fourth-stage voltage and current.
 Electronics 2021, 10, 18 14 of 16
igure 10. Voltage and current of each tap of transformer primary winding. (a) First stage voltage and current. (b) Second-
age voltage and current. (c) Third-stage voltage and current. (d) Fourth-stage voltage and current.

Figure 11. Current waveform

Figure 11. of 4-stage HDCPLN.
Current waveform (a) Current
of 4-stage HDCPLN. (a)on upper on
Current transistor at each stage.
upper transistor (b)stage.
at each Current on upper
transistor at(b) Current
each stage.on upper transistor at each stage.

Figure 11 shows Figure 11 shows

the current the current
waveform waveform
of the transistor ofin
the transistor
each period in
of each
time period
in the of time in the
HDCPLN. It can be seen that the power transistors (IGBTs) at various stages can switch can switch the
HDCPLN. It can be seen that the power transistors (IGBTs) at various stages
on and
the on and off states off statestoaccording
according to strategy,
the control the control
andstrategy, and theconverter
the multistage multistage converter circuit is
circuit
linearly conducted in sections according to the timing. However,
is linearly conducted in sections according to the timing. However, there is an overlapping there is an overlapping
part in period
part in the power-on the power-on
of each period of each
stage. When stage.
two IGBTsWhenare two IGBTs
turned are turned
on linearly, on linearly, there
there
are two-stage power converters working in parallel. This parallel operation can ensurecan ensure that
are two-stage power converters working in parallel. This parallel operation
the output waveform is not distorted during the switching time and reduce the current
change rate of the transistor, but the disadvantage is that the loss is slightly increased.
The waveforms of the transistor voltage drops vcei and vcei 0 at all stages and the currents
0
ioi and ioi flowing through the transistor are shown in Figure12. It can be seen that when
each stage of IGBT is turned on linearly, its transistor voltage drop is in a low state, and the
minimum value is close to the IGBT’s saturation voltage drop. According to the waveform
data in Figure 12, the transistor consumption of each stage can be obtained. The comparison
result with the theoretical calculation is shown in Table 5. When calculating the theoretical
value of the transistor loss, the default minimum value of the dynamic transistor voltage
drop can reach zero. However, when the actual IGBT is turned on linearly, its turn-on
voltage is greater than the saturation voltage drop. Therefore, the loss of each stage must
be slightly larger than the theoretical data, and the experimental results meet the above
rules. There are other losses with slight effects which cause difference between the working
efficiency of the prototype and the theoretical value.
The current mainstream solutions for power supplies without partial discharge are
linear power supplies, and so are the novel high-efficiency power supplies we proposed.
After experimental analysis, the output waveform is almost pure sine wave without
complex interference signals, which obviously meets the necessary conditions for no partial
discharge. We have done a comparative analysis through series resonance experiments,
and the output voltage is 200 kV. One of the experiments is a series resonance experiment
on the proposed linear power supply. The second experiment is exactly the same as the
first experiment, except that it uses the traditional mechanical contact voltage regulator to
draw electricity directly from the grid, which is the control group. The two experimental
processes are exactly the same, and the partial discharges during the two experimental
processes are measured by a detector. In the two cases, the partial discharge measured by
the detector is almost the same, one is 71.7 pC and the other is 71.8 pC, which shows that
the linear power supply body does not cause additional partial discharge effects.
 comparison result with the theoretical calculation is shown in Table 5. When calculating
the theoretical value of the transistor loss, the default minimum value of the dynamic
transistor voltage drop can reach zero. However, when the actual IGBT is turned on line-
arly, its turn-on voltage is greater than the saturation voltage drop. Therefore, the loss of
Electronics 2021, 10, 18 15 of 16
each stage must be slightly larger than the theoretical data, and the experimental results
meet the above rules. There are other losses with slight effects which cause difference be-
tween the working efficiency of the prototype and the theoretical value.

Figure
Figure 12.
12. Voltage
Voltage drop
drop and
and current
current of
of power
power converter
converter transistor
transistor at
at all stages. (a)
all stages. (a) First-stage
First-stage transistor
transistor voltage
voltage drop,
drop,
current. (b) Second-stage transistor voltage drop, current. (c) Third-stage transistor voltage drop, current. (d) Fourth-stage
current. (b) Second-stage transistor voltage drop, current. (c) Third-stage transistor voltage drop, current. (d) Fourth-stage
transistor voltage drop, current.
transistor voltage drop, current.

The current mainstream solutions for power supplies without partial discharge are
Table 5. Four-stage HDCPLN experiment and theoretical power loss comparison.
linear power supplies, and so are the novel high-efficiency power supplies we proposed.
After experimental
Categoryanalysis, the output waveform
Theoretical is almost pure
Calculation/W sine wave without
Experimental com-
Inquiry/W
plex interference signals, which obviously meets the necessary conditions for no partial
First-stage loss 5.71 8.13
discharge. We haveloss
Second-stage done a comparative analysis
10.02 through series resonance 13.87experiments,
and the output voltage
Third-stage loss is 200 kV. One of the experiments is a series resonance
34.27 39.12 experiment
on the proposed linear
Fourth-stage loss power supply. The59.67
second experiment is exactly66.91
the same as the
Total loss 109.66 128.03
Efficiency 90.12% 87.03%

6. Conclusions
The paper proposes a kind of high-efficiency linear power supply, whose power
device works in the linear state. There is no pulse interference problem so that it can be
used as the input part of high voltage test power supply. In application, the transformer
in HDCPLN can replace the step-up transformer in the high-voltage test power supply,
which can further reduce the volume of the test equipment. In addition, the novel power
amplifier topology also solves the problem that traditional power conversion has low
working efficiency and cannot achieve high power output due to the limitation of P-type
transistor parameters. The converter input by a plurality of power amplifier modules
connected in parallel, which are linearly conducted in a hierarchical manner. Only one
transistor is on at any time and its voltage drop is minimal.
Electronics 2021, 10, 18 16 of 16

(1) The topology based on above principle can achieve efficient power amplification.
(2) The optimized multi-winding transformer ratio of the same number can further
reduce transistor consumption, thereby improving efficiency.
(3) The increase in efficiency increases with the number of segments.

In addition, the analysis of the experimental results found that there is a large differ-
ence between the transistor loss at each stage. A method of making it evenly distributed
among the transistors with the lowest total consumption is worth further exploration.

Author Contributions: Methodology and Supervision, B.C., Y.C. and C.T.; Methodology, Y.Z. and
G.X.; Writing—original draft, W.G.; Writing—review and editing, W.G. All authors have read and
agreed to the published version of the manuscript.
Funding: This research received no external funding.
Data Availability Statement: The data presented in this study are available on request from the
corresponding author.
Conflicts of Interest: The authors declare no conflict of interest.

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