INTERNAL

Unit Code and

Title Digital Electronics SAMPLE

Student Number SURNAME/FAMILY NAME OTHER OR GIVEN NAME/S

SOLUTIONS

Please print clearly

Duration 180 Minutes

Attempt All questions

Marks Section A: 40 marks

Section B: 60 marks
Total: 100 marks

Type of Exam Closed Book Exam

Special Instructions • This examination paper consists of 2 sections.

• Students are allowed to use an ECU School of

Engineering approved scientific calculator only.

• Write your answers in the space provided under each

question. Use the attached spare pages if additional space
is required.

• The entire examination paper should be returned, even if

parts of it have not been attempted. No pages should be
removed from this examination paper. Failure to
comply will attract penalties.

Do not commence reading or writing this

examination until you are told to do so.

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 SECTION A (40 marks)
Important instruction: There are total of 20 questions. For each question, clearly state in the box
provided the one response that best completes the statement or answers the question. If you need to
amend, simply strike out your original answer and place your new answer next to it, which can be outside
the box. Do not write a new answer on top of old one. Ambiguous answers will be marked as wrong.
Each question is worth 2 marks.
For multiple-choice questions, you are required to pick the BEST answer.

1. What is the decimal value of the largest binary number of 15 bits?

a. 32,767.
b. 32,768.
c. 65,535.
d. 65,536
e. None of the above.

2. Assume the delay of a NOT gate is 2ns, a AND gate is 4ns, and a OR gate is 4ns. What is the
maximum delay (in ns) from the inputs to the output of the circuit below?
a. 4.
b. 6.
c. 8.
d. 10.
e. None of the above.

3. Which of the following are legal single-cycle datapath operations.

a. Copy data from a memory location into another memory location.
b. Copy data from a register file location into another register file location.
c. Copy data from a memory location into a register file location.
d. Both b and c.
e. None of the above.

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4. Convert the binary number 1001100110110 to hexadecimal number.

1336

5. The figure below presents the Karnaugh map of the function 𝐹(𝐴, 𝐵, 𝐶, 𝐷). Minimise and express
𝐹 as a Boolean Function

𝐹(𝐴, 𝐵, 𝐶, 𝐷) = 𝐵′ 𝐷 ′ + 𝐴𝐵

6. 2’s complement of 00101001 is ____________ .

a. 00100001
b. 10111001
c. 11111111
d. 00000000
e. None of the above

7. In sequential circuits, two states are equivalent if, for all input combinations, they
a. have the same outputs
b. change to the same or equivalent next states.
c. Both a and b.
d. None of the above.

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8. Express the output 𝐹(𝑥, 𝑦, 𝑧) of the circuit below.
𝑥 𝑦 𝑧

𝐹(𝑥, 𝑦, 𝑧) = (𝑥𝑧 ′ + 𝑧)(𝑥 ′ + 𝑦′𝑧)

9. In a Mealy FSM,
a. The output only depends on the current state.
b. The output only depends on the inputs.
c. The output depends on both the current state and the inputs.
d. None of the above.

10. How many address lines are required to provide a memory capacity of 512M bytes?

29

11. How many memory units of the 256𝐾 × 8 chip are needed to provide a memory capacity of
1𝑀 × 8?
a. 3.
b. 4.
c. 5.
d. None of the above.

12. Which of the following devices can be used to implement combinational circuits?
a. PAL.
b. SPLD.
c. CPLD.
d. All of the above
e. None of the above.

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 D

13. Convert the decimal number 30 to 8-bit two’s complement binary form.

1110 0010

14. Use De Morgan’s Law to convert the following equation 𝐹(𝑎, 𝑏, 𝑐, 𝑑) = (𝑎𝑐′ + 𝑏 ′ 𝑑)′ to sum-of-
products form.

𝐹 = 𝑎′ 𝑏 + 𝑎′ 𝑑 ′ + 𝑏𝑐 + 𝑐𝑑′

15. How many parity bits must be included with the data word to achieve single error correction
and double-error detection using Hamming code, given that the data word contains 10 bits.
a. 3.
b. 4.
c. 5.
d. None of the above.

16. A 12‐bit Hamming code word containing 8 bits of data and 4 parity bits is read from memory.
What was the original 8‐bit data word that was written into memory if the 12‐bit word read out is
101011010100?
a. 11110100.
b. 10111111.
c. 01000000.
d. None of the above.

17. The bitwise operation performs the logical operations on strings of bits by considering each pair
of corresponding bits separately. Given two eight‐bit strings 𝐴 = 10110101 and 𝐵 = 10111100,
evaluate the eight‐bit result after the following logical operations XOR.
a. 10100000.
b. 10111100.
c. 01000011.
d. 00011101.
e. None of the above.

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 E

18. In which circuit the output is dependant on the present input(s) and the previous output(s)?
a. Combinational circuits.
b. Sequential circuits.
c. Both a and b.
d. None of the above.

19. What type of component is described by the VHDL source file below?

a. A multiplexer.
b. A decoder.
c. An adder/subtractor.
d. A comparator.
e. None of the above

20. If a processor’s program counter is 16-bit wide, up to how many words can the processor’s
instruction memory hold (ignore any special tricks to expand the instruction memory size)

65,536

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 SECTION B (60 marks)

Question 1
a. Convert the binary following octal numbers to binary. Show all steps
i. 65
ii. 124

Solution:
Note: one octal digit is presented by 3 binary digits.
o (65)8 = (110 101)2
o (124)8 = (001010100)2

b. Obtain the 1’complement of the following numbers.

i. (11001010)2
ii. (00000000)2

Solution:
Note: 1’s complement is the inversion.
o 1’s complement of 11001010 is 00110101
o 1’s complement of 00000000 is 11111111

c. Determine whether the Boolean function 𝐹 = 𝑥(𝑥 + 𝑦)′ + 𝑥𝑦 and 𝐺 = 𝑥 + 𝑦 are equivalent?

Solution:
We have,
• 𝐹 = 𝑥(𝑥 + 𝑦)′ + 𝑥𝑦 = 𝑥𝑥 ′ 𝑦 ′ + 𝑥𝑦 = 𝑥𝑦, and
• 𝐺 =𝑥+𝑦

Let 𝑥 = 0, 𝑦 = 1 → 𝐹 = 0 and 𝐺 = 1 → 𝐹 and 𝐺 are not equivalent.

Alternative solution: use truth table and compare the output value of 𝐹 and 𝐺.

d. Use DeMorgan’s law to find the inverse of the following equation and then reduce to sum-of-products:
𝐹(𝑥, 𝑦, 𝑧) = (𝑥𝑦𝑧 + 𝑥′𝑦)

Solution:
𝐹 ′ = (𝑥𝑦𝑧 + 𝑥 ′ 𝑦)′
= (𝑥 ′ + 𝑦 ′ + 𝑧 ′ )(𝑥 + 𝑦 ′ )
= 𝑥 ′ 𝑥 + 𝑥 ′ 𝑦′ + 𝑥𝑦 ′ + 𝑦 ′ 𝑦 ′ + 𝑥𝑧 ′ + 𝑦 ′ 𝑧 ′
= 𝑥 ′ 𝑦′ + 𝑥𝑦 ′ + 𝑦 ′ + 𝑥𝑧 ′ + 𝑦 ′ 𝑧 ′
= 𝑥𝑧 ′ + 𝑦′

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 Note: 𝑦 ′ + 𝑦 ′ 𝑥 + 𝑦 ′ 𝑧 ′ + 𝑥′𝑦′ = 𝑦 ′ (1 + 𝑥 + 𝑧 ′ + 𝑥′) = 𝑦′

e. Draw the ASMD chart for the following state transition: “start from state S1 and monitor input
𝑥; control goes to state 𝑆2 if two consecutive 1s are observed. It remains in 𝑆2 until another 1
observed; it then goes back to 𝑆1 ”

Solution
• There are no datapath operations required. The chart will be the same as ASM

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Question 2

Solution
a. Convert the following equation directly to gate-level circuit.
𝐹 = ((𝑎 + 𝑏 ′ )(𝑐 ′ + 𝑑)) + (𝑐 + 𝑑 + 𝑒 ′ )

b. The function 𝐹 is shown in the truth table below

i) Convert to a Boolean equation as sum-of-minterms

𝐹 = 𝑎′ 𝑏 ′ 𝑐 + 𝑎′ 𝑏𝑐 ′ + 𝑎′ 𝑏𝑐 + 𝑎𝑏 ′ 𝑐 + 𝑎𝑏𝑐 ′ + 𝑎𝑏𝑐 = ∑(1,2,3,5,6,7)
ii) Minimise 𝐺 using K-map. Show all groups

𝐹 =𝑏+𝑐

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Question 3
a. Use a 8 to 1 multiplexer as shown in the figure below, design the circuit of which the logic
expression as 𝐺(𝑥, 𝑦, 𝑧) = 𝑥 ′ 𝑦 ′ + 𝑦𝑧 + 𝑥𝑦𝑧′. Show all steps.

Solution:
Present 𝐺 in the form sum of minterms

𝐺 = 𝑥 ′ 𝑦 ′ 𝑧 + 𝑥 ′ 𝑦 ′ 𝑧 ′ + 𝑥𝑦𝑧 + 𝑥 ′ 𝑦𝑧 + 𝑥𝑦𝑧 ′ = ∑(0,1,3,6,7)

• Connect inputs 0,1,3,6,7 to Vcc

• Connect the rest to GND.

b. Let 𝐴 = 𝑎1 𝑎0 and 𝐵 = 𝑏1 𝑏0 be two 2-bit binary numbers. Design a combinational circuit to compare the
magnitudes of 𝐴 and 𝐵. The output will be 1 if 𝐴 equals to 𝐵, and 0 otherwise.

Solution:
Please refer to lecture 4.
- The circuit include 4 inputs (2 inputs for binary 𝐴 = 𝑎1 𝑎0 and the other two for binary 𝐵 = 𝑏1 𝑏0 )
- Let 𝐹 be the output of the comparator, then 𝐹 will be 1 when (𝑎1 = 𝑏1 and 𝑎0 = 𝑏0 ), 0 otherwise.
- The K-map is shown as below:

𝐹 = 𝑎1 𝑎0 𝑏1 𝑏0 + 𝑎′1 𝑎0 𝑏′1 𝑏0 + 𝑎1 𝑎′0 𝑏1 𝑏′0 + 𝑎′1 𝑏′1 𝑎′0 𝑏′0

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- The circuit:

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Question 4
Consider full adder in figure below and assume AND gates have a delay of 3ns, OR gates have a delay
of 3ns, and XOR gates have a delay of 5ns.
a. What is the delay of the adder?
b. Use multiple of the full adders, design a 4-bit carry-ripple binary adder.
c. What is the upper limit of the clock frequency required in Hz for that the operation of the
designed 4-bit binary adder is fully completed.

a. What is the delay of the adder?

• Delay from inputs to sum = 5ns
• Delay from input to co = 3ns+3ns = 6ns
➔ Delay of the adder is 6ns.

b. Use multiple of the full adders, design a 4-bit carry-ripple binary adder.
Refer to lecture 4.

c. What is the upper limit of the clock frequency required in Hz for that the operation of
the designed 4-bit binary adder is fully completed.

• Let 𝑇 be the total time required to complete the adder operation:

𝑇 ≥ 4 × 6 = 24 𝑛𝑠
• A clock frequency 𝑓 must satisfy:
1 1
𝑓≤ = ≈ 41,666,666 (𝐻𝑧)
𝑇 24𝑛𝑠

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Question 5
The state diagram below shows the FSM for a controller which consists of one input 𝑎 and two outputs
𝑥 and 𝑦.
a. What is the type of the FSM machine, Moore or Mealy? Explain the conclusion.
b. Write the state table of the FSM.
c. Write down and simplify the output equations and the state equations.
d. Draw the logic diagram of the outputs.

Solution:
a. What is the type of the FSM machine, Moore or Mealy? Explain the conclusion.
The outputs 𝑥 and 𝑦 are only dependent on the current state → Moore type FSM.
b. Write the state table of the FSM.
• Two FFs required.
• Denote the outputs of the FFs as 𝑄1 and 𝑄0 , we have:
Current States Input Next states Outputs
𝑄1 𝑄0 𝑎 𝑄1 (𝑡 + 1) 𝑄0 (𝑡 + 1) 𝑥 𝑦
0 0 0 0 0 0 1
0 0 1 0 1 0 1
0 1 0 1 1 1 0
0 1 1 0 1 1 0
1 0 0 0 0 0 1
1 0 1 1 0 0 1
1 1 0 1 1 1 0
1 1 1 1 0 1 0
c. Write down and simplify the output equations and the state equations.
• Consider 𝑄1 , 𝑄0 and 𝑎 as the inputs of the equations.
• We need to identify two state equations 𝑄1 (𝑡 + 1), 𝑄0 (𝑡 + 1) and two outputs equations 𝑥, and 𝑦.
• Use Karnaugh maps.

Practice please - An example for 𝑸𝟏 (𝒕 + 𝟏)

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 𝑄1 (𝑡 + 1) = 𝑄1 𝑎 + 𝑄0 𝑎′
Similar for 𝑄0 (𝑡 + 1), 𝑥, and 𝑦.
d. Draw the logic diagram of the outputs.
• Implement the circuits using the expressions 𝑥 and 𝑦 derived in c)
Practice please – These are combinational circuits, considering 𝑸𝟏 , 𝑸𝟎 and 𝒂 as inputs.

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 END OF EXAM PAPER

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