3EC1120 Advanced Digital

System Design using

Programmable Logic

Dr. Vaishali H. Dhare

 Teaching Scheme

Course Examination Scheme

code Course Name
Hours Component
Weightage
SEE SEE CE LPW
Advanced Digital System 3.00 0.4 0.4 0.2
Design using
3EC1120
Programmable Logic

Class Test Sessional Term/ Total CE

Exam Sp. Assign
ment
30 40 30 100

Dr. Vaishali H. Dhare

 Course Outcomes (COs):
At the end of the course, students will be
able to -
❑ Implement the design from specification
to net list level using hardware
description language
❑ Implement the digital designs on FPGA
in context of synthesis, device utilization
and speed and power optimization
❑ Optimize the design using the concepts
of simulation, synthesis and Place &
Route

Dr. Vaishali H. Dhare

 Text /Reference Books
❑ Brown Vranesic, Fundamentals of
Digital Logic with Verilog Design. Tata
McGrawHill
❑ Wyane Wolf, FPGA Based System
Design, Pearson
❑ Sameer Palnitkar, Verilog HDL,
Pearson

Dr. Vaishali H. Dhare

 Text /Reference Books
❑ A Verilog HDL Primer by J. Bhasker,
BS Publications
❑ Verilog HDL by Samir Palnitkar,
Pearson Education

Dr. Vaishali H. Dhare

 Text /Reference Books
❑ C. H. Roth, Digital System Design with VHDL,
PWS/Brookscole
❑ Stiphen M Trimberger, Field Programmable Gate Array
Technology, Springer
❑ Brown Vranesic, Fundamentals of Digital Logic with Verilog
Design. Tata McGrawHill
❑ Stephen Brown and Zvonko Vranesic, Fundamentals of
Digital Logic with VHDL Design. Tata McGrawHill
❑ Sudhakar Yalamanchi, Introductory VHDL From Simulation
to Synthesis, Pearson Education
❑ Mark Zwolinski, Digital System Design with VHDL, Pearson
Education
❑ Peter J Ashenden, The Designer’s Guide to VHDL, Elsevier
❑ Kevin Skahil, VHDL for Programmable Logic, Pearson
❑ Wyane Wolf, FPGA Based System Design, Pearson

Dr. Vaishali H. Dhare

 Other References
❑ https://lms.nirmauni.ac.in/course/v
iew.php?id=689
❑ http://textofvideo.nptel.iitm.ac.in/vid
eo.php?courseId=106105083

Dr. Vaishali H. Dhare

VLSI Design Flow

Dr. Vaishali H. Dhare

Typical Design Flow

Dr. Vaishali H. Dhare

Dr. Vaishali H. Dhare
https://technology.nirmauni.ac.in/author/vaish
alidhare/

Dr. Vaishali H. Dhare

 Processes
1 Design Specification

2 Architecture

3 RTL Coding

4 Simulation and Synthesis

5 Verification

6 Test Development: DFT/ATPG

7 Formal Verification
 Processes
8 Timing Analysis

9 Transistor Level
Physical Design:
10 Floorplan/Placement/Routing/Timing
Analysis/CTS
11 Layout

12 Fabrication

13 Packaging

14 Testing
 Processes
1 Design Specification

2 Architecture

3 RTL Coding
Front
4 Simulation and Synthesis End

5 Verification

6 Test Development: DFT/ATPG

7 Formal Verification
 Processes
8 Timing Analysis

9 Transistor Level
Physical Design:
10 Floorplan/Placement/Routing/Timing
Analysis/CTS
Back
11 Layout End

12 Fabrication

13 Packaging

14 Testing
FPGA Design Flow
 What will we learn?
❑ Hardware Description Languages
(HDLs)
❑ Verilog
❑ VHDL

Dr. Vaishali H. Dhare

 What is HDL?
❑ Hardware Description Language is
used to model a digital system at
different level of abstraction
❑ Behavioral, functional, logic and
switch

Dr. Vaishali H. Dhare

 HDL History
❑ The first HDL was ISP (Instruction-set
Processor language), invented by C.
Gordon Bell and Alan Newell at
Carnegie Mellon University

❑ This language was also the first to

use the term register transfer level
Dr. Vaishali H. Dhare
 Why HDLs?
❑ The complexity of logic circuits has
increased dramatically in the past few
decades
❑ Other forms of EDAs are no longer
effective
❑ HDLs offer a consistent and efficient
method for both design and synthesis
❑ HDLs are relatively easy to learn

Dr. Vaishali H. Dhare

 Why HDLs?
❑ Technology independent
❑ Technology changes- no need to redesign
circuit/ system
❑ Functional verification (simulation)
❑ Can be done early in design cycle
❑ Optimization
❑ Since designer work at RTL level
❑ Designer can modify RTL description until
functionality satisfy
❑ Library support – for reuse and previously
verified components
❑ Timing Information

Dr. Vaishali H. Dhare

 Why not C or other?
❑ Timing information
❑ Sequential and Concurrent
❑ Synthesis

Dr. Vaishali H. Dhare

 History
❑ Verilog HDL originated in 1983 at
Gateway Design Automation
❑ 1995 –Original standard IEEE 1364-
1995 was approved
❑ IEEE 1364-2001 is latest standard
❑ VHDL was developed under the
contract from DARPA

Dr. Vaishali H. Dhare

Verilog

Dr. Vaishali H. Dhare

 Popularity of Verilog HDL
❑ Easy to learn and easy to use
❑ Syntaxes are similar to C programming
❑ Verilog HDL allows different level of
abstraction to be mixed in same model
❑ Most popular logic synthesis tools
support Verilog HDL
❑ All fabrication vendors provide Verilog
HDL libraries
❑ Programming Language Interface (PLI)
Dr. Vaishali H. Dhare
 Verilog
❑ Synthesizable
❑ Non-Synthesizable (simulation based)

Dr. Vaishali H. Dhare

Verilog Basics

Dr. Vaishali H. Dhare

 Verilog Vs VHDL
❑ VHDL was designed to support system
level design and Specifications
❑ Verilog is Preliminary for Digital
Hardware Design (FPGA, ASIC)
❑ VHDL provides some high level
constructs (user defined types like
integer , Boolean etc.)
❑ Verilog
❑ all the gates are available –provides
comprehensive to gate level design
❑ Not available in VHDL—includes as
Pacakages
Dr. Vaishali H. Dhare
 Verilog
❑ Synthesizable
❑ Non-Synthesizable (simulation based)

Dr. Vaishali H. Dhare

 Design Methodologies
❑ Top Down
❑ Bottom Up

Dr. Vaishali H. Dhare

Top Down

Dr. Vaishali H. Dhare

Bottom Up

Dr. Vaishali H. Dhare

4-bit Ripple Carry Counter

Dr. Vaishali H. Dhare

4-bit Ripple Carry Counter

Dr. Vaishali H. Dhare

4-bit Ripple Carry Counter

Dr. Vaishali H. Dhare

 Top Down Vs Bottom up
❑ Optimization
❑ Area
❑ Speed
❑ Power
❑ Time to Market (TTM)
❑ Size of Design

Dr. Vaishali H. Dhare

 Design at Different Level
❑ Behavioural
❑ Dataflow
❑ Structural

Dr. Vaishali H. Dhare

 Design at Different Level:
Behavioural
❑ Behavioral: Algorithmically specify the
behavior of the design
❑ Example: a
Black Box out
if (select == 0) begin
b 2x1 MUX

out = b;
end sel

else if (select == 1) begin

out = a;
end
Dr. Vaishali H. Dhare
 Design at Different Level:
Dataflow
❑ Dataflow: Specify output signals in
terms of input signals
❑ Example:
assign out = (sel & a) | (~sel
& b); b

sel_b
sel
sel_n
out
sel_a

Dr. Vaishali H. Dhare

 Design at Different Level:
Structural
❑ Structural: Logic is described in
terms of Verilog gate primitives
❑ Example: b
not n1(sel_n, sel); sel n1
a1
sel_b

sel_n
and a1(sel_b, b, sel_b); o1 out
a
and a2(sel_a, a, sel); a2 sel_a

or o1(out, sel_b, sel_a);

Dr. Vaishali H. Dhare

Module in Verilog

Dr. Vaishali H. Dhare

Components of Verilog
Modules

Dr. Vaishali H. Dhare

 Modules
❑ The basic hardware unit is called module
❑ Syntax
module <module_name>(<module_terminal_list>);
...
<module internals>
...
endmodule
❑ Example:
module T_ff(q, clock, reset);
...
<functionality of T_flipflop>
endmodule

Dr. Vaishali H. Dhare

 Modules
❑ Module can not contains definition of
other module
❑ A module can be instantiate in
module
❑ Allows the creation of hierarchy in
Verilog description

Dr. Vaishali H. Dhare

 Illegal module Definition
// Define the top level module called ripple carry
// counter. It is illegal to define the module T_FF inside
// this module.
module ripple_carry_counter(q, clk, reset);
output [3:0] q;
input clk, reset;
module T_FF(q, clock, reset);// ILLEGAL MODULE NESTING
:
<module T_FF internals>
:
endmodule // END OF ILLEGAL MODULE NESTING

endmodule

Dr. Vaishali H. Dhare

 Observations
❑ Components of Module
❑ variable declaration, dataflow (assign)
statements, behavioral block (always or
initial)
❑ All components except module,
module name, and endmodule are
optional
❑ Verilog allows multiple modules to be
defined in a single file
Dr. Vaishali H. Dhare
 Exercise (Half Adder)
module HalfAdder(A,B,Sum,Carry);
input A,B;
output Sum,Carry;
assign Sum = A ^ B;
//^ denotes XOR

assign Carry = A & B;

// & denotes AND

endmodule

Dr. Vaishali H. Dhare

Data Types

Dr. Vaishali H. Dhare

 Data Types
❑ Wire
❑ Reg
❑ Vector
❑ String

Dr. Vaishali H. Dhare

 Data Types
❑ Value set
❑ Verilog supports 4 values and 8
strengths to model the functionality of
real hardware
Value Level Condition in Hardware Circuits

0 Logic zero, false condition

1 Logic one, true condition

X Unknown logic value

Z High impedance, floating state

Dr. Vaishali H. Dhare

 Data Types
❑ Nets
❑ Net represents connections between
hardware elements

❑ Nets are primarily declared by keyword

wire
❑ Syntax
wire a;
wire b, c;
wire d=1’b0;
(default it is considered as 1 bit)
Dr. Vaishali H. Dhare
 Data Types
❑ Register
❑ Register represents the data storage
elements
❑ Register retains until another values are
placed into them
❑ A variable which can hold the value
❑ Syntax
reg reset;

Dr. Vaishali H. Dhare

 Data Types
❑ Vectors
❑ Nets and register can be declared as vectors
(multiple bit width)
❑ If not mentioned , the default is scalar (1-
bit)
wire a; // scalar net variable
reg reset; // scalar reg variable
wire [7:0] a;
reg [0:40] virtual_add;
❑ Vector can be defined as [#high:#low] or
[#low:#high]- first is MSB

Dr. Vaishali H. Dhare

 Data Types
❑ Vector
❑ Example
❑ wire [0:3] a;

❑ wire [3:0] a;

❑ a→ 0011

❑ First value defined in square bracket is MSB

Dr. Vaishali H. Dhare
 Array
❑ <array_name> [<subscript>]

❑ integer count[0:7]; //An array of 8 count

variables
❑ reg bool[31:0];// Array of 32 one-bit boolean
register variables
❑ time chk_point[1:100];//Array of 100 time
checkpoint variables
❑ reg[4:0] port_id[0:7];//Array of 8 port_ids and
each port_id is 5 bits wide
❑ interger matrix[4:0][0:255];//Illegal declaration
of Multidimensonal array}
❑ Count[5]//5th element of array of count variables
❑ Chk_point[100]//100th time check point value
❑ Port_id[3]//3rd element if port_id array. This is
a 5-bit value

Dr. Vaishali H. Dhare

 String
reg [8*18:1] string_value;//Declare a
variable that is 18 bytes wide

string_value=“hello verilog world”;

//String can be stored in variable

Dr. Vaishali H. Dhare

Instance in Verilog

Dr. Vaishali H. Dhare

1 2

Dr. Vaishali H. Dhare

 1. D flip-flop
// module DFF with asynchronous reset
module DFF(q, d, clk, reset);
output q;
input d, clk, reset;
reg q;

always @(posedge reset or negedge clk)

if (reset)
q = 1'b0;
else
q = d;
endmodule
Dr. Vaishali H. Dhare
 2. T flip-flop
module TFF(q,clk,reset);
output q;
input clk, reset;
wire d;

DFF dff0(q,d,clk,reset);
not n1(d, q); // not is a Verilog provided primitive.

endmodule

Dr. Vaishali H. Dhare

 Instances
module ripple_carry_counter(q, clk,
reset);

output [3:0] q;
input clk, reset;
//4 instances of the module TFF are
created.
TFF tff0(q[0],clk, reset);
TFF tff1(q[1],q[0], reset);
TFF tff2(q[2],q[1], reset);
TFF tff3(q[3],q[2], reset);

endmodule
Dr. Vaishali H. Dhare
 Connecting Port to
external Signal
❑ Connections between signals
specified in the module instantiations
and the port in the module definition
❑ Connecting by ordered list
❑ Connecting Ports by name

Dr. Vaishali H. Dhare

 Connecting Port to
external Signal
❑ Connecting by ordered list: It should be
in same order
module Top;
//Declare connection variables
reg[3:0]A,B;
reg C_IN;
wire[3:0]SUM;
wire C_OUT;
//Instantiate fulladd4,call it fa_ordered.
//signals are connected to port in order(by
position)
Fulladd4 fa_ordered(SUM,C_OUT,A,B,C_IN);
endmodule
Dr. Vaishali H. Dhare
 Connecting Port to
external Signal
module fulladd4(sum,c_out,a,b,c_in);
output[3:0] sum;
output c_out;
input[3:0] a,b;
input c_in;
…
<module internals>
…
endmodule

Dr. Vaishali H. Dhare

 Connecting Port to
external Signal
❑ Connecting Ports by name

//Instantiate module fa_byname and

connect signals to ports by name fulladd4
fa_name(.c_out(C_OUT),.sum(SUM), .b(B),
.c_in(C_IN), .a(A));

//Instantiate module fa_byname and

connect signals to ports by name fulladd4
fa_byname(.sum(SUM),.b(B), .c_in(C_IN),
.a(A));

Dr. Vaishali H. Dhare

 Lexical Conventions
❑ Number Specifications

❑ <Size><Base format><Number>

❑ 4’b111 //This is a 4-bit binary number

❑ 12’habc //This is a 12-bit hexadecimal number
❑ 16’d255 //This is 16-bit decimal number
❑ 23456 //This is a 32-bit decimal number by default
❑ ‘hc3 //This is a 32-bit hexadecimal number
❑ ‘o21 //This a 32-bit octal number
❑ 1’bx // 1 bit unknown number
❑ 1’bZ // 1 bit high impedance number
❑ 12’b1111_1100_1010 //underscore is just for readability

Dr. Vaishali H. Dhare

 Lexical Conventions

❑ Comments
// Single line comment
/* Another single line comment */
/* Begins multi-line (block) comment
All text within is ignored
Line below ends multi-line comment
*/ This is an illegal comment
/* end with this is also illegal

Dr. Vaishali H. Dhare

Components of SR Latch

Dr. Vaishali H. Dhare

SR Latch

Dr. Vaishali H. Dhare

 SR Latch
//This example illustrates the different components of a
module
//Module name and port list
//SR_latch module
module SR_latch(Q,Qbar,Sbar,Rbar);
//portdeclarations
output Q,Qbar;
input Sbar,Rbar;
//Instantiate lower-level modules
//In this case, instantiate verilog primitive nand gates
//Note, how the wires are connected in a cross-coupled
fashion.
nand n1(Q,Sbar,Qbar);
nand n2(Qbar,Rbar,Q);
//endmodule statement
endmodule Dr. Vaishali H. Dhare
 Ports
❑ Port provides the interface by which
module can communicate

Dr. Vaishali H. Dhare

 Port Declaration

Verilog Keyword Type of Port

input Input Port

output Output Port

inout Bidirectional Port

Dr. Vaishali H. Dhare

Port Connection Rules

Dr. Vaishali H. Dhare

 Port Connection Rules
❑ Inputs
❑ Outputs
❑ Inouts
❑ Width Matching
❑ Unconnected Ports
❑ Fulladd4 fa0(SUM, , A, B, C_IN)//output port
C_out is unconnected

Dr. Vaishali H. Dhare

 Port Connection Rules
❑ Illegal Port Connection
Module Top;
//Declare connection variables
reg[3:0]A,B;
reg C_IN;
reg [3:0]SUM;
wire C_out;
//Instantiate fulladd4,call it fa0
Fulladd4 fa0(SUM,C_OUT,A,B,C_IN);
//Illegal connection because output port sum in
module fulladd4 is connected to a register variable
SUM in module Top.

Dr. Vaishali H. Dhare

Dr. Vaishali H. Dhare