SOME IMPORTANT QUESTIONS OF COMPUTER ARCHITECTURE.

COMPUTER ARCHITECTURE PORTION

1. Show the block diagram of the hardware that implements the following register transfer
statement:
a. 𝑦𝑇2 : 𝑅2 ← 𝑅1 , 𝑅1 ← 𝑅2
b. 𝑥 + 𝑦𝑧: 𝐴𝑅 ← 𝐴𝑅 + 𝐵𝑅
2. A digital computer has a common bus system for 16 registers of 32 bits each. The bus is
constructed with multiplexers.
a. How many selections lines are there in each multiplexers?
b. What size of multiplexers are needed?
c. How many multiplexers are there in the bus?
3. Define micro-operation. Explain the different types of micro-operation. The following
transfer statements specify a memory. Explain the memory operation in each case.
a. 𝑅2 ← 𝑀[𝐴𝑅]
b. M[AR] ← 𝑅3
4. The 8-bits register AR, BR, CR and DR initially have the following values:
AR= 11110010 CR= 10111001
BR= 11111111 DR= 11101010
Determine the 8-bit values in each registers after the execution of the following sequence of
micro-operations.
AR ← 𝐴𝑅 + 𝐵𝑅
CR ← 𝐶𝑅 𝛬 𝐷𝑅, 𝐵𝑅 ← 𝐵𝑅 + 1
AR ← 𝐴𝑅 − 𝐶𝑅
5. An 8-bit register contains the binary value R=10011101, determine the sequence of
binary values in R after logical shift-left, followed by a circular shift-right, followed by a
logical shift-right and a circular shift-left.
6. An 8-bit register contains the binary value 1101110. What is the register value after an
arithmetic shift right? Starting from the initial number 1101110, determine the register
value after an arithmetic shift left, and state whether there is an overflow.
7. Explain different micro-operation.
8. How do you detect overflow while adding 2’s complement data?
9. Convert the 5 bit opcode to 9 bit microinstruction address using maping procedure that
provides eight consecutive microinstructions for each routine.
10. What is the use of CAR ?
11. In which address mode the content of program counter is added to the address part of the
instruction in order to obtain the effective address?
12. Define micro-program control unit. What is the advantages of using floating point
representation?
13. What is meant by pipelining? List the different conflicts that will arise in pipelining.
14. Discuss the instruction cycle of a basic computer.
15. Differentiate between strobe and handshaking.
16. Define locality of reference.
17. What is associative memory?
18. What is the size of data in 8085 microprocessor?
19. What is the maximum address of 8085 microprocessor and what is the maximum data
size of it?
20. When dose the flags get modified?
21. Explain different types of flags in 8085 microprocessor.
22. Given a register R1 = 11100011, determine the value of R1 after execution of following
micro-operations;
a. 𝑅1 ← CIL(R1)
b. 𝑅1 ← ASHR(R1)
c. 𝑅1 ← SHL(R1)
23. A basic computer has an instruction format as follows,
a. Determine the memory size and its data bits for the computer.
b. How many registers does the computer has?
I Opcode =3 bits Register code=4 bits Address =16 bits
24. What is stored program organization?
25. What is the difference between a direct and an indirect address instruction? How many
references to memory are needed for each type of instruction to bring an operand into a
processor register?
26. Design an accumulator logic circuit.
27. A computer uses a memory unit with 256K words of 32 bits each. A binary instruction
code is stored in one memory. The instruction has four parts; an indirect bit, an operation
code, a register code part to specify one of 64 registers and an address part?
a. How many bits are there in the operation code, the register code part, and the
address part?
b. Draw the instruction word format and indicate the number of bits in each part.
c. How many bits are there in the data and address input of the memory?
28. Explain different types of instruction format of basic computer.
29. List the components of CPU. Explain how CPU can be organized into different
organization.
30. Explain the general register organization of CPU.
31. Define control word.
32. When can you say that set of instructions are completed?
33. Explain how CPU can be classified into different organization.
34. Complete the following table
CPU Organization Instruction Address Format
Single Accumulator
General Register
Stack
35. Complete the following table
 Instruction CPU organization Used
MOV R1,R2
ADD B
ADD
PUSH X
ADD X,R1,R3
LOAD X
STOR X
36. Evaluate the arithmetic expression; X=(A+B)*(C-D) using
a. Zero address instruction format (Stack Organized CPU)
b. One address instruction format (Single Accumulator Organized CPU)
c. Three address instruction format (General Register Organized CPU)
d. Two address instruction format (General Register Organized CPU)
37. An instruction is stored at location 300 with its address fields at location 301. The address
field has the value 400. A processor register R1 contain the number 200. Evaluate the
effective address if the addressing mode of the instruction is (a) Direct (b) Immediate (c)
Relative (d) Register Indirect (e) Index with R1 as the Index register.
38. How effective address is computed in different addressing modes.
C(D−F)
39. Evaluate the arithmetic statement X== A + G
a. 1-address c. 3-address
b. 2- address d. 0-addres
A D
40. Evaluate arithmetic expression; X = B + C ∗ E using

a. 1-address c. 3-address
b. 2- address d. 0-address

41. Write a program to evaluate the arithmetic statement with zero, one, two and three
address instruction.
𝐴−𝐵+𝐶
𝑋=
𝐺+𝐻∗𝐾
42. RISC Vs CISC
43. Explain register transfer language with suitable example.
44. Differentiate between restoring and non-restoring division algorithm.
45. What do you mean by pipeline? Explain with space diagram for the six segment pipeline
showing the time it takes to process eight tasks.
46. Draw a space-time diagram for a six segment pipeline showing the time it takes to
process eight tasks. Also draw the pipe line structure.
47. In certain scientific computations it is necessary to perform the arithmetic operation
(Ai + Bi)(Ci + Di) with stream of numbers. Specify a pipeline configuration to carry out
this task. List the contents of all registers in the pipeline for i=1 to 6.
48. Determine the number of clock cycles that it takes to process 200 tasks in a six segment
pipeline.
49. A non-pipeline system takes 50 ns to process a task. The same task can be processed in a
six segment pipeline with a clock cycle of 10 ns. Determine the speedup ratio of the
pipeline for 100 tasks. What is the maximum speedup that can be achieved?
50. The time delay of the four segments in the pipeline are as follows;;
t1=50 ns, t2= 30 ns, t3= 95 ns and t4= 45 ns. The interface registers delay time tr= 5 ns.
a. How long would it take to add 100 pairs of numbers in the pipeline?
b. Determine the speedup factor for the system.
51. Define parallel processing. How parallel processing can be implemented?
52. Explain the speed up factor enhance processing speed and derive its expression.
53. Explain Booth multiplication algorithm with hardware implementation diagram. Multiply
(-4) x (-3) using Booth multiplication algorithm.
54. How performance of computer is increased using pipeline. Explain with practical
example.
55. Perform 10/3 using restoring and non-restoring algorithm division method.
MEMORY MANAGEMENT
56. Consider a direct mapped cache of size 16 KB with block size 256 bytes. The size of
main memory is 128 KB. Find-
a. Number of bits in tag
b. Tag directory size
57. Consider a direct mapped cache of size 512 KB with block size 1 KB. There are 7 bits in
the tag. Find-
a. Size of main memory
b. Tag directory size
58. Consider a direct mapped cache with block size 4 KB. The size of main memory is 16
GB and there are 10 bits in the tag. Find-
a. Size of cache memory
b. Tag directory size
59. Consider a direct mapped cache of size 32 KB with block size 32 bytes. The CPU
generates 32 bit addresses. Determine the number of bits needed for cache indexing and
the number of tag bits.
60. Consider a machine with a byte addressable main memory of 232 bytes divided into
blocks of size 32 bytes. Assume that a direct mapped cache having 512 cache lines is
used with this machine. The size of the tag field in bits is
61. A block-set associative cache memory consists of 128 blocks divided into four block sets.
The main memory consists of 16,384 blocks and each block contains 256 eight bit words.
a. How many bits are required for addressing the main memory?
b. How many bits are needed to represent the TAG, SET and WORD fields?
62. A 4-way set associative cache memory unit with a capacity of 16 KB is built using a
block size of 8 words. The word length is 32 bits. The size of the physical address space
is 4 GB. What is the number of bits for the TAG field?
63. What is the purpose of strobe pulse in asynchronous data transfer? Explain how
handshaking method resolve the problems in strobe control method.
 64. Explain IOP. What is the advantages of DMA over other I/O transfer method? Explain
DMA transfer with diagram

Locality of reference :-
It refers to a phenomenon in which a computer program tends to access same set of memory
locations for a particular time period. In other words, Locality of Reference refers to the
tendency of the computer program to access instructions whose addresses are near one another.
Associative memory:-
Also called as content addressable memory (CAM), associative storage, or associative array.
Associative memory refers to a memory organization in which the memory is accessed by its
content.
It is a special type of computer used in certain very high speed searching application. Associative
memories are used in applications where the search time is very critical and short.
In CAM, the user supplies a data word and then CAM searches its entire memory to see if that
data word is stored anywhere in it. If the data is found, the CAM returns a list of one or more
storage addresses where the word was found

Address space vs. memory space

The addresses programmers use are called virtual addresses. A set of these virtual addresses is
called address space.

The place where the address was saved in the main memory is known as the location. A group of
locations is called memory space.