Srinivas Institute of Management Studies

Pandeshwar, Mangalore – 575 001

BACKGROUND STUDY MATERIAL

MICROPROCESSORS
BCA III Semester

Compiled by
Prof . Sridhara Acharya
SIMS, Mangalore
--------------
2015-2016
Srinivas Institute of Management Studies III Sem BCA

MICROPROCESSORS
Contents
Unit 1
Chapter 1. INTRODUCTION AND ARCHITECTURE OF 8086
1.1 Historical evaluation of microprocessors
1.2 Microprocessor based computer system
1.3 Computer data formats
1.4 Assignment Questions.
Chapter 2. INTERNAL MICROPROCESSOR ARCHITECTURE
2.1 The Programming model
2.2 Different types of registers
2.3 flags
2.4 Segment registers
2.5 Assembler directives.
2.6 Assignment Questions

Unit 2
Chapter 3. ADDRESSING MODES
3.1 Data Movement Instructions
3.1.1 Register
3.1.2 Immediate
3.1.3 Direct
3.1.4 Register Indirect
3.1.5 Base plus Index
3.1.6 Register relative
3.1.7 Base relative plus Index
3.2 Program memory addressing modes
3.3 Stack memory addressing modes
3.4 Segment override prefix

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3.5 Assignment Questions.

Chapter 4. DATA TRANSFER INSTRUCTIONS.
4.1 Various types of MOV instructions.
4.2 PUSH and POP
4.3 LEA LDS and LES
4.4 String transfer instructions
4.4.1 MOVS
4.4.2 LODS
4.4.3 STOS
4.4.4 INS
4.4.5 OUTS
4.5 Assignment Questions

Unit 3
Chapter 5. INSTRUCTION SETS
5.1 Miscellaneous data transfer instructions
5.1.1 XCHG
5.1.2 XLAT
5.1.3 IN and OUT
5.2 Arithmetic and logic instructions
5.2.1 ADD
5.2.2 ADC
5.2.3 SUB
5.2.4 SBB
5.2.5 MUL and IMUL
5.2.6 DIV and IDIV
5.2.7 CMP
5.2.8 TEST

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5.3 BCD arithmetic instructions

5.3.1 DAA
5.3.2 DAS
5.4 ASCII arithmetic instructions
5.4.1 AAA
5.4.2 AAS
5.4.3 AAM
5.4.4 AAD
5.5 Basic Logic instructions
5.5.1 OR
5.5.2 AND
5.5.3 NOT
5.5.4 XOR
5.6 Shift and Rotate instructions
5.6.1 SHL/SAL
5.6.2 SHR
5.6.3 SAR
5.6.4 ROL
5.6.5 ROR
5.6.6 RCL
5.6.7 RCR
5.7 String comparison Instructions
5.7.1 CMPS
5.7.2 SCAS
5.8 Assignment Questions.
Chapter 6 JUMP INSTRUCTIONS
6.1 Unconditional jump instructions
6.2 Conditional jump instructions
6.3 Assignment Questions

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Chapter 7. LOOP INSTRUCTIONS IN MASM 6.X

7.1 Do-while Loop

7.2 Repeat until
7.3 Assignment Questions

Unit 4
Chapter 8. PROCEDURES
8.1 Procedures and parameter passing
8.2 CALL instructions
8.3 RET instructions
8.4 Assignment Questions.
Chapter 9. INTRODUCTION TO INTERRUPTS

9.1 What are interrupts

9.2 Interrupt Vectors
9.3 Interrupt instructions
9.4 Controlling the interrupt flag bit and carry flag bit
9.5 WAIT, HLT, NOP, LOCK, ESC, BOUND, ENTER and LEAVE
9.6 Assignment Questions
Chapter 10. INTRODUCTION AND OVER VIEW OF MICROCONTROLLERS.

10.1Introduction to microcontrollers
10.2 Overview of microcontrollers
10.3 Assignment Questions
Chapter 11 VALUE ADDED CHAPTER.
11.1 Introduction to 80386 Processor

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CHAPTER 1.
INTRODUCTION AND ARCHITECTURE OF 8086
1.1 Historical evaluation of microprocessors
In this a brief history of the computer from the mechanical age to the modern processors are
explained. Here the detailed discussion on various types of processors are given.

The Mechanical age

The idea of a computing system was somewhere around 500 B.C. when the Babylonians
invented the abacus, the first mechanical calculator. The abacus, which used strings of beads to
perform calculations, was used by the ancient Babylonian priests to keep track of their vast
storehouses of grain. The abacus, which was used extensively and is still in use today. The
development in the calculating machine was not improved until 1642, when mathematician
Blaise Pascal invented a calculator that was constructed of gears and wheels. Each gear
contained 10 teeth that, when moved one complete revolution, advanced a second gear one place.
This principle can be seen today in an odometer of a vehicle and is the basis of all mechanical
calculators. The arrival of the first practical geared, mechanical machines used to automatically
compute information dates to the early l800s.
In 1823 Charles Babbage was commissioned by the Royal Astronomical society of Great Britain
to produce a programmable calculating machine. This machine was to generate navigational
tables for the Royal Navy. He accepted the challenge and began to create the same. Later he
called it by the name Analytical Engine. This engine was a mechanical computer that stored
1000 20-digit decimal numbers and a variable program that could modify the function of the
machine to perform various calculating tasks. Input to his engine was through punched cards,
The punched card was an invention of Joseph Jacquard, a Frenchman who used punched cards as
input to a weaving machine he invented in 1801, which is today called Jacquard's loom.
Jacquard's loom used punched cards to select intricate weaving patterns in the cloth that it
produced. The Analytical Engine required more than 50,000 machined parts, which could not be
made with enough precision to allow his engine to function reliably.

The Electrical age

The l800s saw the advent of the electric motor with it came a multitude of motor-driven adding
machines, all based on the mechanical calculator developed by Blaise Pascal. These electrically
driven mechanical calculators were common pieces of office equipments until early 1970s, when
the small hand-held electronic calculator, first introduced by Bomar, appeared. Monroe was also
a leading pioneer of electronic calculators, but its machines were desktop, four-function models
the size of cash registers.
In 1889, Herman Hollerith developed the punched card for storing data. Like Babbage, he too
borrowed the idea of a punched card from Jacquard. He also developed a mechanical machine
driven by one of the new electric motors-that counted, sorted, and collated information stored on
punched cards. The idea of calculating by machinery intrigued the United States government so
much that Hollerith was commissioned to use his punched-card system to store and tabulate
information for the 1890 census.

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In 1896, Hollerith formed a company called the Tabulating Machine Company, which developed
a line of machines that used punched cards for tabulation. After a number of mergers, the
Tabulating Machine Company was formed into the International Business Machines
Corporation, now referred to more commonly as IBM, Inc. The punched cards used in
computer systems are often called Hollerith cards, in honor of Herman Hollerith. The 12-bit code
used on a punched card is called the Hollerith code.
Mechanical machines driven by electrical motors continued to dominate the information
processing world until the construction of the first electronic calculating machine in 1941 by a
German inventor named Konrad Zuse. He called that computer with the name Z3. The Z3 was
used in aircraft and missile design during World War II for the German war effort.
This first electronic computing system, which used vacuum tubes, was invented by Alan Turing.
Turing called his machine Colossus, probably because of its size. A problem with Colossus was
that although its design allowed it to break secret German military codes generated by the
mechanical Enigma machine, it could not solve other problems. Colossus was not
programmable-it was a fixed-program computer system, which today is often called a special
purpose computer.
The first general-purpose, programmable electronic computer system was developed in 1946 at
the University of Pennsylvania. This first modem computer was called the ENIAC (Electronics
Numerical Integrator and Calculator). The ENIAC was a huge machine, containing over
17,000 vacuum tubes and over 500 miles of wires. This massive machine weighed over 30 tons,
yet performed only about 100,000 operations per second. The ENIAC thrust the world into the
age of electronic computers. The ENIAC was programmed by rewiring its circuits-a process that
took many workers several days to accomplish. The workers changed the electrical connections
on plug-boards that looked like early telephone switchboards. Another problem with the ENIAC
was the life of the vacuum tube components, which required frequent maintenance.
Breakthroughs that followed were the development of the transistor in 1948 at Bell Labs,
followed by the 1958 invention of the integrated circuit by Jack Kilby of Texas Instruments. The
integrated circuit led to the development of digital integrated circuits (RTL, or resistor-to-
transistor logic) in the 1960s and the first microprocessor at Intel Corporation in 1971. At that
time, Intel and one of its engineers, Marcian E. Hoff, developed the 4004 microprocessor-the
device that started the microprocessor revolution that continues today at an ever-accelerating
pace.

Programming Advancements
Now that programmable machines were developed, programs and programming languages began
to appear. As mentioned earlier, the first programmable electronic computer system was
programmed by rewiring its circuits. Because this proved too cumbersome for practical
application, early in the evolution of computer systems, computer languages began to appear in
order to control the computer. The first such language, machine language, was constructed of
ones and zeros using binary codes that were stored in the computer memory system as groups of
instructions called programs. This was more efficient than rewiring a machine to program it, but
it was still extremely time consuming to develop a program because of the sheer number of
codes that were required. Mathematician John von Neumann was the first person to develop a
system that accepted instructions and stored them in memory. Computers are often called yon
Neumann machines in honor of John von Neumann.

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Once computer systems such as the UNIVAC became available in the early 1950s, assembly
language was used to simplify the chore of entering binary code into a computer as its
instructions. The assembler allowed the programmer to use mnemonic codes, such as ADD for
addition, in place of a binary number such as 01000111. Although assembly language was an aid
to programming, it wasn't until 1957, when Grace Hopper developed the first high-level
programming language called FLOW-MATIC, that computers became easier to program. In the
same year, IBM developed FORTRAN (FORmula TRANslator) for its computer systems. The
FORTRAN language allowed programmers to develop programs that used formulas to solve
mathematical problems. Note that FORTRAN is still used by some scientists for computer
programming. Another similar language, introduced abouta year after FORTRAN, was ALGOL
(ALGOrithmic Language).
The first truly successful and widespread programming language for business applications was
COBOL (Computer Business Oriented Language). Although COBOL usage has diminished
somewhat in recent years, it is still a major player in many large business systems. Another once-
popular business language is RPG (Report Program Generator), which allows programming by
specifying the form of the input, output, and calculations. Since these early days of
programming, additional languages have appeared. Some of the more common are BASIC,
C/C++, PASCAL, and ADA. The BASIC and PASCAL languages were both designed as
teaching languages, but have escaped the classroom and are used in many computer systems. The
BASIC language is probably the easiest of all to learn. Some estimates indicate that the BASIC
language is used in the personal computer for 80 percent of the programs written by users.
Recently, a new version of BASIC, VISUAL BASIC, has made programming in the WINDOWS
environment easier. The VISUAL BASIC language may eventually supplant C/C++ and
PASCAL.
In the scientific community, C/C++ and (occasionally) PASCAL appear as control programs.
Both languages, especially C/C++, allow the programmer almost complete control over the
programming environment and computer system. In many cases, C/C++ is replacing some of the
low-level, machine control software normally reserved for assembly language. Even so,
assembly language still plays an important role in programming. Most video games written for
the personal computer are written almost exclusively in assembly language. Assembly language
is also interspersed with C/C++ and PASCAL to perform machine control functions efficiently.
The ADA language is used heavily by the Department of Defense. The ADA language was
named in honor of Augusta Ada Byron, Countess of Lovelace. The Countess worked with
Charles Babbage in the early 1800s in the development of his Analytical Engine.

The Microprocessor Age

The world's first microprocessor, the Intel 4004, was a 4-bit microprocessor-a programmable
controller on a chip. It addressed a mere 4096 4-bit wide memory locations. (A bit is a binary
digit with a value of one or zero. A 4-bit wide memory location is often called a nibble.) The
4004 instruction set contained only 45 instructions. It was fabricated with the then-current state-
of-the-art P-channel MOSFET technology that only allowed it to execute instructions at the slow
rate of 50 KIPs (kilo-instructions per second). This was slow when compared to the 100,000
instructions executed per second by the 30-ton ENIAC computer in 1946. The main difference
was that the 4004 weighed much less than an ounce.

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At first, applications abounded for this device. The 4-bit microprocessor debuted in early video
game systems and small microprocessor-based control systems. One such early video game, a
shuffleboard game, was produced by Balley. The main problems with this early microprocessor
were its speed, word width, and memory size. The evolution of the 4-bit microprocessor ended
when Intel released the 4040, an updated version of the earlier 4004. The 4040 operated at a
higher speed, although it lacked improvements in word width and memory size.
Other companies, particularly Texas Instruments (TMS-1000), also produced 4-bit
microprocessors. The 4-bit microprocessor still survives in low-end applications such as
microwave ovens and small control systems, and is still available from some microprocessor
manufacturers Most calculators are still based on 4-bit microprocessors that process 4-bit BCD
(binary-coded decimal) codes.
Later in 1971, realizing that the microprocessor was a commercially viable product, Intel
Corporation released the 8008-an extended 8-bit version of the 4004 microprocessor. The 8008
addressed an expanded memory size (16K bytes) and contained additional instructions (a total of
48) that provided an opportunity for its application in more advanced systems. (A byte is
generally an 8-bit wide binary number and a K is 1024. Often, memory size is specified in K
bytes.)
As engineers developed more demanding uses for the 8008 microprocessor, they discovered that
its somewhat small memory size, slow speed, and instruction set limited its usefulness. Intel
recognized these limitations and introduced the 8080 microprocessor in 1973-the first of the
modem 8-bit microprocessors. About six months after Intel released the 8080 microprocessor,
Motorola Corporation introduced its MC6800 microprocessor. The floodgates opened and the
8080 and, to a lesser degree, the MC6800 ushered in the age of the microprocessor. Soon, other
companies began to introduce their own versions of the 8-bit microprocessor.

Special features of 8080

The 8080 processor executes the instructions 10 time faster than 8008 The execution speed of
8080 was 2µs. (500,000 instructions per second). Also, the 8080 was compatible with TIL
(transistor-transistor logic), whereas the 8008 was not directly compatible. This made interfacing
much easier and less expensive. The 8080 also addressed four times more memory (64K bytes)
than the 8008 (16K bytes). These improvements are responsible for ushering in the era of the
8080 and the continuing saga of the microprocessor. Incidentally, the first personal computer, the
MITS Altair 8800, was released in 1974. (Note that the number 8800 was probably chosen to
avoid copyright violations with Intel.) The BASIC language interpreter, written for the Altair
8800 computer, was developed by Bill Gates, the founder of Microsoft Corporation. The
assembler program for the Altair 8800 was written by Digital Research Corporation, which once
produced DR-DOS for the personal computer.
The 8085 Microprocessor. In 1977, Intel Corporation introduced an updated version of the 8080-
the 8085. This was to be the last 8-bit, general-purpose microprocessor developed by Intel.
Although only slightly more advanced than an 8080 microprocessor, the 8085 executed software
at an even higher speed. An addition that took 2.0µs (500,000 instructions per second) on the
8080 required only 1.3 µs (769, 230 instructions per second) on the 8085. The main advantages
of the 8085 were its internal clock generator, internal system controller, and higher clock
frequency. This higher level of component integration reduced the 8085's cost and increased its
usefulness. Intel has managed to sell well over 100 million copies of the 8085 microprocessor, its
most successful 8-bit, general-purpose microprocessor. Because the 8085 is also manufactured
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(second-sourced) by many other companies, there are over 200 million of these microprocessors
in existence. Applications that contain the 8085 will likely continue to be popular well into the
future. Another company that sold 500 million 8-bit microprocessors is Zilog Corporation, which
produced the Z-80 microprocessor. The Z-80 is machine language code-compatible with the
8085, which means that there are over 700 million microprocessors that execute 8085/Z-80
compatible code!

The Modern Microprocessor

In 1978, Intel released the 8086 microprocessor; a year or so later, it released the 8088. Both
devices are 16-bit microprocessor which execute instructions in as link as 400 ns (2:5MIPs, or
2.5 millions of instructions per second). This represented a major improvement over the
execution speed of the 8085. In addition, the 8086 and 8088 addressed 1M bytes of memory,
which was 16 times more memory than the 8085. (A 1M byte memory contains 1024K byte-
sized memory locations, or 1,048,576 bytes.) This higher execution speed and larger memory
size allowed the 8086 and 8088 to replace smaller minicomputers in many applications. One
other feature found in the 8086/8088 was a small 4- or 6-byte instruction cache or queue that
prefetched a few instructions before they were executed. The queue sped the operation of many
sequences of instructions and proved to be the basis for the much larger instruction caches found
in modem microprocessors.
The increased memory size and additional instructions in the 8086 and 8088 have led to many
sophisticated applications for microprocessors. Improvements to the instruction set included a
multiply-and-divide instruction, which was missing on earlier microprocessors. In addition, the
number of instructions increased from 45 on the 4004, to 246 on the 8085, to well over 20,000
variations on the 8086 and 8088 microprocessors. Note that these microprocessors were called
CISC (complex instruction set computers) because of the number and complexity of instructions.
The additional instructions eased the task of developing efficient and sophisticated applications,
even though the number of instructions was at first overwhelming and time-consuming to learn.
The 16-bit microprocessor also provided more internal register storage space than the 8-bit
microprocessor. The additional registers allowed software to be written more efficiently.
The 16-bit microprocessor evolved mainly because of the need for larger memory systems. The
popularity of the Intel family was ensured in 1981, when IBM Corporation decided to use the
8088 microprocessor in its personal computer. Applications such as spreadsheets, word
processors, spelling checkers, and computer-based thesauruses were memory-intensive and
required more than the 64K bytes of memory found in 8-bit microprocessors to execute
efficiently. The 16-bit 8086 and 8088 provided 1M bytes of memory for these applications.
Soon, even the 1M byte memory system proved limiting for large databases and other
applications. This led Intel to introduce the 80286 microprocessor, an updated 8086, in 1983.
The 80286 Microprocessor.
The 80286 microprocessor (also a 16-bit architecture microprocessor) was almost identical to
the 8086 and 8088, except it addressed a 16M byte memory system instead of a 1M byte system.
The instruction set of the 80286 was almost identical to the 8086 and 8088, except for a few
additional instructions that managed the extra 15M bytes of memory. The clock speed of the
80286 was increased, so it executed some instructions in as little as 250 ns (4.0 MIPs) with the
original release 8.0 MHz version. Some changes also occurred in the internal execution of the
instructions, which led to an eight-fold increase in speed for many instructions when compared
to 8086/8088 instructions.
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The 32-bit Microprocessor.

Applications began to demand faster microprocessor speeds, more memory, and wider data
paths. This led to the arrival of the 80386 in 1986, by Intel Corporation. The 80386 represented a
major overhaul of the 16-bit 8086-80286 architecture. The 80386 was Intel's first practical 32 bit
microprocessor that contained a 32-bit data bus and a 32-bit memory address. (Note that Intel
produced an earlier, although unsuccessful, 32-bit microprocessor called the iapx-432.) Through
these 32-bit buses, the 80386 addressed up to 4G bytes of memory. (IG of memory contains
1024M, or 1,073,741,824 locations.) A 4G byte memory can store an astounding 1,000,000
typewritten, double-spaced pages of ASCII text data. The 80386,was available in a few modified
versions such as the 80386SX, which addressed 16M bytes of memory through a 16-bit data and
24-bit address bus, and the 80386SU80386SLC, which addressed 32M bytes of memory through
a 16-bit data and 25-bit address bus. An 80386SLC version contained an internal cache memory
that allowed it to process data at even higher rates. In 1995, Intel released the 80386EX
microprocessor. The 80386EX microprocessor is called an embedded PC because it contains all
the components of the AT class personal computer on a single integrated circuit.
The 80386EX also contains 24 lines for input/output data, a 26-bit address bus, a 16-bit data bus,
a DRAM refresh controller, and programmable chip selection logic. Applications that require
higher microprocessor speeds and large memory systems include software systems that use a
Gill, or graphical user interface. Modem graphical displays often contain 256,000 or more
picture elements (pixels, or pels). The least sophisticated VGA (variable graphics array) video
display has a resolution of 640 pixels per scanning line with 480 scanning lines. To display one
screen of information, each picture element must be changed, which requires a high-speed
microprocessor. Many new software packages use this type of video interface. These Gill-based
packages require high microprocessor speeds and accelerated video adapters for quick and
efficient manipulation of video text and graphical data. The most striking system, which requires
high-speed computing for its graphical display interface, is Microsoft Corporation's Windows.3
We often call a GUI a WYSIWYG (what you see is what you get) display.
The 32-bit microprocessor is needed because of the size of its data bus, which transfers real
(single-precision floating-point) numbers that require 32-bit wide memory. In order to efficiently
process 32-bit real numbers, the microprocessor must efficiently pass them between itself and
memory. If the numbers pass through an 8-bit data bus, it takes four read or write cycles; when
passed through a 32-bit data bus, however, only one read or write cycle is required. This
significantly increases the speed of any program that manipulates real numbers. Most high level
languages, spreadsheets, and database management systems use real numbers for data storage.
Real numbers are also used in graphical design packages that use vectors to plot images on the
video screen. These include such CAD (computer aided drafting/design) systems as AUTOCAD,
ORCAD, and so forth.
Besides providing higher clocking speeds, the 80386 included a memory management unit that
allowed memory resources to be allocated and managed by the operating system. Earlier
microprocessors left memory management completely to the software. The 80386 included
hardware circuitry for memory management and memory assignment, which improved its
efficiency and reduced software overhead. The instruction set of the 80386 microprocessor was
upward-compatible with the earlier 8086, 8088, and 80286 microprocessors. Additional
instructions referenced the 32-bit registers and managed the memory system.Note that memory
management instructions and techniques used by the 80286 were also compatible with the 80386

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microprocessor. These features allowed older, 16-bit software to operate on the 80386
microprocessor.

The80486 Microprocessor.
In 1989, Intel released the 80486 microprocessor, which incorporated an 80386-like
microprocessor, an 80387-like numeric coprocessor, and an 8K byte cache memory system into
one integrated package. Although the 80486 microprocessor was not radically different from the
80386, it did include one substantial change. The internal structure of the 80486 was modified
from the 80386 so that about half of its instructions executed in one clock instead of two clocks.
Because the 80486 was available in a 50 MHz version, about half of the instructions executed is
50 MIPs). The average speed improvement for a typical mix of instructions was about 50 percent
over the 80386 that operated at the same clock speed. Later versions of the 80486 executed
instructions at even higher speeds with a 66 MHz double-clocked version (80486DX2). The
double-clocked 66 MHz version executed instructions at the rate of 66 MHz, with memory
transfers executing at the rate of 33 MHz. (This is why it was called a double-clocked
microprocessor.) A triple-clocked version from Intel, the 80486DX4, improved the internal
execution speed to 100MHz with memory transfers at 33 MHz. Note that the 80486DX4
microprocessor executed instructions at about the same speed as the 60 MHz Pentium. It also
contained an expanded 16K byte cache in place of the standard 8K byte cache found on earlier
80486 microprocessors. Advanced Micro Devices (AMD) has produced a triple-clocked version
that runs with a bus speed of 40 MHz and a clock speed of 120 MHz. The future promises to
bring microprocessors that internally execute instructions at rates of up to 1 GHz or higher.
Other versions of the 80486 were called Overdrive4 processors. The Overdrive processor was
actually a double-clocked version of the 80486DX that replaced an 80486SX or slower-speed
80486DX. When the Overdrive processor was plugged into its socket, it disabled or replaced the
80486SX or 80486DX, and functioned as a doubled-clocked version of the microprocessor. For
example, if an 80486SX, operating at 25 MHz, was replaced with an Overdrive microprocessor,
it functioned as an 80486DX2 50 MHz microprocessor using a memory transfer rate of 25 MHz.

The Pentium Microprocessor

The Pentium, introduced in 1993, was similar to the 80386 and 80486 microprocessor. This
microprocessor was originally labeled the P5 or 80586, but Intel decided not to use a number
because it appeared to be impossible to copyright a number. The two introductory versions of the
Pentium operated with a clocking frequency of 60 MHz and 66 MHz, and a speed of 110MIPs,
with a higher-frequency 100MHz one and one-half clocked version that operated at 150 MIPs.
The double-clocked Pentium, operating at 120 MHz and 133MHz, was also available, as were
higher-speed versions. (The fastest version produced by Intel is the 233 MHz Pentium, which is
a three and one-half clocked version.) Another difference was that the cache size was increased
to 16K bytes from the 8K cache found in the basic version of the 80486. The Pentium contained
an 8K byte instruction cache and an 8K byte data cache, which allowed a program that transfers
a large amount of memory data to still benefit from a cache. The memory system contained up to
4G bytes, with the data bus width increased from the 32 bits found in the 80386 and 80486 to a
full 64 bits. The data bus transfer speed was either 60 MHz or 66 MHz, depending on the version
of the Pentium. (Recall that the bus speed of the 80486 was 33 MHz.) This wider data bus width
accommodated double-precision floating-point numbers used for modem high-speed, vector
generated graphical displays. These higher bus speeds should allow virtual reality software to
operate at more realistic rates on current and future Pentium-based platforms. The widened data

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bus and higher execution speed of the Pentium allow full-frame video displays to operate at scan
rates of 30 Hz or higher comparable to commercial television. Recent versions of the Pentium
also included additional instructions, called multimedia extensions, or MMX instructions.
Although Intel hoped that the MMX instructions would be widely used, it appears that few
software companies have used them.
Recently, Intel released the long-awaited Pentium OverDrive (P24T) for older 80486 systems
that operate at either 63 MHz or 83 MHz clock. The 63 MHz version upgrades older 80486DX2
50 MHz systems; the 83 MHz version upgrades the 80486DX2 66 MHz systems. The upgraded
83 MHz system performs at a rate somewhere between a 66 MHz Pentium and a 75 MHz
Pentium. If older VESA local bus video and disk-caching controllers seem too expensive to toss
out, the Pentium OverDrive represents an ideal upgrade path from the 80486 to the Pentium.
Probably the most ingenious feature of the Pentium is its dual integer processors. The Pentium
executes two instructions, which are not dependent on each other, simultaneously because it
contains two independent internal integer processors called superscalar technology. This allows
the Pentium to often execute two instructions per clocking period. Another feature that enhances
performance is a jump prediction technology that speeds the execution of programs that include
loops. As with the 80486, the Pentium also employs an internal floating-point coprocessor to
handle floating-point data, albeit at five times the speed improvement. These features portend
continued success for the Intel family of microprocessors. They also may allow the Pentium to
replace some of the RISC (reduced instruction set computer) machines that currently execute one
instruction per clock. Note that some newer RISC processors execute more than one instruction
per clock through the introduction of superscalar technology. Motorola, Apple, and IBM have
recently produced the PowerPC, a RISC microprocessor that has two integer units and one
floating-point unit. The PowerPC certainly boosts the performance of the Apple Macintosh', but
at present is slow to emulate the Intel family of microprocessors. Tests indicate that the current
emulation software executes DOS and Windows applications at speed slower than the 80486SX
25 MHz microprocessor. Because of this, the Intel family should survive for many years in
personal computer systems. Note that there are currently 6 million Apple Macintosh5 systems
and well over 260 million personal computers based on Intel microprocessors. In 1998, reports
stated that 96 percent of all PCs were shipped with the Windows operating system.
In order to compare the speeds of various microprocessors, Intel devised the iCOMP-rating
index. This index is a composite of SPEC92, ZD Bench, and Power Meter. The iCOMPl rating
was used to rate the speed of all Intel microprocessors through the Pentium. Since the release of
the Pentium Pro and Pentium II, Intel has switched to the iCOMP2 index, which is scaled by a
factor of 10 from the iCOMPl index. A microprocessor with an index of 1000 using iCOMPl is
rated as 100 using iCOMP2. Another difference is the benchmarks used for the scores.
Pentium Pro Processor.
A recent entry from Intel is the Pentium Pro processor, formerly code-named the P6
microprocessor. The Pentium Pro processor contains 21 million transistors, 3 integer units, as
well as a floating point unit to increase the performance of most software. The basic clock
frequency was 150 MHz and 166 MHz in the initial offering made available in late 1995. In
addition to the internal 16K level-one (Ll) cache (8K for data and 8K for instructions), the
Pentium Pro processor also contains a 256K level-two (L2) cache. One other significant change
is that the Pentium Pro processor uses three execution engines, so it can execute up to three
instructions at a time, which can conflict and still execute in parallel. This represents a change

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from the Pentium, which executes two instructions simultaneously as long as they do not
conflict. The Pentium Pro microprocessor is optimized to efficiently execute 32-bit code and is
used in servers. Pentium Pro can address either 4G Byte or 64G Byte memory systems. For
accessing 64G Byte memory Pentium pro can be configured of with 36 bit address lines.

1.2 Microprocessor based computer system

The following figure 1.1(a) and (b) shows the block diagram of the microprocessor based
computer system with various possible input devices and various possible output devices. Also
the system is connected to the memory including RAM and ROM for storage of information.
Input devices are required to give the input in various forms and the output devices give the
output in the form that is more suitable to the user.

memory Processor I/O Devices

RAM 8086
Keyboard
ROM 80286
Mouse
EPROM 80386
Scanner
EEPROM 80486
Display

Figure 1.1(a) Microprocessor based computer system

The bus is a set of common connections that carry the same type of information. There are three types of
buses available in 8086 processor, they are address bus, data bus and control bus.

The data bus is used to carry the data between registers and between memory and registers. The size of
data bus is 16 bit. The address bus is used to locate the memory location in 1 MB of location addressed by
8086 processor. The size of the address bus is 20 bits. The control bus carries various control signals to
registers, memory location, other peripheral devices connected to the processor and all. These control
signals are generated from decoding the instructions. These control signals are actually executing the
instructions. The diagram below shows how the various buses are connected to each other in a processor .

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8086
processor

Address Bus

Data Bus

MIEMRD’

MEMWR’

IORD’

IOWC’

ROM RAM Key board Printer

Figure 1.1(b) Microprocessor based computer system with various buses

The 20 bit address bus is used to identify the location in ROM, RAM, Keyboard and Printer. The ROM is
used only to read the data from itself. So unidirectional data bus is used to read the data from ROM to the
processor. Here the processor can only read the data from ROM but not write the data into ROM.

Using RAM processor can read as well as write the data from the RAM and to the RAM. So the
bidirectional data bus is used to read and write. The key board can give the data to the processor and
processor can send the data to the printer. In order to read the data from ROM and RAM MEMRD’
signal should be 0. Similarly in order to write the data to the RAM MEMWR’ should be 0. To read the
data from the keyboard the IORD’ should be 0. To send the data to the printer the IOWC’ should be 0.
These lines are some examples of the control lines.

1.3 Computer data formats

Successful programming requires a precise understanding of data formats. In this section, many
common computer data formats are described as they are used with the Intel family of
microprocessors. Commonly, data appear as ASCII, BCD, signed and unsigned integers, and
floating-point numbers (real numbers). Other forms are available, but are not presented here
because they are not commonly found.
ASCII (American Standard Code for Information Interchange) data represent alphanumeric
characters in the memory of a computer system . The standard ASCII code is a 7-bit code, with
the eighth and most significant bit used to hold parity in some systems. If ASCII data are used
with a printer, the most significant bits are a 0 for alphanumeric printing and 1 for graphics
printing. In the personal computer, an extended ASCII character set is selected by placing a logic
1 in the left-most bit. The extended ASCII characters store some foreign letters and punctuation,

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Greek characters, mathematical characters, box-drawing characters, and other special characters.
Note that extended characters can vary from one printer to another. The list provided is designed
to be use with the IBM Pro Printer which also matches the special character set found with some
word processors. Table 1.1 shows the characters with the ASCII code.

ASCII
Hex Symbol ASCII Hex Symbol ASCII Hex Symbol ASCII Hex Symbol
0 0 NUL 16 10 DLE 32 20 (space) 48 30 0
1 1 SOH 17 11 DC1 33 21 ! 49 31 1
2 2 STX 18 12 DC2 34 22 " 50 32 2
3 3 ETX 19 13 DC3 35 23 # 51 33 3
4 4 EOT 20 14 DC4 36 24 $ 52 34 4
5 5 ENQ 21 15 NAK 37 25 % 53 35 5
6 6 ACK 22 16 SYN 38 26 & 54 36 6
7 7 BEL 23 17 ETB 39 27 ' 55 37 7
8 8 BS 24 18 CAN 40 28 ( 56 38 8
9 9 TAB 25 19 EM 41 29 ) 57 39 9
10 A LF 26 1A SUB 42 2A * 58 3A :
11 B VT 27 1B ESC 43 2B + 59 3B ;
12 C FF 28 1C FS 44 2C , 60 3C <
13 D CR 29 1D GS 45 2D - 61 3D =
14 E SO 30 1E RS 46 2E . 62 3E >
15 F SI 31 1F US 47 2F / 63 3F ?

ASCII Hex Symbol ASCII Hex Symbol ASCII Hex Symbol ASCII Hex Symbol
64 40 @ 80 50 P 96 60 ` 112 70 p
65 41 A 81 51 Q 97 61 a 113 71 q
66 42 B 82 52 R 98 62 b 114 72 r
67 43 C 83 53 S 99 63 c 115 73 s
68 44 D 84 54 T 100 64 d 116 74 t
69 45 E 85 55 U 101 65 e 117 75 u
70 46 F 86 56 V 102 66 f 118 76 v
71 47 G 87 57 W 103 67 g 119 77 w
72 48 H 88 58 X 104 68 h 120 78 x
73 49 I 89 59 Y 105 69 i 121 79 y
74 4A J 90 5A Z 106 6A j 122 7A z
75 4B K 91 5B [ 107 6B k 123 7B {
76 4C L 92 5C \ 108 6C l 124 7C |
77 4D M 93 5D ] 109 6D m 125 7D }
78 4E N 94 5E ^ 110 6E n 126 7E ~
79 4F O 95 5F _ 111 6F o 127 7F 

Table 1.1 ASCII characters.

BCD (Binary Coded Decimal) Data

Binary-coded decimal (BCD) information is stored in either packed or unpacked forms. Packed
BCD data are stored as two digits per byte and unpacked BCD data are stored as one digit per
byte. The range of a BCD digit extends from 00002 to 10012, or 0-9 decimal. Unpacked BCD
data are returned from a keypad or keyboard.
Packed BCD data are used for some of the instructions included for BCD addition and
subtraction in the instruction set of the microprocessor. Table 1-2 shows some decimal numbers
converted to both the packed and unpacked BCD forms. Applications that require BCD data are
point-of-sales terminals and almost any device that performs a minimal amount of simple
arithmetic. If a system requires complex arithmetic, BCD data are seldom used because there is
no simple and efficient method of performing complex BCD arithmetic.

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Decimal Packed Unpacked

12 0001 0010 0000 0001 0000 0010

623 0000 0110 0010 0011 0000011000000010 00000011

910 0000 1001 0001 0000 00001001000000010000 0000

Table 1.1 Packed and Unpacked BCD data

Byte-Sized Data
Byte-sized data are stored as unsigned and signed integers. Figure 1-2 illustrates both the
unsigned and signed forms of the byte-sized integer. The difference in these forms is the weight
of the leftmost bit position. Its value is 128 for the unsigned integer and minus 128 for the signed
integer. In the signed integer format, the leftmost bit represents the sign bit of the number, as
well as a weight of minus 128. For example, an 80H represents a value of 128 as an unsigned
number; as a signed number, it represents a value of minus 128. Unsigned integers range in value
from OOH-FFH (0-255). Signed integers range in value from -128 to 0 to +127.

Figure 1.2 The unsigned and signed bytes illustrating the weights of each binary-bit position.
Although negative signed numbers are represented in this way, they are stored in the two's
complement form. The method of evaluating a signed number by using the weights of each bit
position is much easier than the act of two's complementing a number to find its value. This is
especially true in the world of calculators designed for programmers.
Whenever a number is two's complemented, its sign changes from negative to positive or
positive to negative. For example, the number 00001000 is a +8. Its negative value (-8) is found
by two's complementing the +8. To form a two's complement, first one's complement the
number. To one's complement a number, invert each bit of a number from zero to one or from
one to zero. Once the one's complement is formed, the two's complement is found by adding a
one to the one's complement.

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Word-Sized Data
A word (l6-bits) is formed with two bytes of data. The least significant byte is always stored in
the lowest-numbered memory location, and the most significant byte is stored in the highest.
This method of storing a number is called the little endian format. An alternate method, not used
with the Intel family of microprocessors, is called the big endian format. In the big endian
format, numbers are stored with the lowest location containing the most significant data. The big
endian format is used with the Motorola family of microprocessors. Figure 1-3 shows the
weights of each bit position in a word of data, and Figure 1-4 shows how the number l234H
appears when stored in the memory location 3000H and 3001H. The only difference between a
signed and an unsigned word is the leftmost bit position. In the unsigned form, the leftmost bit is
unsigned; in the signed form, its weight is a -32,768. As with byte-sized signed data, the signed
word is in two's complement form when representing a negative number. Also, notice that the
low-order byte is stored in the lowest-numbered memory location (3000H) and the high-order
byte is stored in the highest-numbered location (3001H).

Fig 1.3 unsigned word

Figure 1.4 The contents of the memory location 3000H and 3001H with 1234H

Doubleword –Sized Data

Doubleword-sized data requires four bytes of memory because it is a 32-bit number. Doubleword
data appear as a product after a multiplication and also as a dividend before a division. In the
80386 through the Pentium 4, memory and registers are also 32 bits in width. Figure 1-5 shows
the form used to store doublewords in the memory and the binary weights of each bit position .
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Figure 1.5 unsigned Double word

Figure 1.6 The contents of the memory location 00100H to 001003H with 12345678H
When a doubleword is stored in memory, its least significant byte is stored in the lowest-
numbered memory location, and its most significant byte is stored in the highest-numbered
memory location using the little endian format. Recall that this is also true for word-sized data.
For example, a l2345678H that is stored in memory location 00100H-00103H is stored with the
78H in memory location 00l00H, the 56H in location 00101H, the 34H in location 00102H, and
the 12H in location 00103H.

Real Numbers
Because many high-level languages use the Intel family of microprocessors, real numbers are
often encountered. A real number, or a floating-point number, as it is often called, contains two
parts: a mantissa, significant, or fraction; and an exponent. Figure 1-7 depicts both the 4- and 8-
byte forms of real numbers as they are stored in any Intel system. Note that the 4-byte real
number is called single-precision and the 8-byte form is called double-precision.

Figure 1-7 both the 4- and 8-byte forms of real numbers

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1.4 Assignment Questions:

Questions carrying 2 marks.
1. Represent 45 10 in packed and unpacked BCD format. (NOV 2012)
2. Which technology was used to design INTEL 4004 microprocessor? What was is
execution speed?(NOV 2011)
3. Expand XMS and TPA (NOV 2011)
4. Write the BCH code of 2AC and BCD code of 89. (NOV 2011)
5. Expand CISC and XMS. (NOV 2010)
6. Represent 58 into packed and unpacked BCD format.(NOV 2010)
7. Define nibble, byte, word and double word.(NOV 2009)
8. List any 2 features of INTEL 4004. (NOV2009)
9. Expand TPA and VESA. ( NOV 2008 )
10. Explain with example two types of BCD data format.
11. What is the difference between AT and XT computer system?

Essay Questions:
1. Represent (-1.75) in single precision format. (NOV 2012)
2. With a suitable block diagram explain the microprocessor based computer system. (NOV
2012)
3. Evolution of microprocessor from 4 bit to 8 bit. (NOV 2012)
4. What is a Bus? Explain how the different parts of computer system are connected through
various buses? (NOV 2011)
5. Write a note on ASCII data. (NOV 2011)
6. Write a note on byte sized data and BCD data. (NOV 2011)
7. Write a note on ASCII and Unicode. (NOV 2010)
8. Write a note on Byte sized and Word sized data. (NOV 2011)
9. Explain how the real numbers are stored in single precision number format with suitable
example. (NOV 2009)

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CHAPTER 2.
INTERNAL MICROPROCESSOR ARCHITECTURE
2.1 The Programming model
The Intel 8086, a 16-bit microprocessor, contains approximately 29,000 transistors and is
fabricated using the HMOS technology. Its throughput is a considerable improvement over that
of the Intel 8080, its 8-bit predecessor. Although some attempt at compatibility with the 8080
CPU architecture was made, the designers decided not to sacrifice sophistication in order to
attain compatibility. By increasing the number of address pins from 16 to 20, the memory
addressing capacity was increased from 64K bytes to 220 = 1 megabyte. The expanded memory
capability made multiprogramming feasible and several multiprogramming features have been
incorporated into the 8086's design. The 8086 also includes a number of features which enhance
its multiprocessing capabilities, thus allowing it to be used with other processing elements such
as the 8087 numeric data processor.
The 8086 has 20 address pins, 16 of which are also used as data pins. The use of pins for both
addresses and data means that both an address and datum cannot be sent to the system bus at the
same time. This multiplexing of addresses and data reduces the number of pins needed, but does
slow down the transfer of data. However, because of the timing on the bus, the transfer rate is not
decreased as much as one might expect. There are 16 control lines for providing handshaking
signals during bus transfers and for permitting at least some external control of the CPU. The
8086 requires only one supply voltage, +5 V, and one clock phase whose frequency can be up to
5 MHz. (There are actually two other versions of the 8086, the 8086-2, which permits a clock
frequency of up to 8 MHz, and the 8086-1, which can handle up to 10 MHz.) Rounding out the
40-pin configuration are two grounds, pins 1 and 20.

2.2 Different types of registers

Figure 2-1 shows the internal architecture of the 8086. Except for the instruction register, which
is actually a 6-byte queue, the control unit and working registers are divided into three groups
according to their functions. There are the data group, which is essentially the set of arithmetic
registers; the pointer group, which includes base and index registers, but also contains the
program counter and stack pointer; and the segment group, which is a set of special purpose base
registers. All of the registers are 16 bits wide. The data group consists of the AX, BX, CX, and
DX registers. These registers can be used to store both operands and results and each of them can
be accessed as a whole, or the upper and lower bytes can be accessed separately. For example
either the 2 bytes in AX can be used together, or the upper byte AH or the lower byte AL can be
used by itself by specifying AH or AL, respectively
In addition to serving as arithmetic registers, the BX, CX and DX registers play special
addressing, counting, and I/O roles:
BX may be used as a base register in address calculations.
CX is used as an implied counter by certain instructions.
DX is used to hold the I/O address during certain I/O operations.

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Instruction Queue
Data Registers Address/Dat
a Bus 20 pins
AX AH AL

BX BH BL
Control Logic
CX CH CL Control Bus
16 pin
DX DH DL

SP
+5V
BP
CS
SI Gnd
ALU DS
DI CLK
ES
PSW IP
SS

Fig: 2.1 Architecture of 8086 microprocessor

The pointer and index group consists of the IP, SP, BP, SI, and DI registers. The instruction
pointer (IP) and SP registers are essentially the program counter and stack pointer registers, but
the complete instruction and stack addresses are formed by adding the contents of these registers
to the contents of the code segment (CS) and stack segment (SS) registers discussed below. BP is
a base register for accessing the stack and may be used with other registers)and/or a
displacement that is part of the instruction. The SI and DI registers are for indexing Although
they may be used by themselves, they are often used with the BX or BP registers and/or a
displacement. Except for the IP, a pointer can be used to hold an operand, but must be accessed
as a whole.
To provide flexible base addressing and indexing, a data address may be formed by adding
together a combination of the BX or BP register contents, SI or DI register contents, and a
displacement. The result of such an address computation is called an effective address (EA) or
offset. [The Intel manuals tend to use the term "effective address" when discussing the machine
language and the term "offset" when discussing the assembler language. The word
"displacement" is used to indicate a quantity that is added to the contents of a register(s) to form
an EA]. The final data address, however, is determined by the EA and the appropriate data
segment (DS), extra segment (ES), or stack segment (SS) register. The segment group consists of
the CS, SS, DS, and ES registers. As indicated above, the registers that can be used for
addressing, the BX, IP, SP, BP, SI, and DI registers, are only 16 bits wide and, therefore, an
effective address has only 16 bits. On the other hand, the address put on the address bus, called
the physical address, must contain 20 bits. The extra 4 bits are obtained by adding the effective
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address to the contents of one of the segment registers as shown in Fig. 2-2. The addition is
carried out by appending four 0 bits to the right of the number in the segment register before the
addition is made; thus a 20-bit result is produced. As an example, if (CS) = 123A and (IP) =
341B, then the next instruction will be fetched from
341B Effective address
+ 123AO Beginning segment address
157BB Physical address of instruction

Segment Address 16 bits

4 bits

Effective address or 16 bits

offset

Physical Address 20 bits

Fig. 2-2 Formation of a physical address.

2.3 flags
The 8086's PSW contains 16 bits, but 7 of them are not used. Each bit in the PSW is called a
flag. The 8086 flags are divided into the conditional flags, which reflect the result of the previous
operation involving the ALU, and the control flags, which control the execution of special
functions. The flags are summarized in Fig. 2-3. The lower byte in the PSW corresponds to the
8-bit PSW in the 8080 and contains all of the condition flags except OF.
The condition flags are:
SF (Sign Flag)-Is equal to the MSB of the result. Since in 2's complement negative numbers have
a 1 in the MSB and for nonnegative numbers this bit is 0, this flag indicates whether the previous
result was negative or nonnegative.
ZF (Zero Flag)-Is set to 1 if the result is zero and 0 if the result is nonzero.
PF (Parity Flag)-Is set to 1 if the low-order 8 bits of the result contain an even number of 1s;
otherwise it is cleared.
CF (Carry Flag)-An addition causes this flag to be set if there is a carry out of the MSB, and a
subtraction causes it to be set if a borrow is needed. Other instructions also affect this flag and its
value will be discussed when these instructions are defined.

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AF (Auxiliary Carry Flag)-Is set if there is a carry out of bit 3 during an addition or a borrow by
bit 3 during a subtraction. This flag is used exclusively for BCD arithmetic.
OF (Overflow Flag)-Is set if an overflow occurs., i.e., a result is out of range. More specifically,
for addition this flag is set when there is a carry into the MSB and no carry out of the MSB or
vice versa. For subtraction, it is set when the MSB needs a borrow and there is no borrow from
the MSB, or vice versa.
As an example, if the previous instruction performed the addition
0010 0011 0100 0101
+ 0011 0010 0001 1001
0101 0101 0101 1110
then following the instruction:
SF=O ZF=O PF=O CF=O AF=O OF=O

Figure 2.3 The flag registers of 8086 Processor

If the previous instruction performed the addition
0101 0100 0011 1001
+ 0100 0101 0110 1010
1001 1001 1010 0011

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then the flags would be:

SF= 1 ZF=O PF=1 CF=0 AF=1 OF=1
DF (Direction Flag)-Used by string manipulation instructions. If clear, the string is processed
from its beginning with the first element having the lowest address. Otherwise, the string is
processed from the high address towards the low address.
IF (Interrupt Enable Flag)-If set, a certain type of interrupt (a maskable interrupt) can be
recognized by the CPU; otherwise, these interrupts are ignored.
TF (Trap Flag)-If set, a trap is executed after each instruction.

2.4 Segment registers

There are four segment registers in the 8086/8088 processor, CS, DS, ES, and SS, also known as
Code Segment, Data Segment, Extra Segment, and Stack Segment.

Any time an address is generated by the processor, it is added to the value of one of the segment
registers, after that segment register is effectively multiplied by 16, or left shifted four bits, in
order to generate the physical address that accesses memory. This gives an effective address
range of 20 bits, or 1mb, but note that only 64kb is addressable through any segment register at
one time, unless you stop to change the contents of that segment register.

This is known as a segmented architecture.

By default, the CS register is used when fetching instructions, the DS register is used when
accessing data, the SS register is used when accessing the stack, and the ES register is used
during certain string type instructions. If desired, an instruction prefix can be used to override,
such as forcing use of CS instead of DS when using a table contained within opcode space.

2.5 Assembler directives.

Assembler instructions are translated into machine language instructions and correspond to
executable statements in high level programs. Just as high-level language programs must have
non executable statements to preassign values, reverse storage, assign names to constants, form
data structures and terminate a compilation assembler programs must contain the directives to
perform the similar tasks. Because of the 8086’s reliance on segment registers, an 8086
assembler must also include directives for indicating to the assembler the assumed contents in
the segment registers under the various circumstances as the assembly progresses.
Moreover since the assembler language programming is closer to the actual operations of the
computer, most assemblers have directives that give the programmer more control over the exact
placement of data and segmentation of the program than is available to the high level language
programmer.

ASSUME Directive - The ASSUME directive is used to tell the assembler that the name of the
logical segment should be used for a specified segment. The 8086 works directly with only 4
physical segments: a Code segment, a data segment, a stack segment, and an extra segment.

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ASUME CS:CODE ;This tells the assembler that the logical segment named CODE contains the
instruction statements for the program and should be treated as a code segment.
ASUME DS:DATA ;This tells the assembler that for any instruction which refers to a data in the
data segment, data will found in the logical segment DATA.
DB - DB directive is used to declare a byte-type variable or to store a byte in memory location.
Example:
1. PRICE DB 49h, 98h, 29h ;Declare an array of 3 bytes, named as PRICE and initialize.
2. NAME DB ‘ABCDEF’ ;Declare an array of 6 bytes and initialize with ASCII code for
letters
3. TEMP DB 100 DUP(?) ;Set 100 bytes of storage in memory and give it the name as
TEMP, but leave the 100 bytes uninitialized. Program instructions will load values into
these locations

DW - The DW directive is used to define a variable of type word or to reserve storage location
of type word in memory.
Example:
MULTIPLIER DW 437Ah ; this declares a variable of type word and named it as
MULTIPLIER. This variable is initialized with the value 437Ah when it is loaded into memory
to run.
EXP1 DW 1234h, 3456h, 5678h ; this declares an array of 3 words and initialized with specified
values.
STOR1 DW 100 DUP(0); Reserve an array of 100 words of memory and initialize all words with
0000.Array is named as STOR1.
END - END directive is placed after the last statement of a program to tell the assembler that
this is the end of the program module. The assembler will ignore any statement after an END
directive. Carriage return is required after the END directive.
ENDP - ENDP directive is used along with the name of the procedure to indicate the end of a
procedure to the assembler
Example:
SQUARE_NUM PROCE ; It start the procedure ;Some steps to find the square root of a number
SQUARE_NUM ENDP ;Hear it is the End for the procedure

END - End Program, ENDP - End Procedure, ENDS - End Segment, EQU – Equate,
EVEN - Align on Even Memory Address.

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ENDS - This ENDS directive is used with name of the segment to indicate the end of that logic
segment.
Example:
CODE SEGMENT ;Hear it Start the logic
;segment containing code
; Some instructions statements to perform the logical
;operation
CODE ENDS ;End of segment named as CODE

EQU - This EQU directive is used to give a name to some value or to a symbol. Each time the
assembler finds the name in the program, it will replace the name with the value or symbol you
given to that name.
Example:
FACTOR EQU 03H ; you has to write this statement at the starting of your program and later in
the program you can use this as follows
ADD AL, FACTOR ; When it codes this instruction the assembler will code it as ADDAL, 03H
The advantage of using EQU in this manner is, if FACTOR is used many no of times in a
program and you want to change the value, all you had to do is change the EQU statement at
beginning, it will changes the rest of all.
EVEN -This EVEN directive instructs the assembler to increment the location of the counter to
the next even address if it is not already in the even address. If the word is at even address 8086
can read a memory in 1 bus cycle.
If the word starts at an odd address, the 8086 will take 2 bus cycles to get the data. A series of
words can be read much more quickly if they are at even address. When EVEN is used the
location counter will simply incremented to next address and NOP instruction is inserted in that
incremented location
Example:
DATA1 SEGMENT
; Location counter will point to 0009 after assembler reads ;next statement
SALES DB 9 DUP(?) ;declare an array of 9 bytes
EVEN ; increment location counter to 000AH
RECORD DW 100 DUP( 0 ) ;Array of 100 words will start
;from an even address for quicker read
DATA1 ENDS
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GROUP - The GROUP directive is used to group the logical segments named after the directive
into one logical group segment.
INCLUDE -This INCLUDE directive is used to insert a block of source code from the named
file into the current source module.
PROC - The PROC directive is used to identify the start of a procedure. The term near or far is
used to specify the type of the procedure.
Example:
SMART PROC FAR ; This identifies that the start of a procedure named as SMART and
instructs the assembler that the procedure is far .
SMART ENDP
This PROC is used with ENDP to indicate the break of the procedure.
PTR -This PTR operator is used to assign a specific type of a variable or to a label.
Example:
INC [BX] ; This instruction will not know whether to increment the byte pointed to by BX or a
word pointed to by BX.
INC BYTE PTR [BX] ;increment the byte ;pointed to by BX. This PTR operator can also be
used to override the declared type of variable . If we want to access the byte in an array.
WORDS DW 437Ah, 0B97h,
MOV AL, BYTE PTR WORDS

PUBLIC - The PUBLIC directive is used to instruct the assembler that a specified name or label
will be accessed from other modules.
Example:
PUBLIC DIVISOR, DIVIDEND ;these two variables are public so these are available to all
modules.If an instruction in a module refers to a variable in another assembly module, we can
access that module by declaring as EXTRN directive.
TYPE - TYPE operator instructs the assembler to determine the type of a variable and
determines the number of bytes specified to that variable.
Example:
Byte type variable – assembler will give a value 1
Word type variable – assembler will give a value 2
Double word type variable – assembler will give a value 4

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ADD BX, TYPE WORD_ ARRAY ; hear we want to increment BX to point to next word in an
array of words.

2.6 Assignment Questions

Questions carrying 2 marks
1. What is the purpose of IP and SP register? ( NOV 2012 )
2. What is the purpose of PUBLIC and EXTRN directive? (NOV 2012 )
3. List the various segment registers of 8086 microprocessor. (NOV 2011)
4. Define a bus. List the various buses available in 8086 based computer system. ( NOV
2010)
5. List the various offset registers in 8086.
6. What is the purpose of IP register? ( NOV 2007 )
7. What is the purpose of SP register?
8. What is the use of AF? When is it going to set?
9. What are instruction queues?
10. List the various status flag of 8086.
11. List the different control flags of 8086.
12. What is a HMOS technology?
13. What are Assembler directives?
14. What is the use of EQU directive?
15. What are the differences between ENDS and ENDP?
16. Give the meaning for ASSIGN directive.
17. What do you mean by SEGMENT and ENDS?
18. Why are we using ORG directive?
19. What do DB, DW and DD stand for?
20. Give the meaning for PROC.
21. If CS=2070H and IP=2004H then find the physical address of the next instruction to be
executed by the processor. (NOV 2012)
22. After executing the following instructions, what will be the status of the carry and parity
flag?(NOV 2011)
MOV AL, 85H
ADD AL, 0A2H
23. Suppose that AX=1000H and BX=2000H and DS=0010H Determine the address
accessed by the following instruction considering the real mode operation(NOV 2008)
i. MOV CX, [AX+BX]
24. Given DS:1000H ARRAY=1100H BX=0300H SI=0200H Determine the following
addressed by the following instruction. MOV ARRAY[BX+SI], DX (NOV 2007)
Essay Questions.
1. With a suitable block diagram explain the microprocessor based computer system (NOV
2012)
2. What are the salient features of 8086 microprocessor? (NOV 2012)
3. Explain the microprocessor based computer system with address bus, data bus and
control buses.(NOV 2011)
4. With the help of a diagram explain the internal architecture of 8086 processor.

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5. Explain the various control flags in 8086 processor.(NOV 2011)

6. Explain the various status flags in 8086 processor.
7. Differentiate the following flag registers. Give example. (NOV 2009)
a. Carry and Auxiliary flags.
b. Parity and Sign flags.
c. Carry and Overflow flags.
8. Explain any four multipurpose registers.(NOV 2009)
9. With neat diagram explain the bus structure of a computer system.(NOV 2008)
10. What is the purpose of segment register in real mode operation? (NOV 2008)
11. With the help of a diagram explain the PSW of 8086 processor. (NOV 2007)
12. Add any two 16 bit numbers and discuss the status of flags that are affected and reflected
in the result. (NOV 2007)
13. What are assembler directives? Explain.
14. Explain the following assembler directives
a. EQU
b. BYTE PTR
c. PROC
d. ENDP
e. ASSUME
15. Explain the procedure of finding the physical address with the help of a segment and
offset registers.

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CHAPTER 3.
ADDRESSING MODES
The way in which an operand is specified is called its addressing mode. The 80x86 processors let
us access memory in many different ways. The 80x86 memory addressing modes provide
flexible access to memory, allowing you to easily access variables, arrays, records, pointers, and
other complex data types. Mastery of the 80x86 addressing modes is the first step towards
mastering 80x86 assembly language. When Intel designed the original 8086 processor, they
provided it with a flexible, though limited, set of memory addressing modes. Intel added several
new addressing modes when it introduced the 80386 microprocessor. Note that the 80386
retained all the modes of the previous processors; the new modes are just an added bonus. Many
programmers still need to write programs that run on 80286 and earlier machines, it's important
to separate the discussion of these two sets of addressing modes for data and for branch
addresses.

3.1 Data Movement Instructions

3.1.1 Register : The datum is in the register that is specified by the instruction. For a 16-bit
operand, a register may be AX, BX, CX, DX, SI, DI, SP, or BP, and for an 8-bit operand a
register may be AL, AH, BL, BH, CL, CR, DL, or DH.

Instruction Register

Register Datum

Figure 3.1.1 Register Addressing Mode

For example MOV AL, BL
MOV CX, DX
MOV BL, BH etc

3.1.2 Immediate

In this mode the datum is either 8 bits or 16 bits long and is a part of the instruction.
Instruction

Datum

Figure 3.1.2 Immediate Addressing Mode

For example MOV AH, 4CH

MOV SI, 0000H etc

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3.1.3 Direct
The 16-bit effective address of the datum is part of the instruction.

Instruction Memory

Effective Datum
Address

Figure 3.1.3 Direct Addressing Mode

For example MOV AL, n1
MOV n2, CX etc

3.1.4 Register Indirect

The effective address of the datum is in the base register BX or an index register that is specified
by the instruction, i.e.,
EA={ (BX), (DI), (SI)}

instruction Register Memory

Register Effective Datum

Address

Figure 3.1.4 Register Indirect Addressing Mode

3.1.5 Base plus Index

The effective address is the sum of a base register and an index register, both of which are
specified by the instruction, i.e.,
EA = {{(BX) or (BP)} Plus {(SI) Or (DI)}} .

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Instruction Register

Base Register Index Index Memory

Register
Register
Datum
+
Base Address

Figure 3.1.5 Base Plus Index Addressing Mode

3.1.6 Register relative

The effective address is the sum of an 8- or 16-bit displacement and the contents of a base
register or an index register, i.e.
EA = {{(BX),(BP), (SI), (DI)} Plus {8 bit displacement ( sign extended) or 16 bit
displacement}}

Instruction

Base Register Memory

Displacement

Datum
+
Address

Register

Figure 3.1.6 Register relative Addressing Mode

3.1.7 Base relative plus Index

The effective address is the sum of an 8- or 16-bit displacement and a based indexed address, i.e
EA = {{(BX),(BP)} Plus { (SI), (DI)} Plus {8 bit displacement ( sign extended) or 16 bit

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displacement}}

Instruction
Base Register Index Register Displacement
Memory

Datum
Register +

Index Address

Base Address

Register

Figure 3.1.7 Base relative Plus Index Addressing Mode

For example if (BX) =0158 (DI)=10A5 Displacement =1B57 (DS)=2100 and OS

is used as the segment register, then the effective and physical addresses produced by these
quantities and the various addressing modes would be
Direct: EA = 1B57
Physical address = IB57 + 21000 = 22B57
Register: No effective ad9ress-datum is in specified register.
Register indirect assuming register BX:
EA = 0158
Physical address = 0158 + 21000 = 21158
Register relative assuming register BX:
EA = 0158 T IB57 = 1CAF
Physical address = 1CAF + 21000 = 22CAF
Based indexed assuming registers BX and DI:
EA = 0158 + lOA5 = 11FD
Physical address = 11FD + 21000 = 221FD
Relative based indexed assuming BX and DI:

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EA = 0158 + lOA5 + IB57 = 2D54

Physical address = 2D54 + 21000 = 23D54

3.2 Program memory addressing modes

The program memory addressing mode calculates the effective address of the next instruction to
be executed. Here the CS and IP registers will be effected accordingly.
In the program memory addressing mode 4 types of addressing modes out of which 2 types are
related to intrasegment and two types are related to intersegment.
Intrasegment Direct-The effective branch address is the sum of an 8- or 16-bit displacement
and the current contents of IP. When the displacement is 8 bits long, it is referred to as a short
jump) Intrasegment direct addressing is what most computer books refer to as relative addressing
because the: displacement is computed "relative" to the IP. It may be used with either conditional
or unconditional branching, but a conditional branch instruction can have only an 8-bit
displacement.

Instruction

Displacement

Plus Effective Address

IP

Figure 3.2 (a) Intrasegment Direct addressing Mode.

Intrasegment Indirect-The effective branch address is the contents of a register or memory
location that is accessed using any of the above data-related addressing modes except the
immediate mode. The contents of IP are replaced by the effective branch address. This
addressing mode may be used only in unconditional branch instructions.

Register

Effective branch
Instruction
address
EA Computed
Addressing Mode according to or memory
addressing mode
Effective branch
address
Figure 3.2 (b) Intrasegment Indirect addressing Mode.

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Intersegment Direct-Replaces the contents of IP with part of the instruction and the contents of
CS with another part of the instruction. The purpose of this addressing mode is to provide a
means of branching from one code segment to another.
CS
Instruction

Offset Segment
IP

Figure 3.2 (c) Intersegment Direct addressing Mode.

Intersegment Indirect-Replaces the contents of IP and CS with the contents of two consecutive
words in memory that are referenced using any of the above data-related addressing modes
except the immediate and register modes.
Two consecutive
Instruction words in memory
EA Computed
Addressing Mode according to the Branch Address offset
addressing mode

Segment Address

Figure 3.2 (d) Intersegment indirect addressing Mode.

To demonstrate how indirect branching works with some of the data-related addressing
modes, suppose that
(BX)= 1256 (SI)= 528F Displacement= 20A1 Then
with direct addressing, the effective branch address is the contents of:
20A1 + (DS) x 1610
With register relative addressing assuming register BX, the effective branch address is the
contents of:
1056 + 20A1 + (DS) x 1610
With based indexed addressing assuming registers BX and SI, the effective branch address is
the contents of:
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1056 + 528F + (DS) x 1610

3.3 Stack memory addressing modes

The stack in the 8086/8088 microprocessor, like that in many microprocessors, is a region of
memory that can store information for later retrieval. It is called a stack, because you "stack"
things on it. Stack memory is LIFO (last-in, first-out) memory describes the way data are
stored and removed from the stack. The philosophy is that you retrieve (pop) things in the
opposite order of storing (push) them.

In the 8086/8088, the stack pointer is SS:SP, which is a 16 bit pointer into a 20 bit address
space. It, at any point of time, points to the last item pushed on the stack. If the stack is
empty, it points to the highest address of the stack plus one.

Data are placed on the stack with a PUSH instruction; removed with a POP instruction.
Stack memory is maintained by two registers:

the stack pointer (SP ) and the stack segment register (SS)

Whenever a word of data is pushed onto the stack, the high-order 8 bits are placed in the
location addressed by SP – 1. Low-order 8 bits are placed in the location addressed by SP – 2

The SP is decremented by 2 so the next word is stored in the next available stack location.

The operation of stack memory addressing mode is shown in the Figure 3.3.The PUSH and
POP instructions: (a) PUSH BX places the contents of BX onto the stack; (b) POP CX
removes data from the stack and places them into CX. Both instructions are shown after
execution.

Some instructions, such as a FAR CALL, or FAR RETURN push or pop more than two bytes
on the stack. It is also possible to allocate temporary storage on the stack. You simply
decrement the SP register by some amount, use that memory, and then increment the SP
register to release the memory. This is known as a stack frame. In fact, the BP register makes
is very easy to do so. You use BP to separate arguments from local data - arguments will be
above BP, and local data will be below BP.

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Figure 3.3 Working of stack for PUSH and POP instructions

3.4 Segment override prefix

A segment override prefix allows any segment register (DS, ES, SS, or CS) to be used as the
segment when evaluating addresses in an instruction. An override is made by adding the
segment register plus a colon to the beginning of the memory reference of the instruction as
in the following examples:

mov ax, [es:60126] ; Use es as the segment

mov ax, [cs:bx] ; Use cs as the segment
mov ax, [ss:bp+si+3] ; Use ss as the segment
3.5 Assignment Questions.
Short answer questions carrying 2 marks each
1. Identify the addressing mode for the following (NOV 2012)
a. MOV AX, 1000H
b. MOV CX, [BX+SI+1004]
c. MOV AX, [SI] (NOV 2011)
d. MOV AX, 2011H

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2. Write an instruction to transfer (move) a byte of data from the data segment memory location
addressed by (pointed) register BX, into register AX. (NOV 2010)
3. Why segment override prefix is used? Give example. (NOV 2009)
4. What are the three program memory addressing modes? (NOV 2008)
5. With a syntax explain the register indirect addressing mode? (NOV 2008)
6. Give DS=1000H, ARRAY=1100H, BX=0300H, SI=0200H. Determine the address accessed
by the following instruction.
MOV ARRAY[BX+ SI], DX. (NOV 2007)
Essay Questions.
1. Define the addressing mode. Explain any three data addressing modes. (NOV 2012)
2. Explain three program memory addressing mode.(NOV 2012)
3. Discuss the register, register indirect and base plus index addressing modes. Write the
necessary examples for the same. (NOV 2011)
4. Suppose that DS=1000H, SS=2000H, BP=0100H, BX=0250H and DI=0200H, determine
the address accessed by each of the following instruction.(NOV 2011)
a. MOV [BX+DI], AX
b. MOV [BP+10H], DX
c. MOV CL, [BX+75H]
d. MOV BL, [DI-100H]
5. Explain the different program memory addressing modes. (NOV 2011)
6. Explain the working of PUSH and POP instructions with the help of an example (NOV
2011)
7. Explain the stack memory addressing modes. (NOV 2010)
8. Suppose DS=3000H, BX=0200H, SI= 0100H, SS=5000H and BP= 1000H. Determine
the physical address accessed by each of the following instructions. (Assuming the real
mode operation) ( NOV 2010)
a. MOV [BP + 25H], AL
b. MOV CX, [BX + SI – 10H]
c. MOV DL, [ SI+ 20H]
9. Determine the address accessed by the following instructions. Given DS=1200H,
BX=0200H, LIST=0340H, SI=500H (NOV 2009)
a. MOV LIST[SI + 20H], AX
b. MOV AL, [BX + SI – 150H]
c. MOV LIST[BX + SI], CX
d. MOV SI, LIST[BX]
10. What are the differences between inter segment and intra segment jump with the help of a
diagram (NOV 2008)

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Chapter 4.
MOV INSTRUCTION
The machine language program code is the only code that can be executed by the processor. The
assembly language code is one of the most primitive forms, in which program can be coded. The
assembly language code has to be processed by the assembler to generate machine language
code. There are two types of statements in assembly language. First, the instructions, which are
translated to the machine code by the assembler, and second the directives, which direct the
assembler during the assembly process for which no machine code is generated.
Assembly language programming is much easier than machine language programming. An
instruction in assembly language is represented by character strings called mnemonics (eg. ADD,
SUB, IMP, etc.). The 80x86 processor provides an exhaustive set of instructions to support
assembly language programming to perform input, processing, and output operations known as
the Instruction Set.
The instructions of 80x86 processor are classified into the following six functional groups.
1. Data Transfer Instructions
2. Arithmetic and Logical Instructions
3. Branch Instructions
4. Processor Control Instructions
5. String Operation Instructions
6. Protection Control Instructions

Following are the conventions used in describing the instructions.

Src Source
Dest Destination
Reg register
r/m register or a memory location
r/m16 16 bit register or a word memory location
immed16 immediate 16 bit number
addr address of a memory location
reg8 8-bit register
reg16 16-bit register
src8 source of type 8-bit

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src16 source of type l6-bit

mem16 16-bit memory location
MOD modulus or a remainder
~ logical NOT operation
& logical AND operation
! logical OR operation
^ 10gical EX-OR (exclusive OR) operation
<- assignment operation
≠ not equal

4.1 Various types

The 80x86 processor supports a variety of instructions for transfer of data, Immediate value, or
addresses into registers, memory locations, or ports. The manner in which the operands are
designated in the data movement instruction, depends on the addressing modes and can be in
anyone of the following forms.
Register to a register
Immediate operand to a register
Immediate operand to the memory
Memory to a register
Register to a memory
Register to a segment register (excluding CS)
Memory to a segment register (excluding CS)
Segment register to a register
Register to an I/O port
I/O port to a register
Data transfer instructions generally involve two operands, the source and destination. The source
can be a register or a memory location or an immediate data. The destination can be a register or
a memory location. Both the source and destination cannot refer to memory locations in the same
instruction. They must be of the same data-type i.e. either of the type byte or type word.

Data transfer instructions do not affect the CPU flags.

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MOV: Move instruction.

Description:
The instruction MOV transfers a byte or a word of data from the source to the destination. The
source can be a register or a memory location or an immediate number. The destination can be a
register or a memory location. Both the source and destination cannot refer to memory locations
in the same instruction. They must be of the same data-type, i.e., either of the type byte or type
word.
Flags Affected: None
Syntax:
MOV dest, src Transfer data from register/memory/immediate to register/memory
dest ← src
Examples:

MOV AX, CX copy contents of CX to AX

MOV AH, AL copy contents of AL to AH
MOV DS, AX copy contents of AX to DS
MOV AX, 100H copy immediate value 100H to AX
MOV BX, [530BH] copy 16-bit data from the memory location 530BH to BX register
MOV DL, [BX] copy 8-bit contents of memory location pointed to by the address
stored in BX to DL
MOV BP, SS copy contents of SS to BP

4.2 PUSH and POP

PUSH and POP instructions are associated with the stack memory where PUSH is used to move
the contents into the stack and POP is used to move the content from the stack.
PUSH: Push the register or memory into the stack.
Description:
The instruction PUSH decrements the stack pointer (SP) by two and loads a word from the
source to the location pointed to by SP. The source word can be a general purpose register
(GPR), a segment register, a pointer, or a memory location. The SS and SP should be initialized
before the use of PUSH instruction to the stack memory. This instruction is used to save data
onto the stack for preserving the data and for passing parameter(s)to the procedure.

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Syntax:
PUSH src Transfer regl6 or r/m 16 to the stack.
SP ← SP - 2; SS:[SP] ← src
Flags Affected: None
Examples:
PUSH AX decrement SP by 2 and copy the content of AX to the stack
PUSH DX decrement SP by 2 and copy the content of DX to the stack
PUSH SS SP ← SP-2 and copy the contents of SS to stack
PUSH BP SP ← SP-2 and copy the contents of BP to stack
PUSH BL an illegal instruction because one can not store an 8 bit data in the
Stack
PUSH AMOUNT[BX] decrement SP by 2 and copy contents of a word from the
memory location AMOUNT + (BX) in data segment to the
stack in SS

PUSHA: Push All registers

Description:
The instruction PUSHA copies the contents of four general purpose registers (AX, BX, CX and,
DX), two pointer registers (SP, BP), and two index registers (SI, DI) to the stack. These registers
are pushed onto the stack in the order AX, CX, DX, BX, SP, BP, SI, and DI. The stack pointer is
decremented by two before every push operation. However, the value pushed for SP is equal to
the value it had before the AX register was pushed onto the stack.
Flags Affected: None
Syntax:
PUSHA Push all : copy all registers onto the stack.
The SP is decremented by two for every push operation.
Registers AX, CX, DX, BX, SP, BP, SI, DI are saved on the stack.

POP : Pop (remove) the register or memory from the stack.

The instruction POP copies a word from the stack location to a specified word register or a word
memory location and then SP is incremented by two. For multiple PUSH and POP operations,
the destination of the instruction POP should be specified in the reverse order of the PUSH
instruction to restore the data saved on the stack. The pop operation removes the element
recently pushed onto the stack. Hence, stack operates on Last In First Out (LIFO) basis.

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Flags Affected: None

Syntax:
POP dest Transfer to reg 16 or rIm 16 from the stack.
dest ← SS:[SP];
SP ← SP + 2Transfer the 16 bit data from the stack to regl6
or r/m 16
Examples:
POP AX copy the content of the stack to AX and increment SP by 2
POP DX copy the content of the stack to DX and increment SP by 2
POP SS copy the contents of stack to SS and SP ← SP+2
POP BP copy the contents of stack to BP and SP ← SP+2
POP BL an illegal instruction because one can not retrieve an 8 bit data
from the Stack

POPA: POP All registers

Description:
The instruction POPA restores four general purpose registers (AX, BX, ex, OX), two pointer
registers (SP, BP), and two index registers (SI, 01) from the stack. These registers are popped out
of stack in the order DI, SI,BP, SP, BX, OX, ex, and AX. The stack pointer is incremented by
two after every pop operation. However, the value of SP after execution of this instruction will
contain the value popped from the stack.
Flags Affected: None
Syntax:
POPA Pop all :restore all registers from the stack.
Registers DI, SI, BP, SP, BX, DX, CX, and AX are restored from the stack
SP is incremented by two for every pop operation

PUSHF: Push the flag registers

Description:
The instruction PUSHF decrements the stack pointer by two and copies the contents of flag
register onto the stack.
Flags Affected: None
Syntax: PUSHF Push flags: transfer flag register to the stack.

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SP← SP - 2; SS← CPU flags

Example:
PUSHF ;decrement SP by 2 and copy flag register onto the stack

POPF: Pop the flag registers

Description:
The instruction POPF will copy the word from the stack pointed to by the stack pointer to the
flag register.
Flags Affected: All
Syntax:
POPF Pop flags: transfer from stack to the flag registers.
Flags← SS:[SP]; SP← SP + 2
Example:
POPF copy stack top contents to the flag register and increment SP by 2

LAHF: Load AH with flag.

Description:
The instruction LAHF copies the lower byte of the flag register to AH register. The lower byte of
the 8086 microprocessor flag register format is same as the 8085 microprocessor flag register.
The instruction LAHF along\ with SAHF instruction is very useful for simulation of the 8085
microprocessor on the 8086 based system.
Flags Affected: None

Syntax:
LAHF Load AH with the lower byte of the flag.

SAHF: Store AH register with the flag.

Description:
The instruction SAHF copies the contents of AH into the lower byte of the flag register. The
lower byte of the8086 microprocessor flag register format is same as the 8085 microprocessor
flag register. The instruction SAHF along with LAHF is useful for simulation of 8085
microprocessor on the 8086 microprocessor based system. It is also useful in modifying the flag
register without the execution of arithmetic instructions.

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Flags Affected: SF, ZF, AF, PF, CF

Syntax
SAHF Store AH into the lower 8 bits of the flag.

4.3 LEA LDS and LES

LEA: Load effective address
Description:
The instruction LEA determines offset of a variable or memory location indicated as a
source(address) and places the offset in the specified 16-bit register The source operand must be
a memory variable and the destination must be a 16-bit general register.
Flags Affected: None
Syntax:
LEA reg 16 , source Load effective address into a register
reg 16← (result of effective address or c<1culatioh of
address offset)
Examples:
Instructions to access amount are
LEA BX, AMOUNT ;BX= offset of AMOUNT
equivalent to MOV EX, OFFSET AMOUNT

LEA BP, SS:STACK_TOP ;load offset of STACK TOP to BP with reference to

SS register
. If EX = 1000 and DI=3 then
LEA AX, [EX] [DI] then AX= 1000+3=1003 will be the effective address in AX.

LDS: Load register and DS register.

Description:
The Instruction LOS copies the contents of first two memory locations to a specified 16-bit
register and the next consecutive two memory locations into the DS register.
Flags Affected: None

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Examples:
LDS BX, [5300H] instruction copies the contents of the memory at 5300H in DS to BL and
530IH to BH register and the next consecutive memory locations 5302H and 5303H in data
segment are copied to DS register i.e., DS - word at memory location 5302.
LDS SI, STR_PTR instruction copies the contents of the memory displacement STR _PTR and
STR_PTR+ 1 in the data segment to SI register and STR _PTR + 2 and STR _PTR +3 in the data
segment to DS register. DS:SI points to the start of the string.
Syntax:
LDS regl6, meml6 Load DS and reg 16 from the memory location.
reg16← [mem16]: DS← [mem16+2]

LES: Load register and ES register

Description:
The instruction LES copies the contents of first two memory locations to a specified 16-bit
register and the next consecutive two memory locations into the ES register.
Flags Affected: None

Syntax:
LES regl, mem 16 Load ES and reg 16 from the memory location.
regl6← [mem16]; ES← [mem16+2]

Examples:
LES BX, [5300H] instruction copies the contents of the memory at 5300H in OS to BL and
530lH to BH register and the next consecutive memory locations 5302H and 5303H in register
DS to register ES.
LES SI, STR_PTR instruction copies the contents of memory displacement STR_PTR and
STR_PTR+ 1 in OS to SI register and STR_PTR+2 and STR_PTR+ 3 in DS to ES register ES:SI
points to the start of the string.

4.4 String transfer instructions

A string is a contiguous (consecutive) sequence of bytes or words. Strings can be used to hold
any type of data or information that will fit into bytes or words. For instance, a string byte(s) may
hold character(s) (one byte per character); a string word(s) may hold signed or unsigned
number(s), etc. There are a number of operations that can be performed with strings. The 80x86
processor supports string instructions for string movement, comparison, scan, load, and store. It
also provides instructions for repeating string operations. The five basic string instructions end in
"S" or "SB" or "SW". "S" represents string, "SB" represents string byte, and "SW" represents

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string word. The string defined with DB (bytes) uses the instructions ending with "SB"; the
string defined with DW (words) uses the instructions ending with "SW". The processor also
provides instructions (CLD and STD) for direction control which controls the generation of the
offset address of the next element of a string.
String Instruction Operands: All string instructions requires two operands. However, no operands
are specified as a part of the instruction. The processor implicitly uses the values in certain
registers. All instructions assume that the source operand is in the data segment (DS) and the
destination is in the extra segment (ES), However, string instructions for load, scan, and store
assumes one of the operand in the accumulator. The register SI(source index) is used to store the
offset address of the source operand in DS (i.e., the source operand is identified by SI in DS, the
combination as DS: [SI]. The register DI (destination index) is used to store the offset address of
destination operand in ES (i.e., the destination operand is identified by DI in ES, combination as
ES:[SI]). The register CX is used as a counter in the repeat string instructions like REP, REPE,
REPNE,REPZ, etc.
In string instructions, the operands are not mentioned explicitly. Therefore, all the registers used
by the Instruction must be loaded prior to the execution of the instruction. On execution of a
string instruction, SI and DI registers are automatically updated to point to the next element of
the source and destination. If the direction flag (DF) is reset (DF = 0), the register SI and DI will
be incremented by one for byte move and incremented by two for word move. If the direction
flag (DF) is set (DF = 1) the register SI and DI will be decremented by one for movement of
bytes and decremented by two for movement of words.
To reset the direction flag DF=0 we use CLD instruction which will reset DF. To set the
direction flag DF=1 we use STD instruction.

4.4.1 MOVS
MOVS Move String
MOVSB Move String Byte
MOVSW Move String Word
Description:
The instruction MOVS transfers a byte or a word from the source string to the destination string.
The source is in the data segment and destination is in the extra segment. The offset of the source
byte or a word must be placed in the register SI which is represented as DS:SI and the offset of
the destination byte or a word must be placed in the register DI which is represented as ES:DI.
On execution of a string instruction, SI and DI are automatically updated to point to the next
element of the source and destination. If the direction flag (DF) is reset (DF = 0), the register SI
and DI will be incremented by one for byte move and incremented by two forward move. If
direction flag (DF) is set (DF = 1), the register SI and DI will be decremented by one for byte
move and decremented by two for word move. In instruction MOVS, the source and destination
must be explicitly declared either with DB (define byte) or OW (define word). The source and
destination does not load the segment and offset registers (OS:SI and ES:DI), hence, OS:SI and
ES:DI must be loaded prior to the execution of MOVS instruction.
Another method to move a byte or a word string is by using implicit instructions MOVSB or
MOVSW. The instruction MOVSB refers to string byte movement from the source to the
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destination. The instruction MOVSW refers to the string word movement from the source to the
destination. In multiple byte or word moves, the number of elements to be moved is placed in the
register CX which functions as a counter. In the case of multiple movement,
MOVS/MOVSB/MOVSW is prefixed with the repeat string instructions such as REP, REPE,
etc. Note that the registers DS and ES can point to either the same segment or different segments.
Flags Affected: None:
Function:
if( byte movement) then
byte [DI] ← byte [SI]
if( DF = 0 ) then SI ← SI + 1; DI ← DI + 1;
if( DF = 1 ) then SI ← SI - 1; DI ← DI – 1;
if( word movement) then
word [DI] ← word [SI]
if( DF = 0 ) then SI ← SI + 2; DI ← DI + 2;
if( DF = 1 ) then SI ← SI - 2; DI ← DI – 2;
Syntax: MOVS/MOVSB/MOVSW

4.4.2 LODS
LODS: Load String
LODSB: Load String byte
LODSW: Load String word
The instruction LODS transfers a byte or a word from the source string pointed to by SI in DS to
the accumulator (AL for byte and AX for word). On execution of a string instruction, SI is
automatically updated to point to the next element of the source. If the direction flag (DF) is reset
(DF = 0), the register SI will be incremented by one for the byte load and incremented by two for
the word load. If the direction flag (DF) is set (DF=1), the register SI will be decremented by one
for the byte load and decremented by two for the word load. In the instruction LODS, the source
must be explicitly declared either with DB (define byte) or with DW (define word).
Another method to load a byte or a word string is by using the implicit instructions LODSB or
LOOSW. The instruction LOOSB refers to string byte-load from the source to AL. The
instruction LODSW refers to string word-load from the source to AX. In multiple byte or word
loads, the number of elements to be loaded is placed in the register CX which functions as a
counter. In the case of multiple loads, LODS/LOOSB/LODSW is prefixed with the repeat string
instructions such as REP, REPE, etc.
Flags Affected: None
syntax:

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LODS / LOOSB / LOOSW Copy string byte(word) into AL(AX)

(byte= 1, word= 2)
byte: AL ← DS:[SI]; SI = SI + 1
word: AX ← DS:[SI]; SI = SI + 2

4.4.3 STOS
STOS Store String
STOSB Store string byte
STOSW Store string word

Description:
The instruction STOS transfers a byte or a word from the accumulator (AL for byte and AX for
word) to the destination string pointed to by DI in ES. On execution of a string instruction, DI is
automatically updated to point to the next element of the destination. If the direction flag (DF) is
reset (DF = 0), the register DI1 will be incremented by one for byte store and incremented by
two for word store. If the direction flag (DF) is set (DF =1), the register DI will be decremented
by one for byte store and decremented by two for word store. In instruction STOS, the
destination must be explicitly declared either with DB (define byte) or DW (define word).
Another method to store a byte or a word string is by using the implicit instructions STOSB or
STOSW. The instruction STOSB refers to store the string byte from AL to the destination. The
instruction STOSW refers to store the string word from AX to the destination. In multiple byte or
word store, the number of elements to be stored is placed in the register CX which functions as a
counter. In the case of multiple stores, STOS/STOSB/STOSW ; prefixed with .the repeat string
instructions such as REP, REPE, etc.
Flags Affected: None
Function:
if( byte movement) then
Byte ES:[DI] ← AL
if( DF = 0) then DI=DI + 1;
if( DF = 1 ) then DI=DI- 1;
if( word movement) then
Word ES:[DI] ← AX
if(DF = 0 ) then DI=DI + 2;
if(DF = 1 ) then DI=DI - 2;

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4.4.4 INS
INS Input String
INSB Input String Byte
INSW: Input String Word

Description:
The instruction INS transfers a byte or a word from the port to the destination string pointed to
by DI in ES. Execution of a string instruction, DI is automatically updated to point to the next
element of the source. If the direction flag (DF) is reset (DF = 0), the register DI will be
incremented by one for byte input and incremented by two for a word input. If the direction flag
(DF) is set (DF = 1), the register DI will be decremented by one for a byte input and decremented
by two for a word input. In the instruction LODS, the destination must be explicitly declared
either with DB (define byte) or DW (define word).
Another method to input a byte or a word string is by using the implicit instructions INSB or
INSW. The instruction INSB refers to string byte input from the port to the destination. The
instruction INSW refers to string byte input from the port to the destination. In multiple byte or
word inputs, the number of elements to be read from the port is placed in the register CX which
functions as a counter. In the case of multiple input, INS/INSB/INSW is prefixed with the repeat
string instructions such as REP, REPE, etc.
Flags Affected: None
Function:
if( byte input) then
Byte ES:[DI] ← byte [port]
if( DF = 0 ) then DI ← DI + 1;
if( DF = 1 ) then DI ← DI - 1;
if( word input) then
Word ES:[DI] ← word [port]
if( DF = 0 ) then DI ← DI + 2;
if( DF = 1 ) then DI ← DI - 2;
Syntax:
INS / INSB / INSW dest, port Store byte(words) into string from port
(byte=1, word=2)
byte: ES:[DI] ← [port]; DI = DI + 1

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word: ES:[DI] ← [port]; DI = DI + 2

4.4.5 OUTS
OUTS Output String
OUTSB Output String Byte
OUTSW Output String Word
Description:
The instruction OUTS transfers a byte or a word from the source string pointed to by SI in DS to
I/O port. On execution of a string instruction, SI is automatically updated to point to the next
element of the source. If the direction flag (DF) is reset (DF = 0), the register SI will be
incremented by one for byte output and incremented by two for word output. If the direction flag
(DF) is set (DF = 1), the register SI will be decremented by one for byte output and decremented
by two for word output. In the instruction OUTS, the source must be explicitly declared either
with DB (define byte) or DW (define word).
Another method to output a byte or a word string is by using the implicit instructions OUTSB or
OUTSW. The instruction OUTSB refers to string byte output from the source to port. The
instruction OUTSW refers to string word output from the source to port. In multiple byte or
word output, the number of elements to be output to the port is placed in the register CX which
functions as a counter. In the case of multiple output, OUTS/OUTSB/OUTSW is prefixed with
the repeat string instructions such as REP, REPE, etc.
Flags Affected: None
Function:
if ( byte output ) then
byte [port] ← DS:[SI]
if( DF = 0 ) then SI← SI + 1;
if( DF = 1 ) then SI ← SI - 1;
if(word movement) then
word [port] ← DS:[SI]
if( DF = 0 ) then SI ← SI + 2;
if( DF = 1 ) then SI ← SI - 2;
Syntax:
OUTS/OUTSB/OUTSW port, source Port output byte(word) from string
(byte:1, word:= 2)
[port DX] ←DS:[SI];SI=SI+1

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[port DX]←DS:[SI];SI=SI+2

4.5 Assignment Questions

Questions carrying 2 marks.
1. Explain LEA instruction. (NOV 2011)
2. Explain the PUSHF instruction. (NOV 2011)
3. Comment on LAHF and SAHF instructions. (NOV 2011)
4. Write an instruction to transfer (move) a byte of data from the data segment memory
location addressed (pointed) by register BX into register AX. (NOV 2010)
5. Explain the purpose of SCAS instruction. (NOV 2009)
6. Explain the purpose of LDS (NOV 2009)
7. Which registers move onto the stack with PUSHA instruction? (NOV 2007)
8. List the differences between PUSHF and PUSHA.
9. Give a single instruction that can do the following work
a. LODSB
b. STOSB
10. What is the role of Direction flag in string instruction?
11. What does CMPSB instruction do?
12. Explain INS (NOV 2009)

Essay questions.
1. Explain LEA and LDS instructions with examples. (NOV 2012)
2. Explain the following instructions. (NOV 2012)
a. PUSHA
b. PUSH AX
c. POPE
d. PUSH 1234H
3. Explain the PUSH and POP instructions with example. (NOV 2011)
4. Explain any three string instructions. (NOV 2012)
5. Explain the following instructions (NOV 2011)
a. MOVS
b. LODS
6. Explain the PUSH instruction with the help of a diagram. (NOV 2010)
7. Discuss the functioning of MOVS and STOS instructions. Also explain the effect of REP
prefix on these instructions. (NOV 2010)
8. Give the purpose of PUSHA, PUSH AX, POPF and POPA (NOV 2009)
9. With the help of a diagram explain LEA, LDS and LES instructions. (NOV 2008)
10. Explain the REP prefix with an example and also explain the condition for the execution
of the same. (NOV 2008)

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CHAPTER 5.
INSTRUCTION SETS
5.1 Miscellaneous data transfer instructions
5.1.1 XCHG: Exchange
Description:
The instruction XCHG swaps (exchanges) the contents of a source register or memory with the
contents of a destination register or memory. The source can be a register or a memory location.
The destination can be a register or a memory location. Both the source and destination cannot
refer to memory locations in the same instruction. They must be of the same data-type, i.e., either
of the type byte or type word.
Flags Affected: None
Syntax:
XCHG dest, src Exchange the contents of the source and destination
dest ←→ src

5.1.2 XLAT: Translate a byte

Description:
The instruction XLAT replaces a byte in the AL register with a byte from the lookup table.
Before execution of the XLAT instruction, BX should be loaded with the offset address of
lookup table in the data segment (DS) and AL with the code to be converted. When XLAT is
executed, the byte pointed to by (BX+AL) IS transferred to the AL register.
Flags Affected: None
Syntax:
XLAT Translate AL into a value in a translation table at BX
AL ← DS:[BX+(AL)]

5.1.3 IN and OUT

IN and OUT instructions are used to receive or send the data (8 bit or 16 bit) from or to external
device through the port.
IN: Input from the port:
Description:
The instruction IN reads data from the port and copies into the accumulator. An 8-bit access to
the port will place the data in AL register while a 16-bit access to port will place the data in AX
register. The instruction IN has two formats: fixed port and variable port. Each of them can again
be classified into an 8-bit or a 16-bit access.

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Flags Affected: None

Syntax:
IN accumulator, port(or DX) Input to AL ( or AX ) from I/O port.
byte: AL ← [port]
word: AL ← [port], AH ← [port+ 1]
Fixed Port Format:
The address of a port is directly specified in the instruction
Examples:
IN AL, OD8H ; input a byte from port OD8H to AL
IN AX, 09AH ; input a word from port 09Ah, 09Bh to AX
Variable Format:
The address of a port is stored in the DX register before the instruction IN is executed. The
advantage of the variable format IN instruction is that the port address can be loaded
dynamically during the execution of a program.
Examples:
MOV DX, OF70H ; Initialize DX with the port address OF70H
IN AL, DX ;reads 8-bit value from port pointed by DX in AL
IN AX, DX ; reads 16-bit value from port whose address is in DX to AX

OUT: OUTput to a port

Description:
The instruction OUT writes the contents of the accumulator (AL for 8-bit and AX for I6-bit) to a
specified port. The instruction OUT has two formats: fixed port format and variable port format.
Each of them can again be classified into an 8-bit or a I6-bit access.
Flags Affected: None
Fixed Port Format
The address of a port is directly specified in the instruction.
Syntax:
OUT port ( or DX) , accumulator Output from AL ( or AX ) to I/O port.
byte: [port] ← AL
word: [port] ← AL, [port+l] ← AH

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Examples:
OUT 0AH, AL ; copy contents of AL register to port 0AH
OUT 0CH, AX ; copy contents of AX register to port 0CH
Variable Format
The address of a port is stored in the DX register before the instruction OUT is executed. The
advantage of the variable format OUT instruction is that the port address can be loaded
dynamically during the execution of a program.
MOV DX, OF72H ; Initialize DX with the port address OF72H
OUT DX, AL ; copy contents of AL to the port pointed to by DX
OUT DX, AX ; copy contents of AX to the port pointed to by DX

5.2 Arithmetic and logic instructions

The 80x86 instruction set includes the instructions for performing arithmetic on binary, packed
BCD, and unpacked BCD numbers. Arithmetic instructions generally involve two operands, i.e.,
the source and destination. The source can be a register or a memory location or an immediate
number. The destination can be a register or a memory location. Both the source and destination
cannot refer to memory locations in the same instruction. They must be of the same data-type,
i.e., either of the type byte or type word. If a byte and a word is to be added, then the byte is
converted to a word by filling the upper byte with zeros before adding. Some instructions use
single operand and some do not use explicit operands.
Arithmetic instructions affect the CPU flags to reflect the status of operation. The various
arithmetic and logical instructions such as ADD, ADC, INC, NOT, OR, XOR, etc., are described
below.

5.2.1 ADD : Addition

Description:
The instruction ADD adds the contents of the source to the destination and places the result in
the destination. The source can be a register or a memory location or an immediate number. The
destination can be a register or a memory location. Both the source and destination cannot refer
to memory locations in the same instruction. They must be of the same data-type, i.e., either of
the type byte or type word. If a byte and a word is to be added, then the byte is converted to a
word by filling the upper byte with zeros before performing an addition operation.
Flags Affected: AF, CF, OP, PF, SF, ZF
Syntax:
ADD dest, src ; Adds two operands and stores the result in dest
dest ← (src+dest)

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Coding Example:
ADD AH, 09H ; AH ←.AH + 09H
ADD AX, 12H ; AX ←AX + 12H (12H will be converted to word)
ADD EX, AX ; EX ←EX + AX
ADD EX, [SI] ; EX ←EX + [SI] (contents of memory location pointed by
SI in Data Segment
ADD AX, AMOUNT [EX]; AX ←AX + AMOUNT [EX]
ADD AMOUNT [EX], AX; AMOUNT [EX] ←AMOUNT [EX] + AX

5.2.2 ADC :ADD with Carry

The instruction ADC adds the contents of the source to the destination and CF and places the
result in the destination. The source can be a register or a memory location or an immediate
number. The destination can be a register or a memory location. Both the source and destination
cannot refer to memory locations in the same instruction. They must be of the same data-type,
i.e., either of the type byte or type word. If a byte and a word is to be added, then the byte is
converted to a word by filling the upper byte with zeros before performing an addition operation.
ADC will be used when we add multiple precision numbers.
Flags Affected: AF, CF, OP, PF, SF, ZF
Syntax:
ADC dest, src ; Adds two operands with CF and stores the result in dest
dest ← (src+dest+ CF)
Coding Example:
ADC AH, 09H ; AH←AH + 09H + CF

ADC AX, 12H ;AX ←AX + 12H + CF, 12H is converted to a

word and added

ADC BX, AX ;BX ←BX + AX + CF

ADC BX, [SI] ; BX ← BX + [SI] + CF, contents of memory location pointed to

by SI in DS is added with BX and CF, and the sum is placed in
BX
ADC AX, AMOUNT [BX] ; AX ←AX + AMOUNT [BX] + CF
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ADD AMOUNT [BX], AX ;AMOUNT [BX] ← AMOUNT [BX] + AX + CF

INC: Increment
Description:
The instruction INC adds one to the specified register or a memory location and stores the result
in the destination. Carry flag will not be affected by the execution of this Instruction.
Flags Affected: AF, OF, PF, SF, ZF
Syntax:
INC dest ;Add one to dest (reg or mem ).
dest← (dest+ 1)
Examples:
INC AL ;AL← AL+1
INC AX ;AX← AX+1
INC SI SI ← SI + 1
INC BYTE PTR[BX] ;The byte pointed to by the register BX is incremented by 1

5.2.3 SUB :Subtraction

Description:
The instruction SUB, subtracts the source from the destination and places the result in the
destination. The source can be a register or a memory location or an immediate number. The
destination can be a register or a memory location. Both the source and destination cannot refer
to memory locations in the same instruction. They must be of the same data-type, i.e., either of
the type byte or type word. If a byte is to be subtracted from word the byte is converted to a
word by filling the upper byte with zeros before performing a subtraction.
flags Affected: AF, CF, OF, PF, SF. ZF
Syntax:
SUB dest, src ; Subtracts source from destination and keeps the resultant
in the destination
dest ← (dest-src)
Coding Example:
SUB AH, 09H ; AH ←.AH - 09H

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SUB AX, 12H ; AX ←AX - 12H (12H will be converted to word)

SUB EX, AX ; EX ←EX - AX
SUB EX, [SI] ; EX ←EX - [SI] (contents of memory location pointed by
SI in Data Segment
SUB AX, AMOUNT [EX]; AX ←AX - AMOUNT [EX]
SUB AMOUNT [EX], AX; AMOUNT [EX] ←AMOUNT [EX] - AX

5.2.4 SBB :Subtract with borrow

Description:
The instruction SBB, subtracts the source from the destination and CF and places the result in the
destination. The source can be a register or a memory location or an immediate number. The
destination can be a register or a memory location. Both the source and destination cannot refer
to memory locations in the same instruction. They must be of the same data-type, i.e., either of
the type byte or type word. If a byte is to be subtracted from word the byte is converted to a
word by filling the upper byte with zeros before performing a subtraction. The SBB is normally
used when Multiple precision subtraction is needed.
flags Affected: AF, CF, OF, PF, SF. ZF
Syntax:
SBB dest, src ; Subtracts source and CF from destination and keeps the
resultant in the destination
dest ← (dest-src-CF)
Coding Example:
SBB AH, 09H ; AH ←.AH - 09H-CF
SBB AX, 12H ; AX ←AX - 12H –CF (12H will be converted to word)
SBB EX, AX ; EX ←EX – AX-CF
SBB EX, [SI] ; EX ←EX - [SI]-CF (contents of memory location pointed
By SI in Data Segment
SBB AX, AMOUNT [EX]; AX ←AX - AMOUNT [EX]-CF
SBB AMOUNT [EX], AX; AMOUNT [EX] ←AMOUNT [EX] – AX-CF

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DEC: Decrement
Description:
The instruction DEC, subtracts one from the specified register or a memory location and stores
the result in the destination. Carry flag will not be affected by the execution of this instruction.
Flags Affected: AF, OF, PF, SF, ZF
Syntax:
DEC dest ;Subtract one from dest (reg or rim ).
dest ← (dest-l)
Examples:
DEC AL ;AL←AL-l
DEC AX ;AX←AX-l
DEC SI ;S1 ←S1 - 1
DEC BYTE PTR [BX] ;The byte pointed to by BX is decremented by 1
DEC WORD PTR [BX] ;The word pointed to by BX is decremented by 1
DEC AMOUNT [BX] ;BX is an array index, word decrement is performed
NEG: Negative
Description:
The instruction NEG, replaces the number in the destination with its equivalent 2's complement.
The destination can be a register or a memory location. Negation is performed by subtraction of
destination operand from zero and placing the result in the destination.
Flags Affected: AF, CF, OF, PF, SF, ZF
Syntax:
NEG dest Change sign of an operand.
dest ← (0 - dest )
Examples:
NEG AL ;AL 2's complement of AL
NEG BX ;BX 2's complement of BX
NEG BYTE PTR [BX] ; [BX] 2's complement of byte [BX]
NEG WORD PTR [BX] ;[BX] 2's complement of word [BX]
NEG COUNT ;COUNT = 2's complement of COUNT

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5.2.5 MUL and IMUL: Multiplication (Unsigned and Signed)

The 8086 processor performs verity of multiplication. Here for multiplication Signed and
unsigned integers are treated separately with IMUL and MUL instructions.

MUL: Unsigned Multiplication

Description:
The instruction MUL can be used to perform unsigned multiplication of the source operand with
the accumulator. The source can be a register or a memory location. If the source is a byte, then
it is multiplied by the register AL and the double length result is stored in AH and AL registers.
The most significant byte of the result is stored in AH. If the source is a word, then it is
multiplied by the register AX and the double length results stored in DX and AX registers. The
most significant word of the result is stored in DX. The operands are treated as unsigned binary
numbers. If the most significant byte of a 16-bit result or the most significant word of a 32-
bitresult is non-zero, CF and OF are set, otherwise, they are cleared. When CF and OF are set,
they indicate significant digits of the result in AH or DX. If a byte and a word is to be multiplied
then the byte is moved to a word location and the upper byte is filled with zeros. The result of the
multiplication of 8-bit numbers cannot exceed 16-bits while the result of the multiplication of 16-
bit numbers cannot exceed 32-bits.
Flags Affected : CF, OF
Flags Undefined: AF, PF, SF, ZF
Syntax
MUL src Multiply AL(AX) by unsigned value (reg/mem).
byte: AX ← (AL * src8), word: DX:AX ← (AX * src 16)
MUL BH ; AX ← AL * BH (8-bit multiplication and high byte in AH)
MUL BX ; DX:AX ←AX * BX (16-bit multiplication and high word in DX)
MUL BYTE PTR [BX]; AX ← AL * [BX] (8-bit multiplication)
MUL AMOUNT [BX] ; DX:AX ← AX * AMOUNT [BX](16-bit multiplication)
IMUL: Integer Multiply
Description:
The instruction IMUL can be used to perform signed multiplication of the source operand with
the accumulator. The source can be a register or a memory location. If the source is a byte, then
it is multiplied by the register AL and the double length result is stored in AH and AL. The most
significant byte of the result is stored in AH. If the source is a word, then it is multiplied by
register AX and the double length result is stored in DX and AX. The most significant word of
the result is stored in DX. The operands are treated as signed binary numbers. If the most
significant byte (AH) of a 16-bit result or most significant word (DX) of a 32-bit result is not the
sign extension of the lower byte of the result, then CF and OF are set, otherwise, they are
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cleared. When CF and OF are set, they indicate significant digits of the result in AH or DX. If a
byte and a word is to be multiplied, then the byte is moved to a word location and the upper byte
is filled with zeros. The result of the multiplication of 8-bit numbers cannot exceed 16-bits while
that of 16-bit numbers cannot exceed 32-bits. The negative operands are stored in 2's
complement form with MSB (sign bit) set to I to indicate a negative value.
Flags Affected: CF, OF
Flags Undefined: AF, PF, SF, ZF
Syntax:
IMUL src Multiply AL(AX) by signed value (reg/mem).
byte: AX ← (AL * src8)
word: DX:AX ← (AX * src 16)
Examp!as:
lMUL CL ;AX ←AL * CL, all (AX, AL, CL) operands are signed
lMUL BX ; DX:AX← AX * BX, all (AX,BX,DX) operands are signed
lMUL AMOUNT [BX] ;DX:AX ← AX * AMOUNT
lMUL COUNT ;8-bit signed multiplication if COUNT is defined as DB
;16-bit signed multiplication if COUNT is defined as DW

5.2.6 DIV and IDIV

The 8086 microprocessor performs the divide operation including signed and unsigned data. The
DIV instruction is used for unsigned division and IDIV is used for signed division.
DIV : Division
Description:
The instruction DIV performs an unsigned division of accumulator and its extension (DX if
necessary) by the source operand. The source can be a register or a memory location. When a
word is divided by a byte, the word must be in AX register. On 8-bit division, AL will contain
the quotient and AH will contain the remainder.
When a double word is divided by a word, the double word must be in DX and AX registers
(DX:AX) with the lower word in AX and the higher word in DX. AX will contain a I6-bit
quotient and DX will contain a 16-bit remainder after the division is performed, If the quotient is
not an integer, its fractional part is truncated, If a byte is to be divided by a byte, the dividend
byte is placed in the register AL and register AH is filled with zeros, Similarly, a division of a
word by a word requires the dividend word in AX, and the register DX is filled with zeros. An
attempt to divide by zero or if the quotient is too large to fit in AL (8-bit division) or AX
(16·bitdivision), then 80x86 will generate an interrupt of type 0 (INT 0OH),

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Flags Affected : None

Flags Undefined: AF, CF, OF, PF, SF, ZF
Syntax
DIV src Divide accumulator by unsigned value stored in (reg/mem).
Division by zero or result too large causes INT 00H
byte: AL ← (AX / src8);
AH ← (AX MOD src8)
word: AX ← (DX:AX / src 16);
DX ← (DX:AX MOD srcI6).
Examples:
DIV CL ; 8-bit division, unsigned word in AX and unsigned byte in CL
AL ← quotient, AH ← remainder
IDIV CX ; 16-bit division, unsigned double word DX:AX and word in CX
AX ← quotient, DX ←remainder

IDIV: Signed Divide

Description:
The instruction IDIV is used to divide a signed word by a signed byte or a signed double word
by a signed word. The source can be a register or a memory location. When a signed word is
divided by a byte, the word must be in AX register. On 8-bit division, AL register will contain
signed quotient and AH register will contain signed remainder. When a signed double word is
divided by a signed word, the double word must be in DX and AX registers (DX:AX) with the
lower word in AX and the higher word in DX. AX will contain a 16-bitsigned quotient and DX
will contain a 16-bit signed remainder after the division is performed. If the quotient is not an
integral number, it is truncated, and not rounded.
If a byte is to be divided by a byte, the dividend byte is placed in AL register and AH register is
filled with zeros. Similarly, a division of a word by a word requires the dividend word in AX and
DX register is filled with zeros. An attempt to divide by zero or if a quotient is too large to fit in
AL ( > 127 or < -128 in case of 8 bit division) or AX ( > 32767 or < -32768 in case of 16-bit
division), then 80x86 generates an interrupt of type 0 (INT 0).
Flags Affected : None
Flags Undefined: AF, CF, OF, PF, SF, ZF
Syntax:
IDIV src Divide accumulator by signed value.

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Division by zero or result too large causes INT 00H

byte: AL ← (AX / src8);
AH ← (AX MOD src8)
word: AX ← (DX:AX / src 16);
DX ← (DX:AX MOD srcI6).
Examples:
IDIV CL ; 8-bit division, signed word in AX and signed byte in CL
AL ← quotient, AH ← remainder
IDIV CX ; 16-bit division, signed double word DX:AX and word in CX
AX ← quotient, DX ←remainder

5.2.7 CMP: Compare

Description:
The instruction CMP, compares a byte or a word in a specified destination with a byte or a word
in a specified source respectively. The source can be a register or a memory location or an
immediate number. The destination can be a register or a memory location" Both the source and
destination cannot refer to memory locations in the same instruction. They must be of the same
data-type, i.e., either of the type byte or type word.
If a byte and a word is to be compared, the byte is converted to a word by filling the upper byte
with zeros before compare operation is performed. The instruction compare performs a non
destructive subtraction (destination - source, i.e., destination is not modified) and sets the
flags based on the magnitude of the operands.
The compare instruction is used with conditional jump instructions.
Flags Affected: AF, CF, OF, PF, SF, ZF
Syntax
CMP dst, src ; Non destructive sub operation compares the
content of source with the destination And set or
reset the flag registers.
Examples:
CMP AH, BL ;compare AH with BL and sets the flags
CMP AH, 25 ;compare AH with 25 and sets the flags
CMP BX, AX ; compare BX with AX and sets the flags
CMP AX, COUNT ; compare AX with COUNT and sets the flags

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CMP COUNT, AX ;compare COUNT with AX and sets the flags

CMP AMOUNT [BX], CX ; compare AMOUNT [BX] with CX and sets the

5.2.8 TEST
TEST: Test and Set flags
Description:
The instruction TEST performs the logical 'and' of two operands (word or byte) and updates the
flags, but neither of the operands are modified. The source can be a register or a memory
location or an immediate number. The destination can be a register or a memory location. Both
the source and destination cannot refer to memory locations in the same instruction. They must
be of the same data-type, i.e., either of the type byte or type word. CF and OF are set to zero on
execution of this instruction. PF has meaning only for the lower eight bits of the destination.
Flags Affected: CF, OF, PF, SF, ZF
Syntax:
TEST dest, src ;Non destructive AND ;flags ← (set as for dest & src)

5.3 BCD arithmetic instructions

5.3.1 DAA
DAA: Decimal Adjust for Addition
Description:
The instruction DAA, can be used to change the content of AL register to a pair of valid packed
decimal digits. This instruction should be issued after an addition instruction. On execution of
this instruction, if the lower nibble in AL register is greater than 9 or the AF flag was set, then 6
will be added to the AL register and AF is set. If the result of the upper nibble in AL register is
greater than 9 or CF flag is set by the addition, then 60 is added to the AL register and the carry
flag (CF) is set.
Flags Affected: AF, CF, PF, ZF
Flags Undefined: OF.
Syntax:
DAA ;Adjust after BCD addition
AL ← ( AL corrected for BCD addition)
Example
ADD
DAA AL = 01000010 = 42 BCD, BL = 00101000 = 29 BCD
AL = 01101011 = 6BH

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add 6 to AL because 1011>9 therefore AL=AL + 6=71 BCD

5.3.2 DAS
DAS Decimal Adjust for Subtraction.
Description:
The instruction DAS, can be used to change the content of AL register to a pair of valid packed
decimal digits. This instruction should be issued after the subtraction instruction. On execution
of this instruction, if the lower nibble in AL register is greater than 9 or AF flag was set, then 6
will be subtracted from AL register and AF flag is set. If the result of upper nibble in AL register
is greater than 9 or CF flag is set by the subtraction, then 60 is subtracted from the AL register
and the carry flag (CF) is set.
Flags Affected : AF, CF, PF, ZF
Flags Undefined: OF
Syntax
DAS ;Adjust after BCD subtraction
AL ← ( AL corrected for BCD subtraction)
Example
;AL=1 0 0 0 0 1 0 1 85 (assumed),
;BL=0 1 0 1 0 1 1 1 57(assumed)
SUB AL, BL ; AL 0 0 1 0 1 1 1 0 2EH
DAS ; subtract 6 from AL because 1110>9. AL = AL - 6 28 BCD

5.4 ASCII arithmetic instructions: The 8086 processor has 4 instructions for unpacked BCD
arithmetic operations. They are AAA for addition, AAS for subtraction, AAM for multiplication
and AAD for division. The first three instructions are used after the arithmetic operation whereas
the last one is used before the arithmetic operation.

5.4.1 AAA :ASCII Adjust for Addition

Description:
The instruction AAA can be used to convert the contents of the AL register to BCD result. The
higher nibble of the AL register are filled with zeros. This instruction should be executed after
the ADD instruction and result is placed in the AL register.
Function:
I. Clear the high order nibble of AL ( AL = AL & OFH )
2. if( lower nibble of AL > 9 or AF = I ) then

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a. Add 6 to AL ( AL = AL + 6 )
b. Add I to AH ( AH =AH + I )
c. Set AF and CF to one ( AF = CF = I ).
d. Clear high order nibble of AL ( AL = AL & OFH )
Flags Affected: AF, CF
Syntax:
AAA Adjust after ASCII addition.
AL ← (AL corrected for ASCII addition)
Examples:
AH 00H, AL=0BH
AAA AH OlH, AL=01H
AH 03H, AL=02H Flag AF=1
AAA AH 04H, AL=08H

5.4.2 AAS: ASCII adjust for Subtraction.

Description:
The instruction AAS can be used to convert the contents of the AL register to the BCD result.
The higher nibble of the AL register are filled with zeros. This instruction should be executed
after the SUB instruction and the result is placed in the AL register.
Function:
1. Clear the high order nibble of AL ( AL = AL & OFH )
2. if( lower nibble of AL > 9 or AF = 1 ) then
a. Subtract 6 from AL ( AL =AL - 6 )
b. Subtract 1 from AH ( AH =AH· 1 )
c. Set AF and CF to one ( AF = CF = 1 )
d. Clear high order nihble of AL ( AL = AL & OFH )
Flags Affected: AF, CF
Syntax:
AAS Adjust after ASCII subtraction.

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AL ← (AL corrected for ASCII subtraction)

AH 02H, AL=0BH
AAS AH OlH, AL=05H

5.4.3 AAM: ASCII Adjust for Multiplication

Description:
The instruction AAM, can be used t9 convert the result of the multiplication of two valid
unpacked BCD numbers. This Instruction should be issued after the multiplication instruction.
The operation of MUL on unpacked BCD numbers is always less than 100, hence, the result will
be in the register AL. The binary number In AL register is divided by 10 and the quotient is
stored in the register AL and remainder is stored in the AH register.
Function:
a) AH =AL MOD 10
b) AL = AL / 10 ( only integer part is considered)
Flags Affected: PF, SF, ZF
Syntax:
AAM Adjust after ASCII multiplication.
AH:AL ← (AH:AL corrected for ASCII multiplication)
Examples:
AL=00000110 = unpacked BCD 6
BH=00001000 = unpacked BCD 8
MUL BH AL * BH = 00110000 = 48 decimal
AAM AH=00000100 = 04 (Decimal), AL = 00001000=08(Decimal)

5.4.4 AAD: ASCII Adjust for Division

Description:
The instruction AAD, can be used to convert the unpacked BCD digit in AH and AL registers to
the equivalent binary number in the register AL. This instruction should be issued before the
division instruction. The division instruction will place the quotient in the AL register and
remainder in AH register. The high order half bytes (nibble) of AH and AL are filled with zeros.
Flags Affected: PF, SF, ZF
Function:
1. AL = AH * 10 + AL
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2. AH=00H
Syntax:
AAD Adjust before ASCII division.
AH:AL ← (AH:AL prepared for division of ASCII codes)

Examples:
AH =03H, AL = 09H
AAD AH =00H, AL = 39H
AX 0205H unpacked BCD for 25 decimal
AAD AX 19H = 25 decimal, BL = 7 decimal
DIV BL Divide AX by BL
AL=quotient=3 unpacked BCD, AH=remainder after division =4

5.5 Basic Logic instructions

Basic logical operations like AND, OR and NOT are performed with respective instructions. In
addition to the basic logic operations the processor performs XOR operations.

5.5.1 OR: Logical OR

Description:
The instruction OR performs the logical 'or' of two operands ( word or byte) and places the result
in the destination. Each bit in the result is set to 1 if anyone of the corresponding bits in the
original operands are 1, otherwise, bit is cleared. The result of each bit follows the truth table of
two input OR gate. The source can be a register or a memory location or an immediate number.
The destination can be a register or a memory location Both the source and destination cannot
refer to memory locations in the same instruction. They must be of the same data-type, i.e., either
of the type byte or type word. CF and OF are set to zero on execution of this instruction. PF has
meaning only for the lower eight bits of the destination.
Flags effected: CF, OF, PF, SF, ZF
Syntax:
OR dest, src Inclusive OR ( set dest bits which are in src ).
dest ← (dest | src )
Coding Examples:
OR AH, CH AH ← bit wise 'or' of AH and CH
OR BX, OOFFH BX ← BX | OOFFH

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OR CX, [SI] OR CX with word at offset location pointed to by SI

i.e CX ← CX | [SI]

5.5.2 AND: Logical AND

Description:
The instruction AND performs the logical 'and' of two operands (word or byte) and places the
result in the destination. Each bit in the result is set to 1 if both the corresponding bits of the
original operands are 1, otherwise. the bit is cleared. The result of each bit follows the truth table
of the two input AND gate. The source can be a register or a memory location or an immediate
number. The destination can be a register or a memory location. Both the source and destination
cannot refer to memory locations in the same instruction. They must be of the same data-type,
i.e., either of the type byte or type word. This instruction can also be used for masking the bits in
the destination. CF and OF are set to zero on execution of this instruction. PF has meaning only
for the lower eight bits of the destination.
Flags Affected: CF, OF, PF, SF, ZF
Syntax:
AND dest, src Logical AND ( mask or reset dest bits which are zeros in
src ). dest ← (dest & src ).
Coding Examples:
AND AH, CH AH ← bit wise 'and' of AH and CH
AND BX, OOFFH BX ← BX & OOFFH
AND CX, [SI] AND CX with word at offset location pointed to by SI
i.e CX ← CX & [SI]

TEST: Test and Set Flags

Description:
The instruction TEST performs the logical 'and' of two operands (word or byte) and updates the
flags, but neither of the operands are modified. The source can be a register or a memory
location or an immediate number. The destination can be a register or a memory location. Both
the source and destination cannot refer to memory locations in the same instruction. They must
be of the same data-type, i.e., either of the type byte or type word. CF and OF are set to zero on
execution of this instruction. PF has meaning only for the lower eight bits of the destination.
Flags Affected: CF, OF, PF, SF, ZF
Syntax:
TEST dest, src Non destructive AND
Flags ← (set as for dest & src)

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Example:
TEST AL, BL ; If AL=10101010 binary and BL=11000110 binary then
AL and BL will retain the same content But
CF=OF=ZF=0, PF=SF=1

5.5.3 NOT: Logical NOT

Description:
The instruction NOT inverts each bit (generates one's complement) of a byte or a word and
places the result in the destination. The result of each bit follows the truth table of the NOT gate.
Destination can be a register or a memory location.
Flags Affected: None
Syntax:
NOT dest Converts dest to its I's complement (toggle every bit in dest)
dest ← (~dest)

5.5.4 XOR: Logical Exclusive OR

Description:
The instruction XOR performs the logical 'xor' of two operands (word or byte) and places the
result in the destination. Each bit in the result is set to I if anyone of the corresponding bits in the
original operands are different, otherwise, bit is cleared. The result of each bit follows the truth
table of the two input XOR gate. The source can be a register or a memory location or an
immediate number. The destination can be a register or a memory location. Both the source and
destination cannot refer to memory locations in the same instruction. They must be of the same
data-type, i.e., either of the type byte or type word. CF and OF are set to zero on execution of
this instruction. PF has meaning only for the lower eight bits of the destination.
Flags Affected: CF, OF, PF, SF, ZF
Syntax:
XOR dest, src ; Exclusive OR ( toggle dest bits which are in src ).
dest ← (dest^ src ).

5.6 Shift and Rotate instructions

Shift instructions are used to shift the bits of the registers to either left or right to the specific
positions mentioned in the count.

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5.6.1 SHL: Shift Logical Left.

Description:
The instruction SHL shifts the destination byte or a word left, by the number of bits specified in
the count. Zeros are shifted into the right most bit (LSB). MSB bits are shifted out of the left
most bit and placed in the CF. CF will contain the bit shifted in from the MSB. Bit stored in CF
previously will be lost. The operation performed by this Instruction is shown in the figure below.

CF←MSB LSB←0
Figure:5.1 working of SHL instruction.

The destination can be a byte or a word operand. It can be a register (8-bit or 16-bit) or a
memory location. The count operand (byte) can be a register (CL) or an immediate value. If
count is equal to one, it may be specified directly in the instruction. If count is greater than one, it
may be specified in the CL register prior to its usage, however, advanced processors allow the
users to specify count greater than one directly in the instruction itself.
The value of the immediate count can range from 1 to 15. The flexibility of using CL as a count
in this instruction is that count value can be dynamically calculated as the program executes This
instruction produces the effect of multiplying an unsigned number by the power of two (i.e
destination * 2count). If count is one, it is equivalent to multiplying the number by two. Shifting
the number by 2 bits left multiplies the number by 4. Shifting the number by 3 bits left multiplies
the number by 8, etc. The machine code generated by the assembler for SAL (shift arithmetic
left) is same as the SHL instruction.
Flags Affected : CF, OF, PF (if destination is AL), SF, ZF
Flags Undefined: AF
Syntax:
SHL dest, count ; The destination byte or a word is shifted left by the
number of bits specified in count
Example:
If the value of AL is 25H and CL is 02 then SHL instruction woks as follows
SHL AL, CL
AL= 0 0 1 0 0 1 0 1
CF=0
AL= 0 1 0 0 1 0 1 0

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CF=0
AL= 1 0 0 1 0 1 0 0
After executing SHL instruction the value of AL=94H

5.6.2 SHR: Shift Logical Right.

Description:
The instruction SHR shifts the destination byte or a word right, by the number of bits specified in
the count. Zeros are shifted into the left most bit (MSB). LSB bits are shifted out of the right
most bit and placed in the CF. CF will contain the bit shifted in from the LSB. Bit stored in CF
previously will be lost. The operation performed by this Instruction is shown in the figure 5.2
below.
0→ MSB LSB → CF
Figure:5.2 working of SHR instruction.
The destination can be a byte or a word operand. It can be a register (8-bit or 16-bit) or a
memory location. The count operand (byte) can be a register (CL) or an immediate value. If
count is equal to one, it may be specified directly in the instruction. If count is greater than one, it
may be specified in the CL register prior to its usage, however, advanced processors allow the
users to specify count greater than one directly in the instruction itself.
The value of the immediate count can range from 1 to 15. The flexibility of using CL as a count
in this instruction is that count value can be dynamically calculated as the program executes This
instruction produces the effect of deviding an unsigned number by the power of two (i.e
destination / 2count). If count is one, it is equivalent to deviding the number by two. Shifting the
number by 2 bits left devides the number by 4. Shifting the number by 3 bits left devides the
number by 8, etc.
Flags Affected : CF, OF, PF (if destination is AL), SF, ZF
Flags Undefined: AF
Syntax:
SHR dest, count ; The destination byte or a word is shifted right by the
number of bits specified in count
Example:
If the value of AL is 25H and CL is 02 then SHR instruction woks as follows
SHR AL, CL
AL= 0 0 1 0 0 1 0 1
CF=1

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AL= 0 0 0 1 0 0 1 0
CF=0
AL= 0 0 0 0 1 0 0 1
After executing SHR instruction the value of AL=09H

5.6.3 SAR: Shift Arithmetic Right

Description:
The instruction SAR shifts the signed destination byte or a word right by the number of bits
specified in the count. As the destination operand bits are shifted right, the bit value in MSB(sign
bit) is retained(preserved) so that the sign bit will not change. LSB bits are shifted out of the
right most bit and placed in the CF. CF will contain the bit shifted in from the LSB. Bit stored in
CF previously will be lost.
The destination can be a byte or a word operand. It can be a register (8-bit or 16-bit) or a
memory location. The count operand (byte) can be a register (CL) or an immediate value. If
count is equal to one, it may be specified directly in the instruction. If count is greater than one, it
may be specified in CL register prior to its usage, however, advanced processors allow the users
to specify count greater than one directly in the instruction itself. The value of the immediate
count can range from 1 to 15. The flexibility of using CL as a count in this instruction is that
count value can be dynamically calculated as the program executes. This instruction produces the
effect of dividing signed number by the power of two (i.e destination / 2count). If count is one it is
equivalent to dividing the signed number by two. Shifting the number by 2 bits right divides it by
4. Shifting the number 3 bits right divides the number by 8, etc.
Flags Affected : CF, OF, PF (if destination is 8-bit), SF, ZF
Flags Undefined: AF
MSB LSB → CF
Figure:5.3 working of SAR instruction.

Syntax:
SAR dest, count ;The destination byte or word is shifted right, by the
number of bits specified in count with preserving sign bit.
Example:
If the value of AL is 25H and CL is 02 then SAR instruction woks as follows
SAR AL, CL
AL= 0 0 1 0 0 1 0 1
CF=1

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AL= 0 0 0 1 0 0 1 0
CF=0
AL= 0 0 0 0 1 0 0 1
After executing SAR instruction the value of AL=09H
Where as
If the value of AL is 85H and CL is 02 then SAR instruction woks as follows
SAR AL, CL
AL= 1 0 0 0 0 1 0 1
CF=1
AL= 1 1 0 0 0 0 1 0
CF=0
AL= 1 1 1 0 0 0 0 1
After executing SAR instruction the value of AL=D1H

5.6.4 ROL: Rotate Left

Description:
The instruction ROL rotates the destination byte or a word left by the number of bits specified in
the count.MSB bits are shifted into the right most bit (LSB) and into the CF. CF will contain the
bit shifted in from the MSB. Bit stored in CF previously will be lost. The operation performed by
this instruction is shown in the figure 5.4 below
CF←MSB LSB

Figure 5.4 ROL instruction

The destination can be a byte or a word operand and it can be a register (8-bit or 16-bit) or a
memory location. The count operand (byte) can be a register (CL) or an immediate value. If
count is equal to one, it may be specified directly in the instruction. If count is greater than one, it
may be specified in the CL register prior to its usage, however, advanced processors allow the
user to specify count greater than one directly in the instruction itself. The value of the
immediate count can range from 1 to 15. The flexibility of using CL register as a count in this
instruction is that the count value can be dynamically calculated as the program executes.
Flags Affected: CF, OF
Syntax:
ROL dest, count ; The destination byte or a word is rotated left by the

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number of bits specified in count

Example
If the value of AL is 85H and CL is 02 then ROL instruction woks as follows
ROL AL, CL
AL= 1 0 0 0 0 1 0 1
CF=1
AL= 0 0 0 0 1 0 1 1
CF=0
AL= 0 0 0 1 0 1 1 0
After executing ROL instruction the value of AL=16H

5.6.5 ROR: Rotate Right

Description:
The instruction ROR rotates the destination byte or a word right by the number of bits specified
in the count. LSB bits are shifted into the left most bit (MSB) and into the CF. CF will contain
the bit shifted in from the LSB. Bit stored in CF previously will be lost. The operation performed
by this instruction is shown in the figure 5.5 below.
The destination can be a byte or a word operand. It can be a register (8-bit or I6-bit) or a memory
location. The count operand (byte) can be a register (CL) or an immediate value. If count is equal
to one, it may be specified directly in the instruction. If count is greater than one, it may be
specified in the CL register prior to usage, however. advanced processors allow the users to
specify count greater than one directly in the instruction itself. The value of the immediate count
can range from 1 to 15. The flexibility of using the CL register as a count in this instruction is
that the count value can be dynamically calculated as the program executes.
Flags Affected: CF, OF

MSB LSB → CF
Figure 5.5 ROR instruction
Syntax:
ROR dest, count ; The destination byte or a word is rotated right by the
number of bits specified in count
Example
If the value of AL is 85H and CL is 02 then ROL instruction woks as follows

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ROR AL, CL
AL= 1 0 0 0 0 1 0 1
CF=1
AL= 1 1 0 0 0 0 1 0
CF=0
AL= 0 1 1 0 0 0 0 1
After executing ROL instruction the value of AL=61H

5.6.6 RCL: Rotate through carry Left.

Description:
The instruction RCL rotates the destination byte or a word left through the carry bit by the
number of bits specified in count. MSB bits are shifted into the CF. CF bit is shifted out and
placed in LSB. CF will contain the bit shifted in from the MSB. The operation performed by this
instruction is shown in the figure 5.6 below
CF←MSB LSB

Figure 5.6 RCL instruction.

The destination can be a byte or word operand. It can be a register (8-bit or 16-bit) or a memory
location. The count operand (byte) can be a register (CL) or an immediate value. If count is equal
to one, it may be specified directly in the instruction. If count is greater than one, it may be
specified in the CL register prior to usage, however, advanced processors allow the user to
specify count greater than one directly in the instruction itself. The value of the immediate count
can range from I to 15. The flexibility of using the CL register as a count in this instruction is
that the count value can be dynamically calculated as the program executes.
Flags Affected: CF, OF

Syntax:
RCL dest, count ; The destination byte or a word is rotated left
through carry by the number of bits specified
in count
Example
If the value of AL is 85H, CF=1 and CL is 02 then RCL instruction woks as follows
RCR AL, CL

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CF=1
AL= 1 0 0 0 0 1 0 1
CF=1
AL= 1 1 0 0 0 0 1 0
CF=0
AL= 1 1 1 0 0 0 0 1
After executing RCL instruction the value of AL=E1H

5.6.7 RCR : Rotate through Carry Right

Description:
The instruction RCR rotates the destination byte or a word right by the number of bits specified
in the count through carry bit. LSB bits are shifted into CF. CF bit is shifted out and placed in
MSB. CF will contain the bit shifted in from the LSB. The operation performed by this
instruction is shown in the figure 5.7 below.

MSB LSB →CF

Figure 5.7 RCR instruction.
The destination can be a byte or a word operand. It can be a register (8-bit or 16-bit) or a
memory location. The count operand (byte) can be a register (CL) or an immediate value. If
count is equal to one, it may be specified directly in the instruction. If count is greater than one, it
may be specified in the CL register prior to usage, however, advanced processors allow the user
to specify count greater than one directly in the instruction itself. The value of the immediate
count can range from 1 to 15. The flexibility of using the CL register as a count in this
instruction is that the count value can be dynamically calculated as the program executes.
Flags Affected: CF, OF
Syntax:
RCR dest, count ; The destination byte or a word is rotated right
through carry by the number of bits specified
in count
Example
If the value of AL is 85H, CF=1 and CL is 02 then RCR instruction woks as follows
RCL AL, CL

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CF=1
AL= 1 0 0 0 0 1 0 1
CF=1
AL= 0 0 0 0 1 0 1 1
CF=0
AL= 0 0 0 1 0 1 1 1
After executing RCL instruction the value of AL=17H

5.7 String comparison Instructions

5.7.1 CMPS: Compare String (Byte, Word or Doubleword)

Description
This instruction is used to compare the string data stored in the memory location DS:SI (input
string) in the data segment with ES:DI (output string) in the extra segment. The result will be
seen in the flag registers. Basically the ASCII code of the string data in ES:DI will be subtracted
from the ASCII code of string data in the DS:SI. If the String data is defined as a byte then
CMPSB will be used whereas if the string data is defined as a word then CMPSW will be used.
These instructions do not require any source or destination operators. If the DF=0 then SI and DI
will be automatically incremented by one for a byte string data or two for a word string data
otherwise SI and DI will be decremented.
Syntax

CMPS dst, src

CMPSB
CMPSW
5.7.2 SCAS Compare the string data stored in AL with destination
This instruction is used to compare the string data stored in AL with ES:DI (output string) in the
extra segment. The result will be seen in the flag registers. Basically the ASCII code of the string
data in ES:DI will be subtracted from the ASCII code of string data in AL. If the String data is
defined as a byte then SCASB will be used whereas if the string data is defined as a word then
SCASW will be used. These instructions do not require any source or destination operators. If
the DF=0 then DI will be automatically incremented by one for a byte string data or two for a
word string data otherwise DI will be decremented.
Syntax

SCAS dst, src

SCASB

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SCASW
REP: Repeat
Description:
The instruction REP is used in conjunction with the string instructions and is interpreted as
"repeat while not end-of-string"(CX not equal to 0). To repeat string operations for a byte or a
word, the number of elements to be processed is placed in the register CX which functions as a
counter. String instructions must lie prefixed with the instruction REP to perform repeated
operations.
Repeat string sequences are interruptible the processor will recognize the interrupt before
processing the next string element. Upon return from the interrupt, the repeat operation is
resumed from the point of interruption.
Function:
While( CX<>0 )
1. Execute the string instruction;
2. CX←CX-1
Syntax:
REP ;Repeat: Perform string operation repeatedly.
; CX←CX-1 string operation repeats while( CX<>0)

REPE : Repeat while equal/REPZ :Repeat while zero ;

Description:
The instruction REPE/REPZ is used in conjunction with the string instructions and is interpreted
as "repeat while not end-of-string and string is equal" (CX not equal to 0 and ZF = I). These
instructions are used with the instructions CMPS, SCAS and their variants (eg. SCASB).
To repeat string operations for a byte or a word the number of elements to be processed is placed
in the register CX which functions as a counter. String instructions must be prefixed with the
instruction REPE/REPZ to perform string operations repeatedly. Assembler generates the same
machine code for the instructions REPE and REPZ.
Repeat string sequences are interruptible; the processor will recognize the interrupt before
processing the next string element. Upon return from the interrupt, the repeat operation is
resumed from the point of interruption.
Function:
While( CX "#0 and equal comparison (ZF= I) )
1. Execute the string instruction;
2. CX ~ CX - I;

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Syntax:
REPE/ REPZ Repeat: Perform string operation repeatedly.
CX ← (CX - 1) string operation repeats while (CX<>0 and
equal comparison(ZF= 1) )
Flags Affected: None

5.8 Assignment Questions.

Questions carrying 2 marks
1. Explain AAS instruction. (NOV 2012)
2. Write the necessary instruction to set 4th and 6th bit of a register DH without affecting
remaining bits. (NOV 2010)
3. Discuss the role of Direction flag in string instructions. (NOV 2010)
4. If AL=86H, evaluate TEST AL, 12H
5. What are AAA and AAM instructions? Mention the register used as source and
destination register for the same. (NOV 2008)
6. Differentiate between NOT BX and NEG BX. (NOV 2007)
7. Differentiate between AND and TEST instructions.
8. If AL=85 and CL=4 What will be AL after executing SHL AL, CL
9. If AL=74 and CL=3 What will be AL after executing SHR AL, CL
10. If AL=39 and CL=2 What will be AL after executing SAR AL, CL
11. If AL=85 and CL=3 What will be AL after executing ROL AL, CL
12. If AL=85 and CL=4 What will be AL after executing ROR AL, CL
13. If AL=29 and CL=2 and CF=1 What will be AL after executing RCL AL, CL
14. If AL=96 and CL=3 and CF=0 What will be AL after executing RCR AL, CL
15. Differentiate between CMPS and SCAS instructions.

Essay type Questions.

1. Explain DAA and DAS instruction with an example.( NOV 2012)
2. Explain the various Rotate instructions with example.(NOV 2012)
3. Explain the following Instruction. (NOV 2012)
a. OR
b. XOR
c. ADC
d. INC
e. DEC
4. Explain any three string instructions.( NOV 2011)
5. Write an assembly level program to add and subtract 2 BCD numbers
6. Write an assembly level program to arrange the numbers in an ascending order.
7. Write an assembly level program to find out a maximum and minimum number in an
array.

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8. Explain MUL and DIV instructions.( NOV 2011)

9. Compare MUL with IMUL and DIV with IDIV instructions.
10. Discuss various Shift instructions with the help of a diagram. (NOV 2011)
11. Compare ADD and ADC instructions. (NOV 2010)
12. Write an assembly level program to add 9999H and 31H using BCD arithmetic. Discuss
the output.
13. Explain XLAT and XCHG instructions. (NOV 2009)
14. What will be stored in AL and CL after execution of following sequence of
commands?(NOV 2009)
MOV AL, 0EBH
OR AL, 10H
AND AL, 0A3H
MOV CL, AL
NOT CL
XOR CL, AL
15. Explain the REP prefix with example and also explain the condition to execute the
same.(NOV 2008)
16. Develop a sequence of instructions that set the right most 4 bits of AX, clear the leftmost
3 bits of AX and invert remaining bit.
17. Write an assembly level program to find the GCD and LCM of 2 numbers.
18. Given AL=43H What will be the value of AL after the execution of the following
instruction.
SAR AL, 01H
RCL AL, 01H
ROR AL, 01H

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CHAPTER 6
JUMP INSTRUCTIONS
Jump instructions are also called branch control instructions. A branch instruction transfers
control from the normal sequence of instruction execution to the specified destination or target
instruction. These instructions are broadly categorized as, unconditional branch and conditional
branch instructions. The unconditional branch instructions transfer control to the target location.
The target operand may be obtained from the instruction itself (for direct jump) or from the
memory or a register referenced by the instruction (for indirect jump).
Branch instructions do not affect the CPU flags. The conditional jump instructions transfer
control to the target location if some specified condition is met or satisfied. JA, JB, JE, etc., are
some examples of conditional branch/jump instructions. Conditional instructions are usually
used after a compare instruction or a subtraction instruction. Some branch instructions modify IP
to transfer control known as near jump or jump within a segment or intra-segment jump, while,
other instructions modify both the IP and CS registers to transfer control, known as far jump or
inter-segment jump.

6.1 Unconditional jump instructions

Intel 8086 has one unconditional jump instruction which is called JMP.
Description:
The instruction JMP unconditionally transfers control to the target location. The target operand
may be obtained from the instruction itself(for direct jump) or from the memory or a register
referenced by the instruction (for indirect jump). If the target is in the same code segment as the
instruction JMP, it requires only the instruction pointer (IP) to be changed to transfer control to
the target location. Such a jump is called as intra segment jump (near jump).
If the target for the instruction JMP is in a different code segment (CS) from that containing the
instruction JMP, then IP and CS will be changed to transfer control to the target location. Such a
jump is called as far or inter·segment jump. The jump can be a forward jump or a backward
jump, depending on the sign of the displacement
Flags Affected: None
Syntax:

JMP target Unconditional transfer of control to the label.

short : IP ← (IP+(target displacement sign extended))
near : IP ← (IP+(target displacement))
indirect : IP ←(register or value in memory )
far : CS ←(target_segment)
IP ← (target_offset)

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Different forms of instruction JMP are,

1. Intra-Segment Jumps
2. Inter Segment Jumps

Intra-Segment Jump
Direct Short Jump: (JMP short label)
The target location for a short jump should be in the range of -128 to + 127 bytes from the
current instruction. The target address is computed by adding instruction pointer (IP) and the
sign extended displacement (label of the jump instruction)
Example:
JMP SHORT NEXT I ; NEXTI is a label to which control has to be transferred
Direct Near Jump: (JMP near label)
The target (label) can be anywhere in the current code segment. The target address for jump is
computed by adding IP with the displacement specified in the instruction. The target location for
near jump should be in the range of -32768 to +32767 bytes from the current instruction.
Example:
JMP NEAR PTR NEXT I NEXT I label can be located anywhere in the current segment in
which JMP is located and transfers control to the target.
Indirect Near Jump: (JMP word register/pointer)
This instruction transfers control to the target location by loading IP with the contents of a
specified 16-bit register or contents of the memory specified in the instruction.
Example
JMP BX; ; IP ← BX, loads IP with BX

Inter-Segment Jumps
Direct Far Jump: (JMP far label)
This instruction transfers control to the target location in a different code segment. This is
performed by loading CS with the segment number in which the target exist and IP with the
offset address of an instruction to which control is to be transferred in the new code segment.
The target address loaded in CS and IP are the part of the instruction itself:
Example:
JMP WORD PTR[SI] ;IP ←word pointed to by SI in DS ; DS: [SI]
;CS← word pointed to by SI +2 in DS ; DS: [SI+2]

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6.2 Conditional jump instructions

The conditional jump instructions transfer control to the target location if some specified
condition is met or satisfied, JA, JB, JE etc. are some examples of conditional branch/jump
instructions. Conditional instructions are usually used after a compare instruction or a subtraction
instruction.
Syntax:
J(condition) Short_Label short label Jump when a condition is met
IP ← (IP+(8-bit displacement sign extended to 16-bits)

JA :Jump on Above
JNBE: Jump on Not Below or Equal
Description:
The instructions JA/JNBE transfer control to the target location if carry flag (CF) and zero flag
(ZF) are reset. If this condition fails, the instruction following JA/JNBE will be executed. The
displacement of the target instruction must be within the range of -128 to + 127 bytes from the
address of the instruction before/after the JA/JNBE instruction. The assembler generates the
same machine code for each one of these two mnemonics.
Syntax:
JA / JNBE short label ; Jump if CF=0 and ZF=0
Flags Affected: None
Function:
if( CF = 0 and ZF = 0 ) then
IP ← IP + displacement ( 8-bit sign extended to 16-bit )
else
execute the next instruction in the sequence

JAE Jump on Above or Equal/JNB Jump on Not Below/JNC Jump on Not Carry
Description:
The instructions JAE/JNB/JNC transfer control to the target location if carry flag (CF) is reset. If
this condition fails, the instruction following JAE/JNB/JNC will be executed. The displacement
of the target instruction must be within the range of -128 to +127 bytes from the address of the
instruction before/after the JAE/JNB/JNC instruction. The assembler generates the same
machine cede for each one of these three mnemonics.

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Syntax:
JAE / JNB / JNC short label ; Jump if above or equal (CF=0)
Flags Affected: None
Function:
if( CF = 0 ) then
IP ← IP + displacement (8-bit sign extended to 16-bit)
else
execute the next instruction in the sequence

JB Jump on Below/ JNAE Jump on Not Above or Equal/JC Jump on Carry

Description:
The instructions JB/JNAE/JC transfer control to the target location if carry flag (CF) is set. If this
condition fails, the instruction following JB/JNAE/JC will be executed. The displacement of the
target instruction must be within the range of -128 to +127 bytes from the address of the
instruction before/after the JB/JNAE/JC instruction. The assembler generates the same machine
code for each one of these three mnemonics.
Syntax:
JB / JNAE / JC short label; Jump if below/ jump if carry is set (CF=1)
Flags Affected: None
Function:
if( CF = 1 ) then
IP ← IP + displacement ( 8-bit sign extended to 16-bit)
else
execute the next instruction in the sequence

JE: Jump on Equal/ JZ: Jump on Zero

Description:
The instructions JE/JZ transfer control to the target location if zero flag (ZF) is set. If this
condition fails, the next instruction following JE/JZ will be executed. The displacement of the
target instruction must be within the range of-128to + 127 bytes from the address of the
instruction before/after the JE/JZ instruction. The assembler generates the same machine code
for each one of these two mnemonics.
Syntax:

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JE/ JZ short label ; Jump if the ZF=1

Flags Affected: None
Function:
if(ZF = I ) then
IP ← IP + displacement ( 8-bit sign extended to 16-bit)
else
execute the next instruction in the sequence

JG : Jump on Greater than/JNLE: Jump on Not Less or Equal

Description:
The instructions JG/JNLE transfer control to the target location if the sign flag is same as the
overflow flag (OF) and zero flag (ZF) is reset. If this condition fails, the instruction following
JG/JNLE will be executed. The displacement of the target instruction must be within the range of
-128 to +I27 bytes from the address of the instruction before/after the JG/JNLE instruction. The
assembler generates the same machine code for each one of these two mnemonics.
The instructions JG/JNLE are used to compare the relationship between two signed numbers.
Greater means more positive. For example, the number -2 is more positive than the number -4;
the 8-bit number 0000 10 10 (binary)is greater than 10 10 10 10 (binary), because the first
number is positive and the second number is negative
Syntax:
JG / JNLE short label ; Jump if greater (SF=OF and ZF=0)
Flags Affected: None
Function:
if( SF =OF and ZF = v) then
IP ← IP + displacement ( 8-bit sign extended to 16-bit )
else
execute the next instruction in the sequence

JGE Jump on Greater or Equal/JNL Jump on Not Less

Description:
The instructions JGE/JNL transfer control to the target location if the sign flag is same as the
overflow. If this condition fails, the instruction following JGE/JNL will be executed. The
displacement of the target instruction must be within the range of - 128 to +127 bytes from the
address of the instruction before/after the JGE/JNL instruction. The assembler generates the

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same machine code for each one of these two mnemonics. The instructions JGE/JNL are used to
compare the relationship between two signed numbers. Greater mean more positive. For
example, the number -2 is more positive than the number -4; the number 00001010 (binary) is
greater than 10101010 (binary), because the first number is positive and the second number is
negative.
Syntax:
JGE / JNL short label ; Jump if Greater or equal SF=OF
Flags Affected: None
Function:
if( SF =OF ) then
IP ←IP + displacement ( 8-bit sign extended to 16-bit)
else
execute the next instruction in the sequence

JL: Jump on Less than/JNGE: Jump on Not Greater than or Equal

Description:
The instructions JL/JNGE transfer control to the target location if the sign flag is not equal to the
overflow flag If this condition fails, the instruction following JL/JNGE will be executed. The
displacement of the target instruction must be within the range of -128 to +127 bytes from the
address of the instruction before/after the LL/JNGE instruction. The assembler generates the
same machine code for each one of these two mnemonics.
The instructions JL/JNGE are used to compare the relationship between two signed numbers.
Greater means more positive.
For example, the number -2 is more positive than the number -4; the number 00001010 (binary)
greater than 10101010(binary), because the first number is positive and the second number is
negative.
Syntax:
JL/JNGE ;short label Jump if less (SF <> OF) after signed math
Flags Affected: None
Function:
If(SF<> OF ) then
IP← IP + displacement ( 8-bit sign extended to 16-bit)
else
execute the next instruction in the sequence

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JLE :Jump on Less than or Equal/JNG Jump on Not Greater

Description:
The instructions JLE/JNG transfer control to the target location if the sign flag is not equal to the
overflow flag or zero flag is set. If this condition fails, the instruction following JLE/JNG will be
executed. The displacement of the target instruction must be within the range of -128 to +127
bytes from the address of the instruction before/after the JLE/JNG instruction. The assembler
generates the same machine code for each one of these two mnemonics.
The instructions JLE/JNG are used to compare the relationship between two signed numbers.
Greater means more positive. For example, the number -2 is more positive than the number -4;
the number 00001010 (binary) is greater than 10101010(binary), because the first number is
positive and the second number is negative.
Syntax:
JLE/ JNG short label ; Jump if Less than or equal( SF<>OF|| ZF=1) after signed match
Flags Affected: None
Function:
if( SF # OF or ZF = 1 ) then
IP ← IP + displacement ( 8-bit sign extended to 16-bit)
else
execute the next instruction in the sequence

JNE Jump on Not Equal/JNZ Jump on Not Zero

Description:
The instructions JNE/JNZ, transfer control to the target location if the zero flag (ZF) is reset. If
this condition fails, the instruction following JNE/JNZ will be executed. The displacement of the
target instruction may be within the range of -128 to +127 bytes from the address of the
instruction before/after the JNE/JNZ instruction. The assembler generates the same machine
code for each one of these two mnemonics.
Syntax:
JNE / JNZ short label; Jump if not equal (ZF=0)
Flags Affected: None
Function:
if( ZF = 0 ) then
IP ← IP + displacement ( 8-bit sign extended to l6-bit)

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else
execute the next instruction in the sequence

JNO: Jump on not overflow

Description:
The Instruction JNO, transfers control to the target location if overflow flag (OF) is reset. If this
condition fails, the instruction following JNO will be executed. The overflow flag will be set if
signed arithmetic is too large to fit in the destination register or a memory location. The
displacement of the target instruction must be within range of - 128 to +127 bytes from the
address of the instruction before/after the JNO instruction.
Syntax:
JNO short label; Jump if not overflow (OF=0)
Flags Affected: None
Function:
if(OF = 0 ) then
IP ← IP + displacement ( 8-bit sign extended to 16-bit )
else
execute the next instruction in the sequence

JNP Jump on Not Parity/JPO Jump on Parity Odd

Description:
The instructions JNP/JPO, transfer control to the target location if the parity flag (PF) is reset. If
this condition fails, the instruction following JNP/JPO will be executed. The displacement of the
target instruction must be within the range of -128 to +127 bytes from the address of the
instruction before/after the JNP/JPO instruction. The assembler generates the same machine code
for each one of these two mnemonics.
Syntax:
JNP JPO short label jump if parity odd (PF = 0)
(count of 1-bits is ODD)
Flags Affected: None
Function:
if( PF = 0 ) then
IP ← IP + displacement,( 8-bit sign extended to 16-bit)
else

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execute the next instruction in the sequence

JNS: Jump on no sign

Description:
The instruction JNS, transfers control to the target location if sign flag (SF) is reset. If this
condition fails, the instruction following JNS will be executed. This instruction can be termed as
"Jump if positive" because 0 in the sign flag indicates a positive signed number. The
displacement of the target instruction must be within the range of -128 to +127 bytes from the
address of the instruction before/after the JNS instruction.
Syntax:
JNS short label ; Jump if not signed( SF=0)
Flags Affected: None
Function:
if( SF = 0 ) then
IP ← IP + displacement ( 8-bit sign extended to 16-bit)
else
execute the next instruction in the sequence

JO: Jump on overflow

Description:
The instruction JO, transfers control to the target location if overflow flag (OF) is set. If this
condition fails, the instruction following JO will be executed. The overflow flag will be set if
signed arithmetic is too large to fit in tile destination register or memory location. The
displacement of the target instruction must be within the range of -128 to -127 bytes from the
address of the instruction before/after the JO instruction.
Syntax:
JO short label ;jump if overflow ( OF = 1)
Flags Affected: None
Function:
if(OF= I ) then
IP ← IP + displacement ( 8-bit sign extended to 16-bit )
else
execute the next instruction in the sequence

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JP Jump on Parity even/JPE Jump on Parity Equal

Description:
The instructions JP/JPE, transfer control to the target location if parity flag (PF) is set. If this
condition fails, the instruction following JP/JPE will be executed. The displacement of the target
instruction must be within the range of-128 to +127 bytes from the address of the instruction
before/after the JP/JPE instruction. The assembler generates the same machine code for each one
of these two mnemonics.
Syntax:
JP/JPE short_label jump if parity EVEN (PF = 1)
(count of 1-bits is EVEN)
Flags Affected: None
Function:
if( PF = I ) then
IP ← IP + displacement ( 8-bit sign extended to 16-bit )
else
execute the next instruction in the sequence

JS : Jump on sign
Description:
The instruction JS. transfers control to the target location if sign flag (SF) is set. If this condition
fails, the instruction following JS will be executed. This instruction can be termed as "Jump if
negative" because 1 in the sign flag indicates a negative signed number. The displacement of the
target must be within the range of -128 to +127 bytes from the address of the instruction
before/after the JS instruction.
Syntax:
JS short label ; Jump if sign (SF = 1)
; ( same as high bit of dest)
Flags Affected: None
Function:
if( SF = 1 ) then
IP ← IP + displacement (8-bit sign extended to 16-bit)
else
execute the next instruction in the sequence

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6.3 Assignment Questions

Questions carrying 2 marks.
1. What is the use of branch control instructions?
2. When will the JNS be executed?
3. What are the conditions to execute JLE instruction?
4. What are the conditions to execute JCXZ instructions. ( NOV 2009)
5. Discuss the three types of unconditional jump instructions with their byte size. (NOV
2008)
Essay questions.
1. Explain the working of JMP instruction.
2. What are the different ways of execution of JMP instruction?
3. What are intra segment jump instructions?
4. What are inter segment jump instructions?
5. What are conditional jump instructions? How do they execute?
6. Describe the following conditional jump instructions
a. JC
b. JNC
c. JZ
d. JNZ
e. JPO
f. JPE
g. JS
h. JO
7. Explain the short jump with the diagram. (NOV 2012)

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CHAPTER 7.
LOOP INSTRUCTIONS IN MASM 6.X
7.1 Do-while Loop
As with most higher level languages, the assembler also provides the DO-WHILE loop
construct, available to MASM version 6.X. The .WHILE statement is used with a condition to
begin the loop, and the .ENDW statement ends the loop.
• @ C0001
CMP AL, 0DH

JNE C0002

MOV BYTE PTR[DI-1}, ‘$’

MOV DX, OFFSET MES

MOV AH, 09H

INT 21H

.EXIT

END

.MODEL SMALL

MES DB 13,10

BUF DB 256 DUP(?)

.CODE

.STRARTUP

MOV AX, DS

MOV ES, AX

CLD

MOV DI, OFFSET BUFF

.WHILE AL!=ODH

JMP @C0001

• @C0002
MOV AH, 1

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INT 21H
STOSB
.ENDW

Example 7.1 Program to explain the DO-While loop

Example 7.1 shows how the .WHILE statement is used to read data from the keyboard and store
it into an array called BUF until the enter key (ODH)is typed. This program assumes that BUF is
stored in the extra segment because the STOSB instruction is used to store the keyboard data in
memory. Note that the .WHILE loop portion of the program is shown in expanded form so that
the statements inserted by the assembler (beginning with a *) can be studied. After the enter key
(ODH)is typed, the string is appended with a $ so it can be displayed with DOS INT21H
function number 9.

7.2 Repeat until

Also available to the assembler is the REPEAT-UNTIL construct. A series of instructions is
repeated until some condition occurs. The .REPEAT statement defines the start of the loop; the
end is defined with the .UNTIL statement that contains a condition. Note that .REPEAT and
.UNTIL are available to version 6,X of MASM.

• @ C0001
CMP AL, 0DH

JNE C0002

MOV BYTE PTR[DI-1}, ‘$’

MOV DX, OFFSET MES

MOV AH, 09H

INT 21H

.EXIT

END

.MODEL SMALL

MES DB 13,10

BUF DB 256 DUP(?)

.CODE

.STRARTUP
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MOV AX, DS

MOV ES, AX

CLD

MOV DI, OFFSET BUFF

C0002 .REPEAT

JMP @C0001

MOV AH, 1
INT 21H
STOSB
.UNTIL AL= =0DH

Example 7.2 Repeat until loop

If Example 7.1 is once again reworked using the REPEAT-UNTIL construct, this appears to be
the best solution. Refer to Example 7.2 for the program that reads keys from the keyboard and
stores keyboard data into extra segment array BUF until the enter key is typed. This program
also fills the buffer with keyboard data until the enter key (ODH)is typed. Once the enter key is
typed, the program displays the character string using DOS INT 21H function number 9, after
appending the buffer data with the required dollar sign. Notice how the .UNTIL AL == ODH
statement generates code (statements beginning with a *) to test for the enter key.

7.3 Assignment Questions

Essay questions
1. Explain the working of Do- While instruction with an example.
2. Explain the working of Repeat-Until instruction with an example.
3. Compare and contrast between LOOP and Do- While loop.

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CHAPTER 8.

PROCEDURES
8.1 Procedures and parameter passing
The procedure or subroutine is an important part of any computer system's architecture. A
procedure is a group of instructions that usually performs one task. A procedure is a reusable
section of the software that is stored in memory once, but used as often as necessary. This saves
memory space and makes it easier to develop software. The only disadvantage of a procedure is
that it takes the computer a small amount of time to link to the procedure and return from it. The
CALL instruction links to the procedure and the RET (return) instruction returns from the
procedure. The stack stores the return address whenever a procedure is called during the
execution of a program. The CALL instruction pushes the address of the instruction following
the CALL (return address) on the stack. The RET instruction removes an address from the stack
so the program returns to the instruction following the CALL. With the assembler, there are
specific rules for the storage of procedures. A procedure begins with the PROC directive and
ends with the ENDP directive. Each directive appears with the name of the procedure. This
programming structure makes it easy to locate the procedure in a program listing. The PROC
directive is followed by the type of procedure: NEAR or FAR. Example 8.1 shows how the
assembler uses the definition of both a near (intrasegment) and far (intersegment) procedure. In
MASM version 6,X, the NEAR or FAR type can be followed by the USES statement. The USES
statement allows any number of registers to be automatically pushed to the stack and popped
from the stack within the procedure. For example
Sum PROC NEAR USES BX CX DX
ADD AX, BX
ADD AX, CX
MOV DX, AX
RET
Sum1 PROC FAR
ADD AX, BX
ADD AX, CX
ADD AX, DX
RET

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8.2 CALL instructions

Code Mnemonic Description

E8 cw CALL rel16 Call near, relative, displacement relative to next instruction

E8 cd CALL rel32 Call near, relative, displacement relative to next instruction

FF /2 CALL r/m16 Call near, absolute indirect, address given in r/m16

FF /2 CALL r/m32 Call near, absolute indirect, address given in r/m32

9A cd CALL ptr16:16 Call far, absolute, address given in operand

9A cp CALL ptr16:32 Call far, absolute, address given in operand

FF /3 CALL m16:16 Call far, absolute indirect, address given in m16:16

FF /3 CALL m16:32 Call far, absolute indirect, address given in m16:32

Description
Saves procedure linking information on the stack and branches to the procedure (called
procedure) specified with the destination (target) operand. The target operand specifies the
address of the first instruction in the called procedure. This operand can be an immediate value, a
general-purpose register, or a memory location.

This instruction can be used to execute four different types of calls:

• Near call—A call to a procedure within the current code segment (the segment currently
pointed to by the CS register), sometimes referred to as an intrasegment call.
• Far call—A call to a procedure located in a different segment than the current code
segment, sometimes referred to as an intersegment call.
• Inter-privilege-level far call—A far call to a procedure in a segment at a different
privilege level than that of the currently executing program or procedure.
• Task switch—A call to a procedure located in a different task.

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Near Call.
When executing a near call, the processor pushes the value of the IP register (which contains the
offset of the instruction following the CALL instruction) onto the stack (for use later as a return-
instruction pointer). The processor then branches to the address in the current code segment
specified with the target operand. The target operand specifies either an absolute offset in the
code segment (that is an offset from the base of the code segment) or a relative offset (a signed
displacement relative to the current value of the instruction pointer in the EIP register, which
points to the instruction following the CALL instruction). The CS register is not changed on near
calls.
For a near call, an absolute offset is specified indirectly in a general-purpose register or a
memory location (r/m16 bits). The operand-size attribute determines the size of the target
operand (16 bits). Absolute offsets are loaded directly into the IP register. If the operand-size
attribute is 16, the upper two bytes of the IP register are cleared to 0s, resulting in a maximum
instruction pointer size of 16 bits. (When accessing an absolute offset indirectly using the stack
pointer [SP] as a base register, the base value used is the value of the SP before the instruction
executes.)

A relative offset (rel16) is generally specified as a label in assembly code, but at the machine
code level, it is encoded as a signed, 16-bit immediate value. This value is added to the value in
the IP register. As with absolute offsets, the operand-size attribute determines the size of the
target operand (16 bits).
Far Calls in Real-Address or Virtual-8086 Mode. When executing a far call in real-address or
virtual-8086 mode, the processor pushes the current value of both the CS and IP registers onto
the stack for use as a return-instruction pointer. The processor then performs a "far branch" to the
code segment and offset specified with the target operand for the called procedure. Here the
target operand specifies an absolute far address either directly with a pointer (ptr16:16) or
indirectly with a memory location (m16:16). With the pointer method, the segment and offset of
the called procedure is encoded in the instruction, using a 4-byte (16-bit operand size) far address
immediate. With the indirect method, the target operand specifies a memory location that
contains a 4-byte (16-bit operand size) far address. The operand-size attribute determines the size
of the offset (16 bits) in the far address. The far address is loaded directly into the CS and IP
registers. If the operand-size attribute is 16, the upper two bytes of the IP register are cleared to
0s.
Flags
All flags are affected if a task switch occurs; no flags are affected if a task switch does not occur.
8.3 RET instructions

Code Mnemonic Description

C3 RET Near return to calling procedure

CB RET Far return to calling procedure

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C2 iw RET imm16 Near return to calling procedure and pop imm16 bytes from stack

CA iw RET imm16 Far return to calling procedure and pop imm16 bytes from stack

Description
Transfers program control to a return address located on the top of the stack. The address is
usually placed on the stack by a CALL instruction, and the return is made to the instruction that
follows the CALL instruction.

The optional source operand specifies the number of stack bytes to be released after the return
address is popped; the default is none. This operand can be used to release parameters from the
stack that were passed to the called procedure and are no longer needed. It must be used when
the CALL instruction used to switch to a new procedure uses a call gate with a non-zero word
count to access the new procedure. Here, the source operand for the RET instruction must
specify the same number of bytes as is specified in the word count field of the call gate.

The RET instruction can be used to execute three different types of returns:

• Near return - A return to a calling procedure within the current code segment (the
segment currently pointed to by the CS register), sometimes referred to as an
intrasegment return.
• Far return - A return to a calling procedure located in a different segment than the
current code segment, sometimes referred to as an intersegment return.
• Inter-privilege-level far return - A far return to a different privilege level than that of
the currently executing program or procedure.

The inter-privilege-level return type can only be executed in protected mode. See the section
titled "Calling Procedures Using Call and RET" in Chapter 4 of the Intel Architecture Software
Developer's Manual, Volume 1, for detailed information on near, far, and inter-privilege-level
returns.

When executing a near return, the processor pops the return instruction pointer (offset) from the
top of the stack into the EIP register and begins program execution at the new instruction pointer.
The CS register is unchanged.
When executing a far return, the processor pops the return instruction pointer from the top of the
stack into the EIP register, then pops the segment selector from the top of the stack into the CS
register. The processor then begins program execution in the new code segment at the new
instruction pointer.
The mechanics of an inter-privilege-level far return are similar to an intersegment return, except
that the processor examines the privilege levels and access rights of the code and stack segments
being returned to determine if the control transfer is allowed to be made. The DS and ES

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segment registers are cleared by the RET instruction during an inter-privilege-level return if they
refer to segments that are not allowed to be accessed at the new privilege level. Since a stack
switch also occurs on an inter-privilege level return, the SP and SS registers are loaded from the
stack.
If parameters are passed to the called procedure during an inter-privilege level call, the optional
source operand must be used with the RET instruction to release the parameters on the return.
Here, the parameters are released both from the called procedure's stack and the calling
procedure's stack (that is, the stack being returned to).

8.4 Assignment Questions.

Questions carrying 2 marks.
1. Which instruction links to the procedure and which instruction returns from the
procedure?
2. Write a note on near CALL.
3. What is an Inter-privilege-level far call?
4. What are conditional CALL instructions?
5. What happens with RET instruction?
6. What are conditional RET instructions?
7. What is the purpose of RET instruction? (NOV 2012)
8. How many bytes are used in far CALL instruction? Explain (NOV 2009)
Essay Questions.
1. What are procedures? Why are they needed in Assembly language?
2. Explain the different type of CALL instructions.
3. Explain how a CALL instruction is executing?
4. Explain the CALL with register as operand with example. (NOV 2012)
5. Write a note on procedure.( NOV 2012)
6. Write a note on CALL with indirect memory addresses and register operand.(NOV 2009)
7. Write a note on near CALL, far CALL and CALL with register operands. (NOV 2008)
8. Explain the various CALL instructions with examples (NOV 2007)

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CHAPTER 9.
INTRODUCTION TO INTERRUPTS
9.1 What are interrupts
The interrupts are either hardware-generated CALL (externally derived from a hardware signal)
or software-generated CALL (internally derived from the execution of an instruction or by some
other internal event). An internal interrupt is sometimes called an exception. Either type
interrupts the program by calling an interrupt service procedure or interrupt handler. This section
explains software interrupts, which are special types of CALL instructions. This section explains
the three types of software interrupt instructions (INT, INTO, and INT 3), provides a map of the
interrupt vectors, and explains the purpose of the special interrupt return instruction (IRET).

9.2 Interrupt Vectors

An interrupt vector is a 4-byte number stored in the first 1,024 bytes of the memory(00000H-
OO3FFH)when the microprocessor operates in the real mode. In the protected mode, the vector
table is replaced by an interrupt descriptor table that uses 8-byte descriptors to describe each of
the interrupts. There are 256 different interrupt vectors. Each vector contains the address of an
interrupt service procedure. Each vector contains a value for IP and CS that forms the address of
the interrupt service procedure. The first two bytes contain the IP, and the last two bytes contain
the CS. Intel reserves the first 32 interrupt vectors for the present and future microprocessor
products. The remaining interrupt vectors (32-255) are available for the user. Some of the
reserved vectors are for errors that occur during the execution of software, such as the divide-
error interrupt. Some vectors are reserved for the coprocessor. Still others occur for normal
events in the system. In a personal computer, the reserved vectors are used for system functions,
as detailed later in this section. Vectors 1--6,7, 9, 16, and 17 function in the real mode and
protected mode; the remaining vectors function only in the protected mode.

9.3 Interrupt instructions

The microprocessor has three different interrupt instructions available to the programmer: INT,
INTO, and INT 3. In the real mode, each of these instructions fetches a vector from the vector
table and then calls the procedure stored at the location addressed by the vector. In the protected
mode, each of these instructions fetches an interrupt descriptor from the interrupt descriptor
table. The descriptor specifies the address of the interrupt service procedure. The interrupt call is
similar to a far CALL instruction because it places the return address (IPIEIP and CS) on the
stack. INTs. There are 256 different software interrupt instructions (INT) available to the
programmer. Each INT instruction has a numeric operand whose range is o to 255 (OOH-FFH).
For example, the INT 100 uses interrupt vector 100,which appears at memory address 190H-
193H.

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IRET/IRETD The interrupt return instruction (IRET) is used only with software or hardware
interrupt service procedures. Unlike a simple return instruction (RET), the IRET instruction will

• pop stack data back into the IP,

• pop stack data back into CS, and
• pop stack data back into the flag register.

The IRET instruction accomplishes the same tasks as the POPF, followed by a far RET
instruction. Whenever an IRET instruction executes, it restores the contents of I and T from the
stack. This is important, because it preserves the state of these flag bits. If interrupts were
enabled before an interrupt service procedure, they are automatically re enabled by the IRET
instruction, because it restores the flag register. In the 80386 through the Pentium Pro processors,
the IRETD instruction is used to return from an interrupt service procedure that is called in the
protected mode. It differs from the IRET because it pops a 32-bit instruction pointer (IP) from
the stack. The IRET is used in the real mode, and the IRETD is used in the protected mode.

INT3. An INT 3 instruction is a special software interrupt designed to be used as a breakpoint.

The difference between it and the other software interrupts is that INT 3 is a 1-byte instruction,
while the others are 2-byte instructions. It is common to insert an INT 3 instruction in software to
interrupt or break the flow of the software. This function is called a breakpoint. A breakpoint
occurs for any software interrupt, but because INT 3 is a I-byte instruction long, it is easier to use
for this function. Breakpoints help to debug faulty software.

INTO. Interrupt on overflow (INTO) is a conditional software interrupt that tests the overflow
flag (0). If 0 =0, the INTO instruction performs no operation; if 0 =1 and an INTO instruction
executes, an interrupt occurs via vector type number 4.

The INTO instruction appears in software that adds or subtracts signed binary numbers.With
these operations it is possible to have an overflow. Either the JO instruction or INTO instruction
detect the overflow condition.

An Interrupt Service Procedure. Suppose that, in a particular system, a procedure is required

to add the contents of DI, SI, BP, and BX and save the sum in AX. Because this is a common
task in this system, it may occasionally be worthwhile to develop the task as a software interrupt.
Realize that interrupts are usually reserved for system events, and this is merely an example
showing how an interrupt service procedure appears. Example 6-20 shows this software
interrupt. The main difference between this procedure and a normal far procedure is that it ends
with the IRET instruction instead of the RET instruction, and the contents of the flag register are
saved on the stack during its execution.

9.4 Controlling the interrupt flag bit

Although this section does not explain hardware interrupts, two instructions are introduced that
control the INTR pin. The set interrupt flag instruction (STI) places a 1 into the I flag bit, which
enables the INTR pin. The clear interrupt flag instruction (CLI) places a 0 into the I flag bit,

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which disables the INTR pin. The STI instruction enables INTR, and the CLI instruction disables
INTR.
In a software interrupt procedure hardware interrupts are enabled as one of the first steps. This
is accomplished by the STI instruction. The reason interrupts are enabled early in an interrupt
service procedure is that just about all of the I/O devices in the personal computer are interrupt
processed. If the interrupts are disabled too long, severe system problems result.

9.5 WAIT, HLT, NOP, LOCK, ESC, BOUND, ENTER and LEAVE
WAIT

The WAIT instruction monitors the hardware BUSY pin on the 80286 and 80386 and the TEST
pin on the 8086/8088. The name of this pin was changed in the 80286 microprocessor from
TEST to BUSY. If the WAIT instruction executes while the BUSY pin =I, nothing happens and
the next instruction executes. If the BUSY pin =0 when the WAIT instruction executes ,the
microprocessor waits for the BUSY pin to return to a logic I. This pin indicates a busy condition
when at a logic 0 level.

The BUSY/TEST pin of the microprocessor is usually connected to the BUSY pin of the 8087
through the 80387 numeric coprocessors. This connection allows the microprocessor to wait
until the coprocessor finishes a task. Because the coprocessor is inside the 80486 through the
Pentium Pro, the BUSY pin is not present in these microprocessors.

HLT

The halt instruction (HL T) stops the execution of software. There are three ways to exit a halt:
by an interrupt, by a hardware reset, or during a DMA operation. This instruction normally
appears in a program to wait for an interrupt. It often synchronizes external hardware interrupts
with in software system.

NOP

When the microprocessor encounters a no operation instruction (NOP), it takes a short time ID
execute. In early years, before software development tools were available, a Nap, which forms
absolutely no operation, was often used to pad software with space for future machine language
instructions. If you are developing machine language programs, which is extremely rare it is
recommended that you place approximately 10 or so Naps in your program at 50.byte intervals.
This is done in case you need to add instructions at some future point. A NOP may also find
application in time delays to waste short periods of time. Realize that a NOP used for timing is
not very accurate because of the cache and pipelines in modern microprocessors.

LOCK Prefix

The LOCK prefix appends an instruction and causes the LOCK pin to become a logic 0. The
LOCK pin often disables external bus masters or other system components. The LOCK prefix
causes the lock pin to activate for the duration of a locked instruction. If more than one

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sequential instruction is locked, the LOCK pin remains a logic 0 for the duration of the sequence
of locked instructions. The LOCK:MOV AL,[SI] instruction is an example of a locked
instruction,

The escape (ESC) instruction passes information to the8087-Pentium Pro numeric coprocessor
whenever an ESC instruction executes, the microprocessor provides the memory address if
required, but otherwise performs a NOP. Six bits of the ESC instruction provide the opcode to
the coprocessor and begin executing an instruction.

The ESC opcode never appears in a program as ESC and in itself is considered obsolete as an
opcode. In its place are a set of coprocessor instructions (FLD,FST, FMUL,etc.) that assemble as
ESC instructions for the coprocessor.

BOUND

The BOUND instruction, first made available in the 80186 microprocessor, is a comparison
instruction that may cause an interrupt (vector type number 5). This instruction compares the
contents of any 16- or 32-bit register against the contents of two words or doublewords of
memory an upper and a lower boundary. If the value in the register compared with memory is
not within. the upper and lower boundary, a type 5 interrupt ensues. If it is within the boundary,
the next instruction in the program executes.

For example, if the BOUND SI,DA TA instruction executes, word-sized location DATA
contains the lower boundary and word-sized location DATA + 2 bytes contains the upper
boundary. If the number contained in SI is less than memory location DATA or greater than
memory location DATA + 2 bytes, a type 5 interrupt occurs. Note that when this interrupt occurs
the return address points to the BOUND instruction, not the instruction following BOUND. This
differs from a normal interrupt, where the return address points to the next instruction in the
program.

ENTER and LEAVE

The ENTER and LEAVE instructions, first made available to the 80186microprocessor, are used
with stack frames. A stack frame is a mechanism used to pass parameters to a procedure through
the stack memory. The stack frame also holds local memory variables for the procedure. Stack
frames provide dynamic areas of memory for procedures in multi-user environments.

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9.6 Assignment Questions

Questions carrying 2 marks.
1. List the instructions to control the carry flag bit. (NOV 2012)
2. What is IRET?
3. Give the instructions that are used to control the INTR pin of 8086 microprocessor.
(NOV 2010)
4. What are interrupt vectors? How many types are available? (NOV 2009)
5. What is an interrupt? How many types of interrupts available in 8086? (NOV 2008)
6. Differentiate between RET and IRET instructions. (NOV 2008)
7. List the instructions to control the interrupt flag.
Essay questions.
1. Define interrupts and interrupt vectors. Discuss INT 03H instruction. (NOV 2012)
2. Explain the following
a. ESC
b. BOUND
c. WAIT
d. NOP
e. ENTER
f. LEAVE
g. HLT
3. List the steps associated with the software interrupt instruction. (NOV 2011)
4. Discuss the role of RET instruction. Compare it with IRET. (NOV 2011).
5. Discuss the following interrupt instructions (NOV 2011)
a. INTO
b. INT 3
c. IRET
6. Explain the HLT and BOUND instructions. (NOV 2011).
7. List out the steps taken by the processor when it executes an INT instructions. (NOV
2010)

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CHAPTER 10
INTRODUCTION AND OVER VIEW OF MICROCONTROLLERS.
10.1Introduction to microcontrollers
As the technology moved from LSI to VLSI, it became possible to build the microprocessor,
memory and other I/O devices on a single chip. This came to be known as microcontrollers. A
microcontroller contains a microprocessor and also one of the following components.

• Memory
• Analog to digital converter(ADC)
• Digital to analog converter(DAC)
• Parallel I/O interface
• Serial I/O interface
• Timers and counters.
The figure 10.1 shows the block diagram of a typical microcontroller, which is a true computer
on chip. The first 4 bit microcontroller was developed by different companies like HITACHI,
NATIONAL, TOSHIBA etc. Soon after this 8 bit microcontroller was developed by INTEL,
MOTOROLA, ZILOG , Microchip Technology etc.

Interrupt RAM ROM Timers/Coun

Control ters

CPU

OSC ADC/DAC I/O Ports Serial

Ports

Figure 10.1 Block diagram of typical microcontroller

10.2 Overview of microcontrollers

A brief overview of some microcontrollers like PIC microcontrollers, Intel microcontrollers,
Atmel microcontrollers are given below. The microcontrollers must be selected depending on the
needs of a given application.

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Device Register On chip program Speed Counters I/O On chip

memory memory(ROM/EPROM) MHz Lines peripherals
on chip
(bytes)
8031 128 ROMless 12 2 32 UART
MCS51
family
8051 128 -4K ROM 12 2 32 UART
MCS51
family
8052 256 8K ROM 12 3 32 UART
MCS51
family
87511 256 8K EPROM 12 3 32 UART
MCS51
family
87C58 256 32K EPROM 12-24 3 32 UART
MCS 51
Family
87C51GB 256 8K EPROM `12-16 3 48 UART 8
MCS51 channel
family ADC
DMA
89C61x2 1024 64K Flash 20-33 3 32 UART
MCS
51family
AT89S8252 256 8K Flash/ 2K EPROM 24 3 32 UART SPI
Atmel
16C74 192 4K ROM 20 3 32 USART 8
Microchip bit ADC
SPI
16F874/877 256 8K 20 3 32 USART 10
Microchip bit ADC

10.3 Assignment Questions

Questions carrying 2 Marks.
1. 8251 is a __________ bit microcontroller.
2. _________ INTEL micro controller is ROM less.
3. 8052 has __________ bytes of on chip RAM and ___________ bytes of on chip ROM.
4. 8751 has _______ number of I/O lines.
5. 16F874 microchip operates with speed __________ MHz.

Essay Questions.
1. List the components of micro controller with the help of a diagram.
2. List the commercial microcontrollers with their important features.

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112. Pin Connection

when operated at 33 MHz Note that during some modes.

version that requires 600 mA of power supply current. The power sup current for the 80386EX is 320 mA
80386, 500mA for the 20 MHz version. and 450 mA forth16 MHz version. Also available is a 33 MHz
power supply for operation. The power supply current averages 550 mA for the 25 MHz version of the
As with earlier versions of the Intel family of microprocessors, the 80386 requires a sin +5.0 V
systems, but it is becoming very popular in embedded applications.
80386 still can be used for many applications. For example. the 80386EX does not appear computer
microprocessor. Even though the 80486 has become a less expensive upgrade path for newer system the
required fewer than 16 bytes of memory, so the 80386SX is a popular version of the 80386
as the 80286. At the time that t 80386SX was popular, most applications, including Windows 3.11,
The 80386SX was found in many early personal computers that used the same basic motherboard design
80386SX, was developed after the 80386DX for application that didn't require the full 32-bit bus version.
The 80386DX addresses 4G bytes of memory through its 32-bit data bus and 32address. The

Srinivas Institute of Management Studies III Sem BCA

CHAPTER 11
VALUE ADDED CHAPTER
The 80386 Microprocessors
11.1 Introduction
The 80386 microprocessor is a full 32-bit version of the earlier 8086 80286 l6-bit
microprocessors, and represents a major advancement in the architecture switch from l6-bit architecture to
32-bit architecture. Along with this larger word size are many improvements and additional features.
The 80386 microprocessor features multitasking, memory management, virtual memory (with or
without paging), software protection, and a large memory system. All software written for the early 8086
8088 and the 80286 are upward-compatible to the 80386 microprocessor. The amount of memory
addressable by the 80386 is increased from the 1M byte found in the 8086 8088 and the 16M bytes found
in the 80286, to 4G bytes in the 80386.
The 80386 can switch between protected mode and real mode without resetting the
microprocessor. Switching from protected mode to real mode was a problem on the 80286
microprocessor because it required a hardware reset

The 80386DX is packaged in a 132-pin PGA (pin grid array).two versions of the 80386 are commonly
available, the 386DX which is illustrated and the other is the 80386SX which is a reduced bus version of
the 80386. A new version of the 80386-the 80386EX incorporates the AT bus system, dynamic RAM
controller. programmable chip selection logic, 2 address pins, 16 data pins, and 24 IO pins

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Figure 11.1 Pin specifications of 80386 processor

Table 11.1 Pin specifications of 80386 processor

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Data bus(D0-D31) Data bus connections transfer data between the microprocessor and its
memory and I/O system.
Bank enable(be0,be1,be2,be3) signals select the access of a byte, word, or double word of
data. These signals are generated internally by the microprocessor from address bits A1
and A0,
Memory\IO (M/IO’) selects a memory device when a logic I or an I/O device when a logic O.
During the I/O operation, the address bus contains a 16-bit I/O address on address connections
AI5-A2'
Write/Read(W/R’) indicates that the current bus cycle is a write when a logic I or a read when a
logic 0.
The address data strobe (ADS’) becomes active whenever the 80386 has issued a valid
memory or I/O address. This signal is combined with the W/R signal to generate the separate
read and write signals present in the earlier 8086-80286 microprocessor-based systems.
Reset initializes the 80386, causing it to begin executing software at memory location
0xFFFFFFF0 The 80386 is reset to the real mode, and the leftmost 12 address connections
remain logic Is (FFFH) until a far jump or far call is executed. This allows compatibility with
earlier microprocessors.
Clock times 2(CLK2) is driven by a clock signal that is twice the operating frequency of the
80386. For example, to operate the 80386 at 16 MHz, apply a 32 MHz clock to this pin.
Ready controls (READY’) the number of wait states inserted into the timing to lengthen
memory accesses.
Lock (LOCK’) becomes logic 0 whenever an instruction is prefixed with the LOCK: prefix.
This is used most often during DMA accesses.
Data/control (D/C’) indicates that the data bus contains data for or from memory or I/O when a
logic I. If D/C is a logic 0, the microprocessor is halted or execute an interrupt acknowledge.
Bus size 16 (BS16’) selects either a 32-bit data bus (BS16 = 1) or a 16-bit data bus (BS16 = 0).
In most cases, if an 80386DX is operated on a 16-bit data bus, we use the 80386SX that has a 16-
bit data bus. On the 80386EX, the BS8 pin selects an 8-bit data bus.
Next address (NA’) causes the 80386 to output the address of the next instruction data in the
current bus cycle. This pin is often used for pipelining the address.
Hold requests (HOLD) a DMA action.
Hold acknowledge (DLDA) indicates that the 80386 is currently in a hold condition.
Busy is an input used by the WAIT or FWAIT instruction that waits for the coprocessor to
become available. This is also a direct connection to the 80387 from the 80386.
Error (ERROR’) indicates to the microprocessor that an error is detected by the coprocessor.
An interrupt request (INTR) is used by external circuitry to request an interrupt.
Nun-maskable interrupt (NMI)A non-maskable interrupt requests a non-maskable interrupt as
it did on the earlier versions of the microprocessor.

11.3. The Memory System

The memory is divided into four 8-bit-wide memory banks of memory. This 32-bit-wide
memory organization allows bytes. or double words of memory data to be accessed directly. The
80386DX transfer up to a 32-bit-wide number in a single memory cycle. whereas the early 8088
requires four cycles to accomplish the same transfer. and the 80286 and 80386SX require two
cycles. Today. the data is important. especially with single-precision floating-point number that
are 32 bits wide. High-level software normally uses floating-point number for data storage, so
32-bit memory locations speed the execution of high-level software when it is written to take

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advantage of this wider memory.

Each memory byte is numbered in hexadecimal as they were in prior versions of the family. The
difference is that the 80386DX uses a 32-bit-wide memory address, with memory bytes
numbered from location 00000000H to FFFFFFFFH
The two memory banks in the 8086, 80286. and 803S6SX system are accessed via BLE ( on
the 8086 and 80286) and BHE. In the 80386DX. the memory banks are accessed via four bank
enable signals, BE3-BE0. It also allows a word to be addressed when two bank enable signals are
activated. In most system. a word is addressed in banks 0 and 1, or in banks 2 and 3. Memory
location 00000000H is in bank 0. location 00000001H is in bank I, location 00000002H is in
bank 2, and location 00000003H is in bank 3. The 80386DX does not contain address
connections A0 and A1 because these have been encoded as the bank enable signals. Likewise,
the 80386SX does not contain the A0 address pin because it is encoded in the BLE and BHE
signals. The 80386EX addresses data either in two banks for a 16-bit-wide memory system if
BS8 = 1 or as an 8-bit system if BS8 = 0.

11.4. Buffering System

80386DX connected to buffers that increase fan-out from its address, Data, and control
connections. This microprocessor is operated at 12.5 MHz using a 25 MHz clock input signal
that is generated by an integrated oscillator module.

We used 74F244 for buffering all output signals like Address bus, be0-be3, ads, d/c’, m/io’, and
w/r’And by-directional try-state buffers 74f245 for buffering data bus. The (W/R’ ) is used to
control direction of data on Data bus.

11.5. The Input/output System

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The 80386 input/output system is the same as that found in any Intel 8086 family micro-
processor-based system. There are 64K different bytes of I/O space available if isolated I/O is

implemented. With isolated I/O, the IN and OUT instructions are used to transfer I/O data
between the microprocessor and I/O devices. The I/O port address appears on address bus
connections AI5-A2, with BE3-BEO used to select a byte, word, or double word of I/O data. If
memory-mapped I/O is implemented, then the number of I/O locations can be any amount up to
4G bytes. With memory-mapped I/O, any instruction that transfers data between the
microprocessor and memory system can be used for I/O transfers because the I/O device is
treated as a memory device. Almost all 80386 systems use isolated I/O because of the I/O
protection scheme provided by the 80386 in protected mode operation.
Unlike the I/O map of earlier Intel microprocessors, which were 16 bits wide. the 80386 uses a
full 32-bit-wide I/O system divided into four banks. This is identical to the memory system,
which is also divided into four banks. Most I/O transfers are 8 bits wide because we often use
ASCII code (a seven-bit code) for transferring alphanumeric data between the microprocessor
and printers and keyboards. This may change if Unicode, a 16-bit alphanumeric code, becomes
common and replaces ASCII code. Recently, I/O devices that are 16 and even 32 bits wide have
appeared for systems such as disk

11.6 Memory and I/O Control Signals

The memory and I/O are controlled with separate signals. The M/IO’ signal indicates whether
the data transfer is between the microprocessor and the memory (M/IO’ = I) or I/O (M/IO’ = 0).
In addition to M/IO’, the memory and I/O systems must read or write data. The W/R signal is

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logic 0 for a read operation and logic 1 for a write operation. The ADS’ signal is used to qualify
the M/IO’ and W/R’ control signals.

This is a slight deviation from earlier Intel microprocessors, which didn't use ADS’ for
qualification. Notice that two control signals are developed for memory control (MRDC’ and
MWTC’) and two (or I/0 controls (IORC’ and IOWE’). These signals are consistent with the
memory and I/O control signals generated for use in earlier versions of the Intel microprocessor.
10k

IO write U22A
5 2
6 Q D Vcc
Q 3 ADS
CLK
1 R1 10k
CLR 4 READY' IO decoder
PRE int_ack 15 1 r/w'
74F74 don_occare 14 Y0 A 2 c/d'
IO_read 13 Y1 B 3 m/io'
Mem write U23B IO_write 12 Y2 C
9 12 M_code read 11 Y3 6
8 Q D HLT 10 Y4 G1 4
Q 11 ADS M_data read 9 Y5 G2A 5
CLK M_data write 7 Y6 G2B
13 Y7
CLR 10 READY' 74F138
PRE 0
74F74

U24A
Mem read 2 M_code read
3
1 M_data read
MEMOR /IO (READ/WRITE)
Interrupt Control
74F08 segnals

11.7 Timing
Tuning is important for understanding how to interface memory and I/O to the 80386
microprocessor. Note that the timing is referenced to the CLK2 input signal and that a bus cycle
consists of four clocking periods.
Each bus cycle contains two clocking states with each state (T1 and T2) containing two clocking
periods time for the two states equal 4/CLK2. The 12.5 MHz version allows memory access time
of time(T0,T1)-47ns which is equal 160ns-47ns=113ns before wait states are inserted

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11.8 .Wait States

Wait states are needed if memory access times are long compared with the time allow 80386 for
memory access. In a no pipelined 12.5 MHz system, only a few DRAM memories exist that
have an access time of 113 ns. This mean, often wait states must be introduced to access the
DRAM (one wait for 120 ns DRAM) ,EPROM that has an access time of 150 ns (one waits).
Each wait state added increase access time with 80ns,to ensure compatibility with IO devices we
added 3 hardwired wait states for each read or writ access, whether it’s an IO access or memory
access.
The READY input controls whether or not wait states are inserted into the timing READY input
on the 80386 is a dynamic input that must be activated during each bus.to generate three wait
states we used the following circuit:-

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U28

10k 15 3 U29D
1 P0 Q0 2 12 READY
10 P1 Q1 6 11
9 P2 Q2 7 13
P3 Q3
4 13 74F00
CLK2 5 CLKD BO 12
CLKU CO
14
11 CLR
LOAD

74F193

U29A
ADS 1 U29B
3 4 U29C
2 6 9
C/D' 5 8
74F00 10
74F00
74F00

CLK2 input increase the counter value by one, if the counter value reached 0110(count to 6) the
ready output is asserted (which cause the microprocessor to end the current read or write cycle)
when a new read or write cycle begins (ADS=0, C/D’=1) the counter CLR’ input is asserted to
clear the counter.

11.9.Timing with Wait states

The physical data bus width for any non-pipelined bus cycle can be either 32-bits or 16-bits. At
the beginning of the bus cycle, the processor behaves as if the data bus is 32-bits wide. When the
bus cycle is acknowledged, by asserting READY’ at the end of a T2 state, the most recent

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sampling of BS16’ determines the data bus size for the cycle being acknowledged. If BS16’ was
most recently negated, the physical data bus size is defined as 32 bits. If BS16Ý was most
recently asserted, the size is defined as 16 bits.

When BS16’ is asserted and two 16-bit bus cycles are required to complete the transfer, BS16’
must be asserted during the second cycle; 16-bit bus size
is not assumed. Like any bus cycle, the second 16-bit cycle must be acknowledged by asserting
READY’.

When a second 16-bit bus cycle is required to complete the transfer over a 16-bit bus, the
addresses generated for the two 16-bit bus cycles are closely related to each other. The addresses
are the same except BE0’ and BE1’ are always negated for the second cycle. This is because data
on D0-D15 was already transferred during the first 16-bit cycle.

11.10 A0, A1, BLE, and BHE generating

In 32-bit-wide physical memories each physical Dword begins at a byte address that is a multiple
of 4. A2-A31 are directly used as a Dword select and BE0’-BE3’ as byte selects. BS16’ is
negated for all bus cycles involving the 32-bit array.
When 16-bit-wide physical arrays are included in the system, each 16-bit physical word begins at
an address that is a multiple of 2.

Note the address is decoded, to assert BS16’ only during bus cycles involving the 16-bit array.
~~~~~~~~~~~~~~~~~~~~~~~~~~~

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