Visvesvaraya Technological University

Belagavi, Karnataka-590 018

!
A
SYNOPSIS
ON
DESIGN, IMPLEMENTATION AND CHARACTERIZATION OF 180nm STANDARD
CELL LIBRARY FOR INDUSTRIAL SYNTHESIS FLOW

Submitted
in partial fulfillment of the requirement for the award of the Degree of

BACHELOR OF ENGINEERING
IN
ELECTRONICS AND COMMUNICATION ENGINEERING
BY
SRUJAN R 4VV14EC108
SURAJ M 4VV14EC112
VINAY S 4VV14EC124
VISHAL M S 4VV14EC126

Department of Electronics and Communication Engineering

Vidyavardhaka College of Engineering, Mysuru-02
2017-2018
 INTRODUCTION

Standard Cell-based design (SBCD) refers to a design approach that uses a library of basic
building blocks called cells. Using cells from the library, larger, more complex functions are
realized. In contrast to transistor level in situ customization of cell designs, the cells are used
for Design and verification tools and are fully characterized for timing, noise and reliability.

The growing demand for the integration of systems with the maximum possible functionality
by combining High performance with a tolerable amount of power dissipation has been
driving the development and the modeling if CMOS transistor technologies, especially with
the growth of the Embedded and portable devices Market. The need for integration of more
and more components on to a single chip, by improving performance with reasonable energy
loss, motivated the migration from technologies around 180nm to the deep sub-micron
regime.

The key success factor for the rapid growth of the integrated system is the use of ASIC
library for various system functions. It consists of pre-designed and pre-verified logic blocks
that help designers to shorten the product development time and manage the complexity of a
chip having millions or logic gates or more.

In semiconductor design, Standard Cell Methodology is a method of designing Application

specific Integrated Circuits (ASIC) with mostly digital logic features. Standard Cell
Methodology is an example of Design Abstraction whereby a low level VLSI layout is
encapsulated into an abstract logic representation. Standard Cell Based methodology makes it
possible for one designer to focus on high level aspect of digital design. Standard Cell
methodology is responsible for allowing designers to scale ASICs from comparatively simple
single function ICs, to complex multimillion gate devices (SoC).The library usually contains
multiple implementations of the same logic functions, differing in area and speed. The variety
enhances the efficiency of automated synthesis, place and route (SPR) tools. It also gives the
designer greater freedom to perform implementation tradeoff. A complete group of Standard
cell descriptions is commonly called a technology library. Therefore it is important to build
library that fulfills the Synthesis Design Flow requirement.

DIGITAL DESIGN FLOW

The technology independent, register transfer level description is the usual input of
industrially compatible automated digital implementation flows. The mapping of the RTL
description into the technology dependent format, namely the gate level synthesis process, is
performed based on a library of pre-characterized CMOS logic gates known as standard
Cells. These cells are organized in libraries which minimally include an inverter, a NAND
and NOR gate, as well as a multiplexer in tri-state buffer. These are most necessary ones, as
they can be basis for the implementation of more complex circuit.

The gate-level synthesis stage is divided into two steps. First, the RTL description is mapped
to a technology independent net-list of abstract gates. This is an intermediate representation
followed by the final technology-aware mapping to the cells of the library used in the
synthesis. After this mapping step the synthesizer optimizes the design, Considering the
timing, area and power constraints given by the designer, as long as the available cells of the
library. Therefore, the synthesis tools should be aware of the cells timing, area and power
characteristics. Hence, the standard cells should have been already characterized in terms of
performance, area and power dissipation, to enable the synthesis tool’s optimization.

Characterization implies that the transistor-level net-lists of these cells should be fed to an
analog simulator with various input slews and output load capacitances, as well as the
operating conditions of voltage and temperature, and simulated. The result of this process is
the timing, power and area characteristics for each library’s cell, at the specific design corner
and operating conditions. These metrics are written in a different file format adopted by
different tools. (Generally written in a LIB file) The LIB file is also used at the physical
implementation stage, which follows synthesis. At this stage, the place-and-route tools should
be aware of the geometry of cells and interconnects, as well as of design rules like the
minimum inter-metal spacing, given the technology. This information is extracted from the
physical design (layout) of cells. The place-and-route tools need information about the width
and height of cells, as well as the location and the dimensions of their input and output pins.
The cell layouts are driven to the Abstract Generator, which produces the Library Exchange
Format (LEF) file, which contains this information. In addition to the above, LEF files
provide information about the technology’s metal stack and the minimum width, spacing and
thickness of the available layers. The successful completion of placement and routing is
followed by the post-layout simulation step, which verifies the design’s functionality. This
step requires the information about the functionality of standard-cells, comprising the post
layout net-list. This information is produced at the characterization and it is written to a
Verilog file, which includes the gate level net-list of each cell, along with the input-to output
delay of each path. In the RTL-to-GDSII flow of Fig. 1, the LIB is used for timing and power
analysis at both the post-synthesis and the post-layout steps. The information in the LEF file
determines placement and routing, by providing the cell and interconnects physical
dimensions and the design rules regarding wires and VIAS these two files comprise the core
of a standard-cell library. A standard-cell library generation suite should minimally produce
both of them, along with the gate-level net-list of cells, which is given usually in Verilog and
it is required for the post-synthesis and the post-layout simulation of designs built with the
specific standard-cell library.

3. STANDARD CELL DESIGN FLOW

SCHEMATIC DESIGN

The Figure.2 shows the design flow for the standard cell. The design starts with the circuit
topology of the cell either using schematic or net-list entry. At this stage, the width of NMOS
Wn and PMOS Wp, of the transistor are optimized. Wp and Wn are selected to meet design
specifications such as power dissipation, propagation delay, noise immunity and area. The
value of Wp and Wn are determined by:

• DC switching point, which is approximately 50% of the Vdd.

• Driving capability of the cell, i.e. the number of fanout that the cell can drive. For an
approximately same rise and fall time, Wp is normally three times wider than Wn. A circuit
simulator is used to determine the switching point.
LAYOUT METHODOLOGY

If the circuit functions as expected, the physical design for the cell will be created and the
parasitic value such as capacitance is back annotated to obtain the actual delay associated
with the interconnect. The layout uses the standard cell technique, where signals are routed in
poly-silicon perpendicular to the power. This approach result in a dense layout for CMOS
gates, as the vertical poly-silicon wire can serve as the input to both the NMOS and PMOS
transistor. The row of NMOS and PMOS transistor is separated by a distance specified in the
design rule separation between n and p active area. Power and ground busses traverse the cell
at the top and bottom respectively. The internal area of the cell is used for routing the
MOSFET of specific gates. To complete the logic gate, connections is made in metal, where
metal1 routed horizontally and metal2 vertically.

CHARACTERIZATION PROCESS

The cells are simulated to ensure proper functionality and timing. The results from the initial
design and extracted values are compared. There are many models which we can use to
simulate the nominal process from the fabrication. Measurements of all delay times are at
50% to 50% Vdd values. All rise/fall times are 20% to 80% Vdd values. To obtain realistic
manufacturing process characteristic, circuit simulation is performed with temperature,
voltage and process parameter over the range of values that are expected to occur. The critical
values at process comer are simulated with minimum and maximum condition. To exercise
all input-to-output paths through the cells, input stimulus will be provided to the circuit
simulator. Since many repetitive executions of the circuit simulator are required for each cell,
the characterization is done using an automatic cell characterization tool.

The characterization flow for std. cell is a major issue. The major steps are given below

>>> Net-list Extraction:

In this, the layout for the cell to be characterized is made using any good layout editor for a
specific technology & then verified for the technology rules violations & interconnections.
After verifying the design, the parasitic extraction is done in which resistance; capacitance &
other physical parasitic are being extracted from the design.

>>> Specification of Parameters:

After the extraction, some default, process & design dependent parameters are defined. For
example, doping density, voltage, temperature, Fan out etc.

>>> Model Selection and Specification:

After specifying the parameter values, different models are selected depending on their
accuracy, complexity & requirement. A Model estimates the timing, area, power & noise
parameters of the std. cell. In real sense, Models are mathematical equations used to calculate
the output parameters.

>>> Measurement:
The output provided by the simulator is then measured to extract the required characterization
parameters. The output may be in different forms e.g. graphical view, bar chart and shmoo
plot etc. From these characteristics, different parameters like area, power and timing are
calculated for the std. cell.

>>> Model Generation:

Using these parameters, a characterized output model for the std. cell is prepared in a format
to which a design tool can understand. All the measured parameters are attached to std. cell.

>>> Verification:
After the characterization of the std. cell, it is verified for different parameters by building a
design from it. If it gives the desired result then the library is sign out. But if there is any
error then flow is repeated from different stages depending on the severity of the error.

MODEL DEVELOPMENT AND DOCUMENTATION

After characterizing, the cells functional description and timing data are transformed to the
format required by a specific design tools. Most design tools utilize special-purpose model
formats with syntax for explicitly describing propagation delays, timing checks, and other
aspects of cell behavior that are required by the tool. The final requirement is a
documentation that summaries the functionality and timing of each cell. The functionality is
frequently described with truth table, and timing data is presented in a simple format in the
datasheet. The documentation for each library contains:

• Setup and hold times

• Minimum cycle time, enable and disable time
• Truth table for small/medium complexity cells
• Operating range of temperature and voltage
• Fan-in and fan-out
• Variation of timing due to temperature and
• Voltage
• Path delays
• Library cell symbol
• Timing diagrams.

Problem definition:

• Standard library cells are basic building blocks for ASIC (Application-Specific
Integrated Circuit) design. Commercial library cells are companies’ proprietary
information, and understandably, companies usually impose certain restrictions on
the access and use of their library cells. Those restrictions on commercial library cells
severely hamper VLSI research and teaching activities of academia. Standard library
cells improve designers’ productivity through reduced design time and debugging.
 There are many tools available in market which we can use for standard cell library
design like Synopsys, cadence etc.

• At the very beginning of the physical layout design, the designer has to start from
scratch designing each and every basic combinational and sequential logic on the
virtual layout which is extremely time consuming & the designer might also face a
problem with handling DRC (Design Rule Check). Due to this, a lot of time is
consumed in the physical layout design, in turn increasing the overall manufacturing
time of a particular product.

• Even if the designer is able to develop the layout from scratch by handling the DRC
(Design Rule Check) with the required time constraints, the area occupied by the
design will be gradually more i.e (each cell sizing will be more than eleven track to
fifteen track) compared to the size of the cell in the library i.e (each cell with a size of
nine track). This leads to larger ICs, more power consumption, more heat dissipation
and lower reliability.

LITREATURE SURVEY:

1.CMOS VLSI Design: A Circuits and system perspective by Neil H.E Weste, David
Harris, Ayan Banerjee :This book fulfils all those needs by giving a detailed explanation on
CMOS VLSI design.ALL the latest techniques in the design of complex, high level CMOS
chips are explained with their basics.This book is helping us in understanding the circuit
characterizations. The book also covers tutorials on tools and techniques like VHDL,SPICE
and Verilog.

2.CMOS IC LAYOUT Concepts, Methodologies, and Tools by Dan Clein: This book
provides information about the layout design rules and standard cell design rules.

3.IC Mask Layout Design by Christopher saint and Judy Saint: This book also provides
information about the standard cell library development process and layout design
methodology.

REFERENCES: