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DDCO Lab_Solution 5&6

The document outlines the design and implementation of a 4-bit binary adder and a BCD adder using Verilog HDL, including the necessary modules for full and half adders. It also provides testbenches for both the binary and BCD adders, along with an introduction to designing multiplexers, specifically a 2:1 multiplexer, with corresponding Verilog code and testbench. Additionally, it mentions the implementation of a 4:1 multiplexer, although the code for it is not provided.

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Kiran G
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12 views6 pages

DDCO Lab_Solution 5&6

The document outlines the design and implementation of a 4-bit binary adder and a BCD adder using Verilog HDL, including the necessary modules for full and half adders. It also provides testbenches for both the binary and BCD adders, along with an introduction to designing multiplexers, specifically a 2:1 multiplexer, with corresponding Verilog code and testbench. Additionally, it mentions the implementation of a 4:1 multiplexer, although the code for it is not provided.

Uploaded by

Kiran G
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Experiment 5 & 6 DD&CO Lab 3rd semester

Course Instructor: Kiran G

5. Design Verilog HDL to implement 4-bit binary adder. (If time permits implement the 4-bit
binary and decimal adder/Binary coded decimal(BCD) adder)

Fig. Four-bit parallel adder


Verilog code for 4 bit adder:

module adder_4bit(
input [3:0] a,
input [3:0] b,
input c0,
output [3:0] sum,
output carry_out
);

wire c1, c2, c3;

full_adder f1(.a_fa(a[0]),.b_fa(b[0]),.c_in_fa(c0),.sum_fa(sum[0]),.carry_fa(c1)); //Instantiated


full_adder f2(.a_fa(a[1]),.b_fa(b[1]),.c_in_fa(c1),.sum_fa(sum[1]),.carry_fa(c2));
full_adder f3(.a_fa(a[2]),.b_fa(b[2]),.c_in_fa(c2),.sum_fa(sum[2]),.carry_fa(c3));
full_adder f4(.a_fa(a[3]),.b_fa(b[3]),.c_in_fa(c3),.sum_fa(sum[3]),.carry_fa(carry_out));

endmodule

//code for full_adder


module full_adder(
input [3:0] a_fa, b_fa,
input c_in_fa,
output [3:0] sum_fa,
output carry_fa
);

wire temp1, temp2, temp3;

half_adder h1 (.a_ha(a_fa),.b_ha(b_fa),.sum_ha(temp1),.carry_ha(temp3));
half_adder h2 (.a_ha(temp1),.b_ha(c_in_fa),.sum_ha(sum_fa),.carry_ha(temp2));

assign carry_fa = temp2 | temp3;

endmodule

//code for half_adder


module half_adder(
input [3:0] a_ha, b_ha,
output [3:0] sum_ha,
output carry_ha
);

assign sum_ha = a_ha ^ b_ha;


assign carry_ha = a_ha & b_ha;

endmodule
Testbench for 4-bit binary adder:

module tb_binary;

// Inputs
reg [3:0] a;
reg [3:0] b;
reg carry_in;

// Outputs
wire [3:0] sum;
wire carry;

// Instantiate the DUT


adder_4bit dut (.a(a), .b(b), .c0(carry_in), .sum(sum), .carry_out(carry) );

initial begin
// Apply Inputs
a = 0; b = 0; carry_in = 0; #10;
a = 6; b = 9; carry_in = 0; #10;
a = 3; b = 3; carry_in = 1; #10;
a = 4; b = 5; carry_in = 0; #10;
a = 8; b = 2; carry_in = 0; #10;
a = 9; b = 9; carry_in = 1; #10;
end

endmodule
Truth table: Binary to decimal/BCD converter.
Fig. Block diagram of a decimal/BCD adder

Verilog code for Decimal/BCD addition:

module bcd_adder(a,b,carry_in,sum,carry);

input [3:0] a,b;


input carry_in;
output [3:0] sum;
output carry;
//Internal variables
reg [4:0] sum_temp;
reg [3:0] sum;
reg carry;

//always block for doing the addition


always @(a,b,carry_in)
begin
sum_temp = a+b+carry_in; //add all the inputs
if(sum_temp > 9) begin
sum_temp = sum_temp+6; //add 6, if result is more than 9.
carry = 1; //set the carry output
sum = sum_temp[3:0]; end
else begin
carry = 0;
sum = sum_temp[3:0];
end
end

endmodule
Testbench for Decimal/BCD adder:

module tb_bcdadder;

// Inputs
reg [3:0] a;
reg [3:0] b;
reg carry_in;

// Outputs
wire [3:0] sum;
wire carry;

// Instantiate the DUT


bcd_adder dut (.a(a), .b(b), .carry_in(carry_in), .sum(sum), .carry(carry) );

initial begin
// Apply Inputs
a = 0; b = 0; carry_in = 0; #10;
a = 6; b = 9; carry_in = 0; #10;
a = 3; b = 3; carry_in = 1; #10;
a = 4; b = 5; carry_in = 0; #10;
a = 8; b = 2; carry_in = 0; #10;
a = 9; b = 9; carry_in = 1; #10;
end

endmodule

6. (a) Design Verilog program to implement different types of multiplexers like 2:1 and 4:1.

Boolean Expression:
Fig. 2:1 Multiplexer (symbol) Fig. 2:1 Multiplexer (logical)

𝑌 = 𝑠𝑒𝑙 . 𝐴 + 𝑠𝑒𝑙. 𝐵
Table. Truth table of 2:1 Multiplexer
Verilog Code for 2:1 multiplexer using assign statement: Selection Output
Input (sel) (Y)
module mux_assign( 0 Y=A
input a_in,
input b_in, 1 Y=B
input sel_in,
output y_out
);

//assign y_out = (sel_in)? a_in : b_in; //(sel_in)? b_in : a_in;


assign y_out = ~(sel_in)&(a_in)| (sel_in)&(b_in);
endmodule

Testbench:

module mux_assign_tb();

reg a_t, b_t;


reg sel_t;
wire y_out_t;

mux_assign m1 (.a_in(a_t), .b_in(b_t), .sel_in(sel_t), .y_out(y_out_t));

initial
begin
a_t=1'b0; b_t=1'b1; sel_t=1'b0;
#10;
a_t=1'b0; b_t=1'b1; sel_t=1'b1;
#10 $stop;
end

endmodule

4:1 multiplexer: (write the Verilog code using behavioural modelling)

Fig. 4:1 Multiplexer (TT and expr’n) Fig. 4:1 Multiplexer (logical)

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