tldr:

how NMOS and PMOS works

CMOS (Complementary MOS) combines NMOS and PMOS transistors to
create efficient logic gates.
CMOS gates like inverters, NAND, and NOR gates use complementary
transistors to switch outputs between high and low states with minimal power
consumption.
18-100 Introduction to ECE Spring 2024
L04 Notes: CMOS Logic
Tom Zajdel & Jimmy Zhu, Carnegie Mellon University

1 Enter the Transistor

Hopefully by this point, you’ve been convinced about the power of Boolean
logic. Simple operations between 0 and 1 can be used to represent arith-
metic (adder) and control the flow of data (decoder, multiplexer). All of
the logic gates that comprise these more complex logical structures are
made of transistors, electrically-controllable switches, deciding to con-
nect high or low voltages to the output.
Computing existed long before transistors came onto the scene in the
1940s, but transistors revolutionized everything. They can be made very
small physically, and have no moving parts. Billions of transistors power
your phone, ultimately doing a whole bunch of switching.
Modern electronics, both digital and analog, owe a great deal to the
transistor. In the end, the transistor is a three-terminal semiconductor
device that controls the flow of current between two terminals by a control
signal present at its third terminal. In this class, we study the MOSFET:
Metal-Oxide-Semiconductor Field-Effect Transistor, the most
widely-produced transistor that drives all the logic in modern processors.
These transistors are fabricated billions per chip in integrated ciruits
- circuits that are built into a single chunk of semiconductor.

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2 An electrically-controllable switch?
Ideally, we would build logic gates out of electrically-controllable switches.
These are switches that we would be able to open and close by some
electrical control signal. This switch must be able to transition between
these the open and closed states quickly if the control signal changes. Such
a device must have three terminals: two for the current to flow between,
and one for control.

Figure 1: An electrically-controllable switch requires three terminals: the

switch between two terminals is governed by a third control terminal. This
control terminal uses some electrical signal (e.g. voltage) to set the state
of the switch.

Switches that can be controlled by an electric signal are useful be-

cause they make it easy to automate computation. If we are representing
our data as high and low voltages, these signals can directly control the
switches carrying out the computation.

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 The basic function of a logic gate is to determine, based on the voltage
levels present at the inputs, if its output should be connected to the supply
voltage (1) or to ground (0). There is some network (circuit) connecting
the output node to the supply voltage through a series of switches, and
another network connecting the output node to ground. These are known
as a pull-up network and a pull-down network, respectively.

Figure 2: A logic gate has one decision to make: pull up to the supply
voltage, or pull down to ground? The output will be 1 or 0, respectively.
Each network is a circuit that makes the connections to pull Vout up or
down based on the inputs.

The pull-up network could simply be a resistor, or it could include

mechanical switches, or transistors. The specific implementation is not
always of relevance to a digital designer, and can be abstracted away as
digital logic gates, as we have done so far. Virtually all digital electronics
in use today implement CMOS (Complementary MOS) circuits
for these networks due to their small size (billions on a single chip) and
excellent power efficiency. To understand the benefits of CMOS, we must
first understand the structure of the MOSFET.

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3 MOSFET
The MOSFET has three terminals: drain (D), source (S), and gate (G).
The conductivity of the material between the drain and source is controlled
by a voltage applied between the gate and source VGS . There are two main
varieties: NMOS (N-channel) and PMOS (P-channel). Briefly, the NMOS
transistor is ON when the gate voltage is high, and the PMOS transistor
is ON when the gate voltage is low.
D − S
VGS
+
G G
+
VGS
− S D
NMOS Transistor PMOS Transistor
Figure 3: NMOS (left) and PMOS (right) Transistors. The PMOS symbol
has a small circle at its gate to differentiate it from an NMOS. The control
signal is VGS , the voltage between the gate and source.

In both cases, a significant (>1V or so, depending on the transistor’s

design) difference in potential between the gate and source can create a
channel that carries current. In the absence of this potential difference,
there is no channel and no current can pass (i.e. an open circuit).

• In NMOS Transistors, a higher potential at the gate than the source

(i.e. high VGS ) attracts electrons from the semiconductor, creating a
negatively-charged channel that carries current from drain to source.

• In PMOS Transistors, a lower potential at the gate relative to the

source (i.e. negative VGS ) attracts holes from the semiconductor,
creating a positively-charged channel that carries current from source
to drain.

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3.1 N-Channel MOSFET (NMOS)
The basic structure of an N-channel MOSFET is a pair of n-type semicon-
ductor wells embedded into a p-type bulk (sometimes called the body or
substrate). These wells are the source and drain. PN junctions between
the wells and bulk ensure that current cannot flow between the source and
drain, in either direction (see Note 03: Diodes).

Figure 4: A PMOS transistor. An n-type channel spans the drain and

source if a sufficient potential is applied between the gate and the source.

In order to allow current to flow between these terminals, a gate elec-

trode is placed in very close proximity to the p-type bulk. The two are
separated by a thin insulator, a metal oxide. A large positive potential at
the gate relative to the p-type bulk creates a strong electric field that at-
tracts negatively-charged electrons to the surface. The result is a channel
of negative charge carriers between the source and drain, that establishes
a conductive path through the transistor.1
This channel only forms if the gate is at a sufficiently higher po-
tential than the source. In 18-100, we consider this to be the case when
the gate voltage is high (+5V) and the source voltage is low (GND).
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A small detail: positive charges (holes) in the p-type bulk will flow in the opposite direction,
repelled from the gate. The bulk is often connected to the source terminal which, at a lower potential
than the gate, will ultimately attract these positive charges.

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In later courses, you will study more nuanced behavior for intermediate
values of VGS that enable analog signal amplification.

3.2 P-Channel MOSFET (PMOS)

The PMOS is the complement of the NMOS. The basic structure of an
P-channel MOSFET is a pair of p-type wells (source and drain) embedded
into an n-type bulk. Just as in the NMOS case, PN junctions between the
wells and bulk ensure that current cannot flow between the source and
drain, in either direction.

Figure 5: A PMOS transistor. A p-type channel spans the drain and

source if a sufficiently negative potential is applied between the gate and
the source.

This time, a lower potential at the gate relative to the bulk will attract
positively-charged holes to the surface, providing a positive channel con-
necting the source to the drain with a high conductive path for current.2
This channel only forms if the gate is at a sufficiently lower po-
tential than the source. In 18-100, we consider this to be the case when
2
Electrons in the n-type bulk will be repelled from the gate, and will ultimately end up at the
source, which is at a higher potential than the gate.

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the gate voltage is low (+0V) and the source voltage is high (+5V), the
opposite case from the NMOS.

3.3 NMOS and PMOS - Two Flavors of Switch

Here is a summary of our simplified NMOS and PMOS transistor switch
models. There is a lot more nuance in the behavior of MOSFETs (e.g.
intermediate VGS values) that you will get to know very well in 18-220.

Type Gate Source VGS Channel? Drain-to-Source

0V 0V 0V OFF open
NMOS
+5V 0V +5V ON short
0V +5V -5V ON short
PMOS
+5V +5V 0V OFF open

Table 1: Summary of NMOS transistor and PMOS transistor character-

istics, side-by-side.

Why do we need two complementary switch types? Why can’t we

just use NMOS or PMOS alone? Holes naturally move slower than elec-
trons do, so the first PMOS transistors were much slower than NMOS
transistors. As a result, logic circuits were dominated by NMOS tran-
sistors through the 1970s. NMOS logic requires pull-up resistors that
consume power whenever the outputs are pulled down, so they consume
more power than CMOS. As fabrication techniques advanced through the
1980s, CMOS began to match the speed of NMOS-only logic. The vast
power savings of CMOS enables billions of transistors to operate on a
single chip, so CMOS is the dominant technology today.

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4 NMOS Logic
In NMOS logic, NMOS transistors are used to form a pull-down network.
The counterweight for this NMOS pull-down network is a pull-up resistor.
If the NMOS pull-down network is inactive (i.e. if there is an open between
Vout and GND), there will be no current through the pull-up resistor. Since
there would be no voltage drop across the pull-up resistor, Vout would be
“pulled” up to +5V.
The simplest NMOS logic gate is the inverter, which uses one NMOS
transistor to pull Vout down when VA is high. When Vout is pulled low,
+5V drops across the pull-up resistor, so current is drawn and power is
consumed (recall P = I 2R). When VA is low, the NMOS transistor is off,
so there is no drop across the pull-up resistor and Vout = +5V.

+5V

Vout
D
G
VA
S
GND

Figure 6: NMOS Inverter (NOT) Circuit

We can improve on this design by replacing the pull-up resistor with a

switch that opens whenever the NMOS transistor closes and pulls down
Vout. Luckily, this complementary switch exists: the PMOS transistor!

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5 Complementary MOS (CMOS) Logic
CMOS circuits naturally produce inverting logic. NMOS transistors in the
pull-down network are active when their inputs are high. Complementary
PMOS transistors in the pull-up network are active when their inputs are
low. The main advantage is low power consumption, because there is
hardly any current between +5V and GND in either output case. As you
read through this section, think about how you could build the basic logic
gates (AND, OR, XOR) from these inverting circuits.

5.1 CMOS Inverter

In the CMOS Inverter circuit, an NMOS and a PMOS are connected
at their drains where Vout is labeled. Their gates both receive the same
voltage VA.
If VA is high, the NMOS pulls Vout down to ground and the PMOS is
off (open). If VA is low, the PMOS pulls Vout up to +5V and the NMOS
is off (open). This is a NOT gate! Notice that when one transistor pulls
Vout up or down, the other is open.
This is a NOT gate! Critically, There is no direct path for current
between +5V and GND in either case, so vanishingly small current
is drawn from a CMOS inverter.

S
+5V
G
D

VA Vout
D
G
S
GND

Figure 7: CMOS Inverter (NOT) Circuit

https://www.youtube.com/watch?v=docgmTprR5o
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5.2 CMOS NAND
In the CMOS NAND circuit:

• The pull-down network consists of two NMOS transistors in series.

If both NMOS transistors are on, then Vout is pulled down to ground.
This occurs when both VA and VB are high.
• The pull-up network consists of two PMOS transistors in parallel. If
either VA is low or VB is low, then a PMOS transistor pulls Vout up
to +5V.
• The pull-down and pull-up networks are complementary. When one
is closed, the other is open.

This is a NAND gate!

S S +5V
G G
VA VB
D D

D Vout
G
VA
S

D
G
VB
S
GND

Figure 8: CMOS NAND Circuit

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5.3 CMOS NOR
In the CMOS NOR circuit:

• The pull-down network consists of two NMOS transistors in parallel.

If either of the NMOS transistors are on, then Vout is pulled down
to ground. This occurs when either VA or VB are high.
• The pull-up network consists of two PMOS transistors in series. If
both VA is low and VB is low, then the PMOS transistors pull Vout
up to +5V.
• The pull-down and pull-up networks are complementary. When one
is closed, the other is open.

This is a NOR gate!

S +5V
G
VA
D

S
G
VB
D

D D Vout
G G
VA VB
S S
GND

Figure 9: CMOS NOR Circuit

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6 Glossary
• MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor. A
three-terminal device designed to control current flow. The voltage
between the Gate and Source terminals (VGS ) affects the current
that can pass between the Drain and Source (IDS ). A metal oxide
insulator electrically isolates the gate from the substrate (body) of
the transistor. When the potential difference between the gate and
source is sufficiently high, the resulting electric field attracts charge
carriers to the surface, creating a high-conductivity channel within
the substrate.

• Integrated Circuit (IC): A circuit whose elements are built

together on a single die (chunk) of semiconductor material (most
often silicon). An IC usually incorporates transistors with other
circuit elements (resistors, capacitors, etc) built directly onto the
die.

• NMOS: N-channel MOSFET. The majority charge carrier is the

negatively-charged electron, which passes through the n-channel that
connects the drain and source when the gate voltage is sufficiently
high relative to the source. n-type wells at the drain and source are
separated by a p-type bulk.

• PMOS: P-channel MOSFET. The majority charge carrier is the

positively-charged hole, which passes through the p-channel that
connects the drain and source when the gate voltage is sufficiently
low relative to the source. p-type wells at the drain and source are
separated by an n-type bulk.

• CMOS: Complementary Metal-Oxide-Semiconductor. Refers to

the fabrication process and circuits that incorporate both NMOS
and PMOS transistors to lower overall power consumption.

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