KALYANI GOVERNMENT ENGINEERING COLLEGE

DIGITAL SYSTEM DESIGN LAB (EC 392)

DIGITAL SYSTEM DESIGN LAB

LABORATORY MANUAL
Department of Electronics and Communication Engineering
Kalyani Government Engineering College

B.TECH
(2nd Year; 3rd Semester)
Sub Code: EC392

PREPARED BY: DWAIPAYAN GHOSH (ASSISTANT PROFESSOR OF ECE)

 KALYANI GOVERNMENT ENGINEERING COLLEGE

DIGITAL SYSTEM DESIGN LAB (EC 392)

Vision of the Department

To be recognized as a center of excellence producing globally competitive Electronics &
Communication engineering professionals having entrepreneurial abilities and humane values
for betterment of society.

Mission of the Department

 To impart quality education in Electronics & Communication Engineering by offering
updated teaching learning methodologies with a focus on excellence and innovation
 To undertake collaborative projects which offer opportunities for long term interaction
with industry.
 To develop infrastructure for promoting research and consultancy in emerging areas of
technology
 To encourage lab to land activities for social upliftment.
 To produce globally competitive and motivated engineers, researchers and technologists
for sustainable growth of the country.

Program Outcomes (POs)

Engineering Graduates will be able to:

1. Engineering Knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex engineering
problems.
2. Problem Analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate
consideration for public health and safety, and the cultural, societal, and environmental
conditions.
4. Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis
of the information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering
activities with an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant
to the professional engineering practice.
7. Environment and sustainability: Understand the impact of professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and
need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.

PREPARED BY: DWAIPAYAN GHOSH (ASSISTANT PROFESSOR OF ECE)

 KALYANI GOVERNMENT ENGINEERING COLLEGE

DIGITAL SYSTEM DESIGN LAB (EC 392)

9. Individual and team work: Function effectively as an individual, and as a member or leader
in diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and
write effective reports and design documentation, make effective presentations, and give
and receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one's own work, as a member
and leader in a team, to manage projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to engage
in independent and life-long learning in the broadest context of technological change.

Program Educational Objectives (PEOs)

 Be competent to devise and deliver efficient solutions to challenging problems in the
field of Electronics & Communications Engineering and allied disciplines by applying
the theoretical and experimental fundamentals, domain knowledge using modern tools,
techniques and interpersonal skills in a professional manner for early employment in
versatile jobs in reputed industrial organizations/ companies/academia.
 Provide an academic environment that gives adequate opportunity to the students to
cultivate lifelong skills needed for a successful professional career.
 Train students to develop their attitude to adapt new ideas, innovations and technologies
by embracing capability to expand horizons beyond engineering for creativity,
innovation and entrepreneurship.
 Assess and motivate young engineers to become good human beings by inculcating a
sense of ethics, professionalism, and effective communication skills.

Program Specific Outcomes (PSOs)

At the end of the program, the student:
 Should be able to clearly understand the fundamentals of Electronics and
Communication Engineering
 Should possess the skills to communicate in both oral and written forms including
presentations and technical reports, demonstrating the practice of professional ethics and
the concerns for societal and environmental wellbeing.
 Should be able to design electronics and communication systems using electronic
devices, circuits and/or software with the acquired technical knowledge.

PREPARED BY: DWAIPAYAN GHOSH (ASSISTANT PROFESSOR OF ECE)

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DIGITAL SYSTEM DESIGN LAB (EC 392)

Course Outcomes (COs):

1. Realize the fundamentals of digital electronics along with logic gates, their ICs and its
simulation using simulator.

2. Implement different Boolean Functions and construct arithmetic circuits using logic gates.

3. Implement decoder, encoder, multiplexer circuits in breadboard using logic gates and in
VHDL.

4. Realize RS, JK, D and T flip flops using universal logic gates.

5. Realize different types of shift registers and counters using digital ICs as well as using
VHDL.

6. Simulation of inverter circuits using circuit designing softwares.

Correlations between COs & POs

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
EC392.1 3 3 2 2 2 1 1 1 3 3 2 3
EC392.2 3 3 2 2 2 1 1 1 3 3 2 3
EC392.3 3 3 2 2 2 1 1 1 3 3 2 3
EC392.4 3 3 2 2 2 1 1 1 3 3 2 3
EC392.5 3 3 2 2 2 1 1 1 3 3 2 3
EC392.6 3 3 2 2 2 1 1 1 3 3 2 3
3 3 2 2 2 1 1 1 3 3 2 3

Correlations between COs & PSOs

PSO1 PSO2 PSO3
EC692.1 3 2 3
EC692.2 3 2 3
EC692.3 3 2 3
EC692.4 3 2 3
EC692.5 3 2 3
EC692.6 3 2 3
3 2 3

PREPARED BY: DWAIPAYAN GHOSH (ASSISTANT PROFESSOR OF ECE)

 KALYANI GOVERNMENT ENGINEERING COLLEGE

DIGITAL SYSTEM DESIGN LAB (EC 392)

Do’s and Don’ts in the Lab

Do’s Don’ts
Maintain Discipline and follow the Guidelines of
Do not exceed the voltage Rating of the equipment.
the Laboratory.
Understand the theory behind the experiment before Do not interchange the components while doing the
starting the experiment. experiment without consent of the Faculty/TA.

Bring lab copy& manual. Avoid loose connections and short circuits.
Do not use a pen Drive or similar kind devices
All should perform experiments in assigned places.
without permission.
Do not change computer preference settings or
Keep the working table clean.
endeavor to hack into unauthorized areas.
Arrange the chairs/tools and equipment properly
Do not install any programs without permission.
before leaving the lab.

All users of the laboratory are to follow the Do not create any user accounts without
directions of the faculty/Technical Assistants. Faculty/TA permission

Before leaving the lab, you should save your Avoid stepping on electrical wires or any other
programs, and collect your belongings. computer cables.

Shut down the computer after completion of the Do not touch, connect or disconnect any plug or
experiment. cable without your Faculty/ TA’s permission.

Don’t use chat rooms, online games, or multiuser

Keep bags outside before entering the Laboratory
domains.

Collect the components as per the experiments &

Do not come late to the lab.
return after completion.
Do not panic if you don’t get the output, ask
Ask the faculty/TA for assistance if you need help
concerned Faculty/TA for assistance.
Switch of the instruments after completing the
experiments.

Get the experimental results checked by the

concerned Faculty/TA before leaving the
laboratory.

PREPARED BY: DWAIPAYAN GHOSH (ASSISTANT PROFESSOR OF ECE)

 KALYANI GOVERNMENT ENGINEERING COLLEGE

DIGITAL SYSTEM DESIGN LAB (EC 392)

MAKAUT SYLLABUS

1. Introduction to Digital Electronics Lab- Nomenclature of Digital Ics, Specifications, Study of

the Data Sheet, Concept of Vcc and Ground, Verification of the Truth Tables of Logic Gates

using TTL ICs.

2. Implementation of the Given Boolean Function using Logic Gates in Both Sop and Pos
Forms.

3. Verification of State Tables of Rs, J-k, T and D Flip-Flops using NAND & NOR Gates

4. Implementation and Verification of Decoder/De-Multiplexer and Encoder using Logic Gates.

5. Implementation of 4x1 Multiplexer using Logic Gates.

6. Implementation of 4-Bit Parallel Adder Using 7483 IC.

7. Design , and Verify the 4- Bit Synchronous Counter

8. Design, and Verify the 4-Bit Asynchronous Counter.

9. Simulation of MOS Inverter with different loads using PSPICE software

10. Simulation of CMOS Inverter for different parameters Kn, Kp as a design variable in
suitable

circuit simulator software.

11. Design of a 4-bit Multiplexer using VHDL\Verilog

12. Design of a decade counter using VHDL\Verilog.

13. Design of a 3-input NAND gate and its simulation using suitable logic simulator

PREPARED BY: DWAIPAYAN GHOSH (ASSISTANT PROFESSOR OF ECE)

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DIGITAL SYSTEM DESIGN LAB (EC 392)

EXPERIMENT NO: - 1, 2
TITLE: - Introduction to Digital Electronics Lab- Nomenclature of Digital ICs,
Specifications, Study of the Data Sheet, Concept of Vcc and Ground, Verification of the
Truth Tables of Logic Gates using TTL ICs.

Implementation of the Given Boolean Function using Logic Gates in Both SOP and POS
Forms.

OBJECTIVES: -

1. Verification of the truth table of the logic gates

2. To realize the logic gates including the basic gates using Universal logic gates that is to
verify the truth tables of OR, AND, NOT, X-OR and X-NOR gates using NAND and
NOR gates.
3. Realization of random Boolean Function using Basic gates.
4. Realization of random Boolean Function using Universal gates.

THEORETICAL APPROACH: - NAND and NOR gates have the important properties that
using only NAND or only NOR gates repeatedly one can get the logic functions of OR, AND,
NOT, X-OR and X-NOR gates. That is why they are called universal gates. NAND is a
combination gate in which a NOT gate follows an AND gate. NOR is also combination gate in
which a NOT gate follows an OR gate.

PREPARED BY: DWAIPAYAN GHOSH (ASSISTANT PROFESSOR OF ECE)

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DIGITAL SYSTEM DESIGN LAB (EC 392)

Ex-OR

EX-
NOR

Chart 1: - Symbolic diagrams of different Gates and their truth tables.

CIRCUIT DIAGRAM: -

NAND AS NOT:-

NAND AS AND:-

NAND AS OR:-

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DIGITAL SYSTEM DESIGN LAB (EC 392)

NAND AS X-OR:-

NAND AS X-NOR:-

NOR AS NOT:-

NOR AS OR:-

NOR AS AND:-

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DIGITAL SYSTEM DESIGN LAB (EC 392)

NOR AS X-OR:-

NOR AS X-NOR:-

SOME BASIC IDEA ABOUT LOGIC GATE ICs:

In the laboratory we use the combinations of different types of gates to make the circuits. Each
gate has an individual IC number. The following chart gives the IC number of the individual
gates
NUMBER OF
GATE IC NUMBER DESCRIPTION
GATES IN IC
NAND 7400 QUAD TWO INPUT NAND GATE 4

NOR 7402 QUAD TWO INPUT NOR GATE 4

NOT 7404 HEX INVERTER/NOT GATE 6

AND 7408 QUAD TWO INPUT AND GATE 4

NAND(3 I/P) 7410 TRIPLE THREE INPUT NAND GATE 3

AND(3 I/P) 7411 TRIPLE THREE INPUT AND GATE 3

OR 7432 QUAD TWO INPUT OR GATE 4

EX-OR 7486 QUAD TWO INPUT EX-OR GATE 4

EX-NOR 74266 QUAD TWO INPUT EX-NOR GATE 4

Chart 2:- IC number for the individual gates

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DIGITAL SYSTEM DESIGN LAB (EC 392)

Some times for Ex-NOR gate we use the combination of two gates. As Ex-NOR= Ex-OR+NOT
then for Ex-NOR gate we use the combination of Ex-OR & NOT gate (shown in the following
figure).

Fig: - Ex-Nor gate with the combination of Ex-Or & NOT gate

The schematic diagrams of ICs for all of the above gates are same except 7402, 7404, 7410
&7411. Again the 7410 & 7411 have the same IC configuration. We first give a look to the IC
diagram which is same for 7400, 7408, 7432, 7486 and 74266.

Fig: - IC diagram of 7400, 7408, 7432, 7486 and 74266

Now we move to the IC diagram of 7402 and 7404. The following figures shows the IC
diagram of 7402 and 7404

Fig: - IC diagram of 7402 Fig: - IC diagram of 7404

7410 and 7411 have the same IC configuration as both consists of 3 inputs gates.

PREPARED BY: DWAIPAYAN GHOSH (ASSISTANT PROFESSOR OF ECE)

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DIGITAL SYSTEM DESIGN LAB (EC 392)

DEVICES AND COMPONENTS USED IN THIS EXPERIMENT: –

1. Breadboard
2. DC Regulated Power Supply
3. Multimeter
4. Logic Gates
5. Connecting Wires

RESULTS/EXPERIMENTAL OBSERVATIONS: -

• Observation table for Basic gates using universal gates

INPUT OUTPUT
A B Y
LOGIC LED LOGIC LED LOGIC LED
STATE STATUS STATE STATUS STATE STATUS

• Make similar tables for realization of NAND as AND, NOT, X-OR, X-NOR gates and
NOR as OR, AND, NOT, X-OR and X-NOR gate.

• Take a sample Boolean Expression and design that uses Basic gates and Universal
gates. Verify their truth table.

CONCLUSION: -

PREPARED BY: DWAIPAYAN GHOSH (ASSISTANT PROFESSOR OF ECE)

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DIGITAL SYSTEM DESIGN LAB (EC 392)

EXPERIMENT NO: - 3
TITLE: - Verification of State Tables of R-S, J-K, T and D Flip-Flops using NAND and
NOR Gates

OBJECTIVES: -

1. To verify the state tables of RS, JK, T and D flip-flops using NAND and NOR gates.

2. To understand the working of flip-flops.

3. To learn how to implement flip-flops using NAND and NOR gates.

THEORY: - In the case of sequential circuits, the effect of all previous inputs on the outputs is
represented by a state of the circuit. Thus, the output of the circuit at any time depends upon its
current state and the input. These also determine the next state of the circuit. The relationship
that exists among the inputs, outputs, present states, and next states can be specified by either
the state table or the state diagram.

State Table: - The state table representation of a sequential circuit consists of three sections
labeled present state next state and output. The present state designates the state of flip-flops
before the occurrence of a clock pulse. The next state shows the states of flip-flops after the
clock pulse, and the output section lists the value of the output variables during the present
state.

Flip-Flop:- The basic one bit digital memory circuit is known as flip-flop. It can store either 0
or 1. Flip-flops are classified according to the number of inputs.

R-S flip- flop:- The circuit is similar to SR latch except enable signal is replaced by clock
pulse.

Fig:- Block diagram of R-S flip-flop Fig:- State table of R-S Flip-flop

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DIGITAL SYSTEM DESIGN LAB (EC 392)

J-K flip-flop:- - In a RS flip-flop the input R=S=1 leads to an indeterminate output. The R-S
flip-flop circuit may be re-joined if both inputs are 1 than also the outputs are complement of
each other.

Fig:- Block diagram of J-K flip-flop Fig:- State table of J-K Flip-flop

T flip-flop :- T flip-flop is known as toggle flip-flop. The T flip-flop is a modification of the J-

K flip-flop. Both the JK inputs of the JK flip-flop are held at logic 1 and the clock signal
continuous to change.

Fig:- Block diagram of T flip-flop Fig:- State table of T Flip-flop

D flip-flop:- The modified clocked SR flip-flop is known as D-flip-flop. From the truth table of
SR flip-flop we see that the output of the SR flip-flop is in unpredictable state when the inputs
are same and high. In many practical applications, these input conditions are not required.
These input conditions can be avoided by making them complement of each other.

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DIGITAL SYSTEM DESIGN LAB (EC 392)

Fig:- Block diagram of D flip-flop Fig:- State table of D Flip-flop

CIRCUIT DIAGRAM: -

R-S FLIP-FLOP:-

Fig:- R-S flip-flop using NOR gate Fig:- R-S flip-flop using NAND gate

J-K FLIP-FLOP:-

Fig:- J-K flip-flop using NOR gate Fig:- J-K flip-flop using NAND

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DIGITAL SYSTEM DESIGN LAB (EC 392)

T FLIP-FLOP:-

Fig:- T flip-flop using NOR gate Fig:- T flip-flop using NAND

D FLIP-FLOP:-

Fig:- D flip-flop using NOR gate Fig:- D flip-flop using NAND

DEVICES AND COMPONENTS USED IN THIS EXPERIMENT: –

1. Breadboard
2. DC Regulated Power Supply
3. Multimeter
4. Logic Gates
5. Connecting Wires

PREPARED BY: DWAIPAYAN GHOSH (ASSISTANT PROFESSOR OF ECE)

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DIGITAL SYSTEM DESIGN LAB (EC 392)

RESULTS/EXPERIMENTAL OBSERVATIONS: -

 Observation table for R-S flip-flop.

INPUT OUTPUT

A B Qn Qn+1

LOGIC LED LOGIC LED LOGIC LED LOGIC LED

STATE STATUS STATE STATUS STATE STATUS STATE STATUS

 Make similar tables for realization of J-K flip-flop, T flip-flop, D flip-flop.

CONCLUSION: -

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DIGITAL SYSTEM DESIGN LAB (EC 392)

EXPERIMENT NO:- 4
TITLE: Implementation and Verification of Decoder/De- Multiplexer and Encoder
using Logic Gates

OBJECTIVES:-

 To design and implement a decoder, de-multiplexer and an encoder using logic gates.

 To verify the truth tables of the decoder, de-multiplexer and encoder using logic gates.

 To understand the working of the decoder, de-multiplexer and encoder.

THEORY:-

Decoder: A decoder is a combinational logic circuit that converts a binary code into a set of
outputs.

Fig: Block diagram of 2 x 4 decoder

Truth table: Truth table of 2 x 4 decoder

Enable Inputs Outputs

E A1 A0 Y3 Y2 Y1 Y0

0 X X 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0

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DIGITAL SYSTEM DESIGN LAB (EC 392)

De-multiplexer: a de-multiplexer is a combinational logic circuit that takes a single input and
distributes it to one of several possible outputs.

Fig: Block diagram of 1 x 4 de-multiplexer

Truth table: Truth table of 1 x 4 de-multiplexer

Selection Inputs Outputs

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

Encoder: An encoder is a combinational logic circuit that converts a set of inputs into a binary
code. It is the reverse of a decoder function. It has 2n input and n output lines.

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DIGITAL SYSTEM DESIGN LAB (EC 392)

Fig: Block diagram of 4 x 2 encoder

Truth table: Truth table of 4 x 2 encoder

Inputs Outputs

Y3 Y2 Y1 Y0 A1 A0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

CIRCUIT DIAGRAM:-

Fig: 2 x 4 decoder Fig: 1 x 4 de-multiplexer

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DIGITAL SYSTEM DESIGN LAB (EC 392)

Fig: 4 x 2 encoder

DEVICE AND COMPONENTS USED IN THIS EXPERIMENTS:-

 Breadboard

 DC regulated power supply

 Logic Gates

 Connecting wires

RESULT:-

Observation table for decoder

Enable Inputs Outputs

E A1 A0 Y3 Y2 Y1 Y0

LOGIC LED LOGIC LED LOGIC LED LOGIC LED LOGIC LED LOGIC LED LOGIC LED

STATE STAT STATE STAT STATE STAT STATE STAT STATE STAT STATE STAT STATE STAT
US US US US US US US

Make similar tables for realization of de-multiplexer and decoder.

CONCLUSION:-

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DIGITAL SYSTEM DESIGN LAB (EC 392)

EXPERIMENT NO:- 5

TITLE - Implementation of 4x1 Multiplexer using Logic Gates.

OBJECTIVES:- The main objective of this lab is to provide students with hands-on
experience in designing and constructing a 4x1 multiplexer using basic logic gates. This lab
will enhance your understanding of multiplexers, logic gate behavior, and combinational
circuit design. By the end of this lab, you should be able to construct a functional 4x1
multiplexer circuit and verify its operation.

THEORY:-
A 4x1 multiplexer is a device that can select one of four input signals and transmit it to the
output. The selection is done by two control signals, S0 and S1, which can be either 0 or 1.
The output of the multiplexer depends on the combination of S0 and S1, as shown in the truth
table1.

S0 S1 Y
0 0 A0

0 1 A1

1 0 A2
1 1 A3

Y = S0’.S1’.A0 + S0’.S1.A1 + S0.S1’.A2 + S0.S1.A3

This means that the output is equal to A0 when S0 and S1 are both 0, A1 when S0 is 0 and S1
is 1, A2 when S0 is 1 and S1 is 0, and A3 when S0 and S1 are both 1.

The logic expression can be implemented using logic gates, such as AND, OR, and NOT
gates. The circuit diagram for the implementation is shown below:

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DIGITAL SYSTEM DESIGN LAB (EC 392)

The circuit consists of four AND gates, one OR gate, and two NOT gates. Each AND gate
have three inputs: one from the data inputs (A0, A1, A2, or A3), and two from the control
inputs (S0, S1, or their complements). The outputs of the AND gates are connected to the
inputs of the OR gate, which produces the final output.

The multiplexer can be used for various purposes, such as data selection, data routing,
parallel-to-serial conversion, function generation, etc. For example, a multiplexer can be used
to implement any Boolean function by assigning the data inputs to different combinations of
0s and 1s. A multiplexer can also be used to construct higher-order multiplexers by using
lower-order multiplexers as building blocks.
DEVICE AND COMPONENTS USED IN THIS EXPERIMENTS:-

 Breadboard
 power supply
 logic gate ICs (7408, 7432, 7404)
 LEDs
 connecting wires

OBSERVATION: Record the output LED status for each combination of data and select
inputs in a table.

RESULT:-
Verify the results with that of the truth table.

CONCLUSION:-

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DIGITAL SYSTEM DESIGN LAB (EC 392)

EXPERIMENT NO:- 6

TITLE: Implementation of 4-Bit Parallel Adder Using 7483 IC

OBJECTIVE: The objective of this lab experiment is to implement a 4-bit parallel adder
circuit using the 7483 Integrated Circuit (IC). This experiment aims to demonstrate the addition
of two 4-bit binary numbers using hardware components.

THEORY: The 7483 IC is a 4-bit binary full adder which can add two 4-bit binary numbers A
and B along with a carry input (Cin). It performs addition using XOR and AND gates
internally. The IC has four binary inputs (A3, A2, A1, A0), four binary inputs (B3, B2, B1, B0),
a carry input (Cin), four sum outputs (S3, S2, S1, S0), and a carry output (Cout).

PIN CONFIGURATION OF 7483 IC:

COMPONENTS REQUIRED:

1. 7483 4-bit Binary Full Adder IC

2. Breadboard

3. Connecting wires

4. Power supply (5V)

PROCEDURE:

1. Place the 7483 IC on the breadboard.

2. Connect the power supply's positive terminal (+5V) to the Vcc pin (pin 16) of the IC.

3. Connect the ground terminal (GND) of the power supply to the GND pin of the IC.

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DIGITAL SYSTEM DESIGN LAB (EC 392)

4. Connect the binary inputs A0, A1, A2, and A3 to any four available pins on the
breadboard.

5. Connect the binary inputs B0, B1, B2, and B3 to any four available pins on the
breadboard.

6. Connect the carry input (Cin) to a pin on the breadboard.

7. Connect the sum outputs S0, S1, S2, and S3 to LEDs via current-limiting resistors.

8. Connect the carry output (Cout) to an LED via a current-limiting resistor.

9. Set the input switches for A and B to represent the desired 4-bit binary numbers to be
added.

10. Set the carry input (Cin) if needed.

11. Observe the output LEDs to note down the sum of the binary numbers and the carry out.

OBSERVATIONS:

1. Note down the input binary numbers A and B.

2. Record the carry input (Cin), if any.

3. Observe and record the output binary sum (S0, S1, S2, S3) and carry out (Cout).

RESULTS AND DISCUSSION: Compare the obtained results with the expected results based
on binary addition rules. Analyze any discrepancies if present. Ensure the connections are
correct and there are no loose connections or shorts.

CONCLUSION:

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DIGITAL SYSTEM DESIGN LAB (EC 392)

EXPERIMENT NO: - 7

TITLE: - Design and Verify the 4 Bit Synchronous Counter

OBJECTIVES: -

1. To design a 4-bit synchronous counter using J-K flip flops

2. To verify the functionality of the counter using logic analyzer.
3. To understand the working principle of synchronous counter.

THEORY: - A synchronous counter is a type of digital circuit that uses a clock signal to
synchronize the state changes of its flip flops. In a 4-bit synchronous counter, four J-K flip
flops are connected in a cascade configuration, with the output of each flip flop connected to
the clock input of the next flip flop. The clock signal is applied to the clock input of the first
flip flop, and the output of each flip flop represents a single bit of the counter. The counter
can count from 0000 to 1111, and the output of the counter can be used for frequency
division.

CIRCUIT DIAGRAM: -
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DIGITAL SYSTEM DESIGN LAB (EC 392)

Fig:- 4 bit synchronous counter “up” counter

DEVICES AND COMPONENTS USED IN THIS EXPERIMENT: –

1. JK Flip flop ICs

2. Logic Gate ICs
3. Breadboard Trainer Kit.

RESULTS/EXPERIMENTAL OBSERVATIONS: -

 Observation table for 4 bit synchronous counter.

OUTPUT
Q3 Q2 Q1 Q0
Clock
LOGIC LED LOGIC LED OGIC LED LOGIC LED
STATE STATUS STATE STATUS STATE STATUS STATE STATUS

CONCLUSION: -

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DIGITAL SYSTEM DESIGN LAB (EC 392)

EXPERIMENT NO: 8
TITLE:- Design and Verify the 4-Bit Asynchronous Counter

OBJECTIVES:-

 To design and implement a 4-bit asynchronous counter circuit.

 To verify the functionality of the circuit using a logic analyzer.
 To understand the working principle of an asynchronous counter.

THEORY:-

An asynchronous counter is a digital circuit that counts the number of clock pulses applied to
its input. It is also known as a ripple counter because the output of each flip-flop ripples through
to the next flip-flop. In this lab, we will design and implement a 4-bit asynchronous counter
using J-K flip-flops. The circuit will count from 0 to 15 and then repeat.

Truth table: Truth table of 4 bit asynchronous up counter.

CLOCK Q3 Q2 Q1 Q0
1 0 0 0 0
2 0 0 0 1
3 0 0 1 0
4 0 0 1 1
5 0 1 0 0
6 0 1 0 1
7 0 1 1 0
8 0 1 1 1
9 1 0 0 0
10 1 0 0 1
11 1 0 1 0
12 1 0 1 1
13 1 1 0 0
14 1 1 0 1
15 1 1 1 0
16 1 1 1 1

PREPARED BY: DWAIPAYAN GHOSH (ASSISTANT PROFESSOR OF ECE)

 KALYANI GOVERNMENT ENGINEERING COLLEGE

DIGITAL SYSTEM DESIGN LAB (EC 392)

CIRCUIT DIAGRAM:-

Fig: circuit diagram of 4 bit asynchronous up counter

COMPONENTS AND DEVICES USED:-

1. JK Flip flop ICs

2. Logic Gate ICs
3. Breadboard Trainer Kit.

RESULTS / EXPERIMENTAL OBSERVATIONS:- Verification using logic analyzer

Q3 Q2 Q1 Q0

CLOCK LOGIC LED LOGIC LED LOGIC LED LOGIC LED

STATE STATUS STATE STATUS STATE STATUS STATE STATUS

CONCLUSION:-

PREPARED BY: DWAIPAYAN GHOSH (ASSISTANT PROFESSOR OF ECE)

 KALYANI GOVERNMENT ENGINEERING COLLEGE

DIGITAL SYSTEM DESIGN LAB (EC 392)

EXPERIMENT NO: 9

TITLE: Simulation of MOS Inverter with Different Loads Using PSPICE Software

OBJECTIVE: The objective of this experiment is to simulate a MOS (Metal-Oxide-

Semiconductor) inverter circuit with different loads using PSPICE software. By varying the
load resistor, we aim to observe the impact on the voltage transfer characteristics and analyze
the behavior of the inverter under different load conditions.

EQUIPMENT AND SOFTWARE REQUIRED:

1. Computer with PSPICE software installed

2. MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) components

3. Resistors

4. Power supply

CIRCUIT DIAGRAM: The circuit diagram for the MOS inverter with a load resistor is as
follows:

PROCEDURE:

1. Launch PSPICE Software: Turn on the computer and launch the PSPICE software.

2. Create New Project: Start a new project in PSPICE and name it appropriately.

3. Design the Circuit:

 Using the schematic editor in PSPICE, design the MOS inverter circuit as per
the provided circuit diagram.

PREPARED BY: DWAIPAYAN GHOSH (ASSISTANT PROFESSOR OF ECE)

 KALYANI GOVERNMENT ENGINEERING COLLEGE

DIGITAL SYSTEM DESIGN LAB (EC 392)

 Place a MOSFET, a load resistor (R), a voltage source (VDD), and ground
(GND) components onto the workspace.

 Connect these components according to the circuit diagram. Ensure proper

connections and polarities.

4. Define Component Values:

 Assign appropriate values to the components:

 Select an appropriate MOSFET model from the PSPICE library.

 Choose different values for the load resistor (R) to simulate various
load conditions.

5. Set Simulation Parameters:

 Define the simulation parameters such as transient analysis settings (time

duration, time step), and DC sweep settings if necessary.

 Specify the input voltage (VDD) and ground (GND) potentials.

6. Run the Simulation:

 Run the simulation in PSPICE to obtain the voltage transfer characteristics of

the MOS inverter.

 Ensure that the simulation runs without errors.

7. Analyze Results:

 After the simulation is complete, analyze the obtained results.

 Observe the voltage transfer characteristic curve for different load resistor
values.

 Note any changes in the output voltage (Vo) concerning the input voltage
(VDD) under various load conditions.

 Interpret the results and discuss the impact of load resistance on the
performance of the MOS inverter.

8. Documentation and Reporting:

 Document the simulation setup, including component values and simulation

parameters.

 Record the observed results, including voltage transfer characteristic curves

for different load resistor values.

 Summarize the findings and conclusions drawn from the experiment.

PREPARED BY: DWAIPAYAN GHOSH (ASSISTANT PROFESSOR OF ECE)

 KALYANI GOVERNMENT ENGINEERING COLLEGE

DIGITAL SYSTEM DESIGN LAB (EC 392)

 Prepare a comprehensive report documenting the experiment procedure,
results, analysis, and conclusions.

Safety Precautions:

 Ensure that the circuit connections are correct to prevent any short circuits or damage
to the components.

 Handle electronic components and equipment with care to avoid damage.

 Work in a well-ventilated area and be cautious of electrical hazards.

CONCLUSION:

PREPARED BY: DWAIPAYAN GHOSH (ASSISTANT PROFESSOR OF ECE)

 KALYANI GOVERNMENT ENGINEERING COLLEGE

DIGITAL SYSTEM DESIGN LAB (EC 392)

EXPERIMENT NO: 10

TITLE: Simulation of CMOS Inverter for Different Parameters Kn, Kp Using

Circuit Simulator Software

OBJECTIVE: The objective of this experiment is to simulate a CMOS (Complementary

Metal-Oxide-Semiconductor) inverter circuit with varying parameters Kn and Kp, which
represent the transconductance values of NMOS and PMOS transistors respectively. By
adjusting these parameters, we aim to observe their influence on the performance
characteristics of the CMOS inverter and analyze their effects on the circuit's behavior.

EQUIPMENT AND SOFTWARE REQUIRED:

1. Computer with a suitable circuit simulator software installed (e.g., LTspice, Cadence
Virtuoso, etc.)

2. CMOS transistor components (NMOS and PMOS)

3. Resistors

4. Power supply

CIRCUIT DIAGRAM: The circuit diagram for the CMOS inverter is as follows:

PROCEDURE:

1. Launch Circuit Simulator Software: Turn on the computer and launch the circuit
simulator software installed on your system.

2. Create New Project: Start a new project in the circuit simulator software and name it
appropriately.

3. Design the Circuit:

PREPARED BY: DWAIPAYAN GHOSH (ASSISTANT PROFESSOR OF ECE)

 KALYANI GOVERNMENT ENGINEERING COLLEGE

DIGITAL SYSTEM DESIGN LAB (EC 392)

 Using the schematic editor provided by the software, design the CMOS
inverter circuit as per the provided circuit diagram.

 Place NMOS and PMOS transistors, load resistors (R), a voltage source
(VDD), an input signal source, and ground (GND) components onto the
workspace.

 Connect these components according to the circuit diagram. Ensure proper

connections and polarities.

4. Define Transconductance Values (Kn and Kp):

 Specify the transconductance values (Kn and Kp) for the NMOS and PMOS
transistors respectively.

 These values represent the transconductance parameter of the transistors and

can be adjusted to simulate different transistor characteristics.

5. Set Simulation Parameters:

 Define the simulation parameters such as transient analysis settings (time

duration, time step), and input signal characteristics.

 Specify the input voltage (Vin), supply voltage (VDD), and ground (GND)
potentials.

6. Run the Simulation:

 Run the simulation in the circuit simulator software to obtain the output
characteristics of the CMOS inverter.

 Ensure that the simulation runs without errors.

7. Analyze Results:

 After the simulation is complete, analyze the obtained results.

 Observe the voltage transfer characteristics and output waveform of the

CMOS inverter for different transconductance values (Kn and Kp).

 Note any changes in the switching behavior, propagation delay, and noise
margin with varying parameter values.

 Interpret the results and discuss the impact of transconductance values on the
performance of the CMOS inverter.

8. Documentation and Reporting:

 Document the simulation setup, including component values,

transconductance parameters, and simulation parameters.

PREPARED BY: DWAIPAYAN GHOSH (ASSISTANT PROFESSOR OF ECE)

 KALYANI GOVERNMENT ENGINEERING COLLEGE

DIGITAL SYSTEM DESIGN LAB (EC 392)

 Record the observed results, including voltage transfer characteristics and
output waveforms for different parameter values.

 Summarize the findings and conclusions drawn from the experiment.

 Prepare a comprehensive report documenting the experiment procedure,

results, analysis, and conclusions.

Safety Precautions:

 Ensure that the circuit connections are correct to prevent any short circuits or damage
to the components.

 Handle electronic components and equipment with care to avoid damage.

 Work in a well-ventilated area and be cautious of electrical hazards.

CONCLUSION:

PREPARED BY: DWAIPAYAN GHOSH (ASSISTANT PROFESSOR OF ECE)

 KALYANI GOVERNMENT ENGINEERING COLLEGE

DIGITAL SYSTEM DESIGN LAB (EC 392)

EXPERIMENT NO: 11

TITLE: Design of a 4-bit Multiplexer Using VHDL/ Verilog

OBJECTIVE: The objective of this experiment is to design a 4-bit multiplexer using VHDL
(VHSIC Hardware Description Language). The multiplexer will select one of the four input
data streams based on the select lines and output it as a single stream. This experiment aims
to provide hands-on experience in designing digital circuits using VHDL and understanding
the concept of multiplexers.

EQUIPMENT AND SOFTWARE REQUIRED:

1. Computer with VHDL simulation and synthesis tools (e.g., Xilinx ISE, Vivado,
ModelSim, etc.)

2. VHDL code editor (e.g., Notepad++, Visual Studio Code, etc.)

PROCEDURE:

1. Understanding the Multiplexer:

 Familiarize yourself with the concept of a multiplexer (MUX). A multiplexer is a

digital circuit that selects one of several input data streams and forwards it to a single
output line based on a control signal.

2. Circuit Design:

 Design the 4-bit multiplexer circuit using VHDL. The multiplexer should have four
data input lines (D0-D3), two select lines (S0, S1), and a single output line (Y).

 Determine the logic expression for the output (Y) based on the select lines (S0, S1)
and input data lines (D0-D3).

 Define the architecture of the multiplexer using VHDL.

3. VHDL Coding:

 Open a VHDL code editor on your computer.

 Write the VHDL code for the 4-bit multiplexer based on the design specifications.

 Define the entity and architecture of the multiplexer.

 Implement the logic for selecting the appropriate input data based on the select lines.

4. Simulation:

PREPARED BY: DWAIPAYAN GHOSH (ASSISTANT PROFESSOR OF ECE)

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DIGITAL SYSTEM DESIGN LAB (EC 392)

 Simulate the designed multiplexer using VHDL simulation tools.

 Create testbench files to provide input stimuli and verify the functionality of the
multiplexer.

 Run the simulation and observe the output waveform to ensure that the multiplexer
operates correctly under different input conditions.

5. Synthesis:

 Once the simulation is successful, proceed to synthesis to generate the hardware

description file (e.g., .bit, .bitstream) for implementation on FPGA (Field-
Programmable Gate Array) devices.

 Use synthesis tools provided by the FPGA vendor (e.g., Xilinx Vivado, Intel Quartus
Prime) to synthesize the VHDL code and generate the appropriate output files.

6. Implementation on FPGA (Optional):

 If access to FPGA hardware is available, program the synthesized design onto the
FPGA board.

 Verify the functionality of the multiplexer on the FPGA by providing input signals
and observing the output.

7. Documentation and Reporting:

 Document the VHDL code for the 4-bit multiplexer, including the entity declaration,
architecture, and any necessary comments.

 Record the simulation results, including waveforms and testbench outputs.

 Prepare a comprehensive report documenting the experiment procedure, VHDL code,

simulation/synthesis results, and observations.

 Discuss any challenges faced during the design and implementation process, along
with solutions and recommendations for improvement.

Safety Precautions:

 Handle electronic components and equipment with care to avoid damage.

 Ensure proper ventilation and temperature control for the FPGA hardware if
implemented on hardware.

 Follow all safety guidelines provided by the FPGA manufacturer and laboratory
supervisor.

CONCLUSION:

PREPARED BY: DWAIPAYAN GHOSH (ASSISTANT PROFESSOR OF ECE)

 KALYANI GOVERNMENT ENGINEERING COLLEGE

DIGITAL SYSTEM DESIGN LAB (EC 392)

EXPERIMENT NO: 12

TITLE: Design of a Decade Counter Using VHDL/Verilog

OBJECTIVE: The objective of this experiment is to design a decade counter using either
VHDL (VHSIC Hardware Description Language) or Verilog. A decade counter is a digital
circuit that counts sequentially from 0 to 9 and then resets to 0, producing a 4-bit output
representing the current count. This experiment aims to provide hands-on experience in
designing sequential circuits and programming in VHDL/Verilog.

EQUIPMENT AND SOFTWARE REQUIRED:

1. Computer with VHDL/Verilog synthesis and simulation tools (e.g., Xilinx Vivado,
Intel Quartus Prime, ModelSim, etc.)

2. VHDL/Verilog code editor (e.g., Notepad++, Visual Studio Code, etc.)

PROCEDURE:

1. Understanding the Decade Counter:

 Familiarize yourself with the concept of a decade counter. A decade counter is a type
of asynchronous counter that counts sequentially from 0 to 9 and then resets to 0,
producing a 4-bit output representing the current count.

2. Circuit Design:

 Design the decade counter circuit using VHDL or Verilog. The decade counter should
have a clock input (CLK) and a reset input (RESET), and it should produce a 4-bit
output representing the current count (Q3-Q0).

 Determine the logic for incrementing the count and resetting the counter when it
reaches 9.

3. VHDL/Verilog Coding:

 Open a VHDL/Verilog code editor on your computer.

 Write the VHDL/Verilog code for the decade counter based on the design
specifications.

 Define the entity (module) and architecture of the decade counter.

 Implement the logic for incrementing the count and resetting the counter.

4. Simulation:

PREPARED BY: DWAIPAYAN GHOSH (ASSISTANT PROFESSOR OF ECE)

 KALYANI GOVERNMENT ENGINEERING COLLEGE

DIGITAL SYSTEM DESIGN LAB (EC 392)

 Simulate the designed decade counter using VHDL/Verilog simulation tools.

 Create testbench files to provide clock pulses and verify the functionality of the
decade counter.

 Run the simulation and observe the output waveform to ensure that the counter
operates correctly, counting from 0 to 9 and then resetting to 0.

5. Synthesis (Optional):

 If desired, proceed to synthesis to generate the hardware description file (e.g., .bit,
.bitstream) for implementation on FPGA (Field-Programmable Gate Array) devices.

 Use synthesis tools provided by the FPGA vendor (e.g., Xilinx Vivado, Intel Quartus
Prime) to synthesize the VHDL/Verilog code and generate the appropriate output
files.

6. Implementation on FPGA (Optional):

 If access to FPGA hardware is available, program the synthesized design onto the
FPGA board.

 Verify the functionality of the decade counter on the FPGA by providing clock pulses
and observing the output.

7. Documentation and Reporting:

 Document the VHDL/Verilog code for the decade counter, including the entity
declaration, architecture, and any necessary comments.

 Record the simulation results, including waveforms and testbench outputs.

 Prepare a comprehensive report documenting the experiment procedure,

VHDL/Verilog code, simulation/synthesis results, and observations.

 Discuss any challenges faced during the design and implementation process, along
with solutions and recommendations for improvement.

Safety Precautions:

 Handle electronic components and equipment with care to avoid damage.

 Ensure proper ventilation and temperature control for the FPGA hardware if
implemented on hardware.

 Follow all safety guidelines provided by the FPGA manufacturer and laboratory
supervisor.

CONCLUSION:

PREPARED BY: DWAIPAYAN GHOSH (ASSISTANT PROFESSOR OF ECE)

 KALYANI GOVERNMENT ENGINEERING COLLEGE

DIGITAL SYSTEM DESIGN LAB (EC 392)

EXPERIMENT NO: 13

TITLE: Design of a 3-input NAND Gate and Simulation Using Logic Simulator

OBJECTIVE: The objective of this experiment is to design a 3-input NAND gate and
simulate its behavior using a suitable logic simulator. A NAND gate is a fundamental digital
logic gate that produces an output logic low (0) only when all of its input signals are logic
high (1). This experiment aims to provide hands-on experience in designing combinational
logic circuits and simulating their behavior using a logic simulator.

EQUIPMENT AND SOFTWARE REQUIRED:

1. Computer with a suitable logic simulator software installed (e.g., Logisim, Proteus,
Digital Works, etc.)

2. Logic gate components (AND gates, NOT gates)

3. Input switches and Output display component

PROCEDURE:

1. Understanding the NAND Gate:

 Familiarize yourself with the truth table and logic symbol of a 3-input NAND gate.
Understand its behavior, where the output is low only when all of its inputs are high.

2. Circuit Design:

 Design the circuit for a 3-input NAND gate using AND gates and a NOT gate. Use
the De Morgan's theorem to express the NAND function as a combination of AND
and NOT operations.

 Determine the logic expression for the output of the NAND gate based on its three
input signals.

3. Logic Simulator Setup:

 Launch the logic simulator software on your computer.

 Create a new project or workspace for the NAND gate simulation.

4. Circuit Implementation:

 Implement the designed 3-input NAND gate circuit using the logic simulator.

 Place AND gate components and a NOT gate component onto the workspace.

 Connect these components according to the circuit diagram of the 3-input NAND
gate.

PREPARED BY: DWAIPAYAN GHOSH (ASSISTANT PROFESSOR OF ECE)

 KALYANI GOVERNMENT ENGINEERING COLLEGE

DIGITAL SYSTEM DESIGN LAB (EC 392)

5. Input Configuration:

 Add input switches to the circuit to provide input signals.

 Configure the input switches to generate all possible input combinations for a 3-input
NAND gate (000, 001, 010, 011, 100, 101, 110, 111).

6. Simulation:

 Run the simulation in the logic simulator to observe the behavior of the 3-input
NAND gate.

 Verify that the output of the NAND gate corresponds to the truth table of a 3-input
NAND gate.

 Test different input combinations to ensure that the NAND gate operates correctly
under all scenarios.

7. Observations and Analysis:

 Record the simulation results, including the output waveform and truth table for the 3-
input NAND gate.

 Analyze the behavior of the NAND gate and verify that it functions as expected
according to its truth table.

8. Documentation and Reporting:

 Document the circuit design for the 3-input NAND gate, including the logic
expression and circuit diagram.

 Record the simulation setup, input configurations, and simulation results.

 Prepare a comprehensive report documenting the experiment procedure, circuit

design, simulation results, and observations.

 Discuss any discrepancies between the expected behavior and simulation results,
along with possible explanations and solutions.

Safety Precautions:

 Handle electronic components and equipment with care to avoid damage.

 Ensure proper ventilation and temperature control for the electronic components.

 Follow all safety guidelines provided by the logic simulator software and laboratory
supervisor.

CONCLUSION:

PREPARED BY: DWAIPAYAN GHOSH (ASSISTANT PROFESSOR OF ECE)