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Design and implementation of low power test pattern generator using low
transitions LFSR

Conference Paper · April 2017

DOI: 10.1109/ICCSP.2017.8286401

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 International Conference on Communication and Signal Processing, April 6-8, 2017, India

Design and Implementation of Low Power Test

Pattern Generator Using Low Transitions LFSR
Tejas Thubrikar, Sandeep Kakde, Shweta Gaidhani, Shailesh Kamble and Nikit Shah


Abstract— The testing of VLSI circuits entitles many The test vectors are generated by the random sequence test
challenges in term of area overhead, power and latency. The Low pattern which also known as LFSR. The LFSR is the
transition test pattern generation is a very crucial technique for sequential logic circuits used to create pseudorandom binary
testing of a complex architecture of VLSI design. In this paper,
32-bit test pattern generator has been proposed for testing the
sequences (PRBSs). An LFSR circuit consists of a set of M
VLSI design. This 32-bit test pattern generator is implemented registers and feedback taps that establish the sequence of states
with efficient LFSR and with extra combinational circuitry which that the LFSR transitions through. The feedback taps are
achieved Low power consumption. This paper is implemented described by a modulo-2 polynomial. A primitive polynomial
using Xilinx 13.1 ISE design suite in Verilog HDL. The switching generates a maximal length of m-sequence, where the LFSR
activity between the tests vector are reduced, this results in low transitions through the 2m-1 state before repeat sequences,
power consumption. The design of test pattern generation which
yield a power of 23 mW with a latency of 5.194ns. The switching there is a single unused LFSR state. The PRBS is the binary
activity required for 32-bit test pattern generation has been output of the LFSR. The random binary sequence is described
improved and presented in this paper. The experimental result as pseudorandom, as the sequence is continuous in nature and
shows that the total power in low transition linear feedback shift that results from the correlation properties of a random
register is 50.06% less than the conventional LFSR. sequence. Whereas in testing mode the power consumption
increases due to following reasons: high switching activity
Index Terms— Test Pattern Generator (TPG), Linear
between the two consecutive test pattern, during test mode
Feedback Shift Register (LFSR), VLSI Testing, Low Transistion
LFSR, Switching activity. sequential activation of internal core, power utilized by extra
circuitry during circuit under test and low relationship between
the two test vector. In section III describes the proposed work
I. INTRODUCTION and section IV discuss about the simulation result and section
An evolution of current microelectronics industry allows us V concludes the paper.
to make complex digital systems on a single microchip. To
II. PREVIOUS WORK
design such a system is not an easy task anymore because the
increasing density raises a whole set of different problems such There are several approaches has been taken to work out
as size, speed and power consumption of the chip. Nowadays, with the problem of power consumed by the test circuitry
Complex VLSI testing problems such as BIST technique has during testing mode. There are a few techniques that has been
been implemented and widely studied. In the BIST, the test applied to low power consumption during testing are
vectors are generated by using LFSR (Linear feedback shift mentioned in this section. The first technique introduced the
register) and applied to the device under test (DUT) which test pattern generator model has been proposed using LFSR
increases the area overhead therefore, reducing area which is a which can be used for wireless communication application that
vital problem for the realization of Built-in-self test. As BIST proposed a method of TPG can be used efficiently in security
technique requires high hardware overhead, this results in the transmission of codes and with low power consumption and
memory required is more to store precomputed test pattern. also can be used for applications like Data compression, PN
sequence generation [1]. In [2] approach, the test pattern
generator reduces the number of transition by use of an
effective test pattern generator with high percentage fault
coverage in BIST based application. The generation of
Tejas Thubrikar, Sandeep Kakde, Shweta Gaidhani are with the Dept. of
multiple test patterns with single input chain (SIC) vectors i.e.,
Electronics Engineering. Yeshwantrao Chavan College of Engineering, all test pattern are applied to a scan chain is a SIC vector and
Nagpur, India (email: [email protected], changes it to low-level transition pattern generation for all scan
[email protected],[email protected]) chain. Therefore, the proposed test pattern generator can
Shailesh Kamble are with the Dept. of Computer Technology.
Yeshwantrao Chavan College of Engineering, Nagpur, India (email: minimize power by 7 percent during test mode and achieve
[email protected])
Nikit Shah are with the Dept., of Electrical Engineering, San Jose State
University, California-95192 (email: [email protected])

978-1-5090-3800-8/17/$31.00 ©2017 IEEE

0467
 n-bits

Ti b b b b b b b b
Ni,i+1 <=n/2
i1
Inserted T R RR R R RR R Ni.i+1 <=n
Pattern
Ni1,i+1 <=n/2
T i+1 b b b b b b b b

Fig. 1: Pattern Injection based on RI method

1. Low-Transition Pattern Generation Techniques
high fault coverage about 70 percent without increasing the
number of transitions. In [4], the conventional Linear 1.1 Random Injection Method
Feedback Shift Register is replace with the Low-Power Linear The Random injection method inserts a new test vector T i1
Feedback Shift Register which reduces the power dissipation between two test vector such that the summation of the
of device under test with this they achieve minimum number of switching activities between Ti and Ti1 and Ti1 and Ti+1 is same
transition between two tests vector which ultimately reduces as the switching activity between the Ti and Ti+1.
the power consumption which is required by the extra n n n

circuitry. In another approach the power is optimized for low ¦ | t ij  t ij1 | ¦ | t ij1  t ij1
j 1 j 1
¦| t
j 1
i
j  t ij1 |
power BIST based application rather than Linear Feedback …….(1)
Shift Register. The optimized power for modified LFSR is 46 Therefore, by inserting the T bit pattern in between Ti and
i1

% less than normal LFSR. For BIST implementation low Ti+1, which reduces the switching activities between Ti and
power LFSR is efficiently used in which the circuit is tested Ti+1.Whenever two equal-bit position is same between Ti and
with low switching activity. In [5], they proposed that that Ti+1, then the same bit is injected in that position. When a
power is optimized for the BIST using LP-LFSR which transition occurs between the Ti and Ti+1 then the RI injection
generates the TGP; however, there is a major problem of BIST is in the process as shown in fig 1.
that introduces the more switching activities during testing
mode than during the normal mode. In [7] [6], they award the
low correlation between the test vector. Pattern i: Ti 1 1 0 0 1 1 0 1 1 1 0 1 1 1 0 1

III. PROPOSED WORK 4

This paper focuses on low-power LT-LFSR based test 1 R 0 R1 R 0 1 1 R R 1 R 1 R 1 7
Ti1
pattern generator that can be used for testing of both 3
combinatorial and sequential circuits. The proposed
Pattern i+1: Ti+1 1 0 0 1 1 0 0 1 1 0 1 1 0 1 1 1
architecture step-up the correlation between the two tests
vectors which reduces the number of transition i.e. switching
activities between two test vectors. Minimizing the switching Fig. 2: Example of RI injection (R=0)
activity between test vectors will result in reducing the power
consumption. The conventional LFSR architecture is to be The fig. 2 shows an example of generation of an
customized in such a way that it routinely injects intermediate intermediate pattern. The shaded bit shows the number of
patterns between its unique pair of patterns. This can be done transition i.e. (1<=>0) between T i and Ti+1 bit pattern before
by using two scheme i.e. Bipartite and random injection, which injecting is 7.After injecting T i1 bit pattern with R=0 or R=1,
is further discussed in this section and with a minimal number which reduce the number of transitions as 4 or 3.There is a
of switching activity between two test vectors. maximum of 4 transitions occur which we considered as a
We propose a Low Transition Test Pattern Generator that worst case fig. 3 shows the random injection circuit.
introduces two techniques for test vectors generation called
Random Injection (RI) and Bipartite LFSR. In brief, the RI
1.2 Architecture of Bipartite LFSR Technique
technique injects a new pattern between two successive test
patterns by using a random-bit injection (R) whether it can be The realization of an LFSR can be altered to develop some
either ‘0’ or ‘1’, in the consequent bit of an intermediate design performance, such as dissipated power, while testing.
pattern where there is transition occurs in the corresponding Nevertheless, such an alteration may change the sequence of
bit of pattern pairs. patterns or insertion of new patterns will have an effect on the
overall randomness. This technique inserts an intermediate test
pattern between two consecutive random patterns such that the

0468
number of transitions between them is reduced. In this scheme, significance of Mux circuitry is to select either bit from the
an LFSR is separated into two equal half by applying two bipartite lfsr or from injector bit. The FSA i.e. Finite State
nonoverlapping Clk (clock) signals. In other sense, when one Automation is used to generate the control signal i.e. clk1 and
half of LFSR is working, the other half is in inactive mode. An clk2 as overlapping clock signal and the sel1 and sel2 signal to
LFSR consists of number of flip-flops connected in series with select either the upper bit of RI injection circuit or the lower
clock signal is illustrated in Fig. 4 (a). The Fig. 4 (b) shows the bit of the RI injection circuit.
basic structure of the Bipartite LFSR to generate pattern T i1.
The dummy flip-flop adds to the Bipartite LFSR architecture
to store the n/2th bit of LFSR when clk1clk2 = 10 and send LFSR
this value into the (n/2+1) flip-flop when the second half
becomes working (clk1clk2= 01). The operation LFSR is
. . . .
successfully divided into two equal half, and the sheltered flip- n
flop is a merger between these divisions. ... 1 …. n/2 n/2+1 ….
An n-bit LFSR is alienated into two n/2-bit LFSRs, which
collectively diminish the testing and clock tree power
clk
utilization. The limitation of this technique which cuts down
the randomness functionality of the LFSR due to separation of (a)
it into two LFSR and it also wants to generate and distribute
two nonoverlapping clocks signals (with half frequency), Bipartite
which raise the area overhead.
. . . .
t ij t ij1 R 1
...
n/2 n/2+1
...
n

(b)

Fig.4: Patten Generation techniques using (a) LFSR (b) Bipartite LFSR

A Finite-State Automation (FSA) generates controls signal for

test pattern generation process as follows:
1. During 1st clock cycle, clk1clk2 =10 and sel1sel2 =11.
t ij1 The upper half of bipartite LFSR is in active whereas
the lower half is in inactive condition respectively.
With sel1sel2 =11, both half’s of bipartite LFSR are
Fig. 3: RI Injection Circuit sent to the outputs (Out). In this case, say Ti is
generated
A. Implementation Low-Transition Linear Feedback Shift 2. During 2nd clock cycle, clk1clk2 =00 and sel1sel2 =10.
Register Architecture Both half’s of bipartite LFSR are in inactive mode. The
Our projected techniques accomplish two schemes of test Upper half of bipartite LFSR is sent to the outputs (Out
pattern generation (RI and Bipartite LFSR) with minimum [31:16]) and the RI injector circuit outputs are sent to
the outputs (Out [15:0]). In this step, T i1 is generated.
power utilization. We embed these two techniques with LFSR
3. During 3rd clock cycle, clk1clk2 = 01 and sel1sel2 =
structure to fashion LT-LFSR, which provide reduction in
11. The lower half of bipartite LFSR is in working
average power compared to Bipartite LFSR techniques in an
condition whereas upper half of bipartite LFSR is in
LFSR. Nevertheless, due to the high randomness of the inactive mode. The Bipartite LFSR output is latched to
injected patterns, most of the in-between patterns can serve in the output (Out [31:0]).In this, Ti2 is generated.
addition to figures generated by an conventional LFSR in 4. During 4th clock cycle, clk1clk2 =00 and sel1sel2 =01.
terms of error finding. Both half’s of bipartite LFSR are in inactive mode.
Fig. 5 shows 32-bit LT-LFSR structure with Random injection With sel1sel2 =01, the injector outputs are sent to the
and Bipartite LFSR together combined. The LFSR used in LT- outputs (Out [31:16]) and the lower half of bipartite
LFSR is an external-XOR LFSR. As shown in fig. 5, an LFSR to the outputs (Out [15:0]). This generates T i3.
injector circuit has in input from the lower bits of bipartite lfsr 5. During 5th clock cycle process continues by going
and higher input from the output of upper bipartite lfsr. Non - through step 1 to generate T i+1.
overlapping clock signals clk1 and clk2 select half of the
Bipartite LFSR to generate patterns, as shown in Fig. 5. The

0469
 Bipartite
Xor

Upper 16 d-ff Lower 16 d-ff

Dummy ff

clk1 Upp_[31:16] Low_[15:0]

Te
clk2
F
Random Injection Circuit
S
Clk A
sel1 Upp_[31:16] Low_[15:0]

sel2 Mux for upper bit Mux for lower bit

Out [31:16] Out [15:0]

Fig.5. 32-bit LT-LFSR Structure

The architecture shown in fig. 5 contains the 16-bit upper

D-type flip-flop and 16-bit lower D-type flip-flop respectively. IV. HDL SIMULATION RESULT
The dummy flip-flop is used to store the states of last bit In our experimental simulation, we used expression
generated by the upper flip-flop in the clock cycle. The X- X32+X+1 for both LFSR and LT-LFSR to generate 32-bit
ORing operation is used to generate the different pattern. To different test pattern. The simulation result obtained from the
generate the non-overlapping enable signal and select line of Xilinx 13.1 ISE design suite with the target device xc6slxl6-
Mux required 4-cylce of clock. Select signal 1 is used to select 3csg324 in which, we have created value change dump file
the Mux for upper bit and select signal 2 for lower-bit Mux after the post simulation. X-power analyzer is used to
respectively. determine dynamic as well as quiescent power. The result is
Table I illustrate patterns generation of an 8-bit LT-LFSR obtained for each case and comparison done on the basis of
with expression x8+x+1 and seed =01001010. As given in Power, latency, and area overhead as shown in following table.
table I, among two consecutive pattern T i and Ti+1, three From the Table II it is clearly seen that LT-LFSR is power
transitional Pattern are generated which has a total of transition efficient than LFSR.
between Ti and Ti+1 are 6, but the between T i and Ti1 are 2, Ti1
and Ti2 are 2, Ti2 and Ti3 are 3, Ti3 and Ti+1 are 3 respectively. TABLE II
COMPARISON OF POWER DISSIPATION, LATENCY, NO. OF
TABLE I LUT’S FOR CONVECTIONAL LFSR AND LT-LFSR
EXAMPLE OF 8-BIT LT-LFSR

Clk Pattern en1 en2 sel1 sel2 LT-LFSR (R=0) EDA Tool: Xilinx
1 Ti 1 0 1 1 0010 1010 Product Version: ISE 13.1
Target Device: xc6slx16-3csg324
2 Ti1 0 0 1 0 0010 1111
3 Ti2 0 1 1 1 0010 0101
Type of Random Sequence generator
4 Ti3 0 0 0 1 1111 0101
5 Ti+1 1 0 1 1 0001 0101 Parameter
32-bit LFSR 32-bit LT-LFSR

No. of Slices Register 32 28

This reduction of number of transitions ultimately decreases
No. of LUT’s 12 9
the power while testing of device under test. LT-LFSR
decreases the number of transitions between two successive No. of bounded IOBs 34 36
patterns that can be used for complex VLSI circuit testing
which uses power more efficiently. The table I gives an Total Power (mW) 49.00 23.00
example of No. of transition between the two test vector with
Latency (ns) 3.668 5.194
R=0.

0470
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