NOT RECOMMENDED FOR NEW DESIGNS DATASHEET

PLEASE SEE ISL6744A

ISL6744 FN9147
Intermediate Bus PWM Controller Rev.8.00
September 22, 2005

The ISL6744 is a low cost, primary side, double-ended Features

controller intended for applications using full and half-bridge
topologies for unregulated DC/DC converters. It is a voltage- • Precision Duty Cycle and Deadtime Control
mode PWM controller designed for half-bridge and full- • 100µA Start-up Current
bridge power supplies. It provides precise control of
• Adjustable Delayed Overcurrent Shutdown and Restart
switching frequency, adjustable soft-start, precise deadtime
control with deadtimes as low as 35ns, and overcurrent • Adjustable Oscillator Frequency Up to 2MHz
shutdown. • 1A MOSFET Gate Drivers
Low start-up and operating currents allow for easy biasing in • Adjustable Soft-Start
both AC/DC and DC/DC applications. This advanced
BiCMOS design features low start-up and operating • Internal Over Temperature Protection
currents, adjustable switching frequency up to 1MHz, 1A • 35ns Control to Output Propagation Delay
FET drivers, and very low propagation delays for a fast
• Small Size and Minimal External Component Count
response to overcurrent faults.
• Input Undervoltage Protection
Ordering Information • Pb-Free Plus Anneal Available (RoHS Compliant)
TEMP. PKG.
PART NUMBER RANGE (°C) PACKAGE DWG. # Applications
ISL6744AU -40 to 105 8 Ld MSOP M8.118
• Telecom and Datacom Isolated Power
ISL6744AUZ -40 to 105 8 Ld MSOP M8.118
(Note) (Pb-free)
• DC Transformers

ISL6744AB -40 to 105 8 Ld SOIC M8.15 • Bus Converters

ISL6744ABZ -40 to 105 8 Ld SOIC M8.15 Pinout

(Note) (Pb-free) ISL6744 (SOIC, MSOP)
Add “-T” suffix for tape and reel. TOP VIEW
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% SS 1 8 VDD
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil RTD 2 7 OUTB
Pb-free products are MSL classified at Pb-free peak reflow
CS 3 6 OUTA
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020. CT 4 5 GND

FN9147 Rev.8.00 Page 1 of 18

September 22, 2005
September 22, 2005
FN9147 Rev.8.00

ISL6744
VDD
Internal Architecture FL

VBIAS VBIAS
VDD
5.00 V
OUTA
Q
T
UVLO
+ Q
OUTB
- PWM TOGGLE
INTERNAL VBIAS
BG OT SHUTDOWN
130 - 150 C
70uA
GND

ON

SS
VBIAS

+
SS CLAMP
- 15 uA
RTD 2.0 V - + SS CHARGED 3.9 V
IRTD + -

4.0 V
S Q
VBIAS

R Q
160 uA
OC LATCH
ON
2.8 V - PEAK CLK
S Q
+

R Q
CT Q
RESET
- VALLEY DOMINANT Q SS LOW + 0.27 V
0.8 V + 50 µS
RETRIGGERABLE -
ONE SHOT
SS
FAULT LATCH
SET DOMINANT
I DCH= 55 x IRTD

S Q
S Q FL
IDCH
R Q
R Q

PWM LATCH
ON VBIAS
SET
DOMINANT
VBIAS UV -
+
4.65V 4.80V 
BG
OC DETECT
CS +
0.6 V -
Page 2 of 18

SS COMPARATOR

CT +

SS
0.8
September 22, 2005
FN9147 Rev.8.00

Typical Application using ISL6744 - 48V Input DC Transformer, 12V @ 8A Output

ISL6744
SP1
VIN+ +12V
QR1 C11
L1
QH
QR3
T1
C2 L3
R8
C13 C9 C8

RTN
TP1 R10 L2

C1
T2
R9

QR2 QR4
R2 QL

CR3 C14 R11

C12

C3 CR2

R1
TP2
C7 CR1
R6

U4 R5
TP4
ISL6700
VDD LO C10
HB VSS
HO LI
HS HI
C4
C5
TP5
U1

VIN- GND SS

ISL6744
OUTB CS
OUTA CT
C18
VDD RTD
R7
D2

TP6
Q5
C15
Page 3 of 18

C16
D1
R12

C6
ISL6744

Absolute Maximum Ratings Thermal Information

Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V Thermal Resistance (Typical, Note 1) JA (°C/W)
OUTA, OUTB . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VDD 8 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5V 8 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A Maximum Junction Temperature . . . . . . . . . . . . . . . . -55°C to 150°C
ESD Classification Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .2000V Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . .100V
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . .1000V

Operating Conditions
Temperature Range
ISL6744AU . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 105°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . 9-16 VDC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. All voltages are to be measured with respect to GND, unless otherwise specified.

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic. 9V < VD < 16V, RTD = 51.1k, CT = 470pF, TA = -40°C to 105°C (Note 4), Typical values are at
TA = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

SUPPLY VOLTAGE

Start-Up Current, IDD VDD < START Threshold - - 175 A

Operating Current, IDD RLOAD, COUTA,B = 0 - 2.89 - mA

COUTA,B = 1nF - 5 8.5 mA

UVLO START Threshold 5.9 6.3 6.6 V

UVLO STOP Threshold 5.3 5.7 6.3 V

Hysteresis - 0.6 - V

CURRENT SENSE

Current Limit Threshold 0.55 0.6 0.65 V

CS to OUT Delay (Note 4) - 35 - ns

CS Sink Current 8 10 - mA

Input Bias Current -1 - 1 A

PULSE WIDTH MODULATOR

Minimum Duty Cycle VERROR < CT Offset - - 0 %

Maximum Duty Cycle CT = 470pF, RTD = 51.1k - 94 - %

CT = 470pF, RTD = 1.1k(Note 4) - 99 - %

CT to SS Comparator Input Gain (Note 4) - 1 - V/V

SS to SS Comparator Input Gain (Note 4) - 0.8 - V/V

FN9147 Rev.8.00 Page 4 of 18

September 22, 2005
ISL6744

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic. 9V < VD < 16V, RTD = 51.1k, CT = 470pF, TA = -40°C to 105°C (Note 4), Typical values are at
TA = 25°C (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

OSCILLATOR

Charge Current 143 156 170 A

RTD Voltage 1.925 2 2.075 V

Discharge Current Gain 45 - 65 A/A

CT Valley Voltage 0.75 0.8 0.85 V

CT Peak Voltage 2.70 2.80 2.90 V

SOFT-START

Charging Current 45 - 68 µA

SS Clamp Voltage 3.8 4.0 4.2 V

Overcurrent Shutdown Threshold Voltage (Note 4) - 3.9 - V

Overcurrent Discharge Current 12 15 23 A

Reset Threshold Voltage (Note 4) 0.25 0.27 0.30 V

OUTPUT

High Level Output Voltage (VOH) VDD - VOUTA or VOUTB, - 0.5 2.0 V
IOUT = -100mA

Low Level Output Voltage (VOL) IOUT = 100mA - 0.5 1.0 V

Rise Time CGATE = 1nF, VDD = 12V - 17 60 ns

Fall Time CGATE = 1nF, VDD = 12V - 20 60 ns

THERMAL PROTECTION

Thermal Shutdown (Note 4) - 145 - °C

Thermal Shutdown Clear (Note 4) - 130 - °C

Hysteresis, Internal Protection (Note 4) - 15 - °C

NOTES:
3. Specifications at -40°C are guaranteed by design, not production tested.
4. Guaranteed by design, not 100% tested in production.

FN9147 Rev.8.00 Page 5 of 18

September 22, 2005
ISL6744

Typical Performance Curves

65 1-104
CT DISCHARGE CURRENT GAIN

60 CT =
1000pF
680pF
1-103 470pF

DEADTIME (ns)
55

CT = 270pF
50
CT = 100pF
100

45

40
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 10
10 20 30 40 50 60 70 80 90 100
RTD CURRENT (mA) RTD (k)
FIGURE 1. OSCILLATOR CT DISCHARGE CURRENT GAIN FIGURE 2. DEADTIME vs CAPACITANCE

600
1.03

NORMALIZED CHARGING CURRENT

1.02
OSCILLATOR FREQUENCY (kHz)

500

1.01
400
1.00

300 0.99

0.98
200
0.97
100
0.96

0 0.95
100 200 300 400 500 600 700 800 900 1000 -40 -25 -10 5 20 35 50 65 80 95 110
CT (pF) TEMPERATURE (°C)

FIGURE 3. CAPACITANCE vs OSCILLATOR FREQUENCY FIGURE 4. CHARGE CURRENT vs TEMPERATURE

(RTD = 49.9k)

1.07

1.06

1.05
NORMALIZED VOLTAGE

1.04

1.03

1.02

1.01

1.00

0.99

0.98
0 10 20 30 40 50 60 70 80 90 100
RTD (k)

FIGURE 5. TIMING CAPACITOR VOLTAGE vs RTD

FN9147 Rev.8.00 Page 6 of 18

September 22, 2005
ISL6744

Pin Descriptions Functional Description

VDD - VDD is the power connection for the IC. To optimize Features
noise immunity, bypass VDD to GND with a ceramic
The ISL6744 PWM is an excellent choice for low cost bridge
capacitor as close to the VDD and GND pins as possible.
topologies for applications requiring accurate frequency and
The total supply current, IDD, will be dependent on the load deadtime control. Among its many features are 1A FET
applied to outputs OUTA and OUTB. Total IDD current is the drivers, adjustable soft-start, overcurrent protection and
sum of the quiescent current and the average output current. internal thermal protection, allowing a highly flexible design
Knowing the operating frequency, Fsw, and the output with minimal external components.
loading capacitance charge, Q, per output, the average
output current can be calculated from: Oscillator
The ISL6744 has an oscillator with a frequency range to
I OUT = 2  Q  Fsw (EQ. 1)
2MHz, programmable using a resistor RTD and capacitor CT.

RTD - This is the oscillator timing capacitor discharge current The switching period may be considered to be the sum of
control pin. A resistor is connected between this pin and the timing capacitor charge and discharge durations. The
GND. The current flowing through the resistor determines charge duration is determined by CT and the internal current
the magnitude of the discharge current. The discharge source (assumed to be 160A in the formula). The discharge
current is nominally 55x this current. The PWM deadtime is duration is determined by RTD and CT.
determined by the timing capacitor discharge duration. 4
T C  1.25 10  C T s (EQ. 2)
CT - The oscillator timing capacitor is connected between
1
this pin and GND. T D  -----------------------------------------------------------------------------  R TD  C T s (EQ. 3)
CTDisch arg eCurrentGain
CS - This is the input to the overcurrent protection comparator.
1
The overcurrent comparator threshold is set at 0.600V nominal. T OSC = T C + T D = ---------------- s (EQ. 4)
F OSC
The CS pin is shorted to GND at the end of each switching
cycle. Depending on the current sensing source impedance, a where TC and TD are the approximate charge and discharge
series input resistor may be required due to the delay between times, respectively, TOSC is the oscillator free running
the internal clock and the external power switch. period, and FOSC is the oscillator frequency. One output
Exceeding the overcurrent threshold will start a delayed switching cycle requires two oscillator cycles. The actual
shutdown sequence. Once an overcurrent condition is times will be slightly longer than calculated due to internal
detected, the soft-start charge current source is disabled. propagation delays of approximately 5ns/transition. This
The soft-start capacitor begins discharging through a 15µA delay adds directly to the switching duration, and also
current source, and if it discharges to less than 3.9V causes overshoot of the timing capacitor peak and valley
(Sustained Overcurrent Threshold), a shutdown condition voltage thresholds, effectively increasing the peak-to-peak
occurs and the OUTA and OUTB outputs are forced low. voltage on the timing capacitor. Additionally, if very low
When the soft-start voltage reaches 0.27V (Reset charge and discharge currents are used, there will be an
Threshold) a soft-start cycle begins. increased error due to the input impedance at the CT pin.

If the overcurrent condition ceases, and then an additional The above formulae help with the estimation of the
50µs period elapses before the shutdown threshold is frequency. Practically, effects like stray capacitances that
reached, no shutdown occurs. The SS charging current is affect the overall CT capacitance, variation in RTD voltage
re-enabled and the soft-start voltage is allowed to recover. and charge current over temperature, etc. exist, and are best
evaluated in-circuit. Equation 2 follows from the basic
GND - Reference and power ground for all functions on this dV
capacitor current equation, i = C  . In this case, with
device. Due to high peak currents and high frequency dt
variation in dV with RTD (Figure 5), and in charge current
operation, a low impedance layout is necessary. Ground
(Figure 4), results from Equation 2 would differ from the
planes and short traces are highly recommended.
calculated frequency. The typical performance curves may
OUTA and OUTB - Alternate half cycle output stages. Each be used as a tool along with the above equations as a more
output is capable of 1A peak currents for driving power accurate tool to estimate the operating frequency more
MOSFETs or MOSFET drivers. Each output provides very accurately.
low impedance to overshoot and undershoot.
The maximum duty cycle, D, and deadtime, DT, can be
SS - Connect the soft-start timing capacitor between this pin calculated from:
and GND to control the duration of soft-start. The value of the D = T C  T OSC (EQ. 5)
capacitor determines the rate of increase of the duty cycle
during start-up, controls the overcurrent shutdown delay, and DT =  1 – D   T OSC s (EQ. 6)
the overcurrent and short circuit hiccup restart period.

FN9147 Rev.8.00 Page 7 of 18

September 22, 2005
ISL6744

Soft-Start Operation Typical Application

The ISL6744 features a soft-start using an external capacitor The Typical Application Schematic features the ISL6744 in
in conjunction with an internal current source. Soft-start an unregulated half-bridge DC/DC converter configuration,
reduces stresses and surge currents during start-up. often referred to as a DC Transformer or Bus Converter.
The oscillator capacitor signal, CT, is compared to the The input voltage is 48V ±10% DC. The output is a nominal
soft-start voltage, SS, in the SS comparator which drives the 12V when the input voltage is at 48V. Since this is an
PWM latch. While the SS voltage is less than 3.5V, duty unregulated topology, the output voltage will vary
cycle is limited. The output pulse width increases as the proportionately with input voltage. The load regulation is a
soft-start capacitor voltage increases up to 3.5V. This has function of resistance between the source and the converter
the effect of increasing the duty cycle from zero to the output. The output is rated at 8A.
maximum pulse width during the soft-start period. When the
soft-start voltage exceeds 3.5V, soft-start is completed. Circuit Elements
Soft-start occurs during start-up and after recovery from an The converter design is comprised of the following functional
overcurrent shutdown. The soft-start voltage is clamped blocks:
to 4V.
Input Filtering: L1, C1, R1
Gate Drive Half-Bridge Capacitors: C2, C3
The ISL6744 is capable of sourcing and sinking 1A peak
current, and may also be used in conjunction with a Isolation Transformer: T1
MOSFET driver such as the ISL6700 for level shifting. To Primary Snubber: C13, R10
limit the peak current through the IC, an external resistor
may be placed between the totem-pole output of the IC Start Bias Regulator: CR3, R2, R7, C6, Q5, D1
(OUTA or OUTB pin) and the gate of the MOSFET. This Supply Bypass Components: C15, C4
small series resistor also damps any oscillations caused by
the resonant tank of the parasitic inductances in the traces of Main MOSFET Power Switch: QH, QL
the board and the FET’s input capacitance. Current Sense Network: T2, CR1, CR2, R5, R6, R11, C10,
C14
Overcurrent Operation
Overcurrent delayed shutdown is enabled once the soft-start Control Circuit: U1, C18, C16, D2
cycle is complete. If an overcurrent condition is detected, the
Output Rectification and Filtering: QR1, QR2, QR3, QR4,
soft-start charging current source is disabled and the soft-
L2, C9, C8
start capacitor is allowed to discharge through a 15µA
source. At the same time a 50µs retriggerable one-shot timer Secondary Snubber: R8, R9, C11, C12
is activated. It remains active for 50µs after the overcurrent
FET Driver: U4
condition ceases. If the soft-start capacitor discharges to
3.9V, the output is disabled. This state continues until the Bootstrap components for driver: CR4, C5
soft-start voltage reaches 270mV, at which time a new soft-
ZVS Resonant Delay (Optional): L3, C7
start cycle is initiated. If the overcurrent condition stops at
least 50µs prior to the soft-start voltage reaching 3.9V, the Design Specifications
soft-start charging currents revert to normal operation and The following design requirements were selected for
the soft-start voltage is allowed to recover. evaluation purposes:
Thermal Protection Switching Frequency, Fsw: 235kHz
An internal temperature sensor protects the device should
VIN: 48 ± 10% V
the junction temperature exceed 145°C. There is
approximately 15°C of hysteresis. VOUT: 12V (nominal)

Ground Plane Requirements IOUT: 8A (steady state)

Careful layout is essential for satisfactory operation of the POUT: 100W
device. A good ground plane must be employed. VDD should
be bypassed directly to GND with good high frequency Efficiency: 95%
capacitance. Ripple: 1%

FN9147 Rev.8.00 Page 8 of 18

September 22, 2005
ISL6744

Since the converter is operating open loop at nearly 100%

nSR duty cycle, the turns ratio, N, is simply the ratio of the input
voltage to the output voltage divided by 2.
nS
nP V IN 48
N = ------------------------- = --------------- = 2 (EQ. 7)
nS V OUT  2 12  2

nSR
The factor of 2 in the denominator is due to the half-bridge
topology. Only half of the input voltage is applied to the
FIGURE 6. TRANSFORMER SCHEMATIC primary of the transformer.

A PC44HPQ20/6 “E-Core” plus a PC44PQ20/3 “I-Core” from

Transformer Design TDK were selected for the transformer core. The ferrite
The design of a transformer for a half-bridge application is a material is PC44.
straightforward affair, although iterative. It is a process of
The core parameter of concern for flux density is the
many compromises, and even experienced designers will
effective core cross-sectional area, Ae. For the PQ core
produce different designs when presented with identical
pieces selected:
requirements. The iterative design process is not presented
here for clarity. Ae = 0.62cm2 or 6.2e -5m2

The abbreviated design process follows: Using Faraday’s Law, V = N d/dt, the number of primary
turns can be determined once the maximum flux density is
• Select a core geometry suitable for the application. set. An acceptable Bmax is ultimately determined by the
Constraints of height, footprint, mounting preference, and
allowable power dissipation in the ferrite material and is
operating environment will affect the choice.
influenced by the lossiness of the core, core geometry,
• Determine the turns ratio. operating ambient temperature, and air flow. The TDK
• Select suitable core material(s). datasheet for PC44 material indicates a core loss factor of
~400mW/cm3 with a ± 2000 gauss 100kHz sinusoidal
• Select maximum flux density desired for operation. excitation. The application uses a 235kHz square wave
• Select core size. Core size will be dictated by the excitation, so no direct comparison between the application
capability of the core structure to store the required and the data can be made. Interpolation of the data is
energy, the number of turns that have to be wound, and required. The core volume is approximately 1.6cm3, so the
the wire gauge needed. Often the window area (the space estimated core loss is
used for the windings) and power loss determine the final
core size. mW 3 f act 200kHz
P loss  -----------  cm  --------------- = 0.4  1.6  --------------------- = 1.28 W
3 f meas 100kHz
• Determine maximum desired flux density. Depending on cm
the frequency of operation, the core material selected, and (EQ. 8)
the operating environment, the allowed flux density must
be determined. The decision of what flux density to allow 1.28W of dissipation is significant for a core of this size.
is often difficult to determine initially. Usually the highest Reducing the flux density to 1200 gauss will reduce the
flux density that produces an acceptable design is used, dissipation by about the same percentage, or 40%.
but often the winding geometry dictates a larger core than Ultimately, evaluation of the transformer’s performance in
is indicated based on flux density alone. the application will determine what is acceptable.
• Determine the number of primary turns.
From Faraday’s Law and using 1200 gauss peak flux density
• Select the wire gauge for each winding. (B = 2400 gauss or 0.24 tesla)
• Determine winding order and insulation requirements. –6
V IN  T ON 53  2  10
• Verify the design. N = ------------------------------ = ----------------------------------------------------- = 3.56 turns
2  A e  B –5
2  6.2  10  0.24 (EQ. 9)
For this application we have selected a planar structure to
achieve a low profile design. A PQ style core was selected Rounding up yields 4 turns for the primary winding. The peak
because of its round center leg cross section, but there are flux density using 4 turns is ~1100 gauss. From EQ. 7, the
many suitable core styles available. number of secondary turns is 2.

The volts/turn for this design ranges from 5.4V at VIN = 43V
to 6.6V at VIN = 53V. Therefore, the synchronous rectifier
(SR) windings may be set at 1 turn each with proper FET
selection. Selecting 2 turns for the synchronous rectifier

FN9147 Rev.8.00 Page 9 of 18

September 22, 2005
ISL6744

windings would also be acceptable, but the gate drive losses The primary windings have an RMS current of approximately
would increase. 5 A (IOUT x NS/NP at ~ 100% duty cycle). The primary is
configured as 2 layers, 2 turns per layer to minimize the
The next step is to determine the equivalent wire gauge for
winding stack height. Allowing 0.020 inches edge clearance
the planar structure. Since each secondary winding
and 0.010 inches between turns yields a trace width of
conducts for only 50% of the period, the RMS current is
0.0575 inches. Ignoring the terminal and lead-in resistance,
I RMS = I OUT  D = 10  0.5 = 7.07 A (EQ. 10) and using EQ. 11, the inner trace has a resistance of
4.25m, and the outer trace has a resistance of 5.52m.
The resistance of the primary then is 19.5m at 20°C. The
where D is the duty cycle. Since an FR-4 PWB planar
total DC power loss for the primary at 20°C is 489mW.
winding structure was selected, the width of the copper
traces is limited by the window area width, and the number Improved efficiency and thermal performance could be
of layers is limited by the window area height. The PQ core achieved by selecting heavier copper weight for the
selected has a usable window area width of 0.165 inches. windings. Evaluation in the application will determine its
Allowing one turn per layer and 0.020 inches clearance at need.
the edges allows a maximum trace width of 0.125 inches.
The order and geometry of the windings affects the AC
Using 100 circular mils(c.m.)/A as a guideline for current
resistance, winding capacitance, and leakage inductance of
density, and from EQ. 10, 707c.m. are required for each of
the finished transformer. To mitigate these effects,
the secondary windings (a circular mil is the area of a circle
interleaving the windings is necessary. The primary winding
0.001 inches in diameter). Converting c.m. to square mils
is sandwiched between the two secondary windings. The
yields 555mils2 (0.785 sq. mils/c.m.). Dividing by the trace
winding layout appears below.
width results in a copper thickness of 4.44mils (0.112mm).
Using 1.3mils/oz. of copper requires a copper weight of
3.4oz. For reasons of cost, 3oz. copper was selected.

One layer of each secondary winding also contains the

synchronous rectifier winding. For this layer the secondary
trace width is reduced by 0.025 inches to 0.100 inches(0.015
inches for the SR winding trace width and 0.010 inches
spacing between the SR winding and the secondary
winding).

The choice of copper weight may be validated by calculating

the DC copper losses of the secondary winding. Ignoring the
terminal and lead-in resistance, the resistance of each layer
of the secondary may be approximated using EQ. 11. FIGURE 7A. TOP LAYER: 1 TURN SECONDARY AND SR
WINDINGS
2
R = ------------------------  (EQ. 11)
 r 2
t  ln  -----
 r 1

where

R = Winding resistance
 = Resistivity of copper = 669e-9-inches at 20°C
t = Thickness of the copper (3 oz.) = 3.9e-3 inches
r2 = Outside radius of the copper trace = 0.324 or 0.299
inches
r1 = Inside radius of the copper trace = 0.199 inches

The winding without the SR winding on the same layer has a

DC resistance of 2.21m. The winding that shares the layer
with the SR winding has a DC resistance of 2.65m. With FIGURE 7B. INT. LAYER 1: 1 TURN SECONDARY WINDING
the secondary configured as a 4 turn center tapped winding
(2 turns each side of the tap), the total DC power loss for the
secondary at 20°C is 486mW.

FN9147 Rev.8.00 Page 10 of 18

September 22, 2005
ISL6744

0.689
0.358

0.807

0.639

0.403

0.169

0.000
FIGURE 7C. INT. LAYER 2: 2 TURNS PRIMARY WINDING

0.000 0.184 0.479 0.774 1.054

FIGURE 7G. PWB DIMENSIONS

MOSFET Selection
The criteria for selection of the primary side half-bridge FETs
and the secondary side synchronous rectifier FETs is largely
based on the current and voltage rating of the device.
However, the FET drain-source capacitance and gate
charge cannot be ignored.

The zero voltage switch (ZVS) transition timing is dependent

on the transformer’s leakage inductance and the
FIGURE 7D. INT. LAYER 3: 2 TURNS PRIMARY WINDING capacitance at the node between the upper FET source and
the lower FET drain. The node capacitance is comprised of
the drain-source capacitance of the FETs and the
transformer parasitic capacitance. The leakage inductance
and capacitance form an LC resonant tank circuit which
determines the duration of the transition. The amount of
energy stored in the LC tank circuit determines the transition
voltage amplitude. If the leakage inductance energy is too
low, ZVS operation is not possible and near or partial ZVS
operation occurs. As the leakage energy increases, the
voltage amplitude increases until it is clamped by the FET
body diode to ground or VIN, depending on which FET
conducts. When the leakage energy exceeds the minimum
required for ZVS operation, the voltage is clamped until the
energy is transferred. This behavior increases the time
FIGURE 7E. INT. LAYER 4: 1 TURN SECONDARY WINDING
window for ZVS operation. This behavior is not without
consequences, however. The transition time and the period
of time during which the voltage is clamped reduces the
effective duty cycle.

The gate charge affects the switching speed of the FETs.

Higher gate charge translates into higher drive requirements
and/or slower switching speeds. The energy required to
drive the gates is dissipated as heat.

The maximum input voltage, VIN, plus transient voltage,

determines the voltage rating required. With a maximum
input voltage of 53V for this application, and if we allow a
10% adder for transients, a voltage rating of 60V or higher
will suffice.
FIGURE 7F. BOTTOM LAYER: 1 TURN SECONDARY AND SR
WINDINGS

FN9147 Rev.8.00 Page 11 of 18

September 22, 2005
ISL6744

The RMS current through each primary side FET can be Once the estimated transition time is determined, it must be
determined from EQ. 10, substituting 5A of primary current verified directly in the application. The transformer leakage
for IOUT (assuming 100% duty cycle). The result is 3.5A inductance was measured at 125nH and the combined
RMS. Fairchild FDS3672 FETs, rated at 100V and 7.5A capacitance was estimated at 2000pF. Calculations indicate
(rDS(ON) = 22m), were selected for the half-bridge a transition period of ~25ns. Verification of the performance
switches. yielded a value of TD closer to 45ns.

The synchronous rectifier FETs must withstand The remainder of the switching half-period is the charge
approximately one half of the input voltage assuming no time, TC, and can be found from
switching transients are present. This suggests that a device
1 1 –9
capable of withstanding at least 30V is required. Empirical T C = -------------------- – T D = ---------------------------------- – 45  10 = 2.08 s
2  F Sw 3
testing in the circuit revealed switching transients of 20V 2  235  10
(EQ. 14)
were present across the device indicating a rating of at least
60V is required. where FSw is the converter switching frequency.
The RMS current rating of 7.07A for each SR FET requires a Using Figure 3, the capacitor value appropriate to the
low rDS(ON) to minimize conduction losses, which is difficult to desired oscillator operating frequency of 470kHz can be
find in a 60V device. It was decided to use two devices in selected. A CT value of 100pF, 150pF, or 220pF is
parallel to simplify the thermal design. Two Fairchild FDS5670 appropriate for this frequency. A value of 150pF was
devices are used in parallel for a total of four SR FETs. The selected.
FDS5670 is rated at 60V and 10A (rDS(ON) = 14m).
To obtain the proper value for RTD, EQ. 3 is used. Since
Oscillator Component Selection there is a 10ns propagation delay in the oscillator circuit, it
The desired operating frequency of 235kHz for the converter must be included in the calculation. The value of RTD
was established in the Design Criteria section. The selected is 10k.
oscillator frequency operates at twice the frequency of the
Output Filter Design
converter because two clock cycles are required for a
complete converter period. The output filter inductor and capacitor selection is simple
and straightforward. Under steady state operating conditions
During each oscillator cycle the timing capacitor, CT, must be the voltage across the inductor is very small due to the large
charged and discharged. Determining the required duty cycle. Voltage is applied across the inductor only during
discharge time to achieve zero voltage switching (ZVS) is the switch transition time, about 45ns in this application.
the critical design goal in selecting the timing components. Ignoring the voltage drop across the SR FETs, the voltage
The discharge time sets the deadtime between the two across the inductor during the on time with VIN = 48V is
outputs, and is the same as ZVS transition time. Once the
discharge time is determined, the remainder of the period V IN  N S   1 – D 
becomes the charge time. V L = V S – V OUT = ------------------------------------------------  250 mV (EQ. 15)
2N P
The ZVS transition duration is determined by the
transformer’s primary leakage inductance, Llk, by the FET where
Coss, by the transformer’s parasitic winding capacitance,
VL is the inductor voltage
and by any other parasitic elements on the node. The
parameters may be determined by measurement, VS is the voltage across the secondary winding
calculation, estimate, or by some combination of these
VOUT is the output voltage
methods.
If we allow a current ramp, I, of 5% of the rated output
 L lk   2C oss + C xfrmr  (EQ. 12) current, the minimum inductance required is
t zvs  -------------------------------------------------------------------- s
2
V L  T ON 0.25  2.08
L  ------------------------- = ----------------------------- = 1.04 H (EQ. 16)
Device output capacitance, Coss, is non-linear with applied I 0.5
voltage. To find the equivalent discrete capacitance, Cfet, a
charge model is used. Using a known current source, the An inductor value of 1.5H, rated for 18A was selected.
time required to charge the MOSFET drain to the desired With a maximum input voltage of 53V, the maximum output
operating voltage is determined and the equivalent voltage is about 13V. The closest higher voltage rated
capacitance is calculated. capacitor is 16V. Under steady state operating conditions the
ripple current in the capacitor is small, so it would seem
Ichg  t (EQ. 13)
Cfet = -------------------- F appropriate to have a low ripple current rated capacitor.
V
However, a high rated ripple current capacitor was selected

FN9147 Rev.8.00 Page 12 of 18

September 22, 2005
ISL6744

based on the nature of the intended load, multiple buck reduction of the average current through the inductor. The
regulators. To minimize the output impedance of the filter, a implication is that the converter can not supply the same
SANYO OSCON 16SH150M capacitor in parallel with a output current in current limit that it can supply under steady
22F ceramic capacitor were selected. state conditions. The peak current limit setpoint must take
this behavior into consideration. A 5.11 current sense
Current Limit Threshold
resistor was selected for the rectified secondary of current
The current limit threshold is fixed at 0.6V nominal, which is transformer T2 for the ISL6744Eval 1, corresponding to a
the reference to the overcurrent protection comparator. The peak current limit setpoint of about 11A.
current level that corresponds to the overcurrent threshold
must be chosen to allow for the dynamic behavior of an open Performance
loop converter. In particular, the low inductor ripple current The major performance criteria for the converter are
under steady state operation increases significantly as the efficiency, and to a lesser extent, load regulation. Efficiency,
duty cycle decreases. load regulation and line regulation performance are
demonstrated in the following Figures.

14 As expected, the output voltage varies considerably with line

and load when compared to an equivalent converter with a
13 closed loop feedback. However, for applications where tight
regulation is not required, such as those applications that
12
use downstream DC/DC converters, this design approach is
11 viable.

100
10

9 95

8 90
EFFICIENCY (%)

0.9950 0.9960 0.9970 0.9980 0.9990 1.000

TIME (ms) 85
V (L1:1)
I (L1)
85
FIGURE 8. STEADY STATE SECONDARY WINDING
VOLTAGE AND INDUCTOR CURRENT 75

70
15 0 1 2 3 4 5 6 7 8 9 10
LOAD CURRENT (A)

FIGURE 10. EFFICIENCY vs LOAD VIN = 48V

10
12.5

12.25
OUTPUT VOLTAGE (V)

12
5
0.986 0.988 0.990 0.992 0.994 0.996 0.998 1.000
11.75
TIME (ms)
V (L1:1)
I (L1) 11.5

FIGURE 9. SECONDARY WINDING VOLTAGE AND

INDUCTOR CURRENT DURING CURRENT LIMIT 11.25
OPERATION
11
Figures 8 and 9 show the behavior of the inductor ripple 0 1 2 3 4 5 6 7 8 9 10
under steady state and overcurrent conditions. In this LOAD CURRENT (A)
example, the peak current limit is set at 11A. The peak
FIGURE 11. LOAD REGULATION AT VIN = 48V
current limit causes the duty cycle to decrease resulting in a

FN9147 Rev.8.00 Page 13 of 18

September 22, 2005
ISL6744

13.5

13
OUTPUT VOLTAGE (V)

12.5

12

11.5

11

10.5
42 43 44 45 46 47 48 49 50 51 52 53
INPUT VOLTAGE (V)

FIGURE 12. LINE REGULATION AT IOUT = 1A

FIGURE 14. FET DRAIN-SOURCE VOLTAGE

Waveforms
Typical waveforms can be found in the following Figures.
Figure 13 shows the output voltage ripple and noise at a 5A.

FIGURE 15. FET D-S VOLTAGE NEAR-ZVS TRANSITION

FIGURE 13. OUTPUT RIPPLE AND NOISE - 20MHz BW

Figures 14 and 15 show the voltage waveforms at the

switching node shared by the upper FET source and the
lower FET drain. In particular, Figure 15 shows near ZVS
operation at 5A of load when the upper FET is turning off
and the lower FET is turning on. ZVS operation occurs
completely, implying that all the energy stored in the node
capacitance has been recovered. Figure 16 shows the
switching transition between outputs, OUTA and OUTB
during steady state operation. The deadtime duration of
46.9ns is clearly shown.

A 2.7V zener is added between the Vdd pins of ISL6700 and

ISL6744, in order to ensure that the PWM turns on only after
the driver has turned on, thereby ensuring the soft-start
function. Figure 17 shows the soft-start operation.
FIGURE 16. OUTA - OUTB TRANSITION

FN9147 Rev.8.00 Page 14 of 18

September 22, 2005
ISL6744

FIGURE 17. OUTPUT SOFT-START

Component List
REFERENCE
DESIGNATOR VALUE DESCRIPTION

C1 1.0µF Capacitor, 1812, X7R, 100V, 20%

C2, C3 3.3µF Capacitor, 1812, X5R, 50V, 20%

C4 1.0µF Capacitor, 0805, X5R, 16V, 10%

C5 0.1µF Capacitor, 0603, X7R, 16V, 10%

C6, C15 4.7µF Capacitor, 0805, X5R, 10V, 20%

C7 Open Capacitor, 0603, Open or Optional Discrete Stray Capacitance

C8 22µF Capacitor, 1812, X5R, 16V, 20%

C9 150µF Capacitor, Radial, Sanyo 16SH150M

C10, C11, C12, 1000pF Capacitor, 0603, X7R, 50V, 10%

C13, C14

C16 150pF Capacitor, 0603, COG, 16V, 5%

C18 0.01µF Capacitor, 0603, X7R, 16V, 10%

CR1, CR2 Diode, Schottky, BAT54S, 30V

CR3 Diode, Schottky, BAT54, 30V

CR4 Diode, Schottky, SMA, 100V, 2.1A

D1 Zener, 10V,Zetex BZX84C10ZXCT-ND

D2 Zener, 2.7V, BZX84C2V7

L1 190nH Pulse, P2004T

L2 1.5µH Bitech, HM73-301R5

L3 Short Jumper or Optional Discrete Leakage Inductance

P1, P2, P3, P4 Keystone, 1514-2

Q5 NPN Transistor, ON MJD31C

QL, QH FET, Fairchild FDS3672, 100V

FN9147 Rev.8.00 Page 15 of 18

September 22, 2005
ISL6744

Component List (Continued)

REFERENCE
DESIGNATOR VALUE DESCRIPTION

QR1, QR2, QR3, FET, Fairchild FDS5670, 60V

QR4

R1 3.3 Resistor, 2512, 1%

R2 3.01K Resistor, 2512, 1%

R5 5.11 Resistor, 0603, 1%

R6 205 Resistor, 0603, 1%

R7 75.0K Resistor, 0805, 1%

R8, R9 20.0 Resistor, 0805, 1%

R10 18 Resistor, 2512, 1%

R11 100 Resistor, 0603, 1%

R12 10.0K Resistor, 0603, 1%

T1 Custom Midcom 31718

T2 Custom Midcom 31719R

TP1, TP2, TP4, 5002 Keystone

TP5, TP6

SP1 Tektronix Scope Jack, 131-4353-00

U1 Intersil ISL6744AU, MSOP8

U4 Intersil ISL6700IB, SOIC

FN9147 Rev.8.00 Page 16 of 18

September 22, 2005
ISL6744

Mini Small Outline Plastic Packages (MSOP)

N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
E1 E
SYMBOL MIN MAX MIN MAX NOTES

-B- A 0.037 0.043 0.94 1.10 -

INDEX
AREA 1 2 0.20 (0.008) A B C A1 0.002 0.006 0.05 0.15 -
TOP VIEW A2 0.030 0.037 0.75 0.95 -

0.25 4X  b 0.010 0.014 0.25 0.36 9

R1
(0.010) c 0.004 0.008 0.09 0.20 -
R
GAUGE
PLANE D 0.116 0.120 2.95 3.05 3
E1 0.116 0.120 2.95 3.05 4
SEATING
PLANE -C-
L e 0.026 BSC 0.65 BSC -
4X 
A A2 L1 E 0.187 0.199 4.75 5.05 -
L 0.016 0.028 0.40 0.70 6
SEATING
L1 0.037 REF 0.95 REF -
0.10 (0.004) C PLANE
b N 8 8 7
-H- -A-
A1
e R 0.003 - 0.07 - -
D
0.20 (0.008) C C R1 0.003 - 0.07 - -
SIDE VIEW a 0 5o 15o 5o 15o -
CL
 0o 6o 0o 6o -
E1
-B- Rev. 2 01/03
0.20 (0.008) C D END VIEW

NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A - and - B - to be determined at Datum plane
-H- .
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.

FN9147 Rev.8.00 Page 17 of 18

September 22, 2005
 ISL6744

Small Outline Plastic Packages (SOIC)

N
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA H 0.25(0.010) M B M
INCHES MILLIMETERS
E
SYMBOL MIN MAX MIN MAX NOTES
-B-
A 0.0532 0.0688 1.35 1.75 -

1 2 3 A1 0.0040 0.0098 0.10 0.25 -

L
B 0.013 0.020 0.33 0.51 9
SEATING PLANE C 0.0075 0.0098 0.19 0.25 -
-A-
A h x 45°
D 0.1890 0.1968 4.80 5.00 3
D
E 0.1497 0.1574 3.80 4.00 4
-C- e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -
e A1
C h 0.0099 0.0196 0.25 0.50 5
B 0.10(0.004)
L 0.016 0.050 0.40 1.27 6
0.25(0.010) M C A M B S
N 8 8 7
NOTES:  0° 8° 0° 8° -
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Rev. 1 6/05
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

© Copyright Intersil Americas LLC 2004-2005. All Rights Reserved.

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com

FN9147 Rev.8.00 Page 18 of 18

September 22, 2005