Unit-2

MOS Amplifiers
Contents
Text Book
• Adel S. Sedra and Kenneth C. Smith, “Microelectronic circuits”, 7th
Edition, Oxford University Press, 2014.
• Behzad Razavi, “Fundamentals of Microelectronics", 2nd Edition,
Wiley, 2009.
Introduction
• MOSFET stands for Metal Oxide Semiconductor Field Effect Transistor
• Three Terminals: Source(S), Drain(D) and Gate(G)
• Voltage controlled Switch.
• The voltage applied to the gate determines the current flow between the
source and drain terminals
• MOSFET is also known as Insulated Gate Field Effect Transistor or
IGFET
Introduction
• Classification
1. Based on Charge Carriers
i N-Channel
ii P-Channel
2. Based on operation
i Enhancement Type
ii Depletion Type
N-MOSFET device structure
• The Enhancement mode NMOS transistor
is fabricated on a p-type substrate, which is
a single-crystal silicon wafer that provides
physical support for the device
• Two heavily doped n-type regions (n+),
source and drain regions, are created in
the substrate.
• A thin layer of silicon dioxide (SiO2) of
thickness tox (typically 1 nm to 10 nm),
which is an excellent electrical insulator, is
grown on the surface of the substrate,
covering the area between the source and
drain regions.
N-MOSFET device structure
• Metal is deposited on top of the oxide
layer to form the gate electrode of the
device.
• Metal contacts are also made to the source
region, the drain region, and the substrate,
also known as the body.
• Thus four terminals are brought out: the
gate terminal (G), the source terminal (S),
the drain terminal (D), and the substrate or
body terminal (B)
• Another name for the MOSFET is the insulated-gate
FET or IGFET.
• This emphasizes the fact that the gate electrode is
electrically insulated from the device body causing
the current in the gate terminal to be extremely
small.
MOSFET Structure

• With n-type source/drain and p-type substrate, the transistor

operates with electrons and is therefore called an n-type MOS
(NMOS) device
P-MOSFET device structure
• The Enhancement mode PMOS transistor is
fabricated on a n-type substrate, which is a
single-crystal silicon wafer that provides physical
support for the device
• Two heavily doped p-type regions (p+), source
and drain regions, are created in the substrate.
Polysilicon is deposited on top of the oxide layer
to form the gate electrode of the device.
• The four terminals are Gate (G), the source (S),
the drain (D), and the substrate or body terminal
(B).
MOSFET Structure

• Changing the doping polarities of the substrate and the S/D areas
results in a PMOS device.
Physical Structure
• A simple geometry consisting of a metal plate, an insulator (SiO2),
and a doped piece of semiconductor(Si), operates as a capacitor.

• When a potential V1 is applied, the positive charge applied to the top

plate attracts electrons from the piece of silicon creating a “channel"
of free electrons at the interface between the insulator and the piece
of silicon.
Physical Structure
• The density of electrons in the channel varies with V1, as Q = CV ,
where C is the capacitance between the two plates.

• A current, if allowed to flow from through the silicon material, can be

controlled by V1 by adjusting the resistivity of the channel
Physical Structure

• When a voltage V2 is applied between S and D, current flow as a

result of potential difference.
MOSFET Operation
• Consider the MOSFET circuit where the S and D are grounded and the
gate voltage is varied.

• As VG increases from zero, the +charge on the gate repels the holes in
the substrate, thereby creating a depletion region.
MOSFET Operation
• +ve charge on the gate is mirrored by -ve charge in the substrate, but
as no channel of mobile charge is created there is no current flow.
• The MOSFET is said to be OFF
MOSFET Operation
• If VG becomes sufficiently positive, free electrons are attracted to the
oxide-silicon interface, forming a conductive channel.
• The MOSFET is said to be ON

• The gate potential at which the channel begins to appear is called the
threshold voltage (Vth)
MOSFET Operation
• The Gate terminal of the MOSFET draws no current.
• As it rests on the oxide layer, the gate remains insulated from other
terminals and hence the name Insulated Gate Field Effect Transistor
MOSFET as Variable Resistor
Transfer Characteristics
• Consider the MOSFET circuit where the S is grounded and D is
connected to a Voltage Source.

• If VG < Vth, no channel exists, the device is off, and ID = 0 regardless of

value of VD.
Transfer Characteristics
• If VG < Vth, no channel exists, the device is off, and ID = 0 regardless of
value of VD.

• If VG > Vth, then ID > 0.

Channel Pinch-off
Channel Pinch-off
Overall MOS characteristic.
On Resistance (Ron)
Explain the output characteristics of N
channel MOSFET
Channel Length Modulation
• The variation in IDS due to change in channel length caused by
movement of Pinch-off point is known as Channel Length Modulation

• This phenomenon yields a larger drain current as VDS increases

because ID α 1/L

• where λ is called the “Channel Length Modulation Coeficient"

Regions of operations of n-MOSFET
𝑽𝑮𝑺 < 𝑽𝑻𝑯 OFF
𝑽𝑮𝑺 > 𝑽𝑻𝑯 , and 𝑽𝑫𝑺 > 𝑽𝑮𝑺 − 𝑽𝑻𝑯 Saturation
𝑽𝑮𝑺 > 𝑽𝑻𝑯 , and 𝑽𝑫𝑺 < 𝑽𝑮𝑺 − 𝑽𝑻𝑯 Triode
MOSFET Amplifier
• For MOSFET to work as an amplifier, it should operate in saturation
region
• VGS>VTH
• VDS>VGS-VTH
• Determine the region of operation of M1 in each of the circuits
shown in Fig.
• Assume λ = 0, compute W/L of M1 in Fig such that the device
operates at the edge of saturation.
• In the Fig. ,what is the minimum allowable value of VDD if M1 must
not enter the triode region? Assume λ = 0.
MOSFET Biasing-Voltage Divider Biasing
Numerical
Self Biasing
Since IG=0, voltage drop across RG, IGRG=0
Numerical
MOS Transconductance gm
• For a MOS transistor higher value of Transconductance corresponds to a greater
change in the drain current for a given change in VGS
• It is determined in saturation region

𝑔𝑚 2 2𝐼𝐷
= 𝑔𝑚 =
𝐼𝐷 𝑉𝐺𝑆 − 𝑉𝑇𝐻 𝑉𝐺𝑆 − 𝑉𝑇𝐻
MOS Transconductance gm

2 𝐼𝐷 𝐿
𝑉𝐺𝑆 − 𝑉𝑇𝐻 =
𝜇𝑛 𝑐𝑜𝑥 𝑊
MOS Transconductance gm
2𝐼𝐷
𝑔𝑚 =
𝑉𝐺𝑆 − 𝑉𝑇𝐻
Numerical

𝑊
𝜇𝑛 𝑐𝑜𝑥 𝐿
=0.05

𝑉𝐺𝑆 =0.6
MOS DEVICE MODELS
• Large-Signal Model
• For arbitrary voltage and current levels,

Deep Triode region

MOS DEVICE MODELS
• Small-Signal Model
• If the bias currents and voltages of a MOSFET are only slightly disturbed by
signals, the nonlinear, large-signal models can be reduced to linear, small-
signal representations
• Viewing the MOSFET as a voltage controlled current source, we draw the
basic model as in Fig. , where iD = gmvGS and the gate remains open.
MOS DEVICE MODELS
• Small-Signal Model
• To represent channel-length modulation, i.e., variation of iD with vDS, we add a
resistor as in Fig.
MOS AMPLIFIER TOPOLOGIES
• Common-Source Topology
• Common Gate
• Common Drain(Source follower)

49
Common-Source Topology
• Input applied to the gate and the output sensed at the drain
• M1 converts the input voltage variations to proportional drain current
changes, and RD transforms to the output voltage

50
Common-Source Topology

• We deal with the CS amplifier in two phases:

(a) AC analysis of the CS core to understand its fundamental properties, and
(b) AC analysis of the CS stage including the bias circuitry as a more realistic
case

51
AC Analysis of CS Core

• In order to examine the amplifying properties of the CS stage, we

construct the small-signal equivalent of the circuit,

52
AC Analysis of CS Core

• In order to examine the amplifying properties of the CS stage, we

construct the small-signal equivalent of the circuit. Constructing the
small signal model for CS Core neglecting Channel length modulation

53
AC Analysis of CS Core

• AC analysis is performed to obtain the small signal quantities

• Voltage Gain
• Input Impedance
• Output Impedance

54
AC Analysis of CS Core
• Voltage gain Av

• Writing a KCL at the Drain node

55
AC Analysis of CS Core
• Input Impedance
• The input impedance is obtained by applying a small change in the
input voltage and measuring the resulting change in the input current

• Since gate terminal of MOSFET draws zero current,

56
AC Analysis of CS Core
• Output Impedance
• The output impedance is obtained by applying a small voltage change
at the output and measuring the resulting change in the output
current with the input shorted

57
AC Analysis of CS Core Source Degeneration

• The degeneration resistor sustains a fraction of the input voltage

change.

58
AC Analysis of CE Core Emitter Degeneration
• Small-signal equivalent if λ = 0.

59
AC Analysis of CE Core Emitter Degeneration
• Small-signal equivalent if λ = 0.
• Applying KVL at input loop

60
AC Analysis of CS Core with source
degeneration
• Input Impedance
• The input impedance is obtained by applying a small change in the
input voltage and measuring the resulting change in the input current

• Since gate terminal of MOSFET draws zero current,

61
AC Analysis of CS Core with source
degeneration
• Output Impedance
• The output impedance is obtained by applying a small voltage change
at the output and measuring the resulting change in the output
current with the input shorted

𝑣𝑥
𝐴𝑝𝑝𝑙𝑦𝑖𝑛𝑔 𝐾𝐶𝐿 𝑎𝑡 𝐷𝑟𝑎𝑖𝑛 𝑖𝑥 = + 𝑔𝑚 𝑣1
𝑅𝐷

62
AC Analysis of CS Core with source
degeneration
𝑣𝑥
𝐴𝑝𝑝𝑙𝑦𝑖𝑛𝑔 𝐾𝐶𝐿 𝑎𝑡 𝐷𝑟𝑎𝑖𝑛 𝑖𝑥 = + 𝑔𝑚 𝑣1 … . . 1
𝑅𝐷

𝐴𝑝𝑝𝑙𝑦𝑖𝑛𝑔 𝐾𝑉𝐿 𝑎𝑡 𝑡ℎ𝑒 𝑖𝑛𝑝𝑢𝑡 𝑙𝑜𝑜𝑝 − 𝑣1 − 𝐼𝑠 𝑅𝑠 = 0 … (2)

𝐶𝑢𝑟𝑟𝑒𝑛𝑡 𝑡ℎ𝑟𝑜𝑢𝑔ℎ 𝑅𝑠 𝑖𝑠 𝑔𝑚 𝑣1

𝑣𝑥
𝐹𝑟𝑜𝑚 𝑒𝑞𝑢𝑎𝑡𝑖𝑜𝑛 1 𝐼𝑠 = 𝑔𝑚 𝑣1 = 𝑖𝑥 − ….. 3
𝑅𝐷

𝑣𝑥
𝑠𝑢𝑏𝑠𝑡𝑖𝑡𝑢𝑡𝑖𝑛𝑔 3 𝑖𝑛 2 − 𝑣1 − 𝑖𝑥 − 𝑅𝑠 = 0
𝑅𝐷

𝑣𝑥
𝑣1 = − 𝑖𝑥 − 𝑅 … … (4)
𝑅𝐷 𝑠
63
AC Analysis of CS Core with source
degeneration
• Output Impedance

𝑣𝑥
𝐴𝑝𝑝𝑙𝑦𝑖𝑛𝑔 𝐾𝐶𝐿 𝑎𝑡 𝐷𝑟𝑎𝑖𝑛 𝑖𝑥 = + 𝑔𝑚 𝑣1 … . . 1
𝑅𝐷

𝑣𝑥
𝑣1 = − 𝑖𝑥 − 𝑅𝑠 … … (4)
𝑅𝐷
𝑣𝑥 𝑣𝑥
𝑠𝑢𝑏𝑠𝑡𝑖𝑡𝑢𝑖𝑛𝑔 4 𝑖𝑛 1 𝑖𝑥 = − 𝑔𝑚 𝑖𝑥 − 𝑅𝑠
𝑅𝐷 𝑅𝐷
𝑣𝑥
𝑅𝑒𝑎𝑟𝑟𝑛𝑔𝑖𝑛𝑔 𝑖𝑥 1 + 𝑔𝑚 𝑅𝑠 = 1 + 𝑔𝑚 𝑅𝑠
𝑅𝐷

64
AC Analysis of CS Core with source
degeneration
• Output Impedance

𝑣𝑥
𝑅𝑒𝑎𝑟𝑟𝑛𝑔𝑖𝑛𝑔 𝑖𝑥 1 + 𝑔𝑚 𝑅𝑠 = 1 + 𝑔𝑚 𝑅𝑠
𝑅𝐷
𝑣𝑥
𝑍𝑜 = = 𝑅𝐷
𝑖𝑥

65
Numerical
AC Analysis of CS Core with source
degeneration and λ≠0
• Draw a neat circuit diagram of a Common Source stage with
degeneration. Draw its small signal model and obtain the expression
for small signal gain, input and output impedance considering λ≠0.
AC Analysis of CS Core with source
degeneration and λ≠0
• Output impedance
CS Stage with Biasing

73
CS Stage with Biasing

74
CS Stage with Biasing

𝑣𝑥
𝐴𝑝𝑝𝑙𝑦𝑖𝑛𝑔 𝐾𝐶𝐿 𝑎𝑡 𝐷𝑟𝑎𝑖𝑛 𝑖𝑥 = + 𝑔𝑚 𝑣1
𝑅𝐷

75
CS stage with biasing
𝑣𝑥
𝐴𝑝𝑝𝑙𝑦𝑖𝑛𝑔 𝐾𝐶𝐿 𝑎𝑡 𝐷𝑟𝑎𝑖𝑛 𝑖𝑥 = + 𝑔𝑚 𝑣1 … . . 1
𝑅𝐷

𝐴𝑝𝑝𝑙𝑦𝑖𝑛𝑔 𝐾𝑉𝐿 𝑎𝑡 𝑡ℎ𝑒 𝑖𝑛𝑝𝑢𝑡 𝑙𝑜𝑜𝑝 − 𝑣1 − 𝐼𝑠 𝑅𝑠 = 0 … (2)

𝐶𝑢𝑟𝑟𝑒𝑛𝑡 𝑡ℎ𝑟𝑜𝑢𝑔ℎ 𝑅𝑠 𝑖𝑠 𝑔𝑚 𝑣1

𝑣𝑥
𝐹𝑟𝑜𝑚 𝑒𝑞𝑢𝑎𝑡𝑖𝑜𝑛 1 𝐼𝑠 = 𝑔𝑚 𝑣1 = 𝑖𝑥 − ….. 3
𝑅𝐷

𝑣𝑥
𝑠𝑢𝑏𝑠𝑡𝑖𝑡𝑢𝑡𝑖𝑛𝑔 3 𝑖𝑛 2 − 𝑣1 − 𝑖𝑥 − 𝑅𝑠 = 0
𝑅𝐷

𝑣𝑥
𝑣1 = − 𝑖𝑥 − 𝑅 … … (4)
𝑅𝐷 𝑠
76
CS stage with biasing
• Output Impedance

𝑣𝑥
𝐴𝑝𝑝𝑙𝑦𝑖𝑛𝑔 𝐾𝐶𝐿 𝑎𝑡 𝐷𝑟𝑎𝑖𝑛 𝑖𝑥 = + 𝑔𝑚 𝑣1 … . . 1
𝑅𝐷

𝑣𝑥
𝑣1 = − 𝑖𝑥 − 𝑅𝑠 … … (4)
𝑅𝐷
𝑣𝑥 𝑣𝑥
𝑠𝑢𝑏𝑠𝑡𝑖𝑡𝑢𝑖𝑛𝑔 4 𝑖𝑛 1 𝑖𝑥 = − 𝑔𝑚 𝑖𝑥 − 𝑅𝑠
𝑅𝐷 𝑅𝐷
𝑣𝑥
𝑅𝑒𝑎𝑟𝑟𝑛𝑔𝑖𝑛𝑔 𝑖𝑥 1 + 𝑔𝑚 𝑅𝑠 = 1 + 𝑔𝑚 𝑅𝑠
𝑅𝐷

77
CS stage with biasing

• Output Impedance

𝑣𝑥
𝑅𝑒𝑎𝑟𝑟𝑛𝑔𝑖𝑛𝑔 𝑖𝑥 1 + 𝑔𝑚 𝑅𝑠 = 1 + 𝑔𝑚 𝑅𝑠
𝑅𝐷
𝑣𝑥
𝑍𝑜 = = 𝑅𝐷
𝑖𝑥

78
 a) VRS=200mV

=IDRS ID=2mA

For M1 to stay in saturation,

VDS≥VGS-Vt
VDS=VD-VS=(1.8-2mx500)-0.2=0.6V
VGS-Vt≤0.6V
1 𝑊
𝑖𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑣𝐺𝑆 − 𝑣𝑡 2
2 𝐿
𝑊
is minimum when 𝑣𝐺𝑆 − 𝑣𝑡 is maximum
𝐿

ie 𝑣𝐺𝑆 − 𝑣𝑡 =0.6V
𝑊
=56
𝐿

With 𝑣𝐺𝑆 − 𝑣𝑡 =0.6V, VGS=1V, VG=1.2V

Numerical
 CS core with biasing and gate resistor
• For the circuit shown in Figure , draw the small signal model and
obtain the expression for voltage gain Av, input impedance Rin
considering λ=0 𝑣𝑖𝑛 (𝑅1 ||𝑅2 )
′
𝑣𝑖𝑛 =
𝑅𝐺 + (𝑅1 ||𝑅2 )

′
𝑣𝑖𝑛 − 𝑉1 − 𝑔𝑚 𝑉1 𝑅𝑠 = 0

Applying KCL at the output node ′

𝑣𝑖𝑛
𝑉1 =
−𝑉𝑜𝑢𝑡 1 + 𝑔𝑚 𝑅𝑠
= 𝑔𝑚 𝑉1
𝑅𝐷
1 𝑣𝑖𝑛 (𝑅1 ||𝑅2 )
−𝑉𝑜𝑢𝑡 1 𝑣𝑖𝑛 (𝑅1 ||𝑅2 ) 𝑉1 =
= 𝑔𝑚 1 + 𝑔𝑚 𝑅𝑠 𝑅𝐺 + (𝑅1 ||𝑅2 )
𝑅𝐷 1 + 𝑔𝑚 𝑅𝑠 𝑅𝐺 + (𝑅1 ||𝑅2 )
𝑅𝑖𝑛 = 𝑅𝐺 + (𝑅1 ||𝑅2 )
𝑉𝑜𝑢𝑡 𝑔𝑚 𝑅𝐷 (𝑅1 ||𝑅2 )
=−
𝑣𝑖𝑛 1 + 𝑔𝑚 𝑅𝑠 𝑅𝐺 + (𝑅1 ||𝑅2 )
 CS core with biasing and gate resistor
• For the circuit shown in Figure, draw the small signal model and
obtain the expression for voltage gain Av, input impedance Rin
considering λ=0 𝑣𝑖𝑛 (𝑅1 ||𝑅2 )
′
𝑣𝑖𝑛 =
𝑅𝐺 + (𝑅1 ||𝑅2 )

′
𝑣𝑖𝑛 − 𝑉1 = 0

Applying KCL at the output node ′

𝑉1 = 𝑣𝑖𝑛
−𝑉𝑜𝑢𝑡
= 𝑔𝑚 𝑉1
𝑅𝐷
𝑣𝑖𝑛 (𝑅1 ||𝑅2 )
−𝑉𝑜𝑢𝑡 𝑣𝑖𝑛 (𝑅1 ||𝑅2 ) 𝑉1 =
= 𝑔𝑚 𝑅𝐺 + (𝑅1 ||𝑅2 )
𝑅𝐷 𝑅𝐺 + (𝑅1 ||𝑅2 )
𝑅𝑖𝑛 = 𝑅𝐺 + (𝑅1 ||𝑅2 )
𝑉𝑜𝑢𝑡 (𝑅1 ||𝑅2 )
= −𝑔𝑚 𝑅𝐷
𝑣𝑖𝑛 𝑅𝐺 + (𝑅1 ||𝑅2 )
Source follower
• The source follower senses the input at the gate and produces the
output at the source, with the drain tied to VDD.

• The Drain is tied to VDD and hence ac ground

85
Source follower

• We deal with the CD amplifier in two phases:

(a) AC analysis of the Source follower core to understand its fundamental
properties, and
(b) AC analysis of the Source follower including the bias circuitry as a more
realistic case

86
Source Follower
Small signal equivalent considering channel length modulation
Numerical
Source Follower With Biasing

𝐴𝑝𝑝𝑙𝑦𝑖𝑛𝑔 𝐾𝑉𝐿 𝑡𝑜 𝑖𝑛𝑝𝑢𝑡 𝑙𝑜𝑜𝑝, 𝑉𝐷𝐷 − 𝐼𝐺 𝑅𝐺 − 𝑉𝐺𝑆 − 𝐼𝐷 𝑅𝑆 = 0

Since, 𝐼𝐺 =0, 𝑉𝐷𝐷 = 𝑉𝐺𝑆 + 𝐼𝐷 𝑅𝑆
 2𝐼𝐷
𝑔𝑚 =
𝑉𝐺𝑆 − 𝑉𝑇𝐻
Source Follower With Biasing
Source Follower With Biasing
Source follower with voltage divider biasing
Source follower with voltage divider biasing
Source follower with voltage divider biasing
Source follower with voltage divider biasing
P-Channel MOSFET
P-Channel MOSFET
P-Channel MOSFET
Regions of operations of p-MOSFET
|𝑽𝑺𝑮 | > |𝑽𝑻𝑯 | ON
𝑽𝑺𝑮 > |𝑽𝑻𝑯 | , and 𝑽𝑺𝑫 < |𝑽𝑺𝑮 | − |𝑽𝑻𝑯 | Triode
𝑽𝑺𝑮 > |𝑽𝑻𝑯 | , and 𝑽𝑺𝑫 > |𝑽𝑺𝑮 | − |𝑽𝑻𝑯 | Saturation
Body effect
• In a MOSFET substrate is called Bulk/Body
• In I-V analysis we assumed that the bulk/body and source of
transistor were tied to ground
• what happens if the bulk or body voltage of NMOS is drops
below the source voltage ?
Body effect
• To understand this effect, suppose VS = 0
and VD = 0 and VG is somewhat less than
VTH.
• depletion region is formed under the
gate but inversion channel does not exist
as shown in Figure below.
Body effect
• As VB becomes more negative (i.e. VB <
V S where VS = 0) more holes are
attracted to the substrate connection
leaving a larger negatively charged ions
behind i.e. the depletion region becomes
wider as shown in Figure below.
Body effect
• As VB becomes more negative (i.e. VB <
V S where VS = 0) more holes are
attracted to the substrate connection
leaving a larger negatively charged ions
behind i.e. the depletion region becomes
wider as shown in Figure below.
Body effect
• As we know that the threshold voltage is
a function of the total charge in the
depletion region (i.e. Qdep). Thus as the
body voltage V B drops then depletion
charge (Qdep) increases which increases
the threshold voltage (VTH).
• This effect is called as the body effect or
back gate effect.
Body effect
Velocity saturation
• From the physics of semiconductors it is proved that the velocity of
charge carriers is linearly proportional to the electric field and the
proportionality constant is called as mobility of carrier.
• But when we increase the electric field beyond certain velocity called
as the thermal velocity or saturated velocity the velocity of the charge
carrier does not change with electric field as shown in Figure below.
Velocity saturation
• The electric field at which the velocity of carrier saturates is called as
the critical electric field.
• Under velocity saturation condition
Subthreshold-Conduction
• IDS-VGS characteristics of MOSFET is shown in Figure below.

• A closer inspection of the IDS-VGS curve shows that the current does not
drop abruptly to '0' at VGS = VTH. It indicates that the MOS transistor is
partially conducting for voltages below the threshold voltage. This effect is
called as subthreshold or weak inversion conduction
Subthreshold-Conduction
• redraw the curve of on logarithmic scale as shown in Figure below.
Subthreshold-Conduction
• From the IDS-VGS curve in log scale it is
clear that current does not drop to zero
immediately for VGS < VTH but actually
decays in an exponential fashion.

• Thus even VGS < VTH, IDS is finite but it

exhibits exponential dependence on VGS
for smaller values of VDS roughly in the
range of 200 mV.
• This effect is more in for short channel
devices than long channel length devices
• Determine the resistances when observed in the direction shown by
arrows
• Determine the output impedance of each circuit shown in Fig.
Assume λ ǂ 0.
MOSFET Transconductance