IJSRD - International Journal for Scientific Research & Development| Vol.

2, Issue 01, 2014 | ISSN (online): 2321-0613

The Impact of Short Channel Effects MOSFET’s Characteristics Due to

variation in Threshold Voltage
Reenav Shukla1 Apna Joshi2 Himanshu Nautiyal3
1, 2,3
M.Tech.
1,2,3
Department of Electronics & Communication
1,2,3
S.I.R.T.-Bhopal (462010)

Abstract— to get the higher speed, low power dissipation MOSFET’s. It shows that the threshold voltage of the
and higher packing density MOS integrated circuits, the characteristics does not change very much as the body is
dimensions of MOSFETs have continued to shrink, which is reverse-biased, while it becomes lower as the body is
done by scaling. With the scaling of MOSFETs into deep- forward-biased. The threshold voltage VT is not a constant
sub micrometer regime, non-ideal effect is becoming a with respect to the voltage difference between the substrate
resurgent hot topic in the reliability community. One of the and the source of the MOS transistor. This effect is called
non-ideal effects is the expected increase in threshold the body effect or substrate bias effect. The threshold
voltage variation due to worsening short channel effect. In voltage becomes higher as the body is reverse-biased and
this paper we analyzed the role of substrate (the body effect) stops rising when the body bias exceeds a certain value,
on the threshold voltage. The variation in MOSFET while the threshold voltage becomes lower as the body is
threshold voltage will affect the dynamic, static forward-biased. It also shows the dependence on the channel
characteristics and or the short-channel effect (SCE). The impurity concentration, drain voltage, and gate length. It is
most important parameters of a MOSFET are its channel clear that a higher impurity concentration requires a higher
length, the distance between the source and drain. It has body-bias to reach a constant threshold voltage. The higher
been recognized that short-channel MOSFETs offer both drain bias and a shorter gate length decrease the body bias
speed and density advantages over their long-channel for the threshold voltage saturation. We think that this is
counterparts. In a given generation of technology, however, because it is easy for the body region near the drain edge to
there is a minimum channel length below which the gate become fully depleted by the drain bias and this affects all
starts to lose control of the MOSFET current. The short the characteristics of the short-channel device. In addition,
channel prevention circuit uses physically meaningful when the threshold voltage becomes constant with a reverse
parameters provides an easy way for technology body-bias, the - factor simultaneously becomes small and
benchmarking and performance projection. constant.
I. INTRODUCTION
To get the higher speed, low power dissipation and higher III. THE IMPACT OF VARIATION IN THRESHOLD
packing density MOS integrated circuits, the dimensions of VOLTAGE
MOSFETs have continued to shrink, which is done by Supply voltage (Vdd) and threshold voltage (Vt) scaling is
scaling. By the technology scaling the MOSFET’s channel the most effective approach to keep active power dissipation
length is reduced. As the channel length approaches the under control while maintaining performance improvement.
source-body and drain-body depletion widths, the charge in One of the limits to Vdd scaling is the expected increase in
the channel due to these parasitic diodes become Vt variation. In this work a CMOS layout model will be
comparable to the depletion charge due to the MOSFET developed for existing circuit technique that adaptively
gate-body voltage ,rendering the gate and body terminals to biases the body terminal of MOSFET devices to control this
be less effective. With the scaling of MOSFETs into deep- threshold voltage variation. It will show that as MOSFET
sub micrometer regime, non-ideal effects are becoming a technology is scaled, the body bias required for
resurgent hot topic in the reliability community. When the compensating die-to-die Vt variation increases, which in
channel length reduces to dimension below which the gate turn further increases SCE, and, because of this increase in
starts to lose control of the MOSFET current due to the SCE, within-die Vt variation becomes worse. It will also be
increased charge sharing from source/drain. SCE leads to shown that the die that requires larger body bias to match its
several reliability issues including the dependence of device mean Vt to the target Vt will end up with a higher within-die
characteristics, such as threshold voltage, upon channel Vt variation. The resulting increase in within-die Vt
length. The threshold voltage VT for a MOS transistor can variation due to adaptive body bias can impact clock skew,
be defined as the voltage between the gate and the source worst-case gate delay, worst-case device leakage current,
terminals below which the drain to source current total chip leakage power, and analog circuit performance.
effectively drops to zero. This leads to the scatter of device
characteristics because of the scatter of gate length produced The threshold voltage Vth does vary with the
during the fabrication process. voltage difference Vsb between the source and the body
(substrate). Thus including this difference, the generalized
II. SUBSTRATE BIAS (BODY) EFFECTS expression for the threshold voltage is reiterated as
Due to the reverse biased channel to substrate p-n junction Vt = Vt0 + (2εs q Na) 1/2/ Cox ((2 ØF + Vsb) 1/2 - (2 ØF) 1/2)
the channel width becomes reduces by increase in threshold in which the parameter Y, known as the substrate-bias (or
voltage is called as Substrate Bias Effect in Body-Tied body-effect) coefficient is given by

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 The Impact of Short Channel Effects MOSFET’s Characteristics Due to variation in Threshold Voltage
(IJSRD/Vol. 2/Issue 01/2014/012)

= (2*1.6*10-9 11.7*80854*10-14 *1014)1/2 / 1.7265*10-7

= 0.03334
Where,
Na = 3*1016
Tox = 200*10-8
εox = 11.7*8.854*10-14
Cox = εox / Tox
= 3.9*80854*10-14 / 200*10-8
Ү = (2*1.6*10-9* 11.7*80854*10-14 *3*1016)1/2 / Cox Fig. 2: Timing simulation of D latch for short channel
=0.57
ØF= KT/q ln (NA/ni)
= 1.38*10-23 *300/1.6*10-19 ln (1014 / 1.5*1010)
=0.228 V
Vt = Vt0
Then, at Vsb = 2.5 volts

As is clear, the threshold voltage increases by almost half a

volt for the above process parameters when the source is
higher than the substrate by 2.5 volts.

Fig. 3: Effect of MOSFET characteristic due to variation in

substrate bias voltage in short channel

Fig. 1: Layout design of D Latch for short channel

A MOSFET transistor is defined as a short-channel device if Fig. 4: Effect of MOSFET characteristic due to variation in
its channel length is on the same order of magnitude as the substrate bias voltage in long channel
depletion regions thicknesses of source and drain junction. A short-channel will reduce the threshold voltage of ΔVt
Otherwise MOSFET can be defined as a short-channel compare with long-channel device. Vt0 (short-channel) =
device if effective channel length Leaf is approximately Vt0 – ΔVt0. A MOSFET transistor is defined as a narrow-
equal to the S and D junction depth xj. When NMOS is channel device if its channel width is on the same order of
defined as a short-channel device the length of channel will magnitude as the maximum depletion regions thickness into
have impact on the threshold voltage. the substrate (xdm). This effect will have influence in the
threshold voltage and results in higher value for OVt0 if
compared with long-channel device.
Vt0 (narrow-channel) = Vt0 + Δt0

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 The Impact of Short Channel Effects MOSFET’s Characteristics Due to variation in Threshold Voltage
(IJSRD/Vol. 2/Issue 01/2014/012)

IV. CONCLUSION
In this paper, we show that the non-idealities on the
MOSFET characteristics strongly depend on the transistor
aspect ratio and in particular on the transistor channel width,
so that even digital applications may be strongly disturbed
by these effects. Due to the reverse biased channel to
substrate p-n junction the channel width becomes reduces by
increase in threshold voltage is called as Substrate Bias
Effect in Body-Tied MOSFET’s. The drain to source current
varies from 2.518mA to 2.071mA due to variation in body
bias potential for short channel and drain to source current
varies from 1.718mA to 0.1mA due to variation in body bias
potential for long channel . The power dissipation of 15µW
and maximum drain to source current through circuit is
0.212mA.

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