Instruction (Processing) Cycle

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How Are These Instructions Executed?
 By using instructions, we can speak the language of the
computer

 Thus, we now know how to tell the computer to

 Execute computations in the ALU by using, for instance, an

addition

 Access operands from memory by using the load word

instruction

 But, how are these instructions executed on the computer?

 The process of executing an instruction is called is the

instruction cycle (or, instruction processing cycle)
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The Instruction Cycle
 The instruction cycle is a sequence of steps or phases, that an
instruction goes through to be executed
 FETCH
 DECODE
 EVALUATE ADDRESS
 FETCH OPERANDS
 EXECUTE
 STORE RESULT

 Not all instructions require the six phases

 LDR does not require EXECUTE

 ADD does not require EVALUATE ADDRESS

 Intel x86 instruction ADD [eax], edx is an example of instruction

with six phases
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After STORE RESULT, a New FETCH

 FETCH
 DECODE
 EVALUATE ADDRESS
 FETCH OPERANDS
 EXECUTE
 STORE RESULT

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FETCH
 The FETCH phase obtains the instruction from memory and
loads it into the Instruction Register (IR)

 This phase is common to every instruction type

 Complete description
 Step 1: Load the MAR with the contents of the PC, and
simultaneously increment the PC

 Step 2: Interrogate memory. This results in the instruction

being placed in the MDR by memory

 Step 3: Load the IR with the contents of the MDR

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FETCH in LC-3
Step 1: Load
MAR and
increment PC

Step 2: Access
memory

Step 3: Load IR
with the content
of MDR

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DECODE
 The DECODE phase identifies the instruction
 Also generates the set of control signals to process the
identified instruction in later phases of the instruction cycle

 Recall the decoder (from Lecture 5)

 A 4-to-16 decoder identifies which of the 16 opcodes is going

to be processed

 The input is the four bits IR[15:12]

 The remaining 12 bits identify what else is needed to

process the instruction
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DECODE in LC-3

DECODE
identifies the
instruction to be
processed

Also generates
the set of
control signals
to process the
instruction

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Recall: Decoder
 “Input pattern detector”
 n inputs and 2n outputs
 Exactly one of the outputs is 1 and all the rest are 0s
 The output that is logically 1 is the output corresponding to
the input pattern that the logic circuit is expected to detect
 Example: 2-to-4 decoder

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Recall: Decoder (II)
 The decoder is useful in determining how to interpret a bit
pattern
 It could be the A=1
address of a location 0
B=0
in memory, that the
processor intends to
read from 0

 It could be an
instruction in the 1
program and the
processor needs to
decide what action to 0
take (based on
instruction opcode)
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EVALUATE ADDRESS
 The EVALUATE ADDRESS phase computes the address of
the memory location that is needed to process the
instruction

 This phase is necessary in LDR

 It computes the address of the data word that is to be read

from memory

 By adding an offset to the content of a register

 But not necessary in ADD

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EVALUATE ADDRESS in LC-3

LDR calculates
the address by ADD
adding a
register and an
immediate

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FETCH OPERANDS
 The FETCH OPERANDS phase obtains the source operands
needed to process the instruction

 In LDR
 Step 1: Load MAR with the address calculated in EVALUATE
ADDRESS

 Step 2: Read memory, placing source operand in MDR

 In ADD
 Obtain the source operands from the register file

 In some microprocessors, operand fetch from register file can

be done at the same time the instruction is being decoded

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FETCH OPERANDS in LC-3

LDR loads MAR

(step 1), and
places the
results in MDR
(step 2)

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EXECUTE

 The EXECUTE phase executes the instruction

 In ADD, it performs addition in the ALU

 In XOR, it performs bitwise XOR in the ALU

 …

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EXECUTE in LC-3

ADD adds SR1

and SR2

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STORE RESULT
 The STORE RESULT phase writes the result to the
designated destination

 Once STORE RESULT is completed, a new instruction cycle

starts (with the FETCH phase)

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STORE RESULT in LC-3

ADD loads ALU

Result into DR

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STORE RESULT in LC-3

LDR loads
MDR into DR

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The Instruction Cycle

 FETCH
 DECODE
 EVALUATE ADDRESS
 FETCH OPERANDS
 EXECUTE
 STORE RESULT

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Changing the Sequence of Execution
 A computer program executes in sequence (i.e., in program
order)
 First instruction, second instruction, third instruction and so on

 Unless we change the sequence of execution

 Control instructions allow a program to execute out of

sequence
 They can change the PC by loading it during the EXECUTE
phase
 That wipes out the incremented PC (loaded during the FETCH
phase)

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Jump in LC-3
 Unconditional branch or jump

 LC-3 JMP R2

1100 000 BaseR 000000

4 bits 3 bits

 BaseR = Base register

This is register
 PC ← R2 (Register identified by BaseR)
addressing mode

 Variations
 RET: special case of JMP where BaseR = R7
 JSR, JSRR: jump to subroutine

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PC UPDATE in LC-3

JMP loads
SR1 into PC

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Control of the Instruction Cycle
 State 1
 The FSM asserts GatePC and
LD.MAR
 It selects input (+1) in PCMUX and
asserts LD.PC

 State 2
 MDR is loaded with the instruction

 State 3
 The FSM asserts GateMDR and
LD.IR

 State 4
 The FSM goes to next state
depending on opcode

 State 63
 JMP loads register into PC

 Full state diagram in Patt&Pattel,

Appendix C

This is an FSM Controlling the LC-3 Processor 75

The Instruction Cycle

 FETCH
 DECODE
 EVALUATE ADDRESS
 FETCH OPERANDS
 EXECUTE
 STORE RESULT

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The Instruction Set
 It defines opcodes, data types, and addressing modes
 ADD and LDR have been our first examples

ADD
OP DR SR1 SR2

1 0 1 0 00 2

Register mode

LDR
OP DR BaseR offset6

6 3 0 4

Base+offset mode

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The Instruction Set Architecture
 The ISA is the interface between what the software commands
and what the hardware carries out

 The ISA specifies Problem

 The memory organization Algorithm
 Address space (LC-3: 216, ARM Cortex M: 232)
 Addressability (LC-3: 16 bits, ARM Cortex M: 32 bits) Program
 Word- or Byte-addressable ISA
Microarchitecture
 The register set
Circuits
 R0 to R7 in LC-3
Electrons
 The instruction set
 Opcodes
 Data types
 Addressing modes
 Length and format of instructions

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Many Different ISAs Over Decades
 x86
 PDP-x: Programmed Data Processor (PDP-11)
 VAX
 IBM 360
 CDC 6600
 SIMD ISAs: CRAY-1, Connection Machine
 VLIW ISAs: Multiflow, Cydrome, IA-64 (EPIC)
 PowerPC, POWER
 RISC ISAs: Alpha, MIPS, SPARC, ARM, RISC-V, …

 What are the fundamental differences?

 E.g., how instructions are specified and what they do
 E.g., how complex are the instructions
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Complex vs. Simple Instructions
 Complex instruction: An instruction does a lot of work, e.g.
many operations
 Insert in a doubly linked list
 Compute FFT
 String copy
 …

 Simple instruction: An instruction does little work -- it is a

primitive using which complex operations can be built
 Add
 XOR
 Multiply
 …
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Complex vs. Simple Instructions
 Advantages of Complex instructions
+ Denser encoding  smaller code size  better memory
utilization, saves off-chip bandwidth, better cache hit rate
(better packing of instructions)
+ Simpler compiler: no need to optimize small instructions as
much

 Disadvantages of Complex Instructions

- Larger chunks of work  compiler has less opportunity to
optimize (limited in fine-grained optimizations it can do)
- More complex hardware  translation from a high level to
control signals and optimization needs to be done by hardware

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ISA-level Tradeoffs: Number of Registers
 Affects:
 Number of bits used for encoding register address
 Number of values kept in fast storage (register file)
 (uarch) Size, access time, power consumption of register file

 Large number of registers:

+ Enables better register allocation (and optimizations) by
compiler  fewer saves/restores
-- Larger instruction size
-- Larger register file size

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