Lab 4
Lab 4
Introduction
Lab four is an introduction to Oscillators; electronic circuit that produces an output signal of a specific frequency. Essential in nearly every analog and digital electronic circuit are the timing waveforms that are provided by monostable and bistable oscillator circuits. An oscillator generally consists of an amplifier having part of its output returned to the input by means of a feedback loop; the necessary and sufficient condition for oscillation is that the signal, in passing from input to output and back to input via the feedback loop, arrives at the input with no change in amplitude or phase. Inductance-capacitance oscillators operate at high frequencies but are difficult to tune. Crystal oscillators operate at a single frequency. Relaxation oscillators use resistance-capacitance circuits to set the timing intervals. In this lab we design and build a relaxation oscillator using a 741 op amp, a monostable 555 timer circuit, and a 555 relaxation oscillator.
Procedure
Relaxation Oscillator
In this part, we designed an Op-Amp relaxation oscillator by using an LM741. The voltage output of this circuit alternates for some voltage limited as the RC charging circuits brings the inverting voltage V to the non-inverting voltage +V. The main premise is to use an RC time constant, that is, relaxation time of the circuit, to control the frequency and period of the input wave. This will, in turn, control the frequency and period of the square wave output. In this lab we used a frequency of 1 kHz and Two RB=10 k resistors are used from the positive feedback. That means the maximum and minimum values of the output voltage VCLK is limited by the positive and negative supply rails of which are +5V and -5V respectively. When VCLK is +5V, V is 2.5V. At the same time, capacitor C is charged towards +5V. When the Vcc is charged to a little bit higher than +2.5V, the negative input of the op amp is higher than the positive input of the op amp. This will results the op amp to go to negative power supply. When VCLK is 5V, V is -2.5V and the capacitor discharges toward -5V. When Vcc is discharged to a little bit lower than -2.5V, the negative input of the op amp is lower than the positive input of the op amp, so the op amp goes to the positive power supply.
Theoretical Results
Relaxation Oscillator
In a relaxation oscillator the system is in an unstable equilibrium when both inputs and outputs of the Op amp are zero. When any sort of noise brings the output of the Op amp above zero, the positive-feedback results in the output saturating at the value of Vcc. The inverting input and the output of the Op amp are linked by a RC circuit; this causes the inverting input to asymptotically approach the comparator output voltage. At the point where voltage at the inverting input is greater than the non-inverting input, the output of the comparator fall quickly due to positive feedback. A sample figure is shown in figure 1.
The measure period of the clock signal, using the parameter above, is that is different than the expected design period for a 1 kHz clock. Figure 4, below compares the capacitor voltage and the clock voltage as a function of time.
Figure 4: Relaxation Oscillator Clock Voltage and Capacitor Voltage vs. Time
By replacing R, designed above, with a 2.2K resistor the sides of the square wave become slanted. The slope of the new wave is: When the 741 OP Amp is replaces by the 341 the sides of the square wave become less slanted. The new slope of the sides is: This shows that the slew rate is not the same for the two OP Amps, and that the 341 is better for high frequency functions.
( ) ( ) ( ) Using the resistance designed above, the measured pulse width is 86s. This is . Figure 5 shows the clock voltage and the capacitor voltage versus time.
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Figure 5: Monostable 555 timer Clock Voltage and Capacitor Voltage vs. Time
When the frequency of the trigger is increased to 9 kHz decreases slightly, however the separation between positive pulses decreases significantly. This is the result of the trigger triggering the capacitor more often. When the duty cycle is decrease the trigger pulse increase, figure 6 shows the print out of the result.
Figure 6: Monostable 555 timer Clock Voltage and Capacitor Voltage vs. Time with reduced duty cycle
The increase width is due to the fact that the reduce duty cycle causes the capacitors to have more time to saturate.
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From the design r values the observed period and the observed duty cycle are 34.2s and .579 respectively. That means the period is 2.5% different and the duty cycle is 3.6% different. These are small changes and the resulting clock is close enough to the desire values. Figure 7 shows the capacitor and voltage of the circuit versus time.
Figure 7: Atable555 timer Clock Voltage and Capacitor Voltage vs. Time
Conclusion
The goal of this lab was to familiarize us with oscillators. We learned how to design oscillator circuits that provide timing waveforms that are essential in nearly analog and digital electronic circuit. Some of the oscillators that we created were; the op-amp relaxation oscillator, the astable 555 circuit and the monostable 555 circuit. The results from the three experiments came out the way they were supposed to function.