DR.

SUBODH WAIRYA
PROFESSOR & HEAD
Department of Electronic & Communication Engineering
(NBA Accredited Till June 2025)
Institute of Engineering & Technology, Lucknow
(An Autonomous Constitute Institute of Dr. A. P. J. Abdul Kalam Technical University, Lucknow, India)

1. FATHER’S NAME : Shri Prem Prakash Wairya

2. ADDRESS FOR CORRESPONDENCE : Type –IV B 302 Block (3), Institute of
Engineering and Technology Campus,
Sitapur Road, Lucknow- 226021, India.
3. DATE OF BIRTH : 17th March, 1970

4. EMAIL : [email protected],
[email protected]
5. CONTACT NO : +91 9044039593, +91 9415159085
6. PAN No./HIGH SCHOOL Certificate : AADPW3496R/0404752

7. EDUCATIONAL QUALIFICATIONS:

S.N QUALIFICATIONS SUBJECT YEA DIV % of COLLEGE/UNIV

R Marks

1. Ph.D Electronics Engineering 2012 9.5 CPI MNNIT, Allahabad,

(Quality Improvement Program) Uttar Pradesh, India

2. M. E. Tele-Communication Engineering 2002 1st 85% Jadavpur University,

(Quality Improvement Program) Kolkata, India
3. B. TECH. Electronics Engineering 1993 1st 73.1% HBTI, Kanpur, Uttar
Pradesh, India
4. INTERMEDIATE Hindi, English, Mathematics, 1988 1st 70.1% U.P.BOARD
Physics, Chemistry
5. HIGH SCHOOL Hindi, English, Math Science, Social 1986 1st 70.2% U.P.BOARD
Science, Biology,
PUBLICATIONS Journals 82 74 Total 155
International Conference 70 SCI/
 IEEE Xplore Digital Library 18 SCOPUS
 Book Chapter (Lecture Note) 24
 National Conference
12
Book
03
PhD Registered 06 (Awarded) 07 (in Process) 13
M.Tech (Thesis) 42 (Guided) 04 (in Process) 43

1 | Bio-data (Dr. Subodh Wairya)

WORKS EXPERIENCE: 30 years

Teaching: (28 Years) Institute of Engineering and Technology (I.E.T), Lucknow, U.P.

Designation : PROFESSOR
Period : From 12th Dec 2012- till Date
Pay Scale Basic Pay 1,93,300=00 (1st July 2023) 7th Pay Band (14 Level)
Pay Band (Rs.144200-218200) 7th CPC AGP- 10000/-
Pay Band (37,400- 67,000) 6th CPC Grade Pay 10000)
Designation : ASSOCIATE PROFESSOR
Period : From 6th May 2009 to 11th Dec 2012
Pay scale : 37,400- 67,000 Grade Pay 9000)
Designation : ASSISTANT PROFESSOR
Period : From 6th May 2006- 5thMay 2009
Pay scale 15600 - 39100 Grade Pay 8000)
Designation : ASSISTANT PROFESSOR (Lecturer /Sr. Lecture)
Period : From 5th May 1996- 5thMay 2006

(b) Research &Industry: 2 years 6 months

Defence Research & Development Organization (DRDO), Lucknow (One Year)

Period : From January, 1995-January, 1996
Designation : Scientist “B” Adhoc (One Year)
Responsibilities : Certification and Design Projects
Hindustan Aeronautical Limited, Lucknow (One Year)
Period : From January, 1994-January, 1995 (one year)
Designation : Graduate Engineer under Consultancy Project
Responsibilities : Design Project
Govt. Polytechnics, Lucknow (Six Months)
Period : From August 1993-January, 1994 (6 Month)
Designation : Guest Faculty
Responsibilities : Teaching

Research:
 Ph.D on (Thesis) “Performance Evaluation of High Speed Low Power CMOS Full
Adder Circuits For Low Voltage VLSI Design from Motilal Nehru National Institute
of Technology (MNNIT), Allahabad, U.P., India.
 M.Tech Dissertation on (Thesis) “Some Study on Polarization Properties In Single-
Mode Fiber and Passive Component” from Jadavpur University, Kolkata, India,
700032.
Books:
1. A Simplified Approach to Telecommunication and Electronic Switching Systems,
C.B.L. Srivastav, Neelam Srivastava & Subodh Kumar Wairya, Published by Dhanpat
Rai and Company.
2. Design and Testability of Diverse Reversible Error Control Circuits, Neeraj Kumar
Misra, Subodh Wairya, Bibhash Sen, LAP Lambert Academic Publishing German,
August 2017, Pages 107, DOI: 978-620-2-01508-0.
3. Intelligent Systems and Smart Infrastructure Proceedings of ICISSI 2022, Edited
By Brijesh Mishra, Rakesh Kumar Singh, Subodh Wairya, Manish Tiwari, Pages 774,
2023, CRC Press, Taylor &Francis Group, ISBN 9781032412870.

2 | Bio-data (Dr. Subodh Wairya)

 PARTICIPATION
IN

ACADAMIC ACTIVITIES

INSTITUTE ACTIVITES

DEPARTMENTAL ACTIVITES

TECHNICAL UNIVERSITY
ACTIVITIES

3 | Bio-data (Dr. Subodh Wairya)

 ACADAMIC ACTIVITIES:
(a) SHORT TERM COURSES:

1. Workshop on “Active Learning, Autonomy, Academic Governance and R & D”, July
02-06, organized by IIT Roorkee.
2. TEQUIP II Sponsored Faculty Development Programme (FDP) on “Internet of Things”
Conducted by ESCI, The Institution of Engineers (India) Engineering Staff College of India
(ESCI) Hyderabad, held on 06- 10th March 2017 (One Weeks).
3. AICTE Sponsored Short Term Course on “Cyber Crime & Forensic Tools Through ICT” ,Jan.
27th– 31st Jan 2014 (One Week) organized by the Department of Computer Science, NITTTR
Chandigarh, India.
4. Faculty Development Training Programme Entitled “Cadence Tool Training Course for India-
Chip 2010 Tapeout”, organized by Department of Electrical Engineering IIT Kanpur, and held
on 29th June to 4th July 2009 (One Week).
5. AICTE(MHRD) Sponsored Faculty Development Programme on “Issues & Design of
Distributed system and its Application” Jan.27th–Feb. 7th 2009, (Two Week) organized by the
Department of Computer Science and Engineering, Motilal Nehru National Institute of
Technology (MNNIT), Allahabad, India
6. AICTE(MHRD) Sponsored Faculty Development Programme on “VLSI for Signal Processing &
Communication” January 12–24, 2009 (Two Week) organized by the Department of
Electronics and Communication Engineering, Motilal Nehru National Institute of Technology
(MNNIT), Allahabad, India
7. Short Term Course on “Wireless Networks” May 23-28, 2005, (One week) conducted by G.S.
Sanyal School of Telecommunication, IIT, Kharagpur.
8. AICTE-ISTE Short Term Course on “Recent Advance in Power Semiconductor Devices and
Their Application” July 01-12, 2002, (Two Week) organized by the Department of Electrical
Engineering, Delhi College of Engineering , Delhi
9. U.G.C. Sponsored refresher Course on “Computer Aided Design of VLSI Circuits” March 07-
27, 2001, (Three Week) organized by the Department of Electronics &Telecommunication
Engineering, Jadavpur University, Kolkata, India

Workshop/Seminar/Conferences as Resource Person

S. No. Topic of Course Place Date
1. National Conference on “Emerging ITS, Ghaziabad December 06th -07th , 2007
Technology and Trends in IT 2007
(NCET 2007)”
2. National Seminar on “Nanostructures Invertis Institute of Engineering and April 7th -8th , 2007
and Devices” Technology, Bareilly
3. Workshop titled “VLSI Design Tools” Department of Electronics Engineering, November 17th -18th , 2007
Institute of Engineering and Technology,
Lucknow
4. National Seminar on “Recent Trends Invertis Institute of Engineering and February 2nd -3th , 2008
on Digital Communication” Technology, Bareilly
5. Workshop titled “Workshop on Department of Electronics Engineering, April 8th -10th , 2008
Practical on MATLAB for B.Tech Institute of Engineering and Technology,
Courses Lucknow
6. Workshop titled “Practical Workshop Department of Electronics Engineering, February 28th -29th , 2008
on Embedded System Designs Based Institute of Engineering and Technology,
on Micro controllers” Lucknow
7. Workshop on “Curricula Review for Department of Electronics, Institute of June 15th -16th, 2015
B.Tech Electronics and Engineering and Technology, UPTU,
Communication Engineering”

4 | Bio-data (Dr. Subodh Wairya)

WORKSHOP
1. Workshop on Hardware Implementation of Embedded System Design, IoT Development and DSP
Application (HIEID-2019), 19th – 20thSeptember, 2019, EC Deptt IET, Lucknow.
2. Workshop ON Microcontroller Based System Design, 20th September, 2019, EC Deptt IET, Lucknow.
3. TEQUIP III sponsored Workshop on ''Renewable Energy and Environment'' conducted by Department of
Chemical Engineering, Institute of Engineering & Technology Lucknow, Uttar Pradesh on 27th
February,2018.
4. Workshop on ''Advances in Chemical Engineering and Technology'' conducted by Department of Chemical
Engineering, Institute of Engineering & Technology Lucknow, Uttar Pradesh on 23rd-24th March,2018.
5. TEQUIP II Sponsored Faculty Development Programme (FDP) on “Pedagogy and Management Capacity
Enhancement Program For Teaching Staff” Conducted by ESCI, The Institution of Engineers (India)
Engineering Staff College of India (ESCI) Hyderabad, held on 17-19 th March 2017
6. Attended NBA Oriented Workshop on Outcome Based Education and Accreditation for Programme
Evaluators (PEVs), organized by IIT Kanpur, Uttar Pradesh, India 1 st Oct 2016.
7. Attended NBA Workshop on “SAR Filling through Active Instructional Methods” organized by
Engineering Staff College of India (ESCI) Hyderabad in Collaboration with Institute of Engineering &
Technology, Lucknow, held on 12-13 August 2016
8. Attended National Workshop on “Outcome based Education & NBA Accreditation” organized by
State Project Facilitation Unit (SPFU) Uttar Pradesh in Collaboration with Engineering Staff College of
India (ESCI) Hyderabad, held on 01-03 July 2016
9. Attended Workshop on “Curricula Review for B.Tech Electronics and Communication Engineering”
organized by Department of Electronics, Institute of Engineering and Technology, UPTU, Under Technical
Education Quality Improvement Program (TEQIP), held on 15th -16th June, 2015
10. Attended Workshop on “Industry Academia Interaction on Frugal Engineering” organized by Institute of
Engineering and Technology, Gautama Buddha Technical University, Lucknow, held on 26th October,
2013.
11. Attended Workshop on “E-WASTE MANAGEMENT- CHALLENGES, PROSPECTES AND
STRATEGIES” organized by PHD Chamber of Commerce and Industry in association with Ministry of
Environment and Forests, Government of India, held on 26th September, 2013.
12. Attended Workshop on “Industry Academia Interaction for Innovation and Quality Technical Education: A
Path Forward for 2020” organized by Institute of Engineering and Technology, Gautama Buddha Technical
University, Lucknow, held on 04th September, 2013.
13. Attended Workshop on “REAL TIME SIMULATION” organized by Department Of Electrical
Engineering, I.E.T., Lucknow, India held on 26th September, 2011.
14. Attended Workshop on “Virtual Instrumentation & Its Applications (WVAI 09)” organized by Department
of Electrical Engineering, MNNIT Allahabad, India held on 18th -20th March ,2009
15. Organized & attended a Workshop titled “Workshop on Practical on MATLAB for B.Tech Courses
organized by Department of Electronics Engineering, IET Lucknow, India held on 8-10 th April, 2008.
16. Organized & attended a Workshop titled “Practical Workshop on Embedded System Designs Based on
Micro controllers” organized by Department of Electronics Engineering, IET Lucknow, India held on
February 28-29th, 2008.
17. Organized & attended a Workshop titled “VLSI Design Tools” organized by the Department of Electronics
Engineering, Institute of Engineering and Technology, Lucknow, India on 17-18 Nov. 2007.
18. Attended Workshop on “Adhoc and Sensor Networks” organized by IIIT, Allahabad held on 17th -19th
December, 2006.

5 | Bio-data (Dr. Subodh Wairya)

 Innovation Startup and Entrepreneurship work performed:
 Innovation Gallery: Innovation gallery is unique program under which University students are asked to share
innovative idea on specific theme. In Jan 2020, students presented their idea on “Innovation on Automobile” in
which six ideas are selected for prototype development.
 Innovation Gallery: Innovative ideas were invited under the UP government scheme One
District One Project, in which 157 ideas were received from students. After screening 14 ideas
were shortlisted for prototype development.
 DST – NIMAT Programs: Entrepreneurship Institute of India (EDII), Ahemdabad sanctioned two
Entrepreneurship Awareness Camp (EAC) programs to University. These programs were successfully
organized in September – October 2019 and Post Project Report (PPR) and UC submitted to EDII. These
programs were sponsored by Department of Science and Technology (DST), Government of India.

 Organised Aatmnirbhar Bharat Abhiyaan e-lecture series: To aware and strengthen

students for entrepreneurship University started Aatmnirbhar Bharat Abhiyaan e-lecture
series in the time of covid – 19 pandemic. The motive of this series was to connect
students with Vocal for Global initiative.

 Reviewer (Technical Program Committee member) for some reputes (International

Journals): The Journal of Supercomputing, Journal of Computing and Digital Systems,
Electronics Letter, Journal of Engineering Research and Reports, Int. J. of Circuits and
Architecture Design (Inderscience Publishers Ltd), International Journal of Numerical
Modelling: Electronic Networks, Devices and Fields, Optical and Quantum Electronics, etc

 Reviewer and Program/AdvisoryCommittee Member of International Conferences

S. No. Title of Conference Place Date
International Conference On Integrated Circuits, School of Electronics, Indian MARCH 2-3, 2024
Communication, and Computing Systems (ICIC3S) Institute of Information
2024 Technology (IIIT), Uno
1. Second International Conference on Advances in Puducherry Technological 7-8th, Dec. 2023
Computational Intelligence and Communication CIC University, Puducherry
2023
2. International Conference on Signal Processing & AMITY University Noida, 2024-2014
Integrated Networks (SPIN) (Technical Program U.P. India
Committee member)
3. 8th INTERNATIONAL CONFERENCE ON SIGNAL JIIT Noida, U.P. India 1-3 Dec 2022
PROCESSING AND COMMUNICATION (ICSC
2022)
4. International Conference on VLSI, Communication and MNNIT, Prayagraj, U.P. India 2023-2019
Signal Processing (VCAS) (Technical Program
Committee member)
5. 5th International Conference on Multimedia, Signal AMU, Aligarh Musilam
26-27 Nov. 2022
Processing and Communication Technologies (IMPACT University, Aligarh, U.P. India
2022)
6. AICTE Sponsored 2nd International conference on Raj Kumar Goel Institute of
14th-15thJuly 2022
Advancement in Electronics & Communication Technology (RKGIT)
Engineering (AECE-2022)Program Committee member Ghaziabad, Uttar Pradesh, India
7. International Conference on Intelligent Systems and Shambhunath Institute of
21-22 May, 2022
Smart Infrastructure (ICISSI 2022) Program Committee Engineering and Technology,
member Prayagraj UP India,
8. International Conference On VLSI & Microwave and MMMTU, Gorakhpur, India 20-21 March. 2021
Wireless Technologies (ICVMWT-2021), MMMTU,
Gorakhpur, India, 20-21 March. 2021 (subreviewer)

6 | Bio-data (Dr. Subodh Wairya)

 https://login.easychair.org/conferences/review_requests?a=25970358
9. Organized (Coordinator) International Conference on Institute of Engineering & 23-25 August 2019
“Defence and Space Technologies (ICDST) 2019 by Technology, Lucknow, UP,
Department of Electronics & Communication India
Engineering, Institute of Engineering & Technology,
Lucknow, 23-25 August 2019.
https://www.ietlucknow.ac.in/sites/default/files/mag/conference%20-
%20icdst%202019%20leaflet.pdf
10. International Conference on VLSI, Communication and MNNIT Allahabad, India 2021 - 2019
Signal Processing (VCAS 2019) (subreviewer)
https://login.easychair.org/conferences/review_requests?a=23038920
11. International Conference on “Defence and Space Institute of Engineering & 23-25 August
Technologies (ICDST) 2019 ICDST 2019 (subreviewer) Technology, Lucknow, UP, 2019.
https://login.easychair.org/conferences/review_requests?a=22948676 India
12. International Conference- Confluence 2013: The Next AMITY University Noida 2016-2014
Generation Information Technology Summit
(Confluence 2014)
13. International Conference on Medical Imaging, m-Health GL Bajaj Institute Gr. Noida Nov. 7-8 2014
and Emerging Communication Systems
(MedCom-2014)
14. 1st International Conference on Next Generation University of Petroleum & Sept 4-5 2015
Computing Technologies (NGCT 2015) Energy Studies, Dehradun

PARTICIPATION IN CONFERENCES/SEMINAR

1. Best Paper Award, Paper title “Performance analysis of various fast and low power
dynamic comparators”, International Conference on Intelligent Systems and Smart
Infrastructure (ICISSI 2022) India, 21-22 May, 2022 at Shambhunath Institute of
Engineering and Technology, Prayagraj UP India.
2. General-chair, International Conference on Intelligent Systems and Smart
Infrastructure (ICISSI 2022) Organized by Shambhunath Institute of Engineering and
Technology, Prayagraj UP India, Institute of Engineering and Technology (IET)
Lucknow, U.P India, and Manipal University Jaipur, Rajasthan India, CRC Press, 21-22
May, 2022
3. Conference Co-chair, First International Conference on Advances in Computing and
Future Communication Technologies ICACFCT-2021 Organized by Meerut Institute of
Engineering & Technology and ACIC MIET, 16-17 December, 2021.

4. Advisory Committee member in International Conference on Modern Approaches in

Engineering, Science and Management (MAESM-2021) Organized by Bansal Institute of
Engineering and Technology, Lucknow, India, 16-17 April 2021.
5. Best Paper Award, Paper title “A Cost efficient QCA RAM cell for Nanotechnology
Applications”, International Conference On VLSI & Microwave and Wireless
Technologies (ICVMWT-2021), 20-21 March. 2021 at MMMTU, Gorakhpur, India.
6. Presented a paper, “An Efficient QCA Vedic Multiplier for Nanotechnology
applications”, IEEE 2021 The International Conference for Intelligent Technologies,
(CONIT 2021), The KLE Institute of Technology, Hubballi, Kartakata , India, 25-27
June, 2021
7. Presented a paper “Performance Improvement and Comparative Analysis of Memristive
Emulator Networks”, IEEE 2nd International Conference on Emergining Technologies
(IEEE INCET2021), Belguam, Karnataka,, India, 21-23 May 2021..
7 | Bio-data (Dr. Subodh Wairya)
 8. Organized (Coordinator) International Conference on “Defense and Space
Technologies (ICDST) 2019 by Department of Electronics & Communication
Engineering, Institute of Engineering & Technology, Lucknow, 23-25 August 2019.
9. Organised (Co-ordinator) National Conference “Emerging Trends in Electrical &
Electronics Engineering (NCETEEE’16), by Department of Electronics &
Communication Engineering & Department of Electrical Engineering Institute of
Engineering & Technology, Lucknow, 19-20 August, 2016.
10. Attended and Programme Technical Committee member in International Conference on
“Signal Processing and Integrated Network (SPIN-2015),” organized by Department of
Electronics Engineering, AMITY University, Uttar Pradesh, India Feb. 2015
11. Associate as Programme Technical Committee member in International Conference on
“Medical Imaging m-Health & Emerging Areas in Communication Systems (MEDCOM-
2014), “organized by G.L. Bajaj Institute of Technology & Management, Gr. Noida,
Uttar Pradesh, India proposed dates 7th-8th Nov. 2014
12. Associated as Programme Technical Committee member in International Conference on
“Signal Processing and Integrated Network (SPIN-2014),” organized by Department of
Electronics Engineering, AMITY University, Uttar Pradesh, India 20-21st Feb. 2014
13. Attended and Programme Technical Committee member, 4th International Conference on
“The Next Generation Technology Summit (CONFLUENCE-2013),” organized by
Department of Computer Science& Engineering, AMITY University, Uttar Pradesh,
India 26-27th Sept. 2013.
14. Attended International Conference on Advance in Electrical & Electronics Engineering,
(ICAEEE–2011), organized by Department of Electronics & Electrical Engineering,
MIT, Moradabad, 25-26th Feb. 2011.
15. Attended 1stInternational Conference on “Power, Control & Embedded Systems
(ICPCES 2010), organized by Department of Electrical Engineering, Motilal Nehru
National Institute of Technology Allahabad, India, held on Nov. 29-Dec. 1, 2010.
16. Attended National Seminar on “Recent Trends on Digital Communication” organized by
Invertis Institute of Engineering and Technology, Bareilly, held on February 2-3, 2008.
17. Attended International Conference on Ayurvedic Bhasm and Nanomedicine, organized
by OMICS BIOTECHNOLOGY, USA,ACS-BIOINFORMATIC, Biotech Park,
Lucknow, 22nd Dec. 2007.
18. National Conference on “Emerging Technology and Trends in IT 2007 (NCET 2007)”
organized by ITS, Ghaziabad, held on 06-07 December, 2007.
19. National Seminar on “Nanostructures and Devices” organized by Invertis Institute of
Engineering and Technology, Bareilly, held on April 7-8, 2007.
20. Attended 2nd International Conference on “Wireless Communication and Sensor
Networks (WCSN)” organized by IIIT, Allahabad held on 17-19 December, 2006.
21. Attended International Conference on “Fiber Optics and Photonics” Advance Technology
Center IIT Kharagpur, India and Department of Applied Physics University of Calcutta
held on 18-20 December,2000

8 | Bio-data (Dr. Subodh Wairya)

 INVITED LECTURE TALK & CHAIRING A TECHNICAL SESSION:
1. Invited Lecture talk on “Era of Semiconductor Chip, 5G Revolution in Next
Generation Technology" in one-week short term course (STC) in online mode on "
Cutting-Edge Technologies, Innovations & Applications" during January11th-15 th
March, 2024, under the aegis of Department of Electronics and Communication
Engineering SOET, CMR University, Lakeside Campus Hennur- Bagalur Main Road,
Chagalahatti, BANGALORE, Karnataka, INDIA. on 12th March 2023.
2. Invited Lecture talk on 2nd Feb 2024 “How 5G Technology Impacts the
Semiconductor Industry" in one-week short term course (STC) in online mode on
"Future Communications Technologies: 5G & Beyond" during January 29th to
February 3rd, 2024, under the aegis of Department of Electronics Engineering, National
Institute of Technology, Uttarakhand.
3. Invited Lecture talk on “MEMS & Digital Design in VLSI Application” in five day
online Faculty Development Programme (FDP) on " Recent Trends of Emerging
Research Advances in Design Aspects and Innovative Modeling Techniques with
Miniaturization for Electronics Devices and Circuits” from 24-28 January, 2022. The
FDP is sponsored by Online AICTE Training and Learning (ATAL) Academy Delhi and
organized by Department of Electronics Engineering, IERT Prayagraj U.P.
4. Invited Lecture talk on “Advance Digital Circuit Design in VLSI Application” in
five day online Faculty Development Programme on "Current Research Trends in
VLSI design and Device Modelling" organized by Department of ECE, Atria Institute
of Technology, Bengaluru, India in association with IEEE & IETE ATRIA Student
Branch chapter (24th-28th August 2021) .

PARTICIPATION IN TRAINGING PROGRAM AND TUTORIALS:

1. Chairing a Technical Session on 21st March 24 for 11th International Conference on
Signal Processing and Integrated Networks (SPIN2024), organizing by Department of
Electronics & Communication Engineering, Amity University, Noida, India in
Technical Collaboration with IEEE, on 21-22 March 2024.
2. Advisory Committee Member, Five day online Faculty Development Programme
(FDP) Integration of Renewable Energy and Smart Grids for Smart Cities 07 -
12, March 2022.. The FDP is organized by Department of Electrical Engineering,
Bansal Institute of Engineering and Technology, Lucknow, U.P.
3. Advisory Committee Member, Five day online Faculty Development Programme
(FDP) Data Analytics, Big Data, Machine Learning and Applications February 21 -26,
Feb 2022. The FDP is organized by Department of Electrical Engineering, Bansal
Institute of Engineering and Technology, Lucknow, U.P.
4. Chairing a Technical Session on 24th September for 4th International Conference on
VLSI, Communication & Signal Processing (VCAS-2021), ECE Department MNNIT,
Allahabad, India, Sept. 24-26, 2021
5. Chairing a Technical Session on 26th August for 8th International Conference on Signal
Processing and Integrated Networks (SPIN 2021), organizing by Department of
Electronics & Communication Engineering, Amity University, Noida, India in
Technical Collaboration with IEEE, on 26-27 Aug 2021.

9 | Bio-data (Dr. Subodh Wairya)

 6. Invited Lecture talk in IETL online lecture series topic "Advance Digital circuit Design"
organized by Department of EC, IET Lucknow and PEC Pondicherry for faculty under
TEQIPIII twining activity on 13th Feb 2021.
7. Chairing a Technical Session for 3rd International Conference on VLSI,
Communication & Signal Processing (VCAS 2020), MNNIT, Allahabad, October 9-11,
2020 organizing by ECE Deptt, MNNIT Allahabad, Prayagraj, Uttar Pradesh, India,
on October 9-11, 2020.
8. Tutorial “MOSFET Scaling: trends, Challenges and Key Technology Innovations”
organized by Department of Electrical Engineering, Motilal Nehru National Institute of
Technology (MNNIT), Allahabad, India, held on Nov. 28, 2010.
9. Training Programme Entitled “ENERGY AUDITING” on March, 2006 under
Technical Education Quality Improvement program at Institute of Engineering &
Technology, Lucknow.
10. Workshop on “Hindi Sabdawali in Engineering Subject” organized by scientific &
Technical Sabdawali Commission, MHRD Ministry, New Delhi, held on 19-20 th March,
2005.
11. 88 Hours Course on “C,UNIX & DATA STRUCTURES” organized by Computer
Science and Engineering Department, Jadavpur University, Calcutta, held on Sept 08-
12 Dec, 2001.
12. Workshop on “Patent Awareness” organized by Patent Promotion and archival Cell,
Jadavpur University, Calcutta, India held on 19th January, 2001.
13. Tutorial “PHOTONIC 2000” Organized by Advance Technology Center IIT Kharagpur,
India and Department of Applied Physics University of Calcutta held on 17 thDecember,
2000.
14. Presented a paper “Proposing a Novel Low Power High-Speed Mixed GDI Full Adder
Topology” 1st International Conference on Power, Control & Embedded Systems
(ICPCES 2010), organized by Department of Electrical Engineering , Motilal Nehru
National Institute of Technology (MNNIT), Allahabad, India held on Nov. 29-Dec. 1
2010.

10 | Bio-data (Dr. Subodh Wairya)

INSTITUTE ADMINISTRATIVE ACTIVITES:-
 Dean Student Welfare May 2023-Till date
 Chief Warden May 2022-Till date
 Member Institute Library Advisory Committee (Till date)
 Dy. Dean Academics, IET, Lucknow (Jan. 2014-Dec 2016)
 Coordinator/Nodal Officer, AICTE Sponsored Employability Enhancement Training Program
(EETP) organized by Bharat Sanchar Nigam Limited (BNSL). AICTE has entered into a MoU
with BSNL to facilitate the Technical Institutions (June 2013-16).
 Member Examination Committee, IET Lucknow (2014- 2016)

 Co-coordinator, Financial Management TEQIP Phase II Committee, IET Lucknow (2012-2014).

 Member INSTECH Student Sports and Cultural council (ISSACC) IET, Lucknow (2011-2015)
 Faculty Incharge Sports & Culture Activity (ISSACC) I.E.T Lucknow (2002-2008)
 Warden, VA Hostel (July 2016- Sept 2017), VB Hostel (July 2012- Feb. 2014), (97-2000), New
Boys Hostel (July 2011-June 2012), (2003-2007)
 Officer Incharge National Social Service (NSS) (1998-2000),
 Officer Incharge, National Cadet Corps (NCC) 67 UP Battalion ( (2011-2013), 2004-2007)
 Deputy Registrar (officiating), I.E.T., Lucknow(1997-1998).
 Center Superintendent MTech/MPharma End Semester Exam (March 2014),
 Center Superintendent Special Carry Over End Semester Exam (Sep-Oct 2014)
 Assistant Center Superintendent, UPTU End Semester Exams IET Lucknow (2002-2004).
 Member Proctorial Board and Anti Ragging Committee IET, (2011-till date)
DEPARTMENTAL ACTIVITES
 Head of Department with effect from 2nd June 2023 –Till date
 Faculty Advisor Departmental Technical Society “Society for Electronics Exploration
and Development” (SEED) EC Department, IET, Lucknow (2019-2020).
https://www.ietlucknow.ac.in/sites/default/files/mag/Departmental%20Magazine%202019-20.pdf
 Head of Department with effect August 2016 to Oct 2019.
 Coordinator M.Tech (Microelectronics) Program. ( Jan. 2016 to Sept. 2017)
 Member of Board of Studies (BOS) EC Deptt IET Lucknow (2013-till date)
 Deputy Coordinator, M.Tech (Microelectronics) Program. (2011-2015)
 Member interview committee for the interview of Contractual faculty (2011-2014)
 Faculty Advisor, IInd Year EC/EI Students.
 Incharge Contractual Gust Faculty, EC Department, IET, Lucknow
 Faculty Advisor Departmental Technical Society “Society for Electronics Exploration
and Development” (SEED) EC Department, IET, Lucknow (2011-2014)

11 | Bio-data (Dr. Subodh Wairya)

COURSE TAUGHT AT UNDER GRADUATE LEVEL (B.Tech) (1996-till date)
 Basic Electronics
 Electronics Devices and Circuits
 Analog Integrated Circuits
 Digital Logic Switching Theory
 Digital Integrated Circuit
 Signal and Systems
 Digital Signal Processing
 Principle of Communication
 Digital Communication
 Electronics Switching
 VLSI Design

UG LABORATORIES DEVELOPED/PERFORMED
 Basic Electronics Lab
 Printed circuit board (PCB) Lab
 Microprocessor Lab
 CAD Lab

COURSE TAUGHT AT POST GRADUATE LEVEL

M.Tech (Micro Electronics) Regular (July 2011-till date)
 Analog CMOS Design
 VLSI Design
 Hardware Description Language (VHDL),
 Designing with ASICS
 Electronics System Design
 Modelling of Microelectronic Devices
M.Tech VLSI Design (Modular)
Analog VLSI Design,
Low Power VLSI Design,
CMOS RF Design,

PG LABORATORIES DEVELOPED/PERFORMED
 Microelectronics Lab
 Microprocessor and Microcontroller Lab
 VLSI Lab

PARTICIPATION IN TECHNICAL UNIVERSITY ACTIVITIES :

 Dean, Undergraduate Studies and Entrepreneurship (UGSE), Dr. A.P.J. Abdul Kalam
Technical University Uttar Pradesh, Lucknow, India. (Sept. 2019-30th May 2022).

12 | Bio-data (Dr. Subodh Wairya)

  Coordinator Uttar Pradesh Common Entrance Test (former UPSEE), UPCET 2021.
(Dec. 2020- June 2021).
 Convener, Virtual Lab Cell, Dr. A.P.J. Abdul Kalam Technical University Uttar Pradesh,
Lucknow, India. (https://aktu.ac.in/pdf/Upload%20Virtual%20Lab%20Cell%20Report1.pdf)

 Incharge Kalam- Centre for Innovation and Incubation of startup (K-CIIS)

https://innovation.aktu.ac.in/ till July 2021.
 Chief Guest for Inaugural Session of various Faculty Development Program (FDP) organized
by affiliating Institute of AKTU.
 Member of Steering Committee for New Education Policy (NEP) system 2020.
 Member of Standing Committee of Academic Autonomy for Private Institution of
AKTU. (िनजी सं थानों के शैि क ाय ा हे तु ा आवेदनों पर िवचार हे तु गिठत े ं ग कमेटी).
 Member of AKTU MOOC Coordination Committee, affiliation committee, Autonomy Grant
Committee, Internal Quality Assurance Cell (IQAC), Governing Council of Nalanda E-
consortium, various Institute Inspection (Approval Process 2020-21) and Examination
Committees (2019-2022)
 Dean, Recourse Generation & Alumni Matter. Dr. A.P.J. Abdul Kalam Technical
University Uttar Pradesh, Lucknow, India, Sept. 2018- Sept. 2019.
 Associate Dean, Undergraduate Studies and Entrepreneurship, Dr. A. P. J. Abdul Kalam
Technical University Uttar Pradesh, Lucknow, India (Jan. 2017-Sept. 2018)
 External Member RDC Committee for PH.D Program of Electronics Engineering,
IET, Dr. Ram Manohar Lohia Avadh Univ. Faizabad, Uttar Pradesh (2024- till date).
 External Member RDC Committee for PH.D Program of Electronics Engineering,
HBTU, Kanpur, Uttar Pradesh (2022- till date).
 External Member FRC/DRC Committee for PH.D Program, AMITY University,
Lucknow (2016-till date)
 External Member DRC Committee for PH.D Program, MMMUT University
Gorakhpur (2022-till date)
 External Member of Board of Studies (BOS) EC Deptt, HBTU, Kanpur, Uttar Pradesh,
India. (2023-till Date)
 External Member of Board of Studies (BOS) EI Deptt IET, Barelliy University (2013-till
Date)
 External Member of Board of Studies of IET, Dr. Ram Manohar Lohia Avadh Univ.
Faizabad, Uttar Pradesh (2017 till date).

13 | Bio-data (Dr. Subodh Wairya)

  Joint Controller of Examination, Dr. A. P. J. Abdul Kalam Technical University
(AKTU), Lucknow, Uttar Pradesh, (Feb. 2015 to Jan. 2016)
 Dy. Coordinator, Uttar Pradesh State Entrance Examination, Lucknow (UPSEE-2014)
 Member Admission Committee M.Tech & M.Pharma, UPTU, Lucknow (2013-2014).
 Member Seat Matrix Committee, UPSEE (2013- 2014), UPTU, Lucknow
 Member of Scanning supervision Committee for UPSEE-2013
 Center Controller, State Entrance Examination (UPSEE) (2002-2008)
 Nodal Officer (Confidential), State Entrance Examination (2009-2013)
 Observer for UPSEE-2011 Counseling at Document Verification Choice Locking Center
 Member inspection committees regarding affiliation of Private Engineering Colleges
(2002-2008)
 Convener of Hospitality Committee, Annual Convocation, UPTU (2005-2008).
 Member of Hospitality Committee, Annual Convocation, UPTU (2011-2014).
 Head/Dy. Examiner, Central Evaluation (UPTU) regarding Examinations (2002-2014)
 Papers Setter/Thesis Examiner for UG/PG Course of Various Universities Examination (2005-
till date)
 Member Moderation Committee, Examination for Various Universities.
 Member flying Squad, End Semester Examination, UPTU (2004-2008).
 Group Leader (Flying Squad) Special Carry Over End Semester Exam UPTU (Sep 2011)
 External Member of Board of Studies (BOS) EI Deptt IET, Barelliy University (2013-
2017)
 Member of Selection Committee, Allahabad University, Prayagraj UP.

14 | Bio-data (Dr. Subodh Wairya)

Membership for Professional Societies:-
1. Life time member of Institute of Engineers IE (M133861-1)
Project Guide for PG/UG/AMI Student registered from The Institute of Engineers
(India), IE Kolkata (2011-till Date).
 Ashish Ranjan Srivastava (PG 41110022), “Wireless Transmitter.” The Institute of
Engineers (India), IE Kolkata, (2012)
 Mukesh Kumar Sahu (ST No. 509433-5), “Microcontroller based Eye Blink Sensor and
Accident Prevention Device.” The Institute of Engineers (India),IE Kolkata, (2013)
 Divya Khanuja (ST No. 561209-3), “Electronics Eye Controlled Security System.” The
Institute of Engineers (India),IE Kolkata, (2014)
 Anamika Shukla (ST No. 559386-2), “Microcontroller based Safety System for Train.”
The Institute of Engineers (India), IE Kolkata, (2014)
 Gopi Kant (ST No. 120177-3), “Working of 1000KW AM Medium Wave DRM (Digital
Radio Mondiale) Super Power Transmitter.” The Institute of Engineers (India), IE
Kolkata, (2015).
 Neetu Vishwakarma (ST No. 613298-2), “Solar Tracking System & Its Application.” The
Institute of Engineers (India), IE Kolkata, (2016).
2. Life time member of Institute of Electrical and Telecommunication Engineering IETE
(M189081)
3. Member Executive Committee, The Institute of Electronics Telecommunication Engineers
(IETE), Lucknow Chapter, (2015-till date)
4. Life time member of Indian Society for Technical Education (LM33784)

15 | Bio-data (Dr. Subodh Wairya)

 Research
&
Publications

16 | Bio-data (Dr. Subodh Wairya)

 M.E. THESIS GUIDED (42)/M.TECH. THESIS UNDER GUIDANCE (1)
1. Garima Singh, “Performance Analysis of High Speed Low Voltage CMOS Full Adder Circuits,
AIM&ACT, Banasthali University, Rajasthan , India.(2011-2012)
2. Divya Tripathi, “Design Analysis of High-Speed XOR/XNOR based Logic Circuits Suitable for
Low Power VLSI Applications.” Jayoti Vidyapeeth Women’s University, Jaipur, Rajasthan, India
(2012).
3. Meenakshi Shree, “Design Analysis of Mixed Chain Full Adder Circuits for VLSI Applications,”
JayotiVidyapeeth Women’s University, Jaipur, Rajasthan, India (2012).
4. Ritika Mishra, “Low Power Design Analysis of Array Multipliers Using Hybrid CMOS Full
Adder Circuits.” Jayoti Vidyapeeth Women’s University, Jaipur, Rajasthan, India (2012).
5. Sapna Dixit, “Performance Analysis of High Speed Adiabatic Digital Logic Circuits, AIM&ACT,
Banasthali University, Rajasthan , India. (2012-2013)
6. Nidhi Gupta, “Realization and study of Low Power CMOS Current Feedback Amplifier“AIM
&ACT, Banasthali University, Rajasthan, India. (2013-2014).
7. Rahul Verma, “Design and Analysis of Ultra Low Power SRAM Cache Memory Cell”, IET,
Lucknow, India (2014).
8. Monika Jain, “Study and Design of Low Power and Leakage Proof Digital Circuits”, IET,
Lucknow, India (2014).
9. Anjali Tiwari, Design and Performance Analysis of Dynamic Circuits using Multi-Threshold
Technique for Low Power VLSI Circuits, AIM &ACT, Banasthali University, Rajasthan, India.
(2015).
10. Vijata, “Design and Analysis of Different Topologies of CMOS Operational Trans-conductance
Amplifier”, IET, Lucknow, India (2015).
11. Archita Srivastava, “Implementation and Analysis of Adiabatic Logic Circuits.” Jayoti
Vidyapeeth Women’s University, Jaipur, Rajasthan, India. (2015)
12. Shivani Shukla, “Temperature Dependent Leakage Power Characteristic of Dynamic Circuit in
Nanometer CMOS Technologies.” Jayoti Vidyapeeth Women’s University, Jaipur, Rajasthan,
India (2015).
13. Shweta Kumari, “Performance Analysis of GDI Based 1-Bit Full Adder Circuit for Low Power &
High Speed Application.” Jayoti Vidyapeeth Women’s University, Jaipur, Rajasthan, India
(2015).
14. Ravi Prakash Verma, “Filter Antenna Module using Substrate Integrated Waveguide.” SRMS
Barailly, Uttar Pradesh Technical University, Lucknow, India (2015).
15. Ankita Agarawal,“Cross layer optimization of Optical node in High Speed Network.” M.Tech
Modular, Uttar Pradesh Technical University, Lucknow, India (2015).
16. Shashank Gupta, “Design Of Hybrid Code Converters Using Modified Gate Diffusion Input
Technique”, IET, Lucknow, India (2016).
17. Shraddha Pandey, “Designing An Efficient JK and T Flip Flop using QCA with Power
Dissipation Analysis.”, IET, Lucknow, India (2016).
18. Sonali Singh, “Modular Design Of 2n*1 QCA Multiplexers and its application Via Clock Zone
based Crossover”, IET, Lucknow, India (2016)
19. Ragni Tripathi, “Design analysis of low pass GDI circuit in sub-threshold region”, IET, Lucknow,
India (2017)
20. Ritesh Singh, “Implementation of non-restoring reversible divider using QCA”, IET, Lucknow,
India (2017)

17 | Bio-data (Dr. Subodh Wairya)

 21. Sakshi Gupta, “Efficient design of even and odd parity generator using different XOR-XNOR
modules in VLSI design circuit”, IET, Lucknow, India (2017)
22. Yogesh Singh, “Design Analysis for SRAM in Nano-Technology”, M.Tech (Modular), AKTU,
Lucknow, India (2018)
23. Shahneela Jamal Kidwai, “Design of Full Adder with self checking capability using QCA”, IET,
Lucknow, India (2018)
24. Bhoopendra Vikram Singh, “Contact thickness effect on mobility of Organic Thin Film Transistor
and tradeoff with current on-off ratio”, IET, Lucknow, India (2018)
25. Anshu Arya, “Performance Evaluation and design implementation of SRAM Semiconductor
Memory in Nanotechnology”, IET, Lucknow, India (2018)
26. Abhishek Shukla, “Designing and Performance Comparison of Parity Generators Using
Various XOR-XNOR modules”, IET, Lucknow, India, (2019).
27. Prashasti, “Performance Evaluation of High Speed and Low Power Digital Circuits using Energy
Efficient XOR & XNOR logic gates”, IET, Lucknow, India, (2019).
28. Shivangi Jaiswal, “Performance Evaluation of Combinational circuit based on Energy Efficient
Adiabatic Logic Technology for Ultra Low-Power Applications”, IET, Lucknow, India, (2019).
29. Sana, “Implementation of MGDI and Transmission Gate Based Hybrid CMOS Full Adders Using
Triplet Design Approach”, IET, Lucknow, India, (2020).
30. Priti Tripathi, “Low Power Shift Registers Using Contention Free Single-Phase Clocked Flip
Flop”, IET, Lucknow, India, (2020).
31. Sweta Tripathi, “Low Power Voltage Controlled Oscillator (VCO) Using Multi-Threshold
Transistors and Power gating Technique in Deep Submicron Technology”, IET, Lucknow, India,
(2020).
32. Vivek Mishra, “Implementation of Process Supply Voltage and Temperature Compensated
Supply Circuit for A Ring Oscillator”, IET, Lucknow, India, (2020).
33. Semba Walli, “MOSFET Based Memristor Emulator Circuit Analysis and Applications”, IET,
Lucknow, India, (2020).
34. Vivek Saxena, “Power Efficient Frequency Divider Circuit for VLSI Applications”, IET,
Lucknow, India, (2020).
35. Aishita Verma, “Performance Analysis of Hybrid Full Adder and Multiplier Topologies for Fast
Computation”, IET, Lucknow, India, (2021).
36. Nivedita Rai, “Performance Evaluation and Analysis of Comparator Design in VLSI
Application”, IET, Lucknow, India, (2021).
37. Ayushi Kirti Singh, “Design and Realization of QCA based Logic Designs”, IET, Lucknow,
India, (2022).
38. Kunal Kumar, “Design of Low Power Dynamic Comparator Topologies for VLSI”, IET,
Lucknow, India, (2022).
39. Mohd Saqib, “Performance Evaluation and Analysis of Differential Dual stage delay cells VCO”,
IET, Lucknow, India, (2022).
40. Archana, Design and Analysis of Dual Source Vertical TFET with and without channel
overlapped structure for Low Power Applications, IET, Lucknow, India, (2023)
41. Parikalp Gupta, Performance and Design Analysis 0f Ternary Arithmetic Logic Circuits, IET,
Lucknow, India, (2023)
42. Abhinav Saxena, Energy Efficient Architectures of Dynamic Comparator for Low Power VLSI
Application, IET, Lucknow, India, (2023)

18 | Bio-data (Dr. Subodh Wairya)

 PH.D. THESIS AWARDED (05):

1. Neeraj Kumar Mishra PhD/13/ECE/1134, Design and Testability of Diverse Reversible

Logic Circuits for Low cost Nanoelectronics Application, Dr. A.P.J. Abdul Kalam Technical
University Uttar Pradesh (AKTU), Lucknow, India . (2017)
2. Divya Tripathi, (PHD/13/ECE/1413, “Performance Evaluation of Low Power, High Speed
Arithmetic Logic Circuits in Nanotechnology,” Dr. A.P.J. Abdul Kalam Technical
University Uttar Pradesh (AKTU), Lucknow, India (2022)
3. Digvijay Pandey, (PHD/16ECE/2172, Performance Analysis on Text Extraction from
Complex Degraded Images”, Dr. A.P.J. Abdul Kalam Technical University Uttar Pradesh
(AKTU), Lucknow, India. (2023)
4. Jyoti Garg, (PHD/15ECE/2055), Performance Evaluation of Non Volatile Memory for Low
Power VLSI Application, Dr. A.P.J. Abdul Kalam Technical University Uttar Pradesh
(AKTU), Lucknow, India. (2023)
5. Shilpi Gupta, (PHD/16/ECE/2175), Performance Investigation OF SiGe Hetero Junction
Gate Stacked Triple Metal Gate Vertical TFET for Low Power Application, Dr. A.P.J.
Abdul Kalam Technical University Uttar Pradesh (AKTU), Lucknow, India.(2023)
6. Raj Vikram Singh, (PHD/15/ECE/1903, DWT and Neural Network based Watermarking for
Medical Image Security, Dr. A.P.J. Abdul Kalam Technical University Uttar Pradesh
(AKTU), Lucknow, India. 2024.
PH.D. THESIS SUBMITTED:
Anum Khan, (PHD/17/ECE/2211, Performance Evaluation of High Speed Digital Circuits In
Nanotechnology Architecture, Dr. A.P.J. Abdul Kalam Technical University Uttar Pradesh
(AKTU), Lucknow, India July 2024. (Thesis Submitted).

PH.D. THESIS UNDER GUIDANCE (06):

Enrollment Full Name Mobile No Email Id Topic

19ECE2461 Anurag Yadav 7651921092 [email protected] Performance Evaluation of Low

Power High Speed VLSI Design and
Application with Data Converter
Architecture

20ECE2610 SANA 9140159469 [email protected] Low Power VLSI Circuits

21ECE2657 Priyanka Shakya 9451452839 [email protected] Design and Analysis of STT-RAM

using Logic in Memory Architecture

21ECE2713 Preeti Tripathi 7379734552 [email protected] A Novel Cross-Latch Shift Register

Scheme for Low Power Applications

21ECE2715 Sheetal Singh 7006425805 [email protected] High frequency circuit design in

microelectronics

24ECE Rahul Singh [email protected]

19 | Bio-data (Dr. Subodh Wairya)

PUBLICATIONS: https://scholar.google.co.in/citations?user=d-g3yEoAAAAJ&hl=en

PUBLICATIONS: JOURNAL
2024
1. Sheetal Singh, Subodh Wairya, “Linearity and noise evaluation based analysis of extended source heterojunction
double gate tunnel FET”, Micro and Nanostructures, Volume 194,2024,207939, ISSN 2773-0123,
https://doi.org/10.1016/j.micrna.2024.207939.(https://www.sciencedirect.com/science/article/pii/S27730123240018
82)
2. A. Khan, S. Wairya, "Efficient and Power-Aware Design of a Novel Sparse Kogge-Stone Adder using Hybrid Carry
Prefix Generator Adder," Advances in Electrical and Computer Engineering, vol.24, no.1, pp.71-80, 2024,
doi:10.4316/AECE.2024.01008, Print ISSN:1582-7445 Online ISSN: 1844-7600 file:///C:/Users/User/Downloads/
aece_2024_1_8.pdf.
3. Anurag Yadav, Subodh Wairya, “Design and Analysis of Low Power and High Speed Dynamic Comparator with
Transconductance Enhanced in Latching stage for ADC Application”, Journal of Circuits, Systems and
Computers, https://doi.org/10.1142/S0218126624501986.

2023
4. Anum Khan, Arindom Chakraborty, Upal Barua Joy Subodh Wairya Mehedi Hasan, “Carry look-ahead and ripple
carry method based 4-bit carry generator circuit for implementing wide-word length adder” , Microelectronics
Journal, pp. 105949, 2023. DOI : https://doi.org/10.1016/j. mejo.2023. 105949
5. Ayushi Kirti Singh, Subodh Wairya & Divya Tripathi, “Cell Optimization and Realization of Vedic Multiplier
Design in QCA”, Int. J. Com. Dig. Sys. 14, No.1, pp. 10491-10503,,http://dx.doi.org/10.12785/ijcds/1401116. Dec
2023. https://journal.uob.edu.bh/bitstream/handle/123456789/5097/IJCDS1401116_1570862142.pdf?sequence=
3&isAllowed=y, ISSN (2210-142X).
6. Manoj Kumar Jain, Amrita Singh and Subodh Wairya, "Configuration for a Grounded Lossy Impedance Simulator
Employing CC-CFAs and Grounded Passive Elements", Serbian Journal of Electrical Engineering, Vol. 20, Issue 2,
Page 147-162 (2023), Publisher Faculty of Technical Sciences Cacak. https://doi.org /10.2298/ SJEE2302147J.
EISSN: 2217-7183,
7. Jyoti Garg, Subodh Wairya, “Design of Low Power Arithmetic logic unit using SHE assisted STT / MTJ,
International Journal of Computing and Digital Systems Int. J. Com. Dig. Sys.14, No.1 (Jul-23), pp. 107-115, July,
2023, ISSN (2210-142X). DOI: http://dx.doi.org/10.12785/ijcds/140110
8. Raj Vikram Singh, Subodh Wariya Rajiv Kumar Singh, “DWT-SVD Based Robust Watermarking Technique for
Secure Medical Image Diagnosis”, Journal of Survey in Fisheries Sciences, vol. 10 no. 3S (2023) Special Issue 3,
pp. 1087-1098, 2023. DOI: https://doi.org/10.17762/sfs.v10i3S.118.
9. Raj Vikram Singh, Subodh Wariya, Rajiv Kumar Singh, “Watermarking Scheme for Medical Images with
Enhanced Robustness based on Discrete Wavelet Transform and Neural Network”, Journal of Data Acquisition and
Processing, , vol. 38 no. 2, pp. 1234-1246, April 2023.DOI: https://doi.org/10.5281/zenodo.77670. ISSN 1004-9037
10. Aishita Verma, Anum Khan, Subodh Wairya, “Design and Analysis of Efficient Vedic Multiplier for Fast
Computing Applications”, Int. J. Com. Dig. Sys., Vol. 13, Issue 1, pp. 190-201, 2023. ISSN (2210-142X). DOI:
http://dx.doi.org/10.12785/ijcds/130151
11. Digvijay Pandey, Subodh Wairya, “An optimization of target classification tracking and mathematical modelling
for control of autopilot”, The Imaging Science Journal, Taylor & Francis, Vol. 70, Issue 6, pp. 371-386, 2023. DOI:
https://doi.org/10.1080/13682199.2023.2169987
12. Mohd Saqib, Subodh Wairya and Anurag Yadav, “A 6.7GHz, 89.33 µW power and 81.26% tuning range dual input
ring VCO with PMOS varactor”, Journal of Circuits, Systems, and Computers (JCSC) ISSN: 0218-1266.
https://doi.org/10.1142/S0218126623501992.
13. Raj Vikram Singh, Subodh Wariya Rajiv Kumar Singh,“ Different Watermarking Technique used in Medical Image
Security”, Advanced Engineering Science, vol. 55 no. 1, pp. 492-501, 2023.

2022
14. Jyoti Garg, Subodh Wairya, “Performance Evaluation of Low Power Hybrid Combinational Circuits using
Memristor”, International Journal of Electrical and Electronics Research (IJEER), 2022, 10(4), pp. 988–993 ISSN:
2347-470X (Online) FOREX Publication 10.37391/IJEER.

20 | Bio-data (Dr. Subodh Wairya)

 15. Vivek Mishra, Anurag YadavYadav, Subodh Wairya, “Design
Design of Compensated Supply Circuit Topology for a Ring
Oscillator”, International Journal of Computing and Digital System, July
July-2022.
2022. Int. J. Com. Dig. Sys. 12, No.1 (Jul-
(Jul
2022) pp. 1005-1017. https://dx.doi.org/10.12785/ijcds/120181
https://dx.doi.org/10.12785/ijcds/120181. ISSN (2210-142X).
16. D Pandey, S Wairya, B Pradhan
Pradhan, Wangma, “Understanding COVID-19
19 response by twitter users: A text analysis
approach”, pp. 1-6, Heliyon (8)
(8), 2022
17. Divya Tripathi, Subodh Wairya, A Cost Efficient QCA Code Converters for Nano Communication
Applications, International Journal of Computing and Digital System, July-2022.
2022. Int. J. Com.
Com Dig. Sys. 12, No.1
(Jul-2022), pp. 345-352. https://dx.doi.org/10.12785/ijcds/120128
https://dx.doi.org/10.12785/ijcds/120128. ISSN (2210-142X)..
18. Anum Khan, Subodh Wairya, “Performance Evaluation ooff Highly Efficient XOR and XOR-XNOR
XOR Topologies
using CNTFET for Nanocomputation”, International Journal of Computing and Digital System, July-2022.
July Int. J.
Com. Dig. Sys. 12, No.1 (Jul-2022)
2022) pp. 225
225-236. https://dx.doi.org/10.12785/ijcds/120120.
https://dx.doi.org/10.12785/ijcds/120120 ISSN (2210-142X).
19. Pandey, D., Wairya, S., Sharma, M. et al “An
An approach for object tracking, categorization, and autopilot guidance
for passive homing missiles”,
”, Aerospace Systems (2022): pp. 1-14.
14. Springer Nature Singapore, https://doi.org
/10.1007/s42401-022-00150-00.
20. Shilpi Gupta, Subodh Wairya, Shaliendra Singh, “S. Design and Analysis of Triple Metal Vertical
Ve TFET Gate
Stacked with N-Type
Type SiGe Delta
Delta-Doped Layer”, Volume-14 Issue-8, June 2022, pp. 4217-4225
4217 Silicon 2022.
https://doi.org/10.1007/s12633
https://doi.org/10.1007/s12633-021-01211-3
21. Anurag Yadav, Subodh Wairya, “Performance and Area Optimization of SRAM Cell in Nanotechnology Nanotechnol
Application”, International Journal of Computing and Digital Systems (Int. J. Com. Dig. Sys. 11, No.1 (Mar-2022))
(Mar
pp. 1009-1026, March 2022, https://dx.doi.org/10.12785/ijcds/110182
https://dx.doi.org/10.12785/ijcds/110182, ISSN (2210-142X).
2X).
22. Binay Kumar Pandey, Digvijay Pandey, Subodh Wariya, et al “Application
Application of Integrated Steganography
Stegano and
Image Compressing Techniques for Confidential Information Transmission
Transmission,, Cyber Security and Network Security,
169-191, Publisher John Wiley & Sons, Inc.
23. Pandey, Digvijay and Subodh Wairya. "A Novel Algorithm to Detect and Transmit Human-Directed
Human Signboard
Image Text to Vehicle Using 5G
5G-Enabled Wireless Networks." IJDAI vol.14, no.1 2022: pp.1-11.
pp.1 http://doi.
org/10.4018/IJDAI.291084.

2021
24. Akhil Gupta, Rohit Anand, Digvijay Pandey , Nidhi Sindhwani, Subodh Wairya, Binay Kumar Pandey
, Manvinder Sharma: "Prediction of Breast Cancer Using Extremely Randomized Clustering Forests (ERCF)
Technique: Prediction of Breast Cancer." IJDST vol.12, no.4 2021: pp.1-15. http://doi.org/10.4018/IJDST.287859

25. Pandey, B. K., Pandey, D., Wairya, S., & Agarwal, G. (2021). Deep Learning and Particle Swarm Optimisation-
Optimisation
Based Techniques for Visually Impaired Humans' Text Recognition and Identification. Augment Hum Res 6, 14
(2021). https://doi.org/10.1007/s41133
https://doi.org/10.1007/s41133-021-00051-5.

26. Pandey, B. K., Pandey, D., Wairya, S., & Agarwal, G. (2021). An Advanced Morphological Component Analysis,
Steganography, and Deep Learning
Learning-Based
Based System to Transmit Secure Textual Data. International Journal of
Distributed Artificial Intelligence (IJDAI), 13(2), 40
40-62. http://doi.org/10.4018/IJDAI.2021070104.
http://doi.org/10.4018/IJDAI.2021070104

27. Pandey, Binay Kumar and Pandey, Digvijay and Wariya, Subodh and Agarwal, Gaurav (2021) A Deep Neural
Network-Based
Based Approach for Extracting Textual Images from Deteriorate Images. EAI Endorsed Transactions on
Industrial Networks and Intelligent Systems, 8 (28). e3. ISSN 2410
2410-0218.

28. Digvijay Pandey, , Subodh Wairya , Raghda Salam Al.Mahdawi , Saif Al-din din M. Najim , Haitham Abbas Khalaf ,
Shokhan M. Al-Barzinji
Barzinji , Ahmed J. ObaideInt. “Secret data transmission using advance steganography and image
compression”, International Journal of Nonlinear Analysis and Applications
Applications.. Volume 12, Special Issue, Winter and
Spring 2021, 1243-1257
1257 ISSN: 2008
2008-6822
6822 (electronic) http://dx.doi.org/10.22075/ijnaa.2021.5635
29. Shilpi Gupta, Subodh Wairya
Wairya, Shaliendra Singh, “Analytical modeling and simulation
imulation of a triple metal vertical
TFET with hetero-junction gateate stack”, Superlattices and Microstructures Journal. Volume 157,
157 September 2021,
106992. https://doi.org/10.1016/j.spmi.2021.106992
https://doi.org/10.1016/j.spmi.2021.106992.
30. Divya Tripathi, Subodh Wairya, ““An Energy Dissipation and Cell Optimization of Vedic Multiplier Topologies for
Nanocomputing Applications”, ”, Turkish Journal of Computer and Mathematics Education,
Education Vol.12 No.14 (2021),
1490– 1510. https://turcomat.org/index.php/turkbilmat/article/
https://turcomat.org/index.php/turkbilmat/article/view/10473/7889

21 | Bio-data
data (Dr. Subodh Wairya)
 31. Digvijay Pandey, Shaji George, Bashiru Aremu, Subodh Wariya, Binay Kumar Pandey, “Critical Review on
Integration of Encryption, Steganography, IOT and Artificial Intelligence for the Secure Transmission of Stego
Images”, Scientific Research Journal of Engineering and Computer Science, 2021, Sci Res Jr Eng Comp Sci.1(1):-
33-36, Volume 1,Issue: 1 (June-July ) ISSN On line: 2788- 9408. DOI: 10.47310/srjecs.2021.v01i01.005.

2020
32. Jyoti Garg, Niharika Varshney and Subodh Wairya, Comparative study of Magnetic Tunnel Junction based 4 T -
MRAM, International Journal of Advanced Research in Engineering and Technology (IJARET), 11(5), 2020, pp.
1178-1186.doi: 10.34218/IJARET.11.5.2020.128, https://iaeme.com/Home/article_id/IJARET_11_05_ 128, https://
iaeme.com/Home/journal/IJARET#
33. Sana, Anum Khan, Subodh Wairya, “Design and Analysis of Hybrid full adder Topology using Regular and Triplet
Logic Design”, International Journal of Innovative Technology and Exploring Engineering (IJITEE) (Blue Eyes
Intelligence Engineering & Sciences Publication), Volume-9 Issue-12, October 2020 pp. 348-354, DOI:
10.35940/ijitee.L8024.1091220, Oct. 2020. ISSN: 2278-3075, http://www.ijitee.org/wp-content/uploads/papers/
v9i12/L80241091220.pdf.
34. Pandey, D., Pandey, B.K. & Wairya, S. “Hybrid deep neural network with adaptive galactic swarm optimization for
text extraction from scene images”, Soft Comput. 25(2): 1563-1580 (2021), Electronic ISSN: 1433-7479, Print
ISSN: 1432-7643, https://doi.org/10.1007/s00500-020-05245-4, Indexed in Thomson Reuters, (SCIE impact factor
3.05)
35. Divya Tripathi, Subodh Wairya. “Energy Efficient Code Converter For Nanotechnology Applications”, Journal of
Critical Reviews (JCR). 2020; 7(13): 2916-2925, ISSN 2394-5125, doi:10.31838 /jcr.07.13.448
36. Digvijay Pandey, Binay Kumar Pandey, Dr. Subodh Wairya, Dr. Randy Joy M. Ventayen, Bilal Khan, Dr Monika
Gupta, Dr. Tribhuwan Kumar. “Analysis of Text Detection, Extraction and Recognition from Complex Degraded
Images and Videos” Journal of Critical Reviews (JCR) 2020; Vol. 7, Issue 18, pp. 427-433, ISSN 2394-5125,
doi: 10.31838/jcr.07.18.63,
37. D. Pandey, Binay Kumar Pandey, and Subodh Wairya, “An Approach To Text Extraction From Complex Degraded
Scene”, International Journal of Computational and Biological Sciences (IJCBS), Vol. 1 No. 2 (2020): ISSN 2708-
3551 (Online).
38. Tripathi Divya & Subodh Wairya “An Energy Efficient Binary Magnitude Comparator for Nanotechnology
Application”, International Journal of Recent Technology and Engineering (Blue Eyes Intelligence Engineering &
Sciences Publication) Vol.8 Issue-6, pp. 430-436, DOI:10.35940/ijrte.F7000.038620 March 2020. ISSN: 2277-
3878, https://www.ijrte.org/wp-content/uploads/papers/v8i6/F7000038620.pdf.

2019
39. Abhishek Shukla, Subodh Wairya, “Design of Odd-Even Parity Generator using Six Transistors XOR-XNOR
Module”, International Research Journal of Engineering and Technology (IRJET), Vol. 6 Issue 11, Nov 2019, e-
ISSN: 2395-0056.
40. Digvijay Pandey, Binay Kumar Pandey, Subodh Wairya “Study of Various Types Noise and Text Extraction
Algorithms for Degraded Complex Image” Journal of Emerging Technologies and Innovative Research, vol. 6,
Issue 6. pp. 234-246, June 2019. ISSN: 2349-5162. UGC Approved Journal.
41. Digvijay Pandey., Binay Kumar Pandey, Subodh Wairya “Study of Various Techniques Used for Video Retrieval”
Journal of Emerging Technologies and Innovative Research, vol. 6, issue 6, pp.850-853, June 2019. ISSN
Number: 2349-5162.
42. Prashasti, Shivangi Jaiswal, Anum Khan and Subodh Wairya, “High Performance and Low Power D Flip-Flop
using Pulsed Latch Technique” International Journal of Applied Engineering Research (IJAER), ISSN 0973-
4562, Vol. 14, no.2 (Special Issue), pp. 301-305 (2019) ijaerv14n2spl_53.
43. S. Kidwai and Subodh Wairya, “Study of QCA based digital logic circuits to be used in nanotechnology”, Global
Journal of Engineering Science and Researches,[COTII -2018] pp. 289-295, July 2018, ISSN 2348–8034.

2018
44. Divya Tripathi and Subodh Wairya," Performance evaluation of low power Carry save adder for VLSI applications"
International Journal of VLSI design & Communication Systems (VLSICS) Vol. 9, No.3, pp. 51-58, June 2018,
DOI: 10.5121/vlsic.2018.9305, ISSN: 0976-1357. https://ssrn.com/abstract=3288356

22 | Bio-data (Dr. Subodh Wairya)

 45. Raj Vikram Singh, Subodh Waira, Rajiv Kumar Singh & Harsh Vikram Singh, “Robust Watermarking using
Genetic Algorithm in DCT Domain”, International Journal of Engineering and Technology (IJET), Vol. 7, No.
3(12). Special Issue 12, pp. 1202-1204, 2018. ISSN 1793-8236 (Online),. DOI: 10.14419/ijet.v7i3.12.17837.

2017
46. Neeraj Kumar Misra, Subodh Wairya, Bibhash Sen, “Design of conservative, reversible sequential logic for cost
efficient emerging nano circuits with enhanced testability”. Ain Shams Engineering Journal, Elsevier
(Amsterdam, Netherlands), vol. 9, issue 4, pp. 2027-2037, December 2018, DOI: 10.1016/j.asej.2017.02.005, ISSN:
2090-4479, Indexed in Thomson Reuters (SCIE impact factor =3.091)
47. Neeraj Kumar Misra, Bibhash Sen, Subodh Wairya, “Towards designing efficient reversible binary code converters
and a dual-rail checker for emerging nanocircuits”. Journal of Computational Electronics, Springer (New York,
USA), 17 pages, vol. 16, issue 2, pp. 442-458, Feb 25, 2017, DOI: 10.1007/s10825-017-0960-4, ISSN: 1569-8025,
Indexed in Thomson Reuters (SCIE impact factor =1.63)
48. Neeraj Kumar Misra, Bibhash Sen, Subodh Wairya, Bandan Boi, “Testable Novel Parity-Preserving Reversible
Gate and Low-Cost Quantum Decoder Design in 1D Molecular-QCA”. Journal of Circuits, Systems, and
Computers, World Scientific (Singapore), 26 pages, vol. 26, issue 09, pp. 1-26, 28-Feb-2017. DOI:
10.1142/S0218126617501456, ISSN: 0218-1266. Indexed in Thomson Reuters (SCIE impact factor =0.595)
49. Neeraj Kumar Misra, Bibhash Sen, Subodh Wairya, “Novel Tree Structure Based Conservative, Reversible BCD
Adder With Added Testability In Quantum Circuits”, Journal of Computational and Theoretical Nanoscience
(Valencia, California, USA), vol. 14(5), pp. 1-13, 1-May-2017, ISSN: 1546-1955, DOI:10.1166/jctn.2017.6772,
Indexed in SCOPUS
50. Neeraj Kumar Misra, Bibhash Sen, Subodh Wairya, “Novel Conservative Reversible Error Control Circuits Based
On Molecular-QCA”, International Journal of Computer Applications in Technology, Inderscience Publishers
(Switzerland), vol. 56, no. 1, 13-September-2017, DOI: 10.1504/ IJCAT. 2017.086558, ISSN: 1741-5047.Indexed
in Thomson Reuters (ESCI)
51. Neeraj Kumar Misra, Bibhash Sen, Subodh Wairya, “Designing of an Energy-Efficient Nanoelectronics
Architecture for Binary Comparator Based On Quantum-Dot Cellular Automata”, SHRISTI : A Journal of Energy,
Environment & Ecology at School of Management Science, Lucknow at School of Management Science,
Lucknow, 2017.

2016
52. Neeraj Kumar Misra, Bibhash Sen, Subodh Wairya, “Designing Conservative Reversible N-Bit Binary Comparator
for Emerging Quantum-Dot Cellular Automata Nano Circuits”, Journal of Nanoengineering and
Nanomanufacturing American Scientific Publisher (Valencia, California, USA), 16 pages, Vol. 6, No. 3, pp. 201-
216, DOI:10.1166/jnan.2016.1286
53. Prateek Agrawal, S.R.P. Sinha, Neeraj Kumar Misra, and Subodh Wairya “Design of Quantum Dot Cellular
Automata Based Parity Generator and Checker with Minimum Clocks and Latency” International Journal of
Modern Education and Computer Science (IJMECS) vol. 8, no. 8, pp. 11-20, August 2016, ISSN: 2075-0161 ,
DOI: 10.5815/ijmecs.2016.08.02
54. Sonali Singh, Shraddha Pandey and Subodh Wairya, “Modular Design of 2 :1 Quantum Dot Automata
Multiplexers and its Application via Clock zone based Crossover” International Journal of Modern Education and
Computer Science (IJMECS) vol. 8, no. 7, pp. 41-52, ISSN: 2075-0161, July 2016, DOI: 10.5815/
ijmecs.2016.07.05
55. Shraddha Pandey, Sonali Singh and Subodh Wairya, “Designing an Efficient Approach for JK and T flip-flop with
Power Dissipation Analysis using QCA” International Journal of VLSI design & Communication Systems
(VLSICS) vol.7, no.3, pp. 29-48, ISSN 0976-1357 June 2016.
56. Shashank Gupta and Subodh Wairya, “Hybrid Code Converters using Modified GDI Technique" International
Journal of Computer Applications, vol. 143, no.7, pp. 12-19, June 2016. ISSN: 0975–8887,
57. Shashank Gupta and Subodh Wairya, "A GDI Approach to Various Combinational Logic Circuits in CMOS Nano
Technology" International Journal of Engineering and Computer Science, vol. 5, Issue 4 April 2016, pp.
16243-16247. ISSN: 2319-7242
58. Neeraj Kumar Misra, Subodh Wairya, V. K. Singh, “Approach to Design a High Performance Fault-Tolerant
Reversible ALU”, International Journal of Circuits and Architecture Design, Inderscience Publishers
(Switzerland), vol. 2, no. 1, pp. 83-103, 12-April-2016, DOI: 10.1504/IJCAD.2016.075913, ISSN: 2051-7033.
23 | Bio-data (Dr. Subodh Wairya)
 59. Neeraj Kumar Misra, Bibhash Sen, Subodh Wairya, “Designing Conservative Reversible N-Bit Binary Comparator
For Emerging Quantum-Dot Cellular Automata Nano Circuits”, Journal of Nano-engineering and
Nonmanufacturing, American Scientific Publisher (Valencia, California, USA), vol. 6, pp. 1-16, 2016, DOI:
10.1166/jnan.2016.1286, ISSN: 2157-9326.
60. Prateek Agrawal, S.R.P.Sinha, Neeeraj Kumar Misra, Subodh Wairya, “Design of Quantum Dot Cellular Automata
Based Parity Generator and Checker with Minimum Clocks and Latency”, International Journal of Modern
Education and Computer Science, vol. 8, pp. 11-20, 2016, DOI: 10.5815/ijmecs.2016.08.02, ISSN: 2075-0161.
61. Prateek Agrawal, S.R.P. Sinha, Subodh Wairya, "Quantum Dot Cellular Automata Based Parity Generator And
Detector: A Review", International Journal of Electronics and Communication Engineering (IJECE), vol. 5,
Issue 3, pp. 41-50, ISSN(P): 2278-9901; ISSN(E): 2278-991X, 2016.

2015
62. Neeraj Kumar Misra, Subodh Wairya, V. K. Singh, “Optimized Approach for Reversible Code Converters Using
Quantum Dot Cellular Automata”, Book Chapter Advances in Intelligent Systems and Computing, Springer. vol.
404, Book Part: Part VIII, Swagatam Das, et al., Eds., ed: 2015, pp. 367-378, 25 October 2015, Print ISBN: 978-
81-322-2693-2, Online ISBN: 978-81-322-2695-6, DOI: 10.1007/978-81-322-2695-6_31, Indexed in SCOPUS
63. Neeraj Kumar Misra, Subodh Wairya and Vinod Kumar Singh, "Approaches to Design Feasible Error Control
Scheme Based on Reversible Series Gates", European Journal of Scientific Research (United Kingdom), vol. 129,
no. 3, 2015, pp. 224-240, 2015, ISSN 1450-216X..Indexed in SCOPUS
64. Neeraj Kumar Misra, Subodh Wairya and Vinod Kumar Singh, “Frame of Reversible BCD Adder and Carry Skip
BCD Adder and Optimization Using New Reversible Logic Gates for Quantum-Dot Cellular Automata”,
Australian Journal of Basic and Applied Sciences, vol. 9, no. 31, pp. 286-298, 2015, ISSN 1991-8178. Indexed in
SCOPUS
65. Vijata, Subodh Wairya, “A Study of Two Stage Operational Transconductance Amplifier using Floating gate
MOSFET”, International Journal of Engineering And Computer Science, vol 4, issue 10, Oct 2015, pp. 14643-
14648, ISSN: 2319-7242, DOI: 10.18535/ijecs/v4i10.17
66. Neeraj Kumar Misra, Mukesh Kumar Kushwaha, Subodh Wairya and Amit Kumar,” Cost Efficient Design of
Reversible Adder Circuits for Low Power Applications” International Journal of Computer Applications vol. 117,
no.19, ISSN 0975-8887,May 2015.
67. Avinash Singh, Subodh Wairya, “A 16-Bit Ripple Carry Adder Design Using High Speed Modified Feedthrough
Logic”, International Journal of Engineering And Computer Application (IJECS), vol. 4, issue 5, pp. 12058-12061,
ISSN: 2319-7242, May 2015.
68. P Sharma, Subodh Wairya, “ A Feasible Approach to Design a CMOS Domino Circuit at Low Power VLSI
Application”, International Journal Of Engineering And Computer Science, vol 4, issue 7, pp. 13055-13060, ISSN:
2319-7242, July 2015.
69. Avinash Singh, Subodh Wairya, “An Improved Feedthrough Logic for Low Power and High Speed Arithmetic
Circuits”, International Journal of Science and Research (IJSR), vol. 4, issue 5, pp-2277-2280, ISSN (Online):
2319-7064, 2015.
70. Ankita Agarwal & Subodh Wairya “Cross layer Optimization of Optical Node in High Speed Network”
International Journal of Engineering Research & Technology (IJERT), ISSN: 2278-0181 vol. 4, issue 11, pp 599-
603, November-2015.
71. Neeraj Kumar Misra, Mukesh Kumar Kushwaha, Subodh Wairya and Amit Kumar, “Feasible Methodology for
optimization of a novel reversible binary compressor”, International Journal of VLSI design & Communication
Systems (VLSICS), vol.6, no. 4, pp. 1-22, 2014, DOI : 10.5121/vlsic.2015.6401, ISSN: 0976-1357.

2014
72. Neeraj Kumar Misra, Subodh Wairya and Vinod Kumar Singh, “Evolution of structure of some binary group-based
n-bit comparator, n-to-2n decoder by reversible technique”, International Journal of VLSI design &
Communication Systems (VLSICS), vol.5, no. 5, pp. 9-22, 2014, DOI : 10.5121/vlsic.2014.5502, ISSN: 0976-
1357.
73. Neeraj Kumar Misra, Subodh Wairya, Vinod Kumar Singh, “Preternatural Low-Power Reversible Decoder Design
in 90 nm Technology Node”, International Journal of Scientific & Engineering Research, vol 5, issue 6, pp.
969-978, 2014, ISSN 2229-5518.

24 | Bio-data (Dr. Subodh Wairya)

 74. Monika Jain, Subodh Wairya, “Performance Evaluation of Low Power Dynamic Circuit Using Footed Diode
Domino Logic”, International Journal of Engineering and Computer Science (IJECS), vol.3, no. 10, pp., 1-4, ISSN:
2319-7242 , Oct. 2014.

2013
75. Neeraj Kumar Mishra, Subodh Wairya, “Low Power 32×32 bit Multiplier Architecture based on Vedic
Mathematics Using Virtex 7 Low Power Device”, International Journal Of Research Review In Engineering
Science & Technology, Vol. 2, Issue 2, pp. 34-37, June 2013, ISSN 2278–6643.

2012
76. Subodh Wairya, Rajendra Kumar Nagaria and Sudarshan Tiwari, “Comparative Performance Analysis of XOR-
XNOR Function based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design,” International
Journal of VLSI design & Communication Systems (VLSICS), AIRCC Publication,vol.3, no.2, pp. 221-242, 2012.
ISSN: 0976-1357.
77. Subodh Wairya, Rajendra Kumar Nagaria and Sudarshan Tiwari, “Performance Analysis of High Speed Hybrid
CMOS Full Adder Circuits for Low Voltage VLSI Design,” VLSI Design, Hindawi Publication, vol. 2012, Article
ID 173079, vol. 18 no. 10, pp. 1-18, 2012 DOI: 10.1155/2012/173079 Indexed in SCOPUS

2011
78. Subodh Wairya, Rajendra Kumar Nagaria and Sudarshan Tiwari, “New Design Methodologies for High Speed
Mixed-Mode CMOS Full Adder Circuits,” International Journal of VLSI design & Communication Systems
(VLSICS),AIRCC Publication, vol.2, no.2, pp. 78-98, 2011. ISSN: 0976-1357, DOI: 10.5121/vlsic.2011.2207.
79. Subodh Wairya, Rajendra Kumar Nagaria and Sudarshan Tiwari, “New Design Methodologies for High-Speed
Low-Voltage 1-Bit CMOS Full Adder Circuits,” Journal of Computer Technology and Application (JCTA), David
Publications, vol.2, no. 3, pp. 190-198, 2011.

2010
80. R. K. Nagaria, Rakesh Kumar Singh and Subodh Wairya, “On The New Design of Sinusoidal Voltage Controlled
Oscillators Using Multiplier in CFA based Double Integrator Loop”, Journal of Circuits, Systems and Computers
(JCSC), vol. 19, no. 5, pp. 939-948, July 2010. ISSN: 0218-1266. Indexed in Thomson Reuters (SCIE impact
factor =0.595), https://doi.org/10.1142/S0218126610006542,

2009
81. Sourabh Kamthey, T.N.Sharma, R. K. Nagaria and S. Wairya, “A Novel Design for Testability of Multiple
Precharged Domino CMOS Circuits”, World Applied Sciences Journal (WASJ: Special Issue of Computer & IT),
IDOSI Publication, vol. 7, pp.175-181, ISSN 18184952, 19916426, Dec. 2009.
82. Adarsh Kumar Agrawal, S. Wairya, R.K. Nagaria and S. Tiwari, “A New Mixed Gate Diffusion Input Full Adder
Topology for High Speed Low Power Digital Circuits,” World Applied Sciences Journal (WASJ: Special Issue of
Computer & IT), IDOSI Publication, vol. 7, pp. 138-144, ISSN 18184952, 19916426, Dec. 2009.
83. Shiv Shankar Mishra, S. Wairya, R.K. Nagaria and S. Tiwari, “New Design Methodologies for High Speed Low
Power XOR-XNOR Circuits,” Journal of World Academy of Science, Engineering and Technology (WASET), vol.
55, no. 35, pp. 200-206, July 2009.

25 | Bio-data (Dr. Subodh Wairya)

PUBLICATIONS: CONFERENCE & BOOK CHAPTER
2024

1. Agyenya Anand, Anurag Yadav, Subodh Wairya. “Performance Analysis of Fast & Power Efficient Dynamic
Comparator Topologies”, 2nd International Conference on Device Intelligence Computing and Communication
Technologies (DICCT-2024), Graphic Era University, 15-16 March 2024.
2023
2. P. Gupta, A. Khan and S. Wairya, "Performance Evaluation of Novel Ternary Subtractor Circuits using Double Pass
Transistor Logic," 2023 4th IEEE Global Conference for Advancement in Technology (GCAT), Bangalore, India,
2023, pp. 1-6, doi: 10.1109/GCAT59970.2023.10353379.
3. Archana, S. Singh and S. Wairya, "Dual Source Vertical TFET Channel Overlapped Structure with Enhanced
RF/Analog Performance for Low-Power- Applications," 2023 Second International Conference on Trends in
Electrical, Electronics, and Computer Engineering (TEECCON), Bangalore, India, 2023, pp. 198-203, doi:
10.1109/TEECCON59234.2023.10335835.
4. P. Gupta, A. Khan and S. Wairya, "Performance Analysis of Ternary Full Adder designs using proposed Ternary
3:1 MUX," 2023 Second International Conference on Trends in Electrical, Electronics, and Computer Engineering
(TEECCON), Bangalore, India, 2023, pp. 336-341, doi: 10.1109/TEECCON59234.2023.10335872.
5. Archana, Sheetal Singh Subodh Wairya Design and Analysis of Dual Source Vertical TFET with and without
channel overlapped structure, 1-3rd July 2023 (Micro2023), 10th International Conference on Microelectronics
Circuits and Systems, 2023.Organizer: Applied Computer Technology, Kolkata, West Bengal, Venue: Hotel
Vivanta, Guwahati, Assam, India.
6. A. Saxena, A. Yadav and S. Wairya, "Design Analysis of an Energy-Efficient Low-Power Dynamic Comparator
Using NMOS Based Preamplifier," 2023 14th International Conference on Computing Communication and
Networking Technologies (ICCCNT), Delhi, India, 2023, pp. 1-6, doi: 10.1109/ICCCNT56998.2023.10307939.
7. Sheetal Singh, Subodh Wairya, “Sub-threshold swing analysis for NC-TFET in Low-Power Biomedical
Applications”, 5th IEEE International Conference on Devices for Integrated Circuit (DevIC), 2023 held on 7-8
April, 2023, pp. 1-5, organized by ECE Dept., Kalyani Govt. Engg. College, Nadia, West Bengal, India,
8. Abhinav Saxena, Anurag Yadav and Subodh Wairya, " Design Analysis of 3-Bit Flash ADC using Low-Offset and
Low-Power Opamp," 10th International Conference on Signal Processing and Integrated Networks (SPIN 2023),
pp. 502-597, organized by Amity University, Noida, on March 23-24, 2023. Published in IEEE Xplore Digital
Library. DOI: 10.1109/SPIN57001.2023.10116426
9. Nashra Khalid, Anurag Yadav, Subodh Wairya, “Performance analysis of various fast and low power dynamic
comparators”, 1st International Conference on Intelligent Systems and Smart Infrastructure (ICISSI 2022), jointly
Organised by SIET, Prayagraj IET, Lucknow ,U.P. & Manipal University Jaipur, Rajasthan, on 21-22 May 2022.
pp. 64-72 Intelligent Systems and Smart Infrastructure – Brijesh Mishra et al. (eds) @ 2023 Taylor & Francis
Group, London, ISBN 978-1-032-41287-,0 DOI: 10.1201/9781003357346-9. Book Chapter
10. Kunal Kumar, Anurag Yadav, Subodh Wairya, “Design and Analysis of High speed and Low Power Dynamic
Comparator”, 1st International Conference on Intelligent Systems and Smart Infrastructure (ICISSI 2022), jointly
Organized by SIET, Prayagraj IET, Lucknow ,U.P. & Manipal University Jaipur, Rajasthan, on 21-22 May 2022.
pp. 107-117 Intelligent Systems and Smart Infrastructure – Brijesh Mishra et al. (eds) @ 2023 Taylor & Francis
Group, London, ISBN 978-1-032-41287-0, DOI: 10.1201/9781003357346-13 Book Chapter.
11. Ayushi Kirti Singh, Subodh Wairya, Divya Tripathi, “A Comparative Performance Analysis of QCA Full Adder”,
1st International Conference on Intelligent Systems and Smart Infrastructure (ICISSI 2022), jointly Organized by
SIET, Prayagraj IET, Lucknow ,U.P. & Manipal University Jaipur, Rajasthan, on 21-22 May 2022. pp. 509-517
Intelligent Systems and Smart Infrastructure – Brijesh Mishra et al. (eds) @ 2023 Taylor & Francis Group, London,
ISBN 978-1-032-41287-0, DOI: 10.1201/9781003357346-57. Book Chapter
2022
12. Divya Tripathi, Subodh Wairya, “A Cost Efficient QCA RAM cell for Nanotechnology Applications”, Lecture
Notes in Electrical Engineering , 877, VLSI, Microwave and Wireless Technologies: Select Proceedings of
ICVMWT 2021, pp. 127-138, ISSN 1876-1119, ISBN 978-981-1903113, http://doi.org/10.1007/978-981-19-0312-
0, Springer, Singapore, Book Chapter

26 | Bio-data (Dr. Subodh Wairya)

 13. Anum Khan, Subodh Wairya, “High Performance 3-2 Compressor Using Efficient XOR-XNOR in
Nanotechnology”, Lecture Notes in Electrical Engineering , 877, VLSI, Microwave and Wireless
Technologies: Select Proceedings of ICVMWT 2021, pp. 159-170, ISSN 1876-1119, ISBN 978-981-1903113,
http://doi.org/10.1007/978-981-19-0312-0. Springer, Singapore. Book Chapter
14. Digvijay Pandey, Subodh Wairya, “Performance Analysis of Text Extraction from Complex Degraded Image Using
Fusion of DNN, Steganography and AGSO”, Lecture Notes in Electrical Engineering , 877, VLSI, Microwave
and Wireless Technologies: Select Proceedings of ICVMWT 2021, pp. 195-204, ISSN 1876-1119, ISBN 978-
981-1903113, http://doi.org/10.1007/979-981-19-0312-0. Springer, Singapore. Book Chapter
15. Semba Walli, Jyoti Garg, Subodh Wairya, “Analog and Digital Applications of 4-T Based Memristor Emulator ”,
Lecture Notes in Electrical Engineering , 877, VLSI, Microwave and Wireless Technologies: Select
Proceedings of ICVMWT 2021, pp.183-194, ISSN 1876-1119, ISBN 978-981-1903113,
http://doi.org/10.1007/978-981-19-0312-0. Springer, Singapore. Book Chapter
16. Jyoti Garg, Aishita Verma, Subodh Wairya “ Memristor Emulator Circuits an Emerging Technology with
Applications ”, Lecture Notes in Electrical Engineering , 877, VLSI, Microwave and Wireless Technologies:
Select Proceedings of ICVMWT 2021, pp.467-480, ISSN 1876-1119, ISBN 978-981-1903113,
http://doi.org/10.1007/978-981-19-0312-0. Springer, Singapore. Book Chapter
17. Tripathi, D., Wairya, S. (2022). An Ultra Efficient QCA SRAM Cell for Nanotechnology Applications. In: Dhawan,
A., Mishra, R.A., Arya, K.V., Zamarreño, C.R. (eds) Advances in VLSI, Communication, and Signal Processing.
Lecture Notes in Electrical Engineering, vol 911. Springer, Singapore. https://doi.org/10.1007/978-981-19-2631-
0_35. pp. 393-404, Print ISBN 978-981-19-2630-3, Springer, Singapore, Book Chapter
18. Verma, A., Khan, A., Wairya, S. (2022). Performance Analysis of Vedic Multiplier Using High Performance XOR-
MUX Based Adder for Fast Computation. In: Dhawan, A., Mishra, R.A., Arya, K.V., Zamarreño, C.R. (eds)
Advances in VLSI, Communication, and Signal Processing. Lecture Notes in Electrical Engineering, vol 911.
Springer, Singapore. https://doi.org/10.1007/978-981-19-2631-0_60, pp. 693-705, Print ISBN 978-981-19-2630-3,
Springer, Singapore, Book Chapter
19. Gupta, S., Wairya, S. (2022). Performance Estimation of Different Tunnel Field Effect Transistor Based Biosensors
Used in the Biomedical and Its Future Prospective. In: Dhawan, A., Mishra, R.A., Arya, K.V., Zamarreño, C.R.
(eds) Advances in VLSI, Communication, and Signal Processing. Lecture Notes in Electrical Engineering, vol 911.
Springer, Singapore. https://doi.org/10.1007/978-981-19-2631-0_61, pp. 707-717. Print ISBN 978-981-19-2630-3,
Springer, Singapore, Book Chapter
20. Ayushi Kirti Singh, Subodh Wairya, Divya Tripathi, “A Cell Optimization and Realization of XOR based Logic
Design in QCA”, 5th International Conference on VLSI, Communication & Signal Processing (VCAS-2021), ECE
Department MNNIT, Allahabad, India, Oct. 14-16, 2022.
21. Kunal Kumar, Anurag Yadav and Subodh Wairya, “Design Analysis of Ultra Low Power Charge Sharing Based
High Speed Comparator Topology”, 5th International Conference on VLSI, Communication & Signal Processing
(VCAS-2021), ECE Department MNNIT, Allahabad, India, Oct. 14-16, 2022.
22. Mohd Saqib, Subodh Wairya and Anurag Yadav, “Performance Analysis of Differential Dual stage delay cells of
VCO”, 5th International Conference on VLSI, Communication & Signal Processing (VCAS-2021), ECE
Department MNNIT, Allahabad, India, Oct. 14-16, 2022
23. Garg J., Wairya S. (2022) Performance Evaluation of Full Adder Using Magnetic Tunnel Junction. In:
Mahapatra R.P., Peddoju S.K., Roy S., Parwekar P., Goel L. (eds) Proceedings of International Conference on
Recent Trends in Computing. Lecture Notes in Networks and Systems, vol. 341. Springer, Singapore.
https://doi.org/10.1007/978-981-16-7118-0_44. Springer, Singapore. Book Chapter

24. Verma A, Khan A., Wairya S. (2022) Low-Power High-Performance Hybrid Scalable adder for fast computation.
In: Rawat S., Kumar A., Kumar P., Anguera J. (eds) Proceedings of First International Conference on
Computational Electronics for Wireless Communications. Lecture Notes in Networks and Systems, vol. 329.
Springer, Singapore. https://doi.org/10.1007/978-981-16-6246-1_14 . Book Chapter

25. Tripathi P., Khan A., Wairya S. (2022), Low-Power Shift Registers Using Fully Static Contention Free Single-
Phase Clocked Flip Flop. In: Dhawan A., Tripathi V.S., Arya K.V., Naik K. (eds) Recent Trends in Electronics and
Communication. Lecture Notes in Electrical Engineering, vol. 777. Springer, Singapore.
https://doi.org/10.1007/978-981-16-2761-3_44.Book Chapter

27 | Bio-data (Dr. Subodh Wairya)

 26. Tripathi S., Khan A., Wairya S. (2022), Performance Evaluation of Master–Slave D Flip Flop Based on Charge
Retention Feedback Pass Transistor Logic in Nanotechnology. In: Dhawan A., Tripathi V.S., Arya K.V., Naik K.
(eds) Recent Trends in Electronics and Communication. Lecture Notes in Electrical Engineering, vol 777. Springer,
Singapore. https://doi.org/10.1007/978-981-16-2761-3_38. Book Chapter

27. Tripathi D., Wairya S. (2022), A Cost-Efficient QCA XOR Function Based Arithmetic Logic Unit for
Nanotechnology Applications. In: Khanna A., Gupta D., Bhattacharyya S., Hassanien A.E., Anand S., Jaiswal A.
(eds) International Conference on Innovative Computing and Communications. Advances in Intelligent Systems
and Computing, vol 1388. Springer, Singapore. https://doi.org/10.1007/978-981-16-2597-8_9 . Book Chapter

28. Garg J., Wairya S. (2022) STT-MRAM A Universal Memory from Device to Circuit. In: Bansal R.C., Agarwal
A., Jadoun V.K. (eds) Book Chapter Advances in Energy Technology. Lecture Notes in Electrical Engineering, vol
766. Springer, Singapore. https://doi.org/10.1007/978-981-16-1476-7_60, pp. 673-681, .https://doi.org/10.1007/
978- 981-16-1476-7.(Published & Indexed in SCOPUS) Book Chapter

2021
29. N. Rai, A. Yadav and S. Wairya, "Design of a High Speed and Low Power Charge Shared Based Dynamic
Comparator for ADC Application," 2021 First International Conference on Advances in Computing and Future
Communication Technologies (ICACFCT), 2021, pp. 125-130, doi: 10.1109/ICACFCT53978.2021.9837362.
Published in IEEE Xplore Digital Library
30. Divya Tripathi, Subodh Wairya, “An Ultra Efficient QCA SRAM Cell for Nanotechnology Applications”, 4th
International Conference on VLSI, Communication & Signal Processing (VCAS-2021), ECE Department MNNIT,
Allahabad, India, Sept. 24-26, 2021. Lect. Notes Electrical Eng., Vol. 911, Amit Dhawan et al. (Eds): Advances
in VLSI, Communication, and Signal Processing, 978-981-19-2630-3, 521219_1. Book Chapter
31. Aishita Verma, Anum Khan and Subodh Wairya, “Performance Analysis of Vedic multiplier using High
Performance XOR-MUX based adder for Fast Computation”, 4th International Conference on VLSI,
Communication & Signal Processing (VCAS-2021), ECE Department MNNIT, Allahabad, India, Sept. 24-26,
2021. Lect. Notes Electrical Eng., Vol. 911, Amit Dhawan et al. (Eds): Advances in VLSI, Communication,
and Signal Processing, 978-981-19-2630-3, 521219_1_En, (Chapter 60). Book Chapter
32. Shilpi Gupta and Subodh Wariya, “Performance Estimation of Different Tunnel Field Effect Transistor Based
Biosensors used in the Biomedical and its Future Prospective” 4th International Conference on VLSI,
Communication & Signal Processing (VCAS-2021), ECE Department MNNIT, Allahabad, India, Sept. 24-26,
2021. Lect. Notes Electrical Eng., Vol. 911, Amit Dhawan et al. (Eds): Advances in VLSI, Communication,
and Signal Processing, 978-981-19-2630-3, 521219_1. Book Chapter
33. D. Tripathi and S. Wairya, "A Cost Efficient QCA Compressor Topologies for Fast Nano Computing
Applications," 2021 8th International Conference on Signal Processing and Integrated Networks (SPIN), 2021, pp.
1024-1029, doi: 10.1109/SPIN52536.2021.9565997, organized by Amity University, Noida, on 26-27 August 2021.
Published in IEEE Xplore Digital Library
34. Yadav, N. Rai, A. Verma and S. Wairya, "Design of Flash ADC using low offset comparator for analog signal
processing application," 2021 8th International Conference on Signal Processing and Integrated Networks (SPIN),
2021, pp. 76-81, doi: 10.1109/SPIN52536.2021.9566050, organized by Amity University, Noida, on 26-27 August
2021. Published in IEEE Xplore Digital Library
35. A Khan and S. Wairya, "An Efficient ALU Architecture Topology for Nanotechnology Applications," 2021 8th
International Conference on Signal Processing and Integrated Networks (SPIN), 2021, pp. 784-789, doi:
10.1109/SPIN52536.2021.9566043, organized by Amity University, Noida, on 26-27 August 2021. Published in
IEEE Xplore Digital Library
36. S. Gupta and S. Wariya, "Performance analysis of different Tunnel Field Effect Transistors (TFET) device
structures with their Challenges," 2021 8th International Conference on Signal Processing and Integrated Networks
(SPIN), 2021, pp. 790-795, doi: 10.1109/SPIN52536.2021.9566097, organized by Amity University, Noida, on 26-
27 August 2021. Published in IEEE Xplore Digital Library
37. D. Tripathi and S. Wairya, "An Energy Dissipation and Cost Optimization of QCA Ripple Carry Adder," 2021 8th
International Conference on Signal Processing and Integrated Networks (SPIN), 2021, pp. 760-765, doi:
10.1109/SPIN52536.2021.9566068., organized by Amity University, Noida, on 26-27 August 2021. Published in
IEEE Xplore Digital Library

28 | Bio-data (Dr. Subodh Wairya)

 38. D. Tripathi and S. Wairya, "An Efficient QCA Vedic Multiplier for Nanotechnology Applications," 2021
International Conference on Intelligent Technologies (CONIT), 2021, pp. 1-6, doi:
10.1109/CONIT51480.2021.9498464, Organized by The KLE Institute of Technology, Hubballi, Kartakata , India,
25-27 June, 2021. Published in IEEE Xplore Digital Library
39. Aishita Verma, Anum Khan and Subodh Wairya, “Low-Power high performance Hybrid Scalable Full Adder for
Fast Computation”, International Conference On Computational Electronics for Wireless Communication (ICCWC-
2021), NIT, Kurukshetra, India, 11-12 June. 2021.
40. Jyoti Garg, Subodh Wairya “ Performance Evaluation of Full Adder using Magnetic Tunnel Junction ”,
International Conference on Recent Trends in Computing (ICRTC 2021), Department of Computer Science
Engineering, SRM Institute of Science and Technology Delhi-NCR Campus, Ghaziabad, India, 4-5 June. 2021.
41. S. Walli, S.R.P. Sinha and Subodh Wairya, "Performance Improvement and Comparative Analysis of Memristive
Emulator Networks," 2021 2nd International Conference for Emerging Technology (INCET), 2021, pp. 1-7, doi:
10.1109/INCET51464.2021.9456289. Belguam, Karnataka,, India, 21-23 May 2021. Published in IEEE Xplore
Digital Library.
42. Divya Tripathi, Subodh Wairya, “A Cost Efficient QCA RAM cell for Nanotechnology Applications”, International
Conference On VLSI & Microwave and Wireless Technologies (ICVMWT-2021), MMMTU, Gorakhpur, India,
20-21 March. 2021.
43. Anum Khan, Subodh Wairya, “High Performance 3-2 Compressor Using Efficient XOR-XNOR in
Nanotechnology”, International Conference on VLSI & Microwave and Wireless Technologies (ICVMWT-2021),
MMMTU, Gorakhpur, India, 20-21 March. 2021.
44. Digvijay Pandey, Subodh Wairya, “Performance Analysis of Text Extraction from Complex Degraded Image Using
Fusion of DNN, Steganography and AGSO”, International Conference On VLSI & Microwave and Wireless
Technologies (ICVMWT-2021), MMMTU, Gorakhpur, India, 20-21 March. 2021.
45. Semba Walli, Jyoti Garg, Subodh Wairya, “Analog and Digital Applications of 4-T Based Memristor Emulator ”,
International Conference On VLSI & Microwave and Wireless Technologies (ICVMWT-2021), MMMTU,
Gorakhpur, India, 20-21 March. 2021.
46. Jyoti Garg, Aishita Verma, Subodh Wairya “ Memristor Emulator Circuits an Emerging Technology with
Applications ”, International Conference On VLSI & Microwave and Wireless Technologies (ICVMWT-2021) ,
MMMTU, Gorakhpur, India, 20-21 March. 2021.
47. Tripathi D., Wairya S. (2022) A Cost-Efficient QCA XOR Function Based Arithmetic Logic Unit for
Nanotechnology Applications, 4th International Conference on Innovative Computing and Communication (ICICC-
2021), Shaheed Sukhdev College of Business Studies, University of Delhi, New Delhi, India, 20-21 Feb. 2021.
Book Chapter In: Khanna A., Gupta D., Bhattacharyya S., Hassanien A.E., Anand S., Jaiswal A. (eds)
International Conference on Innovative Computing and Communications. Advances in Intelligent Systems and
Computing, vol 1388. Springer, Singapore. https://doi.org/10.1007/978-981-16-2597-8_9
48. D. Tripathi and S. Wairya, "A Cost-Efficient QCA XOR-XNOR Topology for Nanotechnology Applications," 2021
International Conference on Computing, Communication, and Intelligent Systems (ICCCIS), 2021, pp. 911-916,
doi: 10.1109/ICCCIS51004.2021.9397215, School of Engineering and Technology, Sharda University, Greater
Noida, India, 19-20 Feb. 2021. Published in IEEE Xplore Digital Library
49. Tripathi D., Wairya S. (2021) A Cost-Efficient Magnitude Comparator and Error Detection Circuits for Nano-
Communication. In: Suma V., Chen J.IZ., Baig Z., Wang H. (eds) Book Chapter Inventive Systems and Control.
Lecture Notes in Networks and Systems, vol 204. Springer, Singapore. https://doi.org/10.1007/978-981-16-1395-
1_19, 5th International Conference on Inventive Systems and Control, (ICISC-2021) ECE Department, JCT
College of Engineering and Technology, Coimbatore, India, 7-8 January 2021. https://link.springer.
com/chapter/10.1007/978-981-16-1395-1_19. DOI: 10.1007/978-981-16-1395-1_19 (Indexed in SCOPUS)

2020
50. S. Kidwai, D. Tripathi and S. Wairya, “Design of Full Adder with Self Checking Capability using Quantum Dot
Cellular Automata”, Book Chapter, Advances in VLSI, Communication, and Signal Processing Lecture Notes in
Electrical Engineering book series (LNEE), Vol. 587, pp. 719-731, (2020), (Springer), DOI: 10.1007/978-981-
32-9775-3_66, Series ISSN: 1876-1100, .(Published & Indexed in SCOPUS)
51. Divya Tripathi, Sana and Subodh Wairya, “Cell Optimization and Realization of MGDI QCA based Combinational
Logic Circuits for Nanotechnology Applications”, 17th IEEE International Conference on VLSI, Communication &

29 | Bio-data (Dr. Subodh Wairya)

 Signal Processing (INDICON- 2020), Netaji Subhas University of Technology, (NSIT), Delhi, 11-13 December,
2020. Published in IEEE Xplore Digital Library
52. Garg J., Wairya S., STT-MRAM A Universal Memory from Device to Circuit. 1st International Conference on
Energy, Materials Sciences & Mechanical Engineering (EMSME) 2020, National Institute of Technology (NIT),
Delhi, October 30–November 1, 2020 pp. 673-681 .

53. Garg J., Wairya S. (2021) Performance Evaluation of Logic Gates Using Magnetic Tunnel Junction. In: Gopi
E.S. (eds)) Book Chapter Machine Learning, Deep Learning and Computational Intelligence for Wireless
Communication. Lecture Notes in Electrical Engineering, vol 749. Springer, Singapore. https://doi.org/10.1007/
978-981-16-0289-4_23, https://link.springer.com/chapter/10.1007/978-981-16-0289-4_23, National Institute of
Technology (NIT), Tiruchirappalli, October 22-24, 2020. https://link. springer.com/chapter/10.1007/978-981-16-
0289-4_23. DOI: 10.1007/978-981-16-0289-4_23(Published & Indexed in SCOPUS)

54. Sweta Tripathi, Anum Khan and Subodh Wairya, “Performance Evaluation of Charge Retention Feedback Pass
Transistor Logic based Master Slave D Flip Flop in NanoTechnology”, 3rd International Conference on VLSI,
Communication & Signal Processing (VCAS 2020), MNNIT, Allahabad, October 9-11, 2020.
55. Priti Tripathi, Anum Khan and Subodh Wairya, “Low Power Shift Registers using Fully Static Contention Free
Single-Phase Clocked Flip-Flop”, 3rd International Conference on VLSI, Communication & Signal Processing
(VCAS 2020), MNNIT, Allahabad, October 9-11, 2020.
56. Divya Tripathi and Subodh Wairya, “An Efficient Ripple Carry Adder for Nanotechnology Applications with
Energy Dissipation Study”, Presented in 3rd International Conference on VLSI, Communication & Signal
Processing (VCAS 2020), MNNIT, Allahabad, October 9-11, 2020.

2019
57. Prashasti, Jaiswal S., Khan A., Wairya S. (2021) Design and Performance Evaluation of Highly Efficient Adders in
Nanometer Technology. In: Harvey D., Kar H., Verma S., Bhadauria V. (eds) Book Chapter Advances in VLSI,
Communication, and Signal Processing. Lecture Notes in Electrical Engineering, vol. 683. Springer, Singapore.
https://doi.org/10.1007/978-981-15-6840-4_20. 2nd International Conference on VLSI, Communication & Signal
Processing (2nd VCAS-2019), ECE Department MNNIT, Allahabad, October 21-23, 2019. (Published & Indexed
in SCOPUS).
58. Jaiswal S., Prashasti, Khan A., Wairya S. (2021) Performance Evaluation of Energy-Efficient Adiabatic Logic
Circuit-Based Multiplexer for Low Power Applications. In: Harvey D., Kar H., Verma S., Bhadauria V. (eds) Book
Chapter Advances in VLSI, Communication, and Signal Processing. Lecture Notes in Electrical Engineering, vol.
683. Springer, Singapore. https://doi.org/10.1007/978-981-15-6840-4_19. 2nd International Conference on VLSI,
Communication & Signal Processing (2nd VCAS-2019), ECE Department MNNIT, Allahabad, October 21-23,
2019. (Published & Indexed in SCOPUS)
2018
59. Raj Vikram Singh, Subodh Wariya, Javed Ahmad & Balendu Bhushan Pandey, “To conceal and secure digital data
for intellectual property right in Medical Images using DCT and DWT in Watermarking Technique”,4 th
International Conference on “Challenges & Opportunities For Technological Innovation In India”, Feb. 2018, pp.
311-316 Organized by Ambalika Institute of Management & Technology, Lucknow (AIMT), sponsored GJSER.
ISSN No. 2348-8034.
60. Ritesh Singh, Neeraj Kumar Misra, Subodh Wairya, Bandan Boi, “Implementation of Non-restoring Reversible
Divider Using a Quantum-Dot Cellular Automata” In: Behera H., Nayak J., Naik B., Abraham A. (eds) 4th
International Conference on Computational Intelligence in Data Mining (ICCIDM-2017). Advances in Intelligent
Systems and Computing, Springer, Singapore, vol. 711, pp. 459-469, 04 July 2018, Online ISBN: 978-981-10-
8055-5, DOI: 10.1007/978-981-10-8055-5_41.

2017
61. Neeraj Kumar Misra, Bibhash Sen, Subodh Wairya, Bandan Boi, “Novel parity preserving reversible Binary-to-
BCD code converter with testability of building blocks in quantum circuit.”, In: Bhateja V., Tavares J., Rani B.,
Prasad V., Raju K. (eds) Proceedings of the Second International Conference on Computational Intelligence and
Informatics. Advances in Intelligent Systems and Computing, Springer, Singapore, vol. 712, pp. 383-393, 24 July
2018, Online ISBN: 978-981-10-8228-3, DOI: 10.1007/978-981-10-8228-3_35. Indexed in SCOPUS

30 | Bio-data (Dr. Subodh Wairya)

 62. Neeraj Kumar Misra, Subodh Wairya, V. K. Singh., “Optimized Approach for Reversible Code Converters Using
Quantum Dot Cellular Automata”. In: Das S., Pal T., Kar S., Satapathy S., Mandal J. (eds) Proceedings of the 4th
International Conference on Frontiers in Intelligent Computing: Theory and Applications (FICTA),Advances in
Intelligent Systems and Computing, Springer, Vol 404. pp. 367-378, Print ISBN 978-81-322-2693-2, Online ISBN
978-81-322-2695-6, 2016.
63. Raj Vikram Singh, Subodh Wairya,“ Review of Energy–Efficient Biometric Authentication System” International
Conference on “Innovative Entrepreneurship and Startup”, Organized by KNIT Sultanpur, Uttar Pradesh, March
2017, page no.311-316, WB-TEQIP-II. ISBN No 978-93-86256-55-3

2016
64. Raj Vikram Singh, Subodh Wairya,“ Robust Information Hiding Technique for Image security In Open channel”
International Conference on “International Conference of Advance Computational Techniques in Information and
Communication Technology “ ICACTICT”,23-24 September 2016, Organized by Department of Electronics
Engineering, KNIT Sultanpur, Uttar Pradesh, WB-TEQIP-II. ISBN No 978-93-86256-00-33
65. Shraddha Pandey, Sonali Singh and Subodh Wairya, “QCA Implementation Of XOR Based Full Adder Circuit
Using Clock-Zone Based Crossover” in National Conference Emerging Trends in Electrical & Electronics
Engineering (NCETEEE’16),Organized by Department of Electrical Engineering & Department of Electronics &
Communication Engineering, Institute of Engineering & Technology, Lucknow, 19-20 August, 2016.
66. Shashank Gupta and Subodh Wairya, “Gate Diffusion Input (GDI): A Technique for Enhancing Performance of the
Arithmetic Circuit” National Conference Emerging Trends in Electrical & Electronics Engineering
(NCETEEE’16),Organized by Department of Electrical Engineering & Department of Electronics &
Communication Engineering, Institute of Engineering & Technology (IET), Lucknow, 19-20 August, 2016.
67. Neeraj Kumar Misra, Subodh Wairya, V. K. Singh, “Optimized Approach for Reversible Code Converters Using
Quantum Dot Cellular Automata”, Advances in Intelligent Systems and Computing, Springer. vol. 404, Book Part:
Part VIII, Swagatam Das, et al., Eds., ed: 2016, pp. 367-378, 25 October 2015, Print ISBN: 978-81-322-2693-2,
Online ISBN: 978-81-322-2695-6, DOI: 10.1007/978-81-322-2695-6_31, Indexed in SCOPUS

2014
68. Neeraj Kumar Misra, Subodh Wairya, Vinod Kumar Singh, “An Inventive Design of 4*4 Bit Reversible NS Gate”,
IEEE International Conference on Recent Advances and Innovation in Engineering (ICRAIE-2014), pp. 1-6, 2014,
Electronic ISBN: 978-1-4799-4040-0, DOI: 10.1109/ICRAIE.2014.6909323. Published in IEEE Xplore Digital
Library
69. Ravi Prakash Verma, Subodh Wairya, Prateek Gargeya and Mohd. Irshad Khan, “Designing Microstrip Band-pass
Filter at 6 GHz” Paper presented in TEQIP-II Sponsored National Conference on Advances in Computer
Communication and Embedded Systems,21-22 March2014, organized by Department of Electronics and
Communication Engineering of M.M.M University of Technology, Gorakhpur, U.P., India.

2013
70. Deepa Rana and Subodh Wairya, “Robust High Speed Full Adder Design For Low Power VLSI Design,” 2nd
International Conference on Emerging Trends in Engineering & Technology, College of Engineering, Teerthanker
Mahaveer University, April12-13, 2013.

2011
71. Subodh Wairya , Garima Singh, Vishant, R. K. Nagaria and S. Tiwari, “Design Analysis of XOR (4T) based Low
Voltage CMOS Full Adder circuit,” IEEE Proc. International Conference on Current Trends In Technology
(NUiCONE–2011), Institute of Technology, Nirma University, Ahmedabad, India, pp. 1-7, December 2011,
DOI: 10.1109/NUiConE.2011.6153275, Print ISSN: 2375-1282. Published in IEEE Xplore Digital Library
72. Subodh Wairya, Pankaj Kumar Tripathi, Rajendra Kumar Nagaria and Sudarshan Tiwari, “Novel Design
Topologies for MOSCAP Majority Function Full Adder cells,” Proc. International Conference on Frontiers of
Computer Science (ICFoCS-2011), Atria Institute of Technology, IISC Bangalore, India, pp. 55, August 2011.
73. S. Wairya, V. Narendar, R. K. Nagaria and S. Tiwari, “Design of High-Performance CMOS 1-Bit Full Adder
Circuits for VLSI Application,” Proc. International Conference on Advances in Electrical & Electronics
Engineering, (ICAEEE–2011), MIT, Moradabad, India, pp. 37-38, February 2011.

2010
31 | Bio-data (Dr. Subodh Wairya)
 74. S. Wairya, P. K. Tripathi, V. Narendar, R. K. Nagaria and S. Tiwari, “A New High Performance Adder-Cell
Design and Analysis with minimum Transistors,” Proc. International Conference on Current Trends In
Technology,(NUiCONE–2010), Institute of Technology, Nirma University, Ahmedabad, India, pp 1-6, December
2010.
75. S. Wairya, Himanshu Pandey, R. K. Nagaria and S. Tiwari, “Ultra Low Voltage High Speed 1-Bit CMOS Adder,”
IEEE Proc. International Conference on Power, Control and Embedded Systems, (ICPCES 2010), M.N.N.I.T,
Allahabad, India, pp. 1-6, November - December 2010, DOI: 10.1109/ICPCES.2010.5700479.
76. S. Wairya, R. K. Nagaria and S. Tiwari, “New Design Methodologies for High Speed Low-Power 1-Bit CMOS Full
Adder Circuits,” Proc. International Conference on Advances in Information, Communication Technology and
VLSI Design, (ICAICV-2010), Coimbatore, India, pp. 1-6, August 2010.
77. S. Wairya, R. K. Nagaria and S. Tiwari, “A Novel CMOS Full Adder Topology for Low Voltage VLSI
Applications,” IEEE Proc. International Conference on Emerging Trends in Signal Processing & VLSI Design
‘SPVL-2010’, Hyderabad, India, pp. 1142-1146, June 2010.
78. S. Wairya, V. Narendar, R. K. Nagaria and S. Tiwari, “Comparative Study of High–Speed Full adder Circuits for
Low Voltage,” IEEE Proc. International Conference on Recent Advances in e-Communication and i-Technology,
(REACT’10), Anand Institute of Higher Technology, Chennai, India, pp. 90, April 2010.

2009
79. Rakesh Kumar Singh, Shardul Verma, S. Wairya & R. K. Nagaria “Realization of CFA Based Analog Wave
Processors” National Conference titled “Cutting Edge Computer and Electronics Technology, (CECET09),
organized by Department of Computer Engineering & Electronics & Communication Engineering, College of
Technology, G.B.Pant University of Agriculture and Technology Pantnagar (Uttarakhand), India held on Feb 14-16
2009, pp. 537-541.
2008
80. Neelam Srivastava, Subodh Wairya & Sanjay Singh “Nano-Materials revolutionized the world of Electronic
Technology”, National Conference on “Advanced Materials” Organized by Department of Chemistry, Uday
Pratap Autonomous College, Varanasi, India, from 6-8th March 2008.
2007
81. Neelam Srivastava & Subodh Wairya, “Vision of Next Generation Networks: Architecture, Implementation and
Services” National Conference Titled “Emerging Technologies and Trends in IT 2007 (NCET 2007)” organized
by Depart. of IT, Institute of Technology & Science (ITS), Ghaziabad held on April 06-07 2007, pp. 253-263.

82. Subodh Wairya & Neelam Srivastava “Usage Scenarios with Wi-Max for Mobile/High Speed Portable Broad band
Data services Application ”, Zonal Seminar titled “Wireless for Broad Band & Multimedia Communication: A
Global Perspective” on Organized by IETE, Lucknow Center, Lucknow held on 23rd -24th February 2007, pp. 63-
71.
2005
83. Subodh Wairya & Neelam Srivastava “An Overview of Dense Wavelength Division Multiplexing in Optical
Networking”, National Seminar on “Future Broadband, Wireless and Mobile Communication” on Organized by
IETE Lucknow Center, Lucknow held on 11th -12th March 2005.

84. Subodh Wairya & Neelam Srivastava. “Wi-Fi why needed and how implemented” Conference organized by IIIT
Allahabad, held on 5-6 March, 2005.
1998
85. M. S. Singh & Subodh Wairya “Computer Application in Simulation Study of Electric Drives”, Eighth Annual
Conference of Vijnana Parishad of India with Special Theme on Computer Applications in Mathematics, Science
and Engineering, Organized by Institute of Engineering and Technology (IET), Lucknow-21, Held on 15-17 Dec
1998.

32 | Bio-data (Dr. Subodh Wairya)

 BIBLIOGRAPHY

Dr. Subodh Wairya is a Professor, Head of Department of Electronics

and Communication Engineering Department (NBA Accredited) at Institute of
Engineering & Technology, (I.E.T) Lucknow, Uttar Pradesh, India. He received
Doctoral degree from Motilal Nehru National Institute of Technology (MNNIT)
Allahabad, India, Master of Engineering (Telecommunication) degree from
Jadavpur University, Kolkata and the B.Tech (Electronics Engineering) degree
from H.B.T.I., Kanpur, India. He has more than Twenty Nine years
experience in teaching and research. He has served as Scientist “B” in
Defense Research & Development Organization (DRDO) and Graduate
Engineer (Design Project) in Hindustan Aeronautical Limited (HAL), Lucknow
from 1994 to 1996. He has published more than 150 National and
International papers in various Journal and Conference of repute. He guided
(supervised) 5 PhD Thesis and more than 40 M.Tech dissertations (Thesis). Dr.
Subodh Wairya is actively associated with membership for Professional
Societies as Life time member of Institute of Engineers (IE), Institute of
Electrical and Telecommunication Engineering (IETE) and Indian Society for
Technical Education (ISTE). He also served as Dean, Undergraduate Studies
and Entrepreneurship (UGSE) & Convener Virtual Lab Cell for Dr. A.P.J.
Abdul Kalam Technical University, Uttar Pradesh, Lucknow. His Current
research interests are QCA, Nano Memories, High Speed Network, Image
Processing, VLSI Circuits and Analog System design & Image Processing.

33 | Bio-data (Dr. Subodh Wairya)