Digital Design and Computer Organization BCS302

Syllabus
Semester 3
DigitalDesign and Computer Organization
Course Code BCS302 CIE Marks 50
SEE Marks 50
Teaching Hours/Week (L:T:P:S) 3:0:2:0 Total Marks 100
Total Hours of Pedagogy 40 hours Theory +20 Hours of Practicals
Credits 04 Exam Hours 3

Examination nature (SEE)Theory

PRACTICAL COMPONENT OF IPCC

sBmulate the
1. Given a 4-variable logic expression, simplify it using appropriate technique and
sameusing basic gates.
2. Design a 4 bit fulladder and subtractor and simulate the same using basic gates.

3. Design Verilog HDL to implement simple circuits using structural, Data flow and
Behavioural model.

Adder, Half and

4. Design Verilog HDL to implement Binary Adder-Subtractor - Half and Full
Full Subtractor

5. Design Verilog HDL to implement Decimal adder.

6. Design Verilog program to imnplement Different types of multiplexer like 2:1, 4:1 and 8:1.

7. Design Verilog program to mplement types of De-Multiplexer.

8. Design Verilog program for implementing various types of Flip-Flops such as SR, IK and D.
Course outcomes (Course Skill Set):
At the end of the course, the student willbe able to
CO1 Apply the K-Map techniques to simplify various Boolean expressions.
C02: Desgn difterent types of combinational and sequentialcircuits along with Verilog
programs.
cO3 Describe the fundamentals of machine instructions, addressing modes and Processor
performance
C04 Explan the approaches involved in achieving communication between processor and
/o devices
c05 Analyzeinternal Organization of Memory and Impact of cache/Pipelining on Processor
erforThance
 Digital Design and Computer Organization BCS302

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
The minimumpassing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the
SEE minimum passing mark is 35% of the maximum marks (18 out of 50 marks). A student shall be
deemed to have satisied the academic requirements and earned the credits allotted to each subject/
courseif the student secures a minimum of 40% (40marks out of 100) in the sum total of the CIE
(Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.
CIE for the theory component of the IPCC (maximum marks 50)
" IPCC means practical portion integrated with the theory of the course.
CIE marks for the theory component are 25 marks and that for the practical component is 25
marks.
25 marks for the theory component are split into 15 marks for two Internal Assessment T'ests (Two
Tests,each of 15 Marks with 01-hour duration, are to be conducted) and 10 marks for other
assessment methods mentioned in 220B4.2. The first test at the end of 40-50% coverage of the
syllabus hnd the second test after covering 85-90% of the syllabus.
" Scaled-down marks of the sum of two tests and other assessment methods will be CIE marks for the
theory component of IPCC (that is for 25 marks).
" The student has to secure 40% of 25 marks to qualify in the CIE of the theory component of IPCC.
CIE for the practicalcomponent of the IPCC
" 15 marks for the conduction of the experiment and preparation of laboratory record, and 10 marks
for the test to be conducted after the completion of all the laboratory sessions.
" On completion of every experiment/program in the laboratory, the students shall be evaluated
including viva-voce and marks shall be awarded on the same day.
" The CIE marks awarded in the case of the Practicalcomponent shall be based on the continuous
evaluation of the laboratory report. Each experiment report can be evaluated for 10 marks. Marks of
all experiments' write-ups are added and scaled down to 15 marks.
" The laboratory test (duration 02/03 hours) after completion of all the experiments shall be
conducted for 50 marks and scaled down to 10 marks.
"Scaled-down marks of write-up evaluations and tests added willbe CIE marks for the laboratory
component of IPCC for 25 marks.
.The student has to secure 40% of 25 marks to qualify in the CIE of the practical component of the
IPCC.

SEE for IPCC

Theory SEE willbe conducted by University as per the scheduled timetable, with common question
papers for the course (duration 03 hours)
1.The question paper willhave ten questions. Each question is set for 20 marks.
2. There willbe 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 sub-questions), should have a mix of topics under that module.
3. The students have to answer 5 full questions, selecting one full question from each module.
4. Marks scored by thestudent shall be proportionally scaled down to 50 Marks
The theory portion of the IPCC shall be for both CIE and SEE, whereas the practical portion wil
have a CIE component only. Questions mentioned in the SEE paper may includequestions from
the practical component.
 BCS302
Digital Design and Computer Organization
CONTENTS

Name of Experiments
Page No.
S. No.

using appropriate
Given a 4-variable logic expression,simplify it
1
1
technique and simulate the same using basic gates.
and simulate the same using 3
Design a 4-bit fulladder and subtractor
2
basic gates.
simple circuits using structural, 14
3
Design Verilog HDL to implement
model.
Data flow and Behavioural

Binary Adder-Subtractor - Half and 17

4
Design Verilog HDL to implement
Subtractor.
FullAdder, Half and Full
25
Decimal adder.
5 Design Verilog HDL to implement
Different types of multiplexer 26
Design Verilog program to implement
6 like 2:1, 4:1 and 8:1.

32
of De-Multiplexer.
7 Design Verilog program to implement types

various types of Flip-Flops

Design Verilog program for implementing 39
such as SR, JK and D.

Steps To Be Followed for Executing 46

The Verilog Programs Using Xilinx Software
62
10 Viva Questions
 BCS302
Digital Design and Computer Organization
1.Given a4-variable logicexpression, simplify it using appropriate
technique and simulate the same using basic gates.
We can minimize Boolean expressions of 3, 4 variables very easily using K-map without
Product (SOP) and
using any Boolean algebra theorems. K-map can take two forms Sum of
but
Product of Sum (POS)according to the need of problem. K-map is table like representationthen
K-map with O's and 1's
it gives more information than TRUTH TABLE. We fill grid of
solves it by making groups.
Components Required:
1. NOT Gate 74042 Nos
2 AND Gate 7408---2 Nos
3 OR Gate 7432--- 2 Nos
4 Digital trainer kit
5. Patch Chords
F(ABCD)=)m (1,3,4,6,8,9,11,13,15) + d(0,2,14)
CD
AB CD| CD CD

AB X 4 X
2

AB 1
6
5

AB 1 1 X
13 i5

AB 1
10
8

F(ABCD)=A'D' + B'C'+B'D+AD OR F(ABCD)=A'D' + B'C'+A'B'+AD

Truth Table to be Verified: -
Decimal
SL NO Value MINTERMSm terms A BCD A'B'C'D' AD B'C B'D AD F(ABCD)=A'D'+B'C'+8'D+AD
1 -A'B'CD
oooo m0 oo01
ooo oo
o oo
oo1o o
ooo 1
1 o o 1H o o 0

2 A'B'C'D m1 0011 1 0 0 0

3 A'B'CD' m2 00 101 1 0 1 1 1 0 1
4 3 A'B'CD m3 0 0 11|1 1 00 0 1 0
5 4 A'BC'D' m4 1|0 01 0 1 1 0
6 5 A'BC'D m5 0 1 loooooolooo
01| 0 0 0 0

7 6 A'BCD' m6 01 0O 1 0
8 A'BCD m7 1 1 1 0O0 0 0
9 A'B'C'D' m8 1 00 1 1 1 1 1 0 1
10 9 AB'C'D m9 1 10 1 1 0 1 1
11 10 AB'CD m10 1 0 1 00 1 01 0
12 11 AB'CD m11 1 01 10 1 00 0 1
13 12 ABCD' m12 0000 1 0
14 13 ABC'D m13 010 0 1
15 14 ABCD' m14 1 1 o1
16 15 ABCD m15 1 1 10oo0 1
 BCS302
Digital Design and Computer Organization

module plverilog(a,b,c,d,y);
inputa;
input b;
input c;
input d;
output y;

reg y;

always @ (a, b,c,d)

begin
y=(~a &~d) |(~b &~c) | (~b &d) | (a &d);
end

endmodule

OUTPUT:

/plveriog/d

sipnals

EdR vew wndow

Sim /p1 verdoc

S1 939 ps

O ps to 1412096 ps
Slart
 BCS302
Digital Design and Computer Organization
2. Design a4-bit full adder and subtractor and simulate the same using
basicgates.

Full adder

BOOLEAN EXPRESSIONS:

sum= A B C

Hull adode
Sun= AOB c
Bai
To be implkmentd ainT
A
O)
(RB+AE)e +(76+AB)

+ AB+A B

A8 +AB
(a+).(7+a))et
ABE+ ABe
Sun AB+ABLt

carry=AB+ BC+ AC
TRUTH TABLE:

INPUTS
2 OUTPUTS
A B C Sum carry
0 0

0 |---
1

1 0 0

1
1 1 1

1 1
 BCS302
Digital Design and Computer Organization
IMPLEMENTATION OF FUL ADDER USING BASIC GATES :

SU

CARRY

C
PA FAo
FA FA

Full adder: -
Step 1
module p2updated (a,b,sum,carry,c);

input [3:0] a;
input (3:0]b;
output [3:0] sum;
output carry;
 Digital Design and Computer Organization BCS302

input c;
wire c1,c2,c3;

fa FAO(sum[0],c1, a[0],b[0],c);:
fa FA1(sum[1],c2,a[1],b[1],c1);
fa FA2(sum[2],c3,a[2],b[2],c2);:
fa FA3(sum[3],carry,a[3],b[3],c3);
endmodule
Xilinx -Project Navigator - C:\Copyofp2up datedp2updated. npl [p2updaled.v]
Fle Edr View Project Source Process Wndow Help

13module p2updated (a,b,sm, carry, c) :

Socesn Project input [3:0) a;
papdaled input [3:0) b:
a Ato KaI30004-" 4 output [3:0) sn;
D papdeted (p2updated v) output carry:
la (lav) input c:

uire cl, c2,c3

c3:
10 fa FAO (sun[0), c1, a[0) ,b[0),c):
fa FA1 (sn[ 1), c2,a[ 1] ,b[1] , c1) :
11

12
ta FAZ (sum[2) , c3,a[2) ,b[2]) , c2) :
13
ta FA3 (sum[3),carry, a[3) ,b[3), c3):
14 enduodule

BModte iew Snaptht View h o y View 1

47

Procettes for Source "p2updated

Desion Entry Utties
Cieate Schematc Smbol
Lounch ModeSim Simuato
View Command Line Log Fle
View Verkog Instantiabon Templat
User Constiars
Create Tning Constarts
Assign Pchoge Pins
Eda Constrants (Text)
Implement Design
<.|
| Dp2updated v lav
Process Vie

Simlator"
Launchng Apphcathon lor proces "Launch ModeSm

hConsoleFrdin Flet ninguErorn

Ln 17 Col 34
Process launch ModetSm STUator s p to date.

start

Step 2 (create the file fa.v under the main module p2updated.v)
i)right click on main module p2updated.v
ii)select new source ->Verilog module ->enter file name as fa.v
ii)fa.v sub module gets created under the main module as seen in the process window
iv)type the code in the sub module fa.vand save.
v)compile both the main module p2updated.v and sub module fa.v

5
 BCS302
Digital Design and Computer Organization
module fa(sum,carry,a,b, cin);
output sum;

output carry;
input a;

input b;
input cin;

wire w1,w2,w3, w4,w5,w6,w 7, w8,w9,w 10;

not G1(w1,a);
not G2 (w2,b);
not G3(w3,cin);
and G4(w4,a,b, cin);
and G5(w5,w1,w2, cin);
and G6(w6,w1,b, w3);
and G7(w7,a,w2, w3);
and G8(w8,a,b);
and G9(w9,b, cin);
and G10(w10,a,cin);
or G11(sum,w4,w5, w6,w7);
or G12(carry,w8,w9,w10);

endmodule
Digital Design and Computer Organization BCS302

Xitini Project NavigatorC \Copyolp2updatedlp 2up dated.npl [1a v]

Fie Edk Vew Toect Source Process Wndow Helo

Sources n Proect 13module fa (sun,carry, a, b, cin) :

output sum;
A papdsBed out put carry:
input a:
FDpapdrnd(paugpdsled v) input b:
Dla [la v) 1nput cin;

wire
U1, u2, w3, w4, v5, w6, u7, U8, u9, u10;
not G1 (v1, a);
1C not G2 (u2,b) :
1 not G3 (v3,c1n):
and G4 (v4,a,b,cin):
13 and G5 (v5, v1, u2, cin) :
and G6 ( v6, u1, b, u3):
BMoguie Viem Snapshot ViewLrey Yiew 1 and G7 (v7, a, u2,u3):
16 and G8 (v8, a, b):
17 and G9 (v9, b,c1n):
1e and G10 (v10, a, cin);
Processes for Souce 'p2updaied 1 or G11 (sun, v4, v5, v6, w7)
Desgn Entry Utätes 20 Or G12 (carry, v8, v9, v10) :
Create Schemac Symbal
21
Lanch ModeSm Siato endnodule
22
Vew Command Lire Log Fie 23
View Veriog Instartialon Templal
User Constants
Creae Tng Const ant:
Atig Paect oe Pins
Ed Congtran: (Text)
Imclement Desgn
O? SyheizeXST

Dpupdated v la
BtProces Vies

Smdalor'
Laurchng Apphcaton lor peoces "Lonch Moden

nings ÀErors/
EEConsole Firdnfes Ln 21 Col 21
Process launt otalSmSstrr s up to dot
M/eity
start

Stepl output
wave delaul
Copre os Forr rdove
e C Cus0 Zo

1111

tpdye
1000

dis

siRnas
Fte Ek vew Wndow
1U11
t001

sim /p2updated

22450 p:

Ops to 106 ns
starnt

7
 BCS302
Digital Design and Computer Organization
Step2 output

Fermo

alon S1

signals
Fle Ed View Wndow
S1

St1
S1

Cr
C10

S10

Sim./fa

99555 ps

g9050 ps to 101808 ps
Vsh
BO-Frot-ct ang
start
Digital Design and Computer Organization BCS302
BOOLEAN EXPRESSIONS:
Full'subtractor
diff=A@BOC

Jul Substrate
Bas
To be imblcmatd
(A e)6
(A6B) + CA88)

borr= AB+ BC+ AC

TRUTH TABLE

INPUTS OUTPUTS
A B C diff borr
0 0

0 1

1 0

1
1 0 0

1 1

9
Digital Design and Computer Organization BCS302

Full subtractor: -
ImpLEMENTATION DF FULL SUASTRACTOR USING 8ASIC GATES!

FS, FS, FS
B4 B0

diil
 BCS302
Digital Design and Computer Organization
Changes to be made for full subtractor

Step1

moduleps(diff,B4,a,b, B0);
input [3:0] a;
inpst [3:0]b;
input B0;
output [3:0] diff;
output B4;

wire B1,B2, B3;

fs FSO(diff[O],B1,a[0],b[0],B0);:
fs FS1(diff[1],B2,a[1],b[1], B1);
fs FS2(diff[2],B3,a[2],b[2],B2):
fs FS3 (diff[3],B4,a[3],b[3], B3):
endmodule

Xilinx -Project Navigator - C: skisk. npl -[pa.v]

MFie Edit View Project Source Process Window Help

1 module ps (diff, B4, a,b, BO) :

Sources in Project input (3:0) a;
sk 3 input [3:0) b;
OAuto wcr3000»|* 4 input BO;
H D ps (pav) 6 output [3:0) diff;
s(fa.v) output B4:
Uire B1, B2, B3 ;
fs FS0 (diff[o), B1, a[oJ,b[0), BO):
ts FS1(dift[1], B2,a[1) ,b[1) , B1) :
tModudo View Snapshot Yiew D Libary View 10 ts FS2 (diff [2], B3, a[2],b[2], B2):
1 fs FS3 (diff [3), B4, a[3) ,b[3], B3):
12 endnodule

Processes for Source: "ps"

14
Design Entry Utities
Create Schernatic Symbol
Launct ModelSirn 5 roulator
17
View CommandLine Log File 18
View Verilog Instantialion Templat
User Corstraints 19

Proces View pa.v fa.v

Launching Application for process "Launch ModelSin Sinulator'"

a4DN Console Fndin Fies WbmingsErors

Process launch ModelSim Smulator" is up to date.
start w3MCI Osoft off. lir - Project Na. Nish 14y DocUmerts 200P4
 Digital Design and Computer Organization BCS302

step2
module fs (diff, borr,a,b,cin);
input a;
input b;
input cin;
output diff;
output borr;

wire w1,w2,w3, w4,w5,w6,w7,w8,w9,w10;

notG1(w1,a);
not G2(w2,b);
not G3(w3,cin);
and G4(w4,a,b,cin);
and G5(w5,w1,w2,cin);
and G6(w6,w1,b, w3);
and G7(w7,a,w2, w3);
and G8(w8,w1,b);
and G9(w9,b,cin):
and G10(w10,w1,cin);
or G11(diff;w4,w5,w6,w);
or G12(borr,w8,w9,w10);
endmodule
 Digital Design and Computer Organization
BCS302
xilinx Project Navigater bktek pt a

i t e 1 , 2, , ,s6,, 10s
tot G1 (W1,8)

e V e r y Vee Sna G4 (4,6, b,Cin) s

and GS (wS, W1, 2,ein) :
d G6 (W6, w1,b, :
Phocere fo Souce 'p and G7 (W,a,w2,31:
Desgn Erty Utihties and Ge (8,1,b) :
Create Schematic Symbol and Gg (9,b,cin) :
Launch ModelSim Simulator and Gi0(w10, vl,cin):
Vi Command Line Log Fe 19 Or G11 (diff,v4, w5, v6, w71 :
Or G12 (borE, V8, 9,v10):
View Verilog Instantiation Templatt endrncdule
User Constramts
Create Timing Constrair1t 22
Assion Package Pns 28

pa v fay
Prooess Vies

K Console Fnd n Fies MlamingsErmors/

For hielp, press F1 Ln 1Col 1

Output:
wave delault
Fle Edt Cusor Zoom Compare Bouknar Foruet Window

1010 1111 1001 1010 1111

0101 1001 O110 0101

0101 O110 0011 Y0101 1010

pB4
SI0
p/E3

signals
Fle Edit View Window

|1111
|0101

1010
B4
B1
B2

sin:/ps

400000:p:
270221 ps

Ops to 816838 ps
Hstart W2 Microsoft oifice linx Project Naviga. - vish 001 PM
 BCS302
Organization
Digital Design and Computer
Design VerilogHDL to inplement simple circuitsusing structural, Data
3. model.
flow and Behavioural

Structural Model 1

module p3structural(a,b,c,d,e,y);

input a;

input b;

input c;
input d;
input e;

output y:
wire Y1,Y2;

and G1(Y1,a,b);
and G2(Y2,c,d,e);
or G3(Y,Y1,Y2);
endmodule OUTPUT: -
wane

p31/y

apnak

|S

sim /p31

29353

Ops lo 7066E0 pe
starn
 BCS302
Digital Design and Computer Organization
DataFlow Model
module p31(a,b,c,d,e,y):
input a;

input b;
inputc;
input d;

input e;
output y;

wire Y1,Y2;
as_ign Y1 =a & b;
assign Y2= c&d&e;
assign y= Y1|Y2;
endmodule

OUTPUT: -

Ele E Cur uor Zoom Compare Bocksnark Fornst Wivd

sipnals
Fla E View Window

SIO

Sim:/p31

300000 ps

Ops to 706048 ps
stan
 BCS302
ComputerOrganization
DigitalDesign and
Behavioral Model

module p3behavioral(a,b,c,d,e,y);

input a;
input b;

input c;
input d;

input e;

output y;

reg y;

always @(a,b,c,d,e)
begin
y= (a &b) | (c &d &e);
end

endmodule

OUTPUT: -
wavodelnút

o lp3behovoal

sipnals
Al Edt Vew Window

sim /p3beh anoral

226911 ps
 Digital Design and Computer Organization BCS302

4.Design Verilog HDL. to implement Binary Adder-Subtractor - Half and Full

Adder, Half and FullSubtractor.
Half adder: -

BOOLEAN EXPRESSIONS:

sum=A B
cout=AB

TRUTH TABLE

INPUTS OUTPUTS
A B sum cout

1 1

1 1 0
-

1 1

module p4addsub(a,b,sum,cout);

input a;
input b;
output sum;

output cout;

reg sum,cout;

always @(a,b)
begin
Sum = a ^ b:

Cout = a & b;

end

endmodule
 BCS302
Digital Design and Computer Organization
OUTPUT:

SPnals

4start
 BCS302
Digital Design and Computer Organization
Half Subtractor

BOOLEAN EXPRESSIONS:

Diff =A B
Borr =

TRUTH TABLE

INPUTS OUTPUTS
A B Diff Borr

0 0

1 1

0 1 0

1 1

module p4hs(a,b,Diff,Borr);
input a;
input b;
output Diff;

output Borr;

reg Diff, Borr;

always@(a,b)
begin
Diff = a^ b;
Borr =(a)&b;
end

endmodule
 Digital Design and Computer Organization BCS302

OUTPUT: -

esignak
Fie EA Ve Wndo

Ops to 7H48 ps

4star
 Digital Design and Computer Organization BCS302

FullAdder
BOOLEAN EXPRESSIONS

Sum= A B Cin

Cout=A B+ BCin+ ACin

TRUTH TABLE

INPUTS OUTPUTS
A B Cin sum cout
0 0

0 1
0 1
1 1

0 0 0
1
1 0
0 1

1 1

module p4fa(a,b,cin,sum,cout);:
input a;
input b;
input cin;
output sum;

output cout;
reg sum, cout;

always @(a,b,cin)
begin
sum =a^b^cin;

cout= (a &b) | (b &cin) | (a &cin);

end

endmodule
 BCS302
Digital Design and Computer Organization
oUTPUT:

E e Wt

sim /p4fa

300000 ps

Ops to 706046 ps

H start C1elsb mousl docs PraGit Naugà