Digital IC Design

Lec 2: Device and DC Characteristics

黃柏蒼 Po-Tsang (Bug) Huang

[email protected]

International College of Semiconductor Technology

National Chiao Tung Yang Ming University
What is Transistor?

A Switch! An MOS Transistor

VGS ≥ V T |VGS|

Ron
S D

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The NMOS Transistor Cross Section
n areas have been doped with donor ions (arsenic) of
concentration ND - electrons are the majority carriers
Gate oxide
Polysilicon
W Gate
Source Drain Field-Oxide
n+ n+ (SiO2)
L
p substrate
p+ stopper

Bulk (Body)

p areas have been doped with acceptor ions (boron)

of concentration NA - holes are the majority carriers
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Threshold Voltage Concept
G
VGS +
S D
-
n+ n+

n channel p substrate depletion region

The value of VGS where strong inversion

occurs is called the threshold voltage, VT
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Operation of NMOS

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MOS Current
 IDS = WCox(VGS – VTh - VC(x)) μE
 IDS = WCox(VGS – VTh - VC(x)) μ(VC(x)/dx)
 When integrated over the channel:

 Transistor saturates when VGD = VTh, - the channel

pinches off at drain’s side.

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The Threshold Voltage
VT = VT0 + γ(√|-2φF + VSB| - √|-2φF|)
where
VT0 is the threshold voltage at VSB = 0 and is mostly a function of the
manufacturing process
 Difference in work-function between gate and substrate material,
oxide thickness, Fermi voltage, charge of impurities trapped at the
surface, dosage of implanted ions, etc.
VSB is the source-bulk voltage
φF = -φTln(NA/ni) is the Fermi potential (φT = kT/q = 26mV at 300K is the
thermal voltage; NA is the acceptor ion concentration; ni ≈ 1.5x1010 cm-3
at 300K is the intrinsic carrier concentration in pure silicon)
γ = √(2qεsiNA)/Cox is the body-effect coefficient (impact of changes in VSB)
(εsi=1.053x10-10F/m is the permittivity of silicon; Cox = εox/tox is the gate
oxide capacitance with εox=3.5x10-11F/m)

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Transistor Dimensions
 Parameter for design
 W, L, tox, Vt

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FinFET

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 Pass Transistors
 We have assumed source is grounded
 What if source > 0?
 e.g. pass transistor passing VDD VDD
VDD
 Vg = VDD
 If Vs > VDD-Vt, Vgs < Vt
 Hence transistor would turn itself off
 nMOS pass transistors pull no higher than VDD-Vtn
 Called a degraded “1”
 Approach degraded value slowly (low Ids)
 pMOS pass transistors pull no lower than Vtp
 Transmission gates are needed to pass both 0 and 1

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Pass Transistor Ckts

VDD VDD VDD

VDD VDD
VDD
Vs = VDD-Vtn VDD-Vtn
VDD-Vtn VDD-Vtn

VDD
VDD-Vtn
Vs = |Vtp|
VDD VDD-2Vtn
VSS

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 DC Response
 DC Response: Vout vs. Vin for a gate
 Ex: Inverter
 When Vin = 0 -> Vout = VDD
 When Vin = VDD -> Vout = 0
VDD
 In between, Vout depends on
Idsp
transistor size and current Vin Vout
 By KCL, must settle such that Idsn
Idsn = |Idsp|
 We could solve equations
 But graphical solution gives more insight

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 Transistor Operation
 Current depends on region of transistor
behavior
 For what Vin and Vout are nMOS and pMOS in
 Cutoff?
 Linear?
 Saturation?

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NMOS Operation

Cutoff Linear Saturated

Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn
Vout < Vin - Vtn Vout > Vin - Vtn

VDD
Vgsn = Vin Idsp
Vin Vout
Vdsn = Vout Idsn

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PMOS Operation

Cutoff Linear Saturated

Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp
Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp
Vout > Vin - Vtp Vout < Vin - Vtp

VDD
Vgsp = Vin - VDD Vtp < 0 Idsp
Vin Vout
Vdsp = Vout - VDD Idsn

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I-V Characteristics
 Make pMOS is wider than nMOS such that βn =
βp
Idsn = |Idsp| Vgsn5

Idsn Vgsn4

-Vdsp Vgsn3
-VDD Vgsn2
Vgsp1 Vgsn1
Vgsp2 0 VDD
Vgsp3 Vdsn

Vgsp4 -Idsp Vgsp + VDD= Vin

Vgsp5 Vdsp + VDD= Vout

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Current vs. Vout, Vin

Vgsp + VDD= Vin

Vdsp + VDD= Vout
Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout

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Load Line Analysis
 For a given Vin:
 Plot Idsn, Idsp vs. Vout
 Vout must be where |currents| are equal in

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|
VDD
Vin2 Vin3
Idsp
Vin3 Vin2 Vin Vout
Vin4 Vin1 Idsn

VDD
Vout

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DC Transfer Curve
 Transcribe points onto Vin vs. Vout plot

Vin0 Vin1
VDD Vin2
Vin0 Vin5
A B

Vout
Vin1 Vin4
C

Vin2 Vin3
Vin3
Vin3 Vin2 D Vin4 Vin5
Vin4 Vin1 E
0 Vtn VDD/2 VDD+Vtp
VDD VDD
Vout Vin

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Operating Regions
 Revisit transistor operating regions VDD
Region nMOS pMOS
A Cutoff Linear Vin Vout
B Saturation Linear
C Saturation Saturation
D Linear Saturation
VDD
E Linear Cutoff A B

Vout
C

D
E
0 Vtn VDD/2 VDD-Vtp
VDD
Vin

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 Beta Ratio Effects
 If βp / βn ≠ 1, switching point will move from
VDD/2
 Called skewed gate
 Other gates: collapse into equivalent inverter
VDD
βp
= 10
βn
Vout 2
1
0.5
βp
= 0.1
βn

0
VDD
Vin

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Noise Margins
 How much noise can a gate input see before it
does not recognize the input?

Output Characteristics Input Characteristics

VDD
Logical High
Output Range VOH Logical High
Input Range
NMH
VIH
Indeterminate
VIL Region
NML
Logical Low
Logical Low VOL Input Range
Output Range
GND

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Logic Level
To maximize noise margins, select logic levels at
 unity gain point of DC transfer characteristic
Vout

VDD

β p/β n > 1

Vin Vout

Vin
0
VDD

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Regenerative

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Regenerative Property

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 Capacitance
 Any two conductors separated by an insulator have
capacitance
 Gate to channel capacitor is very important
 Creates channel charge necessary for operation
 Gate capacitance
 Source and drain have capacitance to body
 Across reverse-biased diodes
 Called diffusion capacitance because it is associated
with source/drain diffusion

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The Gate Capacitance

=Cpermicron*W Cpermicron = 2fF/um (>90nm)

or 1fF/um (<=90nm)
= C0
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Gate Capacitance with Operation Region
G G G

CGC CGC CGC

S D S D S D

Cut-off Resistive Saturation

Most important regions in digital design: saturation and cut-off

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Diffusion Capacitance

Channel-stop implant
NA1

Side wall
Source
W
ND

Bottom

xj Side wall
Channel
LS Substrate N A

The junction (or diffusion) capacitance is from the

reverse-biased source-body and drain-body pn junctions. 29
 Diffusion Capacitance
 Csb, Cdb
 Undesirable, called parasitic capacitance
 Capacitance depends on area and perimeter
 Use small diffusion nodes
 Comparable to Cg
for contacted diff
 ½ Cg for uncontacted
 Varies with process

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Where Does Power Go in CMOS?
 Switching power
 Charging/Discharging capacitors
 Leakage power
 Transistors are imperfect switches

 Junction diodes

 Short-circuit power
 Both pull-up and pull-down on during transition

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Dynamic Power Dissipation

 Not a function of transistor sizes!

 Need to reduce CL, Vdd, and f to reduce power.
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Activity and Power Transition
 Energy consumed in N cycles, EN,

EN = CL x VDD2 x n0→1
n0→1: number of 0→1 in N cycles

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Short Circuit

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Short Circuit Current
 Short circuit current is usually well
controlled

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Transistor Leakage
Transistors that are supposed to be off-leak

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 Sub-threshold Leakage
Sub-threshold current one of most compelling
issues in low-energy circuit design!

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Source of Leakage

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 Leakage Sources for Static CMOS Transistors
 PN reverse bias junction leakage - IB
 Electron-hole pair generation in the depletion region
 Band to band tunneling when the electric field
approaches 106V/cm
 Subthreshold leakage - Is
 Weak inversion current between source and drain
 It increase exponentially with the reduction of the
threshold voltage
 SCE, DIBL make it even worse
 Gate Induced Drain Leakage(GIDL) - IB
Ioff = IB+IS+IG in normal operating
 Occur at high electric field between drain and gate voltage range
terminal
 Punch-through - ID IB : be careful when back gate
 Occur when the drain and source depletion approach biased
each other
IS : major contribution > 90%
 Gate Oxide Tunneling - IG
 Due to the high electric field in the gate oxide- Direct
IG: can not be ignore from N90
tunnel since tox < 20A
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Leakage Currents of Nano-Scale Transistors
Gate
I7 I8
Source Drain

I2 I3 I6
I5 I1 P-well

Well I4

I1 : p-n Junction Reverse Bias Current

I2 : Weak Inversion
I3 : DIBL (Drain-Induced Barrier Lowering)
I4 : GIDL (Gate-Induced Drain Leakage)
I5 : Punchthrough
I6 : Narrow Width Effect
I7 : Gate Oxide Tunneling
I8 : Hot Carrier Injection
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Power and Energy Figures of Merit
 Power consumption in Watts
determines battery life in hours
 Peak power
determines power ground wiring designs
sets packaging limits
impacts signal noise margin and reliability
analysis
 Energy efficiency in Joules
rate at which power is consumed over time
 Energy = power * delay
Joules = Watts * seconds
lower energy number means less power to
perform a computation at the same frequency 41
Power versus Energy
Power is height of curve
Watts Lower power design could simply be slower

Approach 1

Approach 2

time
Energy is area under curve
Watts Two approaches require the same energy
Approach 1

Approach 2

time

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CMOS Energy & Power Equations

E = CL VDD2 P0→1 + tsc VDD Ipeak P0→1 + VDD Ileakage

f0→1 = P0→1 * fclock

P = CL VDD2 f0→1 + tscVDD Ipeak f0→1 + VDD Ileakage

Dynamic power Short-circuit Leakage power
power

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