Silicon Lattice

Transistors are built on a silicon substrate

Silicon is a Group IV material
Forms crystal lattice with bonds to four
neighbors

Si Si Si

Si Si Si

Si Si Si

0: Introduction CMOS VLSI Design

4th Ed.
 Dopants
Silicon is a semiconductor
Pure silicon has no free carriers and conducts
poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)
Si Si Si Si Si Si
- +

+ -
Si As Si Si B Si

Si Si Si Si Si Si

0: Introduction CMOS VLSI Design

4th Ed.
 p-n Junctions
A junction between p-type and n-type
semiconductor forms a diode.
Current flows only in one direction

p-type n-type

anode cathode

0: Introduction CMOS VLSI Design

4th Ed.
 nMOS Transistor
Four terminals: gate, source, drain, body
Gate – oxide – body stack looks like a capacitor
Gate and body are conductors
SiO2 (oxide) is a very good insulator
Called metal – oxide – semiconductor (MOS) capacitor
Even though gate is
no longer made of metal*
Source Gate Drain
Polysilicon
* Metal gates are returning today! SiO 2

n+ n+
Body
p bulk Si

0: Introduction CMOS VLSI Design

4th Ed.
 nMOS Operation
Body is usually tied to ground (0 V)
When the gate is at a low voltage:
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF

Source Gate Drain

Polysilicon
SiO2

0
n+ n+
S D
p bulk Si

0: Introduction CMOS VLSI Design

4th Ed.
 nMOS Operation Cont.
When the gate is at a high voltage:
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through n-type silicon from source
through channel to drain, transistor is ON

Source Gate Drain

Polysilicon
SiO2

1
n+ n+
S D
p bulk Si

0: Introduction CMOS VLSI Design

4th Ed.
 pMOS Transistor
Similar, but doping and voltages reversed
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior

Source Gate Drain

Polysilicon
SiO 2

p+ p+

n bulk Si

0: Introduction CMOS VLSI Design

4th Ed.
 Transistors as Switches
We can view MOS transistors as electrically
controlled switches
Voltage at gate controls path from source to
drain g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s

0: Introduction CMOS VLSI Design

4th Ed.
 CMOS Inverter

VDD
OFF
ON
0
1
A Y
ON
OFF

A Y
GND
0: Introduction CMOS VLSI Design
4th Ed.
 CMOS NAND Gate

ON
OFF
OFF
ON OFF
ON

1
0
Y
ON
A OFF

0
1
1
0
OFF
ON
B ON
OFF

0: Introduction CMOS VLSI Design

4th Ed.
 CMOS NOR Gate

A
B
Y

0: Introduction CMOS VLSI Design

4th Ed.
 Inverter Cross-section
Typically use p-type substrate for nMOS
transistors
Requires n-well for body of pMOS transistors
A
GND VDD
Y SiO 2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

0: Introduction CMOS VLSI Design

4th Ed.
 Well and Substrate Taps
Substrate must be tied to GND and n-well to
VDD
Metal to lightly-doped semiconductor forms
poor connection called Shottky Diode
Use heavily dopedAwell and substrate
contacts
GND / taps V DD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

well
substrate tap
tap

0: Introduction CMOS VLSI Design

4th Ed.
 Inverter Mask Set
Transistors and wires are defined by masks
Cross-section taken along dashed line

GND V DD

nMOS transistor pMOS transistor

substrate tap well tap

0: Introduction CMOS VLSI Design

4th Ed.
 Detailed Mask Views
Six masks
n-well
n well

Polysilicon
n+ diffusion
p+ diffusion Polysilicon

Contact
Metal
n+ Diffusion

p+ Diffusion

Contact

Metal

0: Introduction CMOS VLSI Design

4th Ed.
 Layout
Chips are specified with set of masks
Minimum dimensions of masks determine
transistor size (and hence speed, cost, and
power)
Feature size f = distance between source and
drain
Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize for feature size when describing
design rules
Express rules in terms of λ = f/2
E.g. λ = 0.3 μm in 0.6 μm process

0: Introduction CMOS VLSI Design

4th Ed.
 Simplified Design Rules
Conservative rules to get you started

0: Introduction CMOS VLSI Design

4th Ed.
 Inverter Layout
Transistor dimensions specified as Width /
Length
Minimum size is 4λ / 2λ, sometimes called 1 unit
In f = 0.6 μm process, this is 1.2 μm wide, 0.6 μm long

0: Introduction CMOS VLSI Design

4th Ed.