Sequential Circuits

And Finite State Machines

Lab 1 checkoff due tomorrow (9/27)

Lab 2 due on Thu (9/28)
Quiz 1 happening on 10/5

September 26, 2023 MIT 6.191 Fall 2023 L06-1

 Something We Cannot Build (Yet)
What if you were given the following design specification:
#1
When the button is pushed:
1) Turn the light on if it is off
button 2) Turn the light off if it is on light

The light should change state

#2 within a second of the button press

What makes this device different from

those we’ve discussed before?

State – i.e., the device has memory

September 26, 2023 MIT 6.191 Fall 2023 L06-2

 Sequential Circuits
Sequence of values
Next
k State
Trigger
Memory
periodically
Device Current
State Combinational
LOAD
Logic
Input Output

Sequential circuits contain digital memory and combinational logic

• Memory stores current state
• Combinational logic computes:
• Next state (from input + current state) Need
• Output bits (from input + current state) loadable
• State changes on LOAD control input memory

September 26, 2023 MIT 6.191 Fall 2023 L06-3

 Memory: Using Feedback
Idea: use feedback to maintain storage indefinitely.
Our logic gates are built to restore marginal signal levels, so
noise shouldn’t be a problem!

Result: a bistable
1
0 0
1 1
0 storage element
VIN VOUT

Not affected
VTC for
Feedback constraint: by noise
inverter pair
VIN = VOUT
VOUT
Three solutions:
• two end-points are stable
• middle point is metastable

VIN We’ll get back to this!

September 26, 2023 MIT 6.191 Fall 2023 L06-4

 D Latch
A simple circuit that can hold state

1 1
Q D 0 Q
D 0
C C
1 0
D V1 V2
if C=1, the value of Q holds
C
if C=0, the value of D passes to Q
Q V1 V2
D
Q tPD tPD
DL
C C D Qt-1 Qt
0 0 X 0
Qt-1 represents the value 0 1 X 1
pass
previously held in DL; 1 X 0 0
Qt represents the current value. hold
1 X 1 1

September 26, 2023 MIT 6.191 Fall 2023 L06-5

 Sequential circuits using D latches?
A terrible idea

Next
State
D Q
Current
DL State Combinational
C
Logic
Input Output

§ When C=0, D latch passes input to output...

§ Creates a cycle from Q to D!
§ Our combinational logic stops being combinational L
§ In practice, very hard to get right: Needs tricky
timing constraints on C=0 pulse + comb logic

Memory should sample an instant, not an interval

September 26, 2023 MIT 6.191 Fall 2023 L06-6
 A Similar Problem…

Gate closed Gate open

How can we ensure

Sequence
of values only one car gets
through?
September 26, 2023 MIT 6.191 Fall 2023 L06-7
 Solution: Use two gates!

Gate 2 Gate 2

Gate 1 Gate 1

Sequence
of values

Gate 1: open Gate 1: closed

Gate 2: closed Gate 2: open

September 26, 2023 MIT 6.191 Fall 2023 L06-8

 D Flip-Flop
D Qint Q
DL1 DL2
C=0 C

§ Two latches driven by inverted C signals, one is

always holding, and one is always passing
§ How does this circuit behave?
§ C = 0: Qint follows the input D, but Q holds its old value

September 26, 2023 MIT 6.191 Fall 2023 L06-9

 D Flip-Flop
D Qint Q
DL1 DL2
C=1 C

§ Two latches driven by inverted C signals, one is

always holding, and one is always passing
§ How does this circuit behave?
§ C = 0: Qint follows the input D, but Q holds its old value
§ C = 1: Qint holds its old value, but Q follows Qint
§ Q doesn’t change when C=0 or C=1
§ It changes when C transitions from 0 to 1 (a rising-edge of C)

September 26, 2023 MIT 6.191 Fall 2023 L06-10

 D Flip-Flop
D Qint=D Q=D
C=0è1 DL1 DL2
C

§ Two latches driven by inverted C signals, one is

always holding, and one is always passing
§ How does this circuit behave?
§ C = 0: Qint follows the input D, but Q holds its old value
§ C = 1: Qint holds its old value, but Q follows Qint
§ Q doesn’t change when C=0 or C=1
§ It changes when C transitions from 0 to 1 (a rising-edge of C)

What happens on a falling edge (C: 1 è 0)?

September 26, 2023 MIT 6.191 Fall 2023 L06-11

 D Flip-Flop
An edge-triggered storage element

D QInt D
Q
DL DL D
Q
C C

C changes periodically (a Clock signal)

t1 t2 t3 Unstable data
Clk
D
Q Metastability

Data is sampled at the rising edge of the clock

and must be stable at that time
September 26, 2023 MIT 6.191 Fall 2023 L06-12
 D Flip-Flop Timing
CLK
≥tSETUP ≥tHOLD
D Q
D D
CLK Q
≤tPD
§ Flip-flop input D should not change around the rising
edge of the clock to avoid metastability
§ Formally, D should be a stable and valid digital value:
§ For at least tSETUP before the rising edge of the clock
§ For at least tHOLD after the rising edge of the clock
§ Flip-flop propagation delay tPD is measured from rising
edge of the clock to valid output (CLKàQ)

September 26, 2023 MIT 6.191 Fall 2023 L06-13

 Sequential Circuits using D Flip-Flops

Next
State
D Q
Current
D State Combinational
Logic
Input Output

§ There is never a combinational cycle between D

and Q!
§ Works correctly, as long as we meet tSETUP and tHOLD
§ More on this later

September 26, 2023 MIT 6.191 Fall 2023 L06-14

 D Flip-Flop with Write Enable
EN EN

D 0
Q
D D 1 Q
Clk
Clk
D

t1 t2 t3
EN D Qt Qt+1
Clk
0 X 0 0
EN hold
0 X 1 1
D 1 0 X 0 copy
Q 1 1 X 1 input

Transitions happen at
Data is captured rising edge of the clock
only if EN is on No need to specify the
clock explicitly
September 26, 2023 MIT 6.191 Fall 2023 L06-15
 How Are Flip-Flops Initialized?
Reset
EN Reset
Initial Value 1
D EN 0
D
Q D Q
Clk 0
D 1
Clk

• When Reset = 1, flip flop is set to initial value

regardless of value of EN

• When Reset = 0, then it behaves like a D flip-flop

with enable

September 26, 2023 MIT 6.191 Fall 2023 L06-16

 Using D Flip-Flops to Build
Sequential Circuits

September 26, 2023 MIT 6.191 Fall 2023 L06-17

 Synchronous Sequential Circuits
§ All the D Flip-Flops use the same periodic clock signal
§ Register: Group of DFFs
§ Stores multi-bit values
§ Registers update their contents simultaneously, at the
rising edge of the clock

D0 DFF Q0
Reg
CLK D Q
n n
…

Dn-1 DFF Qn-1 CLK

September 26, 2023

CLK MIT 6.191 Fall 2023 L06-18
 Synchronous Sequential Circuits
§ Synchronous sequential circuits: All state kept in
registers driven by the same clock
§ This allows discretizing time into cycles and
abstracting sequential circuits as finite state
machines (FSMs)
§ FSMs can be described with state-transition
diagrams or truth tables

Current Next
state state
Combinational
clock logic
input output

September 26, 2023 MIT 6.191 Fall 2023 L06-19

 A Simple Sequential Circuit

Let’s make a digital binary Combination Lock:

IN
Lock U
CLK

Specification:
• A 1-bit input ( “0” or “1”)
• A 1-bit output (“Unlock” signal)
• UNLOCK is 1 if and only if:
Last 4 inputs were the “combination”: 0110

How many states do we need?

September 26, 2023 MIT 6.191 Fall 2023 L06-20
 State-Transition Diagram

0
1
S0 S1 S2 S3 S4
1 U=0 0 U=0 1 U=0 1 U=0 0 U=1

0 0
1 Heavy circle
Means
Designing our lock NAME
INITIAL state

• Need an initial state; call it S0. of state

0
• Must have a separate state for each XXX
step of the proper entry sequence U=0
OUTPUT INPUT
• Must handle other (erroneous) when in this causing
entries state transition

September 26, 2023 MIT 6.191 Fall 2023 L06-21

 Valid State-Transition Diagrams

§ Arcs leaving a state must be:

(1) mutually exclusive

– For a given input value, can’t have two choices

(2) collectively exhaustive

– Every state must specify what happens for each
possible input combination
– “Nothing happens” means arc back to itself

September 26, 2023 MIT 6.191 Fall 2023 L06-22

 Two-Bit Counter
An Example
inc=0 inc=0
Current Next
State State
inc=1
00 01 inc q1t q0t q1t+1 q0t+1
0 0 0 0 0
inc=1 inc=1
0 0 1 0 1
inc=1 0 1 0 1 0
11 10
0 1 1 1 1
inc=0 inc=0
1 0 0 0 1
State-Transition Diagram 1 0 1 1 0

t+1 t t
1 1 0 1 1
q0 = ~inc·q0 + inc·~q0 1 1 1 0 0
t
= inc Å q0
q1t+1 = ~inc·q1t + inc·~q1t·q0t + inc·q1t·~q0t
= ~inc·q1t + inc·(q1t Å q0t)
Output = current state = q1q0
September 26, 2023 MIT 6.191 Fall 2023 L06-23
 Two-Bit Counter Circuit
Using D flip-flops

q0t+1 = ~inc·q0t + inc·~q0t

q1t+1 = ~inc·q1t + inc·(q1t Å q0t)

§ Use two D flip-flops with reset

q0t+1 = ~q0t inc=1
and enable to store q0 and q1 q1t+1 = q1t Å q0t

§ The state only changes when

inc is 1. Let’s connect inc to EN
and simplify the equations inc
D
E q0 Q
0 IV
R

§ Output is q1q0 D
E q1 Q
0 IV R
§ Set Initial Value of both flip-
flops to 0 (initial state: 00)
§ Loaded when Reset = 1

September 26, 2023 MIT 6.191 Fall 2023 L06-24

 Timing Constraints in
Sequential Circuits

September 26, 2023 MIT 6.191 Fall 2023 L06-25

 Recap: D Flip-Flop Timing

CLK
D D Q Q ≥tSETUP ≥tHOLD
D
CLK
Q
≤tPD
§ Flip-flop input D should not change around the rising edge of
the clock to avoid metastability
§ Formally, D should be a stable and valid digital value:
§ For at least tSETUP before the rising edge of the clock
§ For at least tHOLD after the rising edge of the clock
§ Flip-flop propagation delay tPD is measured from rising edge
of the clock to valid output (CLKàQ)

September 26, 2023 MIT 6.191 Fall 2023 L06-26

 Single-clock Synchronous Circuits

Current Next
state state
Combinational
clock logic
input output

Need to analyze
the timing of each
a register-to-register path

b c

clk

September 26, 2023 MIT 6.191 Fall 2023 L06-27

 Meeting the Setup-Time Constraint
tCLK
D1 Q1 D2
D Q CL D Q CLK
tPD,FF1
FF1 FF2
Q1
CLK
tPD,CL
Dœ2
§ To meet FF2’s setup time, ≥tSETUP,FF2
𝑡"#$ ≥ 𝑡&',))* + 𝑡&',"# + 𝑡,-./&,))0

§ The slowest register-to-register path in the system

determines the clock;
§ Equivalently, a given register technology and clock limit
the amount of combinational logic between registers

September 26, 2023 MIT 6.191 Fall 2023 L06-28

 Meeting the Hold-Time Constraint
CLK
D1 Q1 D2 tCD,FF1 tPD,FF1
D Q CL D Q
FF1 FF2 Q1
tCD,CL
CLK
D
œ2
≥tHOLD,FF2
§ Hold time (tHOLD) constraint of FF2 may be violated if D2
changes too quickly
§ Propagation delay (tPD), the upper bound on time from valid
inputs to valid outputs, does not help us analyze hold time!
§ Contamination delay (tCD) is the lower bound on time from
input-to-output transition (invalid input to invalid output)
§ To meet FF2’s hold-time constraint Tools may need to add
logic to fast paths to
𝑡"',))* + 𝑡"',"# ≥ 𝑡12#',))0 meet tHOLD
September 26, 2023 MIT 6.191 Fall 2023 L06-29
 Timing Summary
§ For a sequential circuit to work properly, we must guarantee
that the setup time and hold time constraints of every
register will always be satisfied.

§ The setup time constraint is affected by both the logic in the

circuit and the clock period. To fix violations, either:
§ Change the logic to be faster (lower tPD)
§ Change the clock to be slower (higher tCLK)

§ The hold time constraint is affected only by the logic in the

circuit.
§ Changing the clock period will not fix violations.
§ Sum of contamination delays must be greater than the register hold
time, otherwise the circuit won’t work.

§ If hold time is satisfied, then the fastest clock period can be

set as the maximum sum of the propagation delays plus
setup time across all register-to-register paths.

September 26, 2023 MIT 6.191 Fall 2023 L06-30

 Sequential Circuit Timing Example

Current Next
tCD,Reg = 1ns State State
tPD,Reg = 3ns
tSetup,Reg = 2ns
tHold,Reg = 2ns
Combinational
Clock Logic
tCD,CL = ?
tPD,CL = 5ns
Input Output

Questions:
• Constraints on tCD for the logic?
tCD,Reg (1 ns) + tCD,CL(?) ≥ tHold,Reg(2 ns)

tCD,CL ≥ 1 ns

• Minimum clock period?

tCLK ≥ tPD,Reg+tPD,CL+ tSetup,Reg = 10ns
September 26, 2023 MIT 6.191 Fall 2023 L06-31
 Thank you!

Next lecture:
Sequential logic in Minispec

September 26, 2023 MIT 6.191 Fall 2023 L06-32