GMR Institute of Technology, Rajam

23-May-24

Unit-3
Multilevel Converters
GMR Institute of Technology

By
Dr. G Indira kishore
Asst.Professor
Dept. of Electrical & Electronics Engg.

23-May-24 1

1 1
23-May-24
 Syllabus
Unit-III
Multilevel converters and configurations for wind energy
system
Multilevel converter topologies, Diode-clamped inverter, Capacitor-
clamped inverter, Cascaded H-bridge inverter,
Flying capacitor multilevel inverter.
GMR Institute of Technology
 Inverters:
23-May-24

 The device which converts DC voltage to AC voltage is

called inverter.
 Output voltage should ideally be sinusoidal wave of variable
magnitude and variable frequency. An inverter does the opposite
job of Rectifier.
 Electronic inverters can be used to produce smoothly varying AC
GMR Institute of Technology

output from a DC input.

 Inverters are made up of capacitors and inductors which make the
output current smooth as compared to switching square wave
output you get with a basic inverter.

3
 A best example to understand the use for inverters is in emergency
23-May-24

power supplies, also called uninterruptible power supplies (UPS). In a

typical UPS, when power is flowing normally, the batteries are
charged by DC, which is produced from the AC power supply using a
transformer and rectifier circuit. If the power fails, the batteries
provide DC through an inverter in order to produce AC.
GMR Institute of Technology

4
 23-May-24
GMR Institute of Technology

 Multilevel inverters are the preferred choice of industry for the

application in high voltage and for high power application.
 Multilevel inverter technology has emerged recently as a very
important alternative in the area of high-power medium-voltage
energy control.

5
 Why Multi-level Inverters
23-May-24

The need of multilevel converter is to give a high output power from

medium voltage source. The multi level inverter consists of several
switches.
1. Higher voltage can be generated using the devices of lower rating.
2. Increased number of voltage levels produces better voltage
waveform.
GMR Institute of Technology

3. Switching Frequency can be reduced for the PWM operation

6
 How multilevel inverters Works?
The most common type of inverter which is used to generate AC
23-May-24

voltage from DC Voltage is two level inverter. A two-level Inverter

creates two different voltages for the load i.e. suppose we are
providing Vdc as an input to a two level inverter then it will provide
+ Vdc/2 and – Vdc/2 on output. In order to build an AC voltage, these
two newly generated voltages are usually switched.
GMR Institute of Technology

Although this method of

conversion of voltage is effective
but it has some limitations as it
causes disturbance in the output
voltage. Normally this method
works but in some applications it
creates problems specifically
where high distortion in the
output voltage is not required.
7
 Two Level Inverter
23-May-24
GMR Institute of Technology

Topology of an H- Bridge Inverter

8
 Two Level Inverter
 The input Voltage Vdc is commonly referred as DC Link Voltage.
23-May-24

The higher potential is marked as ‘P’ and lower potential is

marked as ‘N’.
 The load shown can be a resistive load, inductive or capacitive.
The load terminals are indicated as A and B.
 The load voltage is marked as vo(t) and load current is marked as
io(t).
GMR Institute of Technology

Topology of an H- Bridge Inverter

9
 Two Level Inverter
 When the potential at A is higher than B, then vo(t) is considered
23-May-24

as positive, other wise negative.

 Similarly, when the direction of current is from A to B, then io(t)
is considered positive, otherwise it is negative.
 The arrangement as four switches named S1,S2,S3 and S4.
GMR Institute of Technology

Topology of an H- Bridge Inverter

10
 GMR Institute of Technology 23-May-24

11
  For ease of operation, Point ‘N’ of the topology is considered to
23-May-24

be the reference point with a potential of 0V.

 Accordingly, the potential at point ‘P’ w.r.t Point ‘N’ would be
+Vdc.
 When switches S1 and S4 are switched ‘ON’ together, keeping
S2 and S3 ‘OFF’ then the load voltage is +Vdc.
GMR Institute of Technology

12
  When switches S2 and S3 are ‘ON’, keeping S1 and S4 ‘OFF’,
23-May-24

then the load voltage is –Vdc.

 These two switching configurations are referred to as states.
 These two states leads to load voltage being positive and
negative respectively.
GMR Institute of Technology

13
  Hence if H bridge is operated in these two states periodically, then
23-May-24

an alternating waveform (square) is obtained across the load as

shown in figure.
GMR Institute of Technology

14
  With “discrete” nature of the output waveform on the load, it is observed that the
23-May-24

voltage level periodically changes from +Vdc to –Vdc and vice versa in almost no
time.
 This rate of change of voltage imposed on load may cause undesirable effect.
 For example, in the motor windings, such a voltage may cause leakage current through
the insulation. The arrangement of conductor and insulation acts like a capacitance and
the current through a capacitance is dependent on the rate of change of voltage across
it.
GMR Institute of Technology

ic(t)=C

 This rate of change of voltage as seen in the waveform is often expressed as dv/dt
stress on the load. In this per unit form, the dv/dt stress is:
#$ %
lim ∆
∆ →"
 Hence for two-level waveform, the dv/dt stress on load is
& 2
' (. * lim
∆ →" ∆

15
 23-May-24

 For the H Bridge, two more states can be added as shown in below
figure.
 In state 3, switches S1 and S3 are simultaneously turned ‘ON’ such
that voltage obtained across the load is 0 V.
 In state 4, switches S2 and S4 are simultaneously turned ‘ON’ such
that voltage obtained across the load is 0 V.
GMR Institute of Technology

16
 GMR Institute of Technology 23-May-24

17
 23-May-24

 States 3 and 4 give the same output voltage, though they are
distinct in terms of switching combinations.
 Such states are called redundant states.
 If these zero level is included in the operation of an H bridge
topology, a waveform as shown will be obtained.
GMR Institute of Technology

 This waveform has three distinct levels: +Vdc,0 and – Vdc and
hence it is called a three-level waveform.
18
 23-May-24

 One important advantage of this waveform is that the dv/dt

stress across the load is reduced by half as compared to the
two-level waveform.
 ' (. * , ℎ . & / & , 0 lim
∆ →" ∆
 A waveform which has three or more levels is called a
multilevel waveform, and a topology which is capable of
GMR Institute of Technology

synthesizing a multilevel waveform is called an multi level

inverter (MLI)

19
 The concept of multilevel Inverter (MLI) is kind of modification of
23-May-24

two-level inverter. In multilevel inverters create a smoother stepped

output waveform, more than two voltage levels are combined
together. Smoothness of the waveform is directly proportional to the
voltage levels, with increase in voltage level, the waveform becomes
more smoother but the complexity will be increased.
GMR Institute of Technology

20
 GMR Institute of Technology 23-May-24

21
 Diode Clamped Multilevel Inverter
23-May-24

This type of inverter uses diodes and gives different voltage levels to
the capacitor banks connected in series. The benefit of using diode is
to reduce stress on other electrical devices because it gives a limited
amount of voltage. But there is a drawback of this topology that the
maximum voltage which we can get from it cannot be more than half
of input voltage (DC voltage). But this problem can be solved by
GMR Institute of Technology

increasing the number of capacitors, switches and diodes. This type of

inverters provides the high efficiency and it is a simple method of the
back to back power transfer systems. Example: 5- Level diode
clamped multilevel inverter, 9- level diode clamped multilevel
inverter.

22
 Diode Clamped Multilevel Inverter
23-May-24

 NPC is also known as Diode clamped topology.

 As shown in figure 2.14, the structure has a DC link voltage of Vdc
which is generally halved using capacitors, but here it is shown
with two DC sources.
 The leg consists of four bidirectional-conducting-unidirectional-
blocking power switches.
GMR Institute of Technology

 The clamping to the common point “o” is done with the help of
two diodes D1 and D2. Positive and negative DC rails are shown
with “p” and “n”, respectively.

23
 23-May-24
GMR Institute of Technology

(A) (B)

Figure 2.14 (A) One leg of a three-level diode-clamped inverter; (B) leg shown with switches

24
 23-May-24
GMR Institute of Technology

(A) (B)
State 1
State 2
• S1 and S2 are ON; S3 and S4 are OFF
• S2 and S3 are ON; S1 and S4 are OFF
• Potential at a=+VDC/2
• Potential at a = 0
• vao(t) = VDC/2
• vao(t) = 0 V
• Voltage stress across S3 and S4 = VDC/2
• Voltage stress across S1 and S4 = VDC/2
• Voltage stress across D1 and D2 = VDC/2

Figure 2.15 Working states for one leg of a three-level diode-clamped inverter

25
 23-May-24
GMR Institute of Technology

(C)
State 3
• S3 and S4 are ON; S1 and S2 are OFF
• Potential at a = -VDC/2
• vao(t) = -VDC/2
• Voltage stress across S1 and S2 = VDC/2
• Voltage stress across D1 and D2 = VDC/2

Figure 2.15 Working states for one leg of a three-level diode-clamped inverter

26
 23-May-24

 There are three valid states as depicted in fig 2.15.

 For analysis, point “o” is chosen as the reference node with a
potential of 0 V.
 Accordingly, the potentials at p and n are +Vdc/2 and – Vdc/2.
 The potential difference between point “a” and “o” in the circuit
is considered to be the load voltage, vao(t).
GMR Institute of Technology

 In state 1, S1 and S2 are simultaneously switched ON to obtain

vao(t) =Vdc/2, as shown in Fig.2.15 A.
 It can be observed that the voltage stress across the devices in the
OFF state is Vdc/2 which is half of the DC link Voltage.

27
 23-May-24

 In State 2, two equivalent circuits are shown with directions of

currents to emphasize the role of clamping diodes in the topology.
 When switches S2 andS3 are simultaneously switched ON, then the
load voltage is zero.
 At this time, if the load current is positive, then the current
completes its path through S2 and D1 as depicted in Fig.2.15 B.
GMR Institute of Technology

 If the load current happens to be negative, then it completes its

path through S3and D2, again depicted in Fig.2.15B.
 Once again, the device in the OFF block a voltage equal to Vdc/2.

28
 23-May-24

 In state 3, when switches S3 and S4 are simultaneously turned ON,

then the obtained load voltage is –Vdc/2, as shown in Fig.2.15 C.
 In this state also, the voltage stress across the OFF devices is
Vdc/2.
 Hence, three levels are obtained using these three states: +Vdc/2,-
Vdc/2 and 0.
GMR Institute of Technology

29
  In order to modulate this leg, the level shifted.pwm scheme is as
23-May-24

shown in Fig. 2.16A, along with the carrier and reference signals
in Fig.2.16B.
 That is to say, one carrier signal is above the zero reference and
the other is below the zero reference.
 The reference signal is continuously compared with the carrier
signals.
GMR Institute of Technology

 Whenever the reference signal is greater than the carrier signal 1,

switch S1 is turned ON, otherwise S3 is turned ON.
 Similarly, whenever the reference signal is greater than carrier
signal 2, Switch S2 is turned ON, otherwise switch S4 is turned
ON.
 When operated in this manner, the resulting load voltage vao(t) is
as shown in Fig.2.16C. Previously discussed that, for an MLI,
generally, the voltage stress across the power switches is less
than the operating voltage. 30
 23-May-24
GMR Institute of Technology

Figure 2.16 (A) Modulation strategy for one leg of a three-level diode-clamped inverter

31
 23-May-24
GMR Institute of Technology

Figure 2.16 (B) reference and carrier signals for one leg of a three-level diode-clamped inverter

32
 23-May-24
GMR Institute of Technology

Figure 2.16 (C) Output voltage waveform for one leg of a three-level diode-clamped inverter

33
 GMR Institute of Technology 23-May-24

34
 23-May-24

A three phase structure is obtained by adding to more three level

legs as shown in Fig.2.17.
GMR Institute of Technology

35
 The three-phase structure
23-May-24

can be modulated by
modulating all three legs
with level shifted carriers
and sinusoidal references
with a phase difference of
1200 as shown in
GMR Institute of Technology

Fig.2.18.

36
 23-May-24

The corresponding carrier and reference signal are shown in

Fig.2.19
GMR Institute of Technology

37
 When modulated in this manner, the phase voltages have three levels,
23-May-24

with Vdc/2 as the peak value, and they are shifted from one another
by an angle of 120 degress, as shown in Fig.2.20.
GMR Institute of Technology

38
 The line voltages shown in Fig.2.21 are all observed to consist of five levels. These
23-May-24

are all phase-shifted from one another at an angle of 120 degrees and have a peak
value of Vdc, which is twice the blocking voltage requirement. Here we emphasize
the relationship between the number of levels in phase and line voltages:
GMR Institute of Technology

39
 Number of levels in line
23-May-24

voltage = 2*(number of levels

in phase voltage)-1
In order to extend
the number of levels, the
structure can be
systematically extended. One
such example is shown in
GMR Institute of Technology

Fig.2.22 with a single leg.

The reader is encouraged to
determine working valid
states for this structure.

40
 23-May-24

Similarly, for modulation of diode-clamped structures with a higher

number of levels, the number of carrier signals can be increased with
appropriate “ level-shifting as depicted in Fig.2.23
GMR Institute of Technology

41
  In general for a N level diode clamped inverter, for each leg
23-May-24

2 (N-1) switching devices,

 (N-1) * (N-2) clamping diodes and
 (N-1) dc link capacitors are required.
 When N is sufficiently high, the number of diodes and the number
of switching devices will increase and make the system
impracticable to implement.
GMR Institute of Technology

42
 Capacitor-Clamped/Flying Capacitors Multilevel Inverter

The main idea of this topology is the use of capacitors. The capacitors
23-May-24

transfer the limited amount of voltage to electrical devices. In this

inverter switching states are like in the diode clamped
inverter. Clamping diodes are not required in this type of inverters.
Likewise, the maximum voltage which we can get from it cannot be
more than half of input voltage (DC voltage). It can control both the
active and reactive power flow. But due to the high frequency
GMR Institute of Technology

switching, switching losses will takes place. Example: 5-level flying

capacitors multilevel inverter, 9-level flying capacitors multilevel
inverter.

43
  The so-called FC topology
23-May-24

does not use any clamping

diodes.
 Instead it uses capacitors
which are not directly
connected to the positive or
negative DC rails; hence
GMR Institute of Technology

the name "floating" or

"flying" capacitor (FC)
topology.
 A leg of three-level FC
topology is shown in
following fig.

44
 23-May-24

 As shown in figure, the input voltage

is Vdc , shown with two voltage
sources of value Vdc/2 each.
 The common point is marked as “O”
and the load voltage is measured as
the potential difference between
GMR Institute of Technology

points “a” and “o”, Vao(t).

 The structure has four bidirectional-
conducting-unidirectional blocking
switches and one floating capacitor
“C”.
 The positive and negative DC rails
are marked with “p” and “n”,
respectively. The floating capacitor
“c” is “precharged” to a voltage Vdc/2
with polarity as shown fig. 45
 There are four valid states
23-May-24

summarized in fig. 2.25. As can

be observed from fig. 2.25A,
when S1 and S₂ are
simultaneously switched ON, a
voltage of Vdc/2 is obtained
across the load, while the
GMR Institute of Technology

voltage stress across the

blocking switches is Vdc/2.
Similarly, in State 2, shown in
Fig. 2.25B, when Switches S3
and S4 are simultaneously
turned ON. Voltage of -Vdc/2
appears across the load, while
the voltage stress across the
blocking devices is Vdc/2.
46
 GMR Institute of Technology 23-May-24

47
  States 3 and 4, shown in Fig. 2.25C and 2.25D, respectively, both
23-May-24

lead to a load voltage of 0V, although with different switching

combinations, and hence they are redundant states.
 These redundant states are used to balance the capacitor voltages.
As described earlier, the FC has to be precharged and voltages
need to be balanced.
 Such switching procedures are discussed in later chapters, in which
GMR Institute of Technology

control is heavily based on the state selection procedure.

48
 GMR Institute of Technology 23-May-24

49
  A three-phase inverter based on a three-level FC leg is shown in
23-May-24

Fig. 2.26 and an extension of this topology is shown in Fig. 2.27.

GMR Institute of Technology

50
 23-May-24
GMR Institute of Technology

Seven-level capacitor-clamped inverter.

51
  The capacitor clamping requires a large number of bulk capacitors
23-May-24

to clamp the voltage.

 Provided that the voltage rating of each capacitor used is the same
as that of the main power switch, a N level converter will require a
total of (N-1) * (N-2) / 2 clamping capacitors per phase in addition
to the N-1 main dc bus capacitors.
GMR Institute of Technology

52
 GMR Institute of Technology 23-May-24

5 level FC Topology

53
 Cascaded H-bridge Multilevel inverter
The Cascaded H-bridge multilevel inverter uses capacitor and
23-May-24

switches. It requires less number of components in each level as

compared to previous described types. This topology consists of
series of power conversion cells and power can be easily scaled.The
combination of capacitors and switches pair is called an H-bridge.It
consists of H-bride cells and each cell can provide three different
voltages like zero, positive DC and negative DC
GMR Institute of Technology

voltages.Example: 5-H-Bridge, 9-H-Bridge Multilevel inverter

54
 Let us consider three separate H-bridge inverters, with each having
23-May-24

input DC voltage equal to VDC as illustrated in Fig. 2.4, the load

terminal voltages of these bridges are V0,1(t), V0,2(t) and V0,3(t). Each
of these bridges can be operated as a three level inverter. Note that the
blocking voltage for the power witches of each bridge is VDC. These
Bridges can be operated in such a manner that the width of positive
half cycles and negative half cycles are "calculatedly" different, as
GMR Institute of Technology

shown in Fig. 2.4.

55
  Now, if the three bridges are
23-May-24

connected in series, as
shown in Fig. 2.5A, the load
voltage V0,1(t) will be the
sum of V0,1(t), V0,2(t) and
V0,3(t) and as can be seen in
Fig. 2.5B, the load voltage is
GMR Institute of Technology

"stepped" in nature,
consisting of seven levels
(±VDC ,±2VDC ,±3VDC).
 This seven-level waveform
seems to be a better imitation
of a sine wave as compared
to a square waveform or
even a three-level wave
form.
56
 GMR Institute of Technology 23-May-24

57
  Very importantly, in this case, the blocking voltage (equal to c) is
23-May-24

one-third of the operating voltage (equal to 3VDC) and hence

power switches of lesser voltage rating can be used to synthesize a
much higher voltage waveform.
 For an operating voltage of 600 V, the full bridge inverter will
require power switches rated at 600 V, whereas an H-bridge-based
seven level inverter will require power switches rated 200 V. In
GMR Institute of Technology

addition, the dv/dt stress on the load is,

 dv/dt stress in p.u. for a seven-level waveform = lim 1/3∆
∆ →"
 Thus, dv/dt stress on the load for a seven-level waveform is one-
sixth of that of a two-level waveform.
 This concept of the synthesis of a multilevel in which multiple H-
bridges are connected in series is the CHB inverter

58
 CHB Inverter and Modulated Strategies
23-May-24
GMR Institute of Technology

Fig. One-Cell of a CHB-MLI

59
 These two legs are modulated with a sine-triangle PWM scheme as
23-May-24

shown in fig. 2.9. Observe from fig. 2.9A that a common triangular
carrier signal is used for both legs, while two out-of-phase sinusoidal
references are used. Carrier and reference waveforms are shown in
fig. 2.9B and 2.9C. Once both legs are accordingly operated, the load
voltage Vab(t) is obtained as the difference between VAO(t) and VBO(t).
The three waveforms are shown in fig. 2.10
GMR Institute of Technology

60
 GMR Institute of Technology 23-May-24

61
 GMR Institute of Technology 23-May-24

62
 GMR Institute of Technology 23-May-24

63
  If the CHB topology is composed of two "cells" as shown in fig.
23-May-24

2.11. then two carrier signals are used, one for each cell.
 These carrier signals are “phase-shifted" at an electrical angle of 90
degrees.
 The scheme and waveforms are shown in fig. 2.12.
 Both cells give a three-level output and cascading gives a five-level
PWM waveform across the load, as depicted in fig. 2.13.
GMR Institute of Technology

 If there are "n" cells in a CHB inverter, then the "phase-shifted

carrier scheme" can be extended by using carrier signals with a
phase shifting at a 180/n electrical angle

64
 GMR Institute of Technology 23-May-24

65
 GMR Institute of Technology 23-May-24

66
 GMR Institute of Technology 23-May-24

67
 GMR Institute of Technology 23-May-24

68
 Diode Clamped Multilevel Inverter
Advantages
23-May-24

· Capacitance is low.
· Back to back inverters can be used.
· Capacitors are pre charged.
· Efficiency is high at fundamental frequency,
Disadvantages
GMR Institute of Technology

· Number of clamping diodes increases with the increase of

each level.
· Dc level will discharge when control and monitoring are
not precise
Applications
· Static var compensation
· Variable speed motor drives
· High voltage system interconnections
· High voltage DC and AC transmission lines 69
 Flying Capacitors Multilevel Inverter
Advantages
23-May-24

· Static var
· For balancing capacitors’ voltage levels, phase redundancies
are available.
· We can control reactive and real power flow.
Disadvantages
GMR Institute of Technology

· Voltage control is difficult for all the capacitors

· Complex startup
· Poor Switching efficiency
· Capacitors are expansive than diodes
Applications
· Static var generation.
· Both AC-DC and DC-AC Conversion applications.
· Converters with harmonic distortion capability.
· Sinusoidal current rectifiers. 70
 Cascade H Bridge Multilevel Inverters
Advantages
23-May-24

· Capacitance is low.
· Back to back inverters can be used.
· Capacitors are pre charged.
· Efficiency is high at fundamental frequency,
Disadvantages
GMR Institute of Technology

· Every H Bridge needs a separate dc source

· Due to large number of sources, Applications are Limited
Applications
· Motor Drivers
· Active Filters
· Electric vehicle drives
· DC power source utilization.
· Power factor compensators.
· Back to back frequency link systems.
· Interfacing with renewable energy resources. 71
 GMR Institute of Technology 23-May-24

72