AMBA
AMBA
What is AMBA
• AMBA is an open-standard that outlines how to connect and manage
the different components or blocks within an SoC.
• The AMBA specification was developed by ARM and has become the
de facto standard for interfacing components in an SoC.
• While AMBA is currently on its 5 th revision and has evolved
significantly over time, legacy implementations are widely used and
remain relevant.
• Keeping that in mind, this article will use Revision 2.0 as a starting
point and build off of these ideas in a future article.
Why AMBA
• The AMBA specification was developed to solve some key problems in the
design of an SoC.
• One of these is right-first-time development, meaning that if used correctly
AMBA can ensure a coherent design from the beginning, reducing costly
redesigns.
• Another key requirement of AMBA was technological independence or
making designs reusable and agnostic to the specifics of system
components.
• With modular system design, AMBA encourages the development of
component libraries so that work done once need not be repeated. One
final motivation of AMBA was to minimize how much silicon was needed
for both on-chip and off-chip communications.
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Architecture
AMBA buses
• In Revision 2.0 three distinct buses are described for facilitating on-chip communications.
• These are the Advanced High-Performance Bus (AHB), the Advanced System Bus (ASB),
and the Advanced Peripheral Bus (APB).
• The AHB is the backbone of the system and is designed specifically for high performance,
high-frequency components.
• This includes the connections of processors, on-chip memories, and memory interfaces
among others.
• The ASB is an alternative to the AHB where some high-performance features are not
needed.
• The APB is a simplified interface designed for low bandwidth peripherals that do not
require the high performance of the AHB or the ASB.
• These include components like a UART, low-frequency GPIO, and timers.
Advanced High-Performance Bus(AHB)
• The AHB was a new addition to AMBA in revision 2.0. It was added to
accommodate high-performance designs. Some of the new features added
were split transactions, single-cycle bus master handover, single-clock-edge
operation, and wider data bus configurations, i.e., 64/128 bits.
• An AHB must contain a number of components outside of the masters and
slaves. These components are an address and control multiplexer, a read
multiplexer, a write multiplexer, a decoder, and an arbiter. Figure 2 shows
three masters connected to four slaves on an AHB. The signals shown are
the address signal (HADDR), the write data bus (HWDATA), and the read
data bus (HRDATA). The address is used for slave selection, the write data
bus is used to move data from master to slave, and the read data bus is for
moving data between slave and master.
• When a master needs to take control of the bus, it must first send a request
to the arbiter.
• The arbiter grants access based on a prioritization scheme that ensures
masters with a higher priority are given access first. This prioritization
scheme is not defined by AMBA and will differ between designs. A number
of control signals are used to define the direction, width, and type of the
data transfer. The AHB decoder receives the address signal from the master
and decodes it into slave select signals. The slave responds to the master
via an HRESP signal and the data transfer between master and slave begins.
• In total, there are about 20 different AHB signals each with a unique
purpose.
AHB signals
• Advanced Peripheral Bus
• The APB is a simplified interface for low-frequency system
components. Revision 2 simplified the bus further by having all signal
transitions synchronized to the clock's rising edge.
• The APB consists of a single bus master called the APB bridge, which
acts as a slave on the AHB/ASB. Thus, the bridge is the interface
between the high-performance bus and the low-frequency
peripherals. The peripheral devices on the APB are the slaves. Figure
4 lists the APB signal names.
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