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UDC 004.31
A.S. Shashkov

DESIGNING LOW POWER DIGITAL SYSTEMS USING UPF

TECHNOLOGY
POWER SUPPLY SUBSYSTEM DESCRIPTIONS

This review article considers the problem of designing energy-efficient digital systems. Various methods for
reducing energy consumption for such systems are indicated. The need for additional means of formal behavioral
description of the power domain subsystem is explained. Elements of the power domain subsystem, stages of
designing a digital system taking into account its division into power domains are considered. The Unified Power
Format (UPF) is presented as a means of describing the power subsystem. An example of describing a system using
this format is considered.

Introduction

The problem of designing energy-efficient (with reduced power consumption) computing

systems has always been one of the main ones in the electronic systems industry. However,
today, for a number of reasons, this problem has become more acute [1]. The need to reduce
the cost of microcircuits and increase their compactness, caused by both the widespread use of
increasingly complex mobile electronics and the need for highly efficient data processing
centers, has brought the problem of energy saving to a new level. Thus, the performance of
systems on a chip has become significantly limited by the capabilities of autonomous power
sources for mobile systems, while numerous data processing centers have become difficult and
expensive to operate and expand due to the limited resource of electrical energy [2]. One of
the urgent problems is also the design of efficient and compact heat dissipation means in both
mobile and stationary systems. Under such conditions, among all the goals of designing
computer systems, one of the first places has become an increase in productivity per unit of
dissipated power. All this has led to the active development of methods and technologies that
make it possible to reduce the energy consumption of integrated circuits while maintaining
their high performance [2–6].
This review article provides information on existing methods for reducing the power
consumption of electronic systems, but special attention is paid to one of the newest methods
for reducing power consumption - the use of a domain power system, as well as a method for
behavioral design of a power system using the means of a format specially designed for this
purpose and called Unified Power Format (UPF).

1. Overview of power consumption reduction methods for single-chip systems

The power dissipation of an integrated circuit consists of two components: dynamic power and
static power. Dynamic power is proportional to the square of the supply voltage, the switching frequency
of the elements, and the effective capacitance of the elements. Static power consumption is
characterized by the magnitude of leakage currents, which increase with an increase in the supply
voltage, a decrease in the threshold switching voltages of the transistors, and an increase in the width of
the transistors [1, 5]. On the other hand, a decrease in the supply voltage, an increase in the threshold
voltages, and a decrease in the switching frequency lead to a decrease in the computing performance of
the microcircuit.
In technological processes of manufacturing microcircuits over 90 nm, the dynamic
component of power is significantly predominant. The following methods have been developed
to reduce dynamic power [1]:
- optimization of clock signal circuits and control of clock signal transmission;
- isolation of operands;
- restructuring of logic;

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 - optimization of transistor sizes;
- use of buffers to minimize valve switching time;
- exchange of terminals (selection of terminals with the lowest capacitive load).
Research shows [1] that optimization of clock circuits can reduce dynamic power by up to
20%. The other listed methods can reduce dynamic power by up to 5% each.

Dynamic power reduction methods are effectively implemented in CAD during project
synthesis in automatic mode. Some logic optimization tasks can be solved by the developer at
the level of RTL descriptions. Thus, the use of dynamic power reduction methods assumes the
following input data:
-RTL description of the project;
- setting energy consumption optimization parameters for CAD.
With the reduction of technological processes, the threshold voltage of transistor
switching decreases, which causes a significant increase in leakage currents, and therefore an
increase in static power [3]. Modern mass technological processes for the production of
microcircuits have long since crossed the threshold of 65 nm, after which the static power of
microcircuits began to exceed the dynamic power [1]. Also, with the reduction of technological
processes, the density of the dissipated power of crystals has increased significantly [6], which
has made heat removal difficult. All this has caused an urgent need for methods that allow,
along with a decrease in dynamic power, primarily to reduce the static power of the entire
system on a crystal:
- use of several domains (crystal regions) with different voltages
Taniya;
- use of disconnectable power domains;
- dynamic change of supply voltage;
- dynamic change of the synchronization signal frequency;
- distribution of memory into blocks located in different power domains (part of the memory
can be turned off or put into data hold mode without the ability to read or write);

- use of libraries of logic gates with different switching thresholds (real-

(is used automatically in CAD);
- use of technology of biasing the voltage of the transistor substrate in high-
powerful and low power consumption (requires additional power source).
Research shows [1] that for technological processes from 65 nm and below, when combining all
modern energy-saving technologies of systems on a chip, the greatest contribution to energy
conservation is made by the technology of disconnectable power domains, which allows reducing the
average power of leakage currents by up to 50 times. Technologies for dynamically changing the supply
voltage and clock frequency allow reducing the dynamic power by up to 70%, and the static power by up
to three times.
It is not possible to effectively implement domain methods of energy saving
automatically due to the fact that, in fact, these methods are tasks of logical design of an active
domain network or tasks associated with the logical component of the project. Thus, the use of
the above methods assumes the following input data for the synthesis of the project:

-RTL description of the logical hierarchy of the project;

- description of domains and other elements of the power supply network;
- description of the control logic of the active part of the power supply network (also implemented by means of-
(we RTL).
Analyzing the input data required to describe energy-efficient systems on a chip, it can be
concluded that part of the description of an energy-efficient system can be performed using
conventional HDL (Hardware Description Language) tools, such as VHDL [7] or System Verilog
[8], supplemented by a choice of design optimization settings in CAD. However, the description
of the active power domain network and other elements of the

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It is impossible to create a variable system using only VHDL or System Verilog because these
languages were not originally designed for these purposes.This is where it came from
problemformal- description of digital system projects taking into account their energy
efficiency already at the initial stage of their design, i.e. at the level of developing the initial HDL
descriptions.

3. Elements of domain power supply systems

In general, to describe a system with controlled power supply at the behavioral level, the
following main elements can be identified [1, 9, 10].
1. Description of the logical component of the project. Directly RTL descriptions of modules,
constituting a logical part of the project hierarchy.
2. Ports and power supply chains (Supply Ports, Supply Nets).Power and ground circuits connected
to the corresponding power and ground ports, provide power for the corresponding elements
of the design: both logic elements (RTL) and energy efficiency elements have their own power
supplies. Power supply circuits can be logically characterized not only by the on/off parameter,
but also by the voltage level. Insufficient supply voltage inevitably leads to abnormal operation
of the powered component of the system.
3. Power Domains.Logical elements of the project (RTL modules) distribution
are divided into corresponding separate power domains. Domains can be logically nested in
other domains, several domains can be nested in one domain. Thus, the project will have not
only a hierarchy of RTL modules, but also a hierarchy of power domains. Dividing the system
into power domains allows you to select sections of the system with a common power strategy
(with a single set of power rules). Thus, different domains can be powered from different
power circuits with different voltages. Domains can have several different power sources: the
main one for logical elements and special ones for elements ensuring energy efficiency.

4. Power Switches.One of the elements of the nutrition strategy for

domain may be the ability to turn off all logical elements of the domain using a switch(es): in
this case, both dynamic and static energy consumption by domain elements is minimized.
Switches can also have multiple input power ports with one output power port. Power switches
are controlled by special external logical signals.

5. State Retention registers for shutdown domains.Disconnection

power supply from a memory element (register) leads to the loss of its state. Save registers
save and restore the contents of target registers during the process of switching the main
power supply on and off by control signals. Save registers have separate power sources that
are different from the main (and disconnected) power sources for the domain. Save registers
also allow you to speed up the initialization process of the module after its next switch-on.
Thus, the designer of a specific RTL module must allocate a certain subset of registers for
which save registers are required. After the next switch-on of the domain and the restoration
of data from the save registers, the normal logical operability of the subcircuits of this domain
must be guaranteed.
6. Means of isolating signals coming from disconnected domains (Isolation).In progress
When the power is turned off, all signals leaving the domain go into an undefined (floating)
state. The module receiving this signal, which is part of one of the switched-on domains, can
disrupt its logical operation due to the accidental switching of this input signal for itself. An
undesirable intermediate signal level can also lead to high current consumption on this signal
line. To solve these problems, the output signals of the switched-off domain are passed
through isolation blocks. Upon the control signal for switching on, the isolation block outputs,
instead of the input undefined signal, the output signal value specified by the developer: 0, 1, Z,
or the previously defined value of the input signal latched into the register.

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 7. Means for changing the voltage level of signals passing between domains with different
personal stress levels (Level Shifters).At the boundaries of domains with different stresses
power supply, units for changing the signal voltage level are installed. Thus, the voltage of one
for the output signal of one domain will be unambiguously perceived as the voltage of one in
any other domain with a different supply voltage that receives this signal.

8. Means of logical control of elements ensuring energy efficiency

sti.As described above, such elements of the domain power supply system as switches
Domains, domain isolation blocks, and storage registers are controlled by some special signals.
Either a separate RTL device (power management module) can be responsible for generating
these signals, or the control signals can be generated by several devices. Thus, the power
management system can be centralized or distributed, which is specified by the developer. To
transfer a domain from the on state to the off state, a certain sequence of control signals,
separated in time, may be required. Thus, first the domain must be isolated from the domains
external to it. Then it is necessary to save the contents of certain registers in the corresponding
storage registers. Only after this can a power off signal be sent to the domain power switch.
The procedure for turning on a domain must proceed in the logical reverse order: turning on
the power, possibly resetting the domain logical elements, then restoring the state of the
registers from the storage registers, then disabling the isolation blocks. Also, the sequence
controlling the change of the domain power supply mode can be supplemented with signals
for switching on and off the transmission of the synchronization signal.

8. List of energy states of the system.Energy State Management Strategy

The consumption state is characterized by a list of all possible global power states for a specific
system (“on”, “sleep”, “off”, etc.). Each power state is defined by a time-invariant set of states of
all system domains for such a global state. The state of a domain is determined by the state of
the ports and power circuits of the domain (on or off, current voltage). Changing the list of
global energy states may require changing the set of necessary elements to ensure energy
efficiency: for example, there is no need for isolation blocks between domains that are
switched off simultaneously for any global state of system energy consumption.

The above description of the system elements with division into domains assumes some isolation
and independence of the logical component of the project from the elements that ensure the operation
of the power supply subsystem. However, if the development of the logical components of the project is
carried out taking into account the subsequent implementation of the power supply into the domain
structure, then the final structure of the logical component, initially integral, can subsequently be divided
into components intended for different domains: part of the component structure can be disconnected
or can be powered from another power source.
In general, the process of developing a behavioral description of an energy-efficient
domain system can have the following stages [10].
1. Specification of logic by means of RTL and individual verification of RTL-
components.
2. Definition of power domains and distribution of logic elements in them.
3. Specification of the list of power modes.
4. Specification of the necessary elements to ensure energy efficiency for
domains (switches, isolation, storage registers, etc.).
5. Specification of control logic components (described in RTL) for the elements of the
energy efficiency baking.
6. Verification of the entire system taking into account all components, both logical and energy
sional component of the project.

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 4. Basic principles of UPF technology

The elements presented above, which allow to describe the domain structure of the project,
are, in fact, behavioral elements, describing the logical structure of the energy subsystem of the
project. This structure, in turn, is closely related to the logical component of the project: on the one
hand, the power subsystem is controlled by the logical component, on the other hand, the states of
the power subsystem elements affect the operability of the logical component of the project.
However, the current versions of the VHDL and System Verilog logic circuit design languages do
not have any special tools for describing (and therefore verifying and synthesizing) a project taking
into account power circuits. Due to the close interconnection of the logical (HDL) and energy
components, already at the behavioral level of system description, the need to introduce a special
language extension is obvious, allowing such a system to be described at the same level as RTL.

The Unified Power Format (UPF) description language (format), which solves this problem,
was first introduced in the UPF 1.0 standard [11] by the Accellera Systems Initiative in 2007. In 2009,
the IEEE supplemented the UPF format in the IEEE 1801-2009 (UPF 2.0) standard [12]. The latest
version of the standard is IEEE 1801-2013 (UPF 2.1) [13].
The UPF Description Format is a special format intended for behavioral description of the
energy component of the design of an electronic system or its components. The format
provides the ability to describe the power supply network of the project: power supply circuits,
energy domains, switches, isolation means, state saving means and other elements related to
the energy component of the project, directly specified by the developer. UPF allows formal
description of the elements of the power supply subsystem in their relationship with the logical
elements described in the VHDL and System Verilog design languages. It is important to note
that the UPF standard is not conceptually intended to describe the entire set of circuit and
electrical details of the power supply circuits required for analog simulation and verification of
the synthesized project: UPF describes the power supply structure at the behavioral level.
However, UPF descriptions in conjunction with HDL descriptions can be used as input data both
in design simulation and verification [9, 14] and in design synthesis (Fig. 1 [13]). In design
synthesis, abstract models of power subsystem objects are mapped to the corresponding
physical cells.

Fig. 1. The process of designing a system using UPF descriptions

The UPF standard describes four main components [10].

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 1.Energy component description commands (Commands).Language commandsUPF
are an extension of the Tcl scripting language [15]. A sequence of compact commands-
directives, written in a UPF description file with the extension ".upf", describes all elements of
the architecture of the energy component of the project step by step (incrementally). The key
feature of UPF descriptions is that these descriptions do not change the HDL descriptions of
the logical elements of the system in any way. Logical HDL components can still be verified
individually and separately from the energy component. On the other hand, for the same HDL
component or set of components, there can be several possible UPF descriptions for different
use cases.
2.Commands for querying information about the state of the project's energy architecture (Que-
ries).DataTcl commands that make debugging UPF descriptions easier generate detailed
reports on the state of the project's UPF elements.
3.UPF package (UPF Package).Plastic bagUPF, described for both VHDL and System Veri-
log, defines the types and functions needed to describe tests that control both the logical ports
and the power ports of the module under test. These types and functions are also used to
design HDL models that describe the behavior of the energy component of the project. Thus,
using the types and functions from the UPF package, it is possible to behaviorally describe, for
example, a specific VHDL model of a power switch whose input and output ports are power
ports along with logical ports.
The UPF package defines two main data types that allow modeling of power sources:

-state := (OFF | UNDETERMINED | PARTIAL_ON | FULL_ON).Determines the state of the

power source.
-supply_net_type := (state, voltage).Defines the state (state) food chains in aggregate
sti with voltage level (voltage).
The package defines a number of functions for managing ports and power circuits and monitoring
them.
Some functions for controlling the state and voltage of the power supply port (Supply Port)
from the test (function headers are shown in C-like pseudocode):
-supply_on(string port_name, real voltage);
-supply_off(string port_name).
Some functions of power port status and voltage polling:
-get_supply_value(string port_name), returns typesupply_net_type;
-get_supply_state(supply_net_type arg), returns typestate;
-get_supply_voltage(supply_net_type arg), returns typevoltage.
4.SAIF format (Switching Activity Interchange Format).The format is intended for standard-
customization of the representation of the information on the switching activity of elements
generated by the simulator at the end of the simulation (the result is placed in the "reverse"
backward-SAIF file). This file represents the input data for the software tools for analyzing and
optimizing energy consumption. The design automation program can pre-generate a "direct"
forward-SAIF file containing some directives that define the content of the output backward-
SAIF file. It is important to note that the SAIF format, which is part of the IEEE 1801 standard, is
only a typical template for representing the information on switching activity, while the IEEE
1801 standard does not define algorithms or rules for efficiently determining the actual
switching activity: this task is beyond the scope of this standard. It is assumed that during the
development of a block, a test input sequence will be developed that will correspond to the
typical operating conditions of this block; after the end of this sequence, a SAIF-compliant CAD
system should generate the information on switching activity in the form of a SAIF file. This
information will allow us to assessdynamicthe power dissipated by the unit, usinganySAIF-
compatible software package for energy analysis and optimization.

The most important feature of the process of simulating a project with UPF descriptions is that all
HDL domain logic processes with the main power turned off are terminated in a special way.

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simulation processes occur: the contents of the registers become undefined, and all internal
and output signals along the chain go into an undefined state (X).
Today, UPF technology is supported in all leading automated design and simulation
systems from companies such as Mentor Graphics, Synopsys, Cadence Design Systems and
others. However, at the moment, UPF is not the only supported language for describing
energy-efficient systems: the UPF standard competes with the Common Power Format
standard [16], which largely coincides with UPF, but also has some differences from UPF [3, 17].

5. UPF Command Groups

IEEE 1801-2013 [13] standard contains a comprehensive description of UPF commands with
examples of their use, however, for a better understanding of the capabilities of the UPF format, it is
advisable to analyze these commands and group them by semantic purpose. Thus, the commands for
describing the energy component of the project (Commands) of the UPF standard can be conditionally
divided by functional purpose into the following groups (Fig. 2) [10].
Navigation commands determine which partThe following UPF commands will be related to the HDL
hierarchy of the project.
Domain Commands are used to segment the project into separate power supply areas.
defined by a set of logical components (RTL component instances) and a set of main and
special power supplies.
Commands for describing permitted states energy consumption is used for automation
verified verification of the energy system.
Strategy Description Commands define the rules for placing and managing elements isolation
and elements for changing the voltage level of signals at the boundary of the power domain, rules
for the placement and control of state-preserving elements within the power domain.
Implementation Teams define how abstract behavioral elements Power subsystems are
mapped to specified library cells of power elements during the automatic synthesis of the
project.
HDL Interfacing Commands allow you to add to the projectUPF-aware assertions and
these instructions are intended for operations of converting power port types to HDL logic
types and vice versa.
Simulation status commands (Simstate commands) have been added to UPF 2.0 to expand the
capabilities for detailed definition of the status of simulation objects (partially operational states of
domains and power networks have been added).

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 Navigation commands: Chain Group Commands
Code management commands:
- set_scope power supply: Implementation commands:
- upf_version
- set_design_top - create_supply_set - map_retention_cell
- load_upf
- associate_supply_set - map_isolation_cell [x]
- save_upf
Power Network Commands: - connect_supply_set - map_level_shifter_cell [x]
- load_upf_protected
- create_supply_port - set_equivalent [2.1] - map_power_switch_cell
- load_simstate_behavior
- create_supply_net - set_port_attributes - use_interface_cell
- find_objects
- connect_supply_net - set_design_attributes - begin_power_model [2.1]
- create_power_switch
- end_power_model [2.1]
Strategy Teams: HDL interfacing commands:
- apply_power_model [2.1]
Domain commands: - set_repeater [2.1] - bind_checker
- create_power_domain - set_retention_elements - create_hdl2upf_vct
Definition commands
- set_domain_supply_net [x] - set_retention - create_upf2hdl_vct
elements [2.1]:
- create_composite_domain - set_retention_control [x]
- define_always_on_cell
- set_isolation Control logic commands:
- define_diode_clamp
- set_isolation_control [x] - create_logic_port
State commands: - define_isolation_cell
- set_level_shifter - create_logic_net
- add_port_state - define_level_shifter_cell
- connect_logic_net
- create_pst Status commands - define_power_switch_cell
- add_pst_state simulations: Designations: - define_retention_cell
- add_power_state - add_power_state [2.1] : only for UPF 2.1
- describe_state_transition - set_simstate_behavior [x] : removed in UPF 2.1

Fig. 2. UPF Command Groups

Power Chain Group and Attribute Commands (Supply-Sets commands) have been added to UPF 2.0 to
optimize the description and connection of power networks.
Control logic description commands added toUPF 2.0 for certain modeling situations where it
is more convenient to describe the logical signals for controlling the elements of the energy
component of the project within UPF files instead of HDL files (the commands are not intended to
completely replace HDL descriptions).
It is important to note that some of the commands introduced or supplemented in UPF 2.0
replace in functionality some obsolete commands from the subset of commands introduced in UPF
1.0. In UPF 2.1, these obsolete commands are completely excluded, and therefore full backward
compatibility with previous versions is impossible. Due to the novelty of the UPF 2.1 standard, UPF
2.0 [10] can be considered the current version; however, it is highly recommended not to use UPF
2.0 commands excluded from UPF 2.1.

6. Example of project development using UPF technology

To demonstrate the principles of designing an energy-efficient system using UPF descriptions, a

demonstration project was developed. The RTL description files (System-Verilog files upf_demo.sv and
tb.sv) and the UPF description (upf_demo.upf), as well as the run script file “run.do” for the Mentor
Graphics QuestaSim 10.2 environment [18] are available at the link [19]. The diagram of the original
project without the energy component is shown in Fig. 3. The diagram of the project taking into account
the energy component is shown in Fig. 4. The methodology presented in Section 3 was used in
developing the project. Modeling of the project taking into account the energy component was carried
out at the behavioral level.
Here and below, a register is understood as a memory element of arbitrary bit capacity.
The basis of an energy-efficient electronic system is the hierarchy of its logical part, which
is distributed in some optimal way into separate domains with different power supply
strategies. The logical structure of the original project (without the energy component - the
power supply system) is represented by the modulesource_design(copy)
source_design_instance) and the components nested in it (Fig. 3). The module was chosen as the main
logical component of the demonstration project.sum_acc, which at the front of the synchronization signal
en=1 adds the input data of the portinto the current contents of the internal go registeracc[7:0]. Contents
of the registeraccis brought out to the portout[7:0]. Conclusionen_delayis- with the input port value
delayed by one clock cycleen(internal registeren_d). Module instancessum_acc sum_acc_0Andsum_acc_1
are placed in a cascade, where the output issum_acc_0.outunder-
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connected to the input portininstancesum_acc_1, and the output portsum_acc_0.en_delayconnect
chen (via AND gate) to input porteninstancesum_acc_1. Multiplexermux_0by sig- nalu from the port
source_design_instance.modeselects (via portmux_0.sel), exitoutwhich one copiessum_accwill be
directed to the general conclusionsource_design_instance.out[7:0].

Fig. 3. Logical diagram

Thus, whensource_design_instance.mode=1 and after changing the registeracceczema- plyara

sum_acc_0in the next measure in view ofw_en_delay=1 register valueaccinstance sum_acc_1will be
increased by the next register valuesum_acc_0.acc, and the new meaning sum_acc_1.accwill be
submitted for withdrawalsource_design_instance.out.
In modesource_design_instance.mode=0, at which the outputsource_design_instance.out the
value is passedsum_acc_0.out, the AND element to which is connected tosum_acc_0.en_delay,
ensures that the register state is savedsum_acc_1.acc. Thus, in the modemode=0 instancesum_acc_1
is not fully involved, which meanssum_acc_1is a special case of com- component that can be
disconnected from the power supply in one of the operating modes (provided that the contents are
preserved)sum_acc_1.acc).
After receiving the main logical part of the RTL description of the project, presented in the
modulesource_designin Fig.3 (and additional conditions for its functioning) the project can be
divided into the following domains (Fig. 4): the switched-off domainPD_sw, containing an
instance sum_acc_1, and a domain that cannot be switched offPD_top, containing all other
logical components source_design. For demonstration purposes (to ensure the need to install
signal level change units), the power domains of the project with an energy component use
different power supply voltage sources: 1.0 V forPD_top(power portVDD_1) and 2.0 V for PD_sw
(power portVDD_2). ForPD_swpower switch (key) is presentedsw_2with power output port
SW_OUT. Key input portSW_INpowered by voltage2.0 V (VDD_2).SW_OUTis the main source of
nutrition forPD_sw, AVDD_1is the main power source forPD_top. Both domains share a
common earth port.GND.
After selecting the system power domains, it is necessary to compile a table of all possible
simultaneous states of the system domains (table 1). According to the table of all permissible power
states, expressed through the states of the power ports, it is possible to select a complete set of
necessary elements for ensuring energy efficiency: isolation units, storage units, signal voltage level
change units, and synchronization signal shutdown units. Switching off the power circuits in the
table also signals the need to set the power switches.
In FULL_ON power mode, domainsPD_topAndPD_sware fed from various sources supply
voltage. For the correct interpretation of the logical signals connecting these domains (“ON 1.0
V” → “ON 2.0 V” and “ON 2.0 V” → “ON 1.0 V”), it is necessary to introduce blocks for changing
the signal voltage level for both input and output signals.PD_sw (ls_pd_sw_inAndls_pd_sw_outin
Fig.4). The inputs and outputs of the signal level change modules are powered from power
supplies.VDD_1AndVDD_2in accordance with the direction of the level change signal voltage
(Fig. 4).

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 Table 1
Power States

States VDD_1 VDD_2 sw_2/SW_OUT GND

nutrition
(PD_top) (PD_sw)

FULL_ON ON 1.0 V ON 2.0 V ON 2.0 V ON 0 V

PART_ON ON 1.0 V ON 2.0 V OFF ON 0 V

FULL_OFF OFF OFF OFF ON 0 V

In the system power mode PART_ON domainPD_swis in a disabled state (OFF). According
to the above requirements, the state of all internal registers of the module sum_acc_1must be
saved, therefore in the domainPD_swIt is necessary to add registers for saving nia for
sum_acc_1.accAndsum_acc_1.en_d(pd_sw_retin Fig.4) The save registers are powered from the
enabled power port.VDD_2.
In the PART_ON system power mode, domain signalsPD_topare transmitted to the
disconnected domainPD_sw. To avoid negative effects from such a connection, the output port
sum_acc_1.outconnected to the isolation block (signal from the portsum_acc_1.outis forced in the
meaning (which preceded the inclusion of isolation). Output portsum_acc_1.en_delayis not
connected, which means it does not require isolation. The isolation units are powered from the port
VDD_1.
Due to the instance not being usedsum_acc_1in modePART_ON, synchronization signalclk
for this component is disabled using the disable blockclk_gate_0(RTL sync signal pass-through
cut-off circuit with latch).

VDD_1 PD_top
1.0 V vdd_1_n
GND gnd_n
0V
upf_demo: dut clk_gate_0 VDD_1, VDD_2
clk_gate VDD_1 PD_sw Level shifters power connections
clk_in ls_pd_sw_in ls_pd_sw_in
w_gated_clk
clk_out
en_n sum_acc_1 VDD_1 VDD_2
sum_acc SW_VDD_2 ls_pd_sw_out
clk
sum_acc_0 ls_pd_sw_in pd_sw_ret VDD_2 VDD_1
reset_n en_delay
sum_acc VDD_1w_en_delay pd_sw_iso mux_0
cl &en_1 en regs VDD_2
clk ls_pd_sw_out muxVDD_1
k out[7:0
in[7:0] in_1[7:0]
reset_n reset_n en_delay ]
VDD_1 EN out
en en SW_VDD_2 VDD_2 GND VDD_1 out[7:0]
w_out_0
in[7:0] in[7:0] out[7:0] in_0[7:0]
sw_vdd_2_n gnd_n vdd_1_n
mode sel
sw_2 SW_OUT
power_control_0 SW_DIS

power_controlVDD_1
w_iso_en SW_IN
reset_n iso_en
clk w_d1_sw_disable
d1_sw_disable vdd_2_n
mode w_ret_save
ret_save
mode_req mode_req w_ret_restore
ret_restore
mode_ack mode_ack

VDD_2

2.0 V

Fig. 4. Logic diagram taking into account the added power supply system

Once all the power switches, isolation elements, and storage blocks, as well as clock
signal disable blocks, have been defined for the project, the logic for controlling these elements
must be described using RTL. Modulepower_control_0, shown in Fig. 4,
10
is a power supply control module for everythingupf_demo:dut. On signalmode_req component
state machinepower_control_0starts, according to the table1, change the state of the power
switch off signalw_d1_sw_disable, inclusions of insulation w_iso_enand signalsw_ret_saveAnd
w_ret_restoreto save and restore data in blocks saving. In the process of disabling the domain
PD_swThe power management module is first turned on it isolates, then saves the data to the
save registers and only then turns it offsw_2. Upon completion of the power mode change
process, the module signalsdut.mode_ack=1. The process of inclusionPD_swgoes in reverse
order taking into account the restoration of register states sum_acc_1from the storage
registers. To simplify the circuit, the synchro- chronosignalw_gated_clksignal selectedw_iso_en
It is important to note that for real projects, the domain switching on and off sequences can
take a long time due to the inertia of the real physical components of the power supply system
(this is not taken into account in the example for simplicity).

The next step is a formal behavioral description of the information obtained above about the
energy component in the UPF language. The result of the behavioral design (description) of the
domain system for the demonstration project is presented in the file upf_demo.upf [19], this file
with explanations is shown in Fig. 5. It is important to note that in the RTL description of the module
upf_demo:dut(fileupf_demo.sv) signalsw_d1_sw_disable,w_iso_en,w_ret_saveAndw_ret_restore,
coming out of the modulepower_control_0, are not connected, but these signals are clearly
connected to the corresponding energy efficiency elements already in the upf_demo.upf file.

11
# Define the main module: set_design_top # Creating a strategy for automatic
upf_demo # adding input for PD_sw change blocks
set_scope . # voltage level signals: set_level_shifter
ls_pd_sw_in \
- domain PD_sw \
# Create domain PD_top: all elements of the main module
- applies_to inputs \
- rule low_to_high \
# PD_top are enabled: - location itself
create_power_domain PD_top \
- include_scope # Connecting power to input change blocks
# Create domain PD_sw, # voltage level signals: associate_supply_set
# transfer sum_acc_1 to PD_sw domain: pwr_1_ss \
create_power_domain PD_sw \ - handle PD_sw.ls_pd_sw_in.input
- elements {sum_acc_1} associate_supply_set pwr_2_ss \
- handle PD_sw.ls_pd_sw_in.output
# Creating a strategy for automatic
# Create power ports:
# adding output for PD_sw change blocks
create_supply_port VDD_1
# voltage level signals: set_level_shifter
create_supply_port VDD_2 ls_pd_sw_out \
create_supply_port GND - domain PD_sw \
- applies_to outputs \
# Create supply chains: - rule high_to_low \
create_supply_net vdd_1_n \ - location parent
- domain PD_top # Connecting power to the output blocks of changes
create_supply_net vdd_2_n \ # voltage level signals: associate_supply_set
- domain PD_top pwr_2_ss \
- handle PD_sw.ls_pd_sw_out.input
create_supply_net gnd_n \
associate_supply_set pwr_1_ss \
- domain PD_top
- handle PD_sw.ls_pd_sw_out.output

# Connecting power circuits to ports: # Creating a strategy for adding insulation blocks
connect_supply_net vdd_1_n \ # with precise indication of the elements to be isolated:
- ports VDD_1 set_isolation pd_sw_iso \
connect_supply_net vdd_2_n \ - domain PD_sw \
- ports VDD_2 - clamp_value latch \
connect_supply_net gnd_n \ - isolation_signal w_iso_en \
- ports GND - isolation_sense high \
- location parent \
- elements {sum_acc_1/out}
# Grouping power supply chains into the pwr_1_ss set:
# Connecting power to the isolation blocks:
create_supply_set pwr_1_ss \
associate_supply_set pwr_1_ss \
- function {power vdd_1_n} \ - handle PD_sw.default_isolation
- function {ground gnd_n}
# Assigning group pwr_1_ss to # Creating a strategy for automatic addition
# as the main power supply for PD_top: associate_supply_set # save blocks for all registers
pwr_1_ss \ # PD_sw domain (RTL signal control
- handle PD_top.primary # w_ret_save and w_ret_restore):
set_retention pd_sw_ret \
# Grouping power supply chains into the pwr_2_ss set: - domain PD_sw \
- save_signal {w_ret_save posedge} \
create_supply_set pwr_2_ss \
- restore_signal \
- function {power vdd_2_n} \
{w_ret_restore posed}
- function {ground gnd_n} # Connect power to save registers: associate_supply_set
pwr_2_ss \
# Create a group of power chains - handle PD_sw.default_retention
# to connect to PD_sw: create_supply_net
sw_vdd_2_n \ # Defining Power Port States
- domain PD_top # (according to table 1):
create_supply_set sw_pwr_2_ss\ add_port_state VDD_1 \
- function {power sw_vdd_2_n} \ - state {ON_1 1.0} \
- state {OFF_ST OFF}
- function {ground gnd_n}
add_port_state VDD_2 \
# Assigning the sw_pwr_2_ss group as
- state {ON_2 2.0} \
# main supply set for PD_sw: associate_supply_set - state {OFF_ST OFF}
sw_pwr_2_ss \ add_port_state sw_2/SW_OUT \
- handle PD_sw.primary - state {ON_2 2.0} \
- state {OFF_ST OFF}
# Create a model of the sw_2 key managed by add_port_state GND \
# RTL signal w_d1_sw_disable: - state {ON_0 0}
create_power_switch sw_2 \ # Description of table 1 in UPF format (table
- domain PD_sw \ # used to verify the block's operation
# power management):
- input_supply_port \
create_pst DEMO_PST \
{SW_IN pwr_2_ss.power} \
- supplies {VDD_1 VDD_2 sw_2/SW_OUT GND}
- output_supply_port \ add_pst_state FULL_ON -pst DEMO_PST \
{SW_OUT sw_pwr_2_ss.power} \ - state {ON_1 ON_2 ON_2 ON_0}
- control_port \ add_pst_state PART_ON -pst DEMO_PST \
{SW_DIS w_d1_sw_disable} \ - state {ON_1 ON_2 OFF_ST ON_0}
- on_state \ add_pst_state FULL_OFF -pst DEMO_PST \
{ON_STATE SW_IN {!SW_DIS}} \ - state {OFF_ST OFF_ST OFF_ST ON_0}
- off_state {OFF_STATE {SW_DIS}}

Fig. 5. Description of the energy component of the project (upf_demo.upf)

12
 Fig. 6. Project simulation timing diagram

The demo project was simulated at the behavioral level in the Mentor Graphics QuestaSim
10.2 environment in the Power Aware Simulation mode [20]. The timing diagram of the project’s
operation is shown in Fig. 6. During the test (System-Verilog file tb.sv [19]), the system worked as
part of a full cascade (all domains are on). After that, a request was sent to turn off the domain
PD_sw(signalmode=0 → 1,mode_req=1), after which the system worked with the sum_acc_1 module
disconnected from power supply. Registerssum_acc_1.accAndsum_acc_1.en_d were also
disconnected from the power supply (shown in the diagram by the diagonal grid). Before the power
was disconnected, the state of these registers was saved by the signalw_ret_save, and after
switching on the states were restored by a signalw_ret_restore. Solid transparent fill for signal from
portsum_acc_1.outThe diagram shows the inclusion of isolation: output sum_acc_1.outisolated from
all registry changessum_acc_1.accin the process of switching on and off power on.

This section considers a demonstration project, the main logic of which was designed in
such a way as to determine the possibility of dividing the project into power domains, where
one of the power domains was made disconnectable. The system was divided into specific
power domains with different supply voltages, all possible states of these domains were
determined via power networks. A list of all power switches, isolation units, signal level storage
and change units was obtained from the state table. After that, a formal behavioral description
of the energy subsystem of the project was developed in the form of a UPF file. The timing
diagram obtained in the simulation environment shows the specifics of signal changes when
switching the energy states of the project.
Further development of the project involves the synthesis of RTL logic and mapping of
abstract models of power switches, isolation, save and level change registers onto real physical
library cells (UPF implementation commands “map_-”). It is important to note that the effect of
dividing the system into domains with different power sources, some of which are
disconnectable, can only be assessed after synthesizing the project using specific libraries of
logic elements. Indeed, for the demo shown,

13
of the project, the leakage current energy saved during the domain shutdownPD_swfor some
from the results of the synthesis may be less than the energy spent on the continuous
operation of the control modulepower_controland other elements to ensure energy efficiency,
which were added to the system to manage the domain being switched offPD_swHowever, in
real systems, the power domains that can be switched off typically contain many more logic
components, while the cost of supporting and managing the power domains remains
insignificant [2]. The general design methodology for real projects will be consistent with the
methodology shown in this demonstration project.

Conclusion

The article considers the problem of designing energy-efficient electronic systems and specifies
various methods for reducing the energy consumption of such systems. Designing systems with an
active domain power supply system is indicated as one of the most effective measures to reduce energy
consumption for systems on a chip manufactured using modern technological processes. The need for
additional means of behavioral description of the domain power supply subsystem is shown due to the
insufficient capabilities of the VHDL and System Verilog languages. The article considers the elements of
the domain power supply subsystem, considers the stages of designing an electronic system taking into
account the division into power domains. The UPF format is considered as a means of describing the
power subsystem, an example of describing a system using the tools of this format is considered. In the
example of a circuit with separate power domains, it was shown how the original RTL description of the
logical structure of the project can be supplemented with elements of the domain power supply system
using the tools of the UPF format. Modeling of the demonstration project was carried out in a UPF-
compatible CAD system taking into account the operation of the power supply system components.

The UPF format helps to describe systems with an active domain power system, but the
allocation of power domains and the management of power domains in a system is a complex
scientific and engineering task that lies on the shoulders of developers [2]. Thus, for modern
technological processes of microcircuit production, many existing complex computing blocks
can be divided into separate power domains, which will require a thorough revision of the
structure of such components for maximum energy savings. Thus, the UPF format is a tool that
can significantly simplify the design process of the newest class of digital systems - systems
with an active domain power system.

References

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United Institute of Informatics Problems of the National Academy of Sciences of Belarus, Minsk, st. Surganova, 6 e-
mail: [email protected]

A.S. Shashkov

DESIGN OF LOW-POWER ELECTRONIC SYSTEMS USING UPF

POWER INTENT SPECIFICATION TECHNOLOGY

In this overview paper, the problem of the design of energy-efficient electronic systems is surveyed.
Different energy-saving methods are mentioned. The necessity of additional means of formal behavioral
description of the power subsystem of a design is explained. The elements of the power domains energy
subsystem are explained, the design stages for the system with power domains are presented. Unified Power
Format (UPF) is observed as the means to describe power intent in a low-power system, a demonstration
design example with the UPF-description is presented.

15