Department of Electrical and Computer Engineering

Pipelined ADC Design

- A Tutorial -

Based on Slides from Dr. Bibhudatta Sahoo

University of Illinois at Urbana-Champaign

Slides by Bibhudatta Sahoo -1-

 Outline

 Review of Pipelined ADCs

 Impact of Scaling on Data Converter Design
 Why Calibration?
 Basics of Digital Calibration Techniques
 Survey of Digital Calibration Techniques
 Conclusion

Slides by Bibhudatta Sahoo -2-2

 Introduction

 Data Converter Design is challenging in Nanoelectronics Era:

 Low intrinsic device gain
 High nonlinearity
 Reduced headroom (reduced dynamic range)
 Large variability and mismatches
 Survival in digital-driven system-on-chip (SOC) environment
 Trends in data converter design
 Digitally Assisted Analog Design
 Fuelled by aggressive device scaling

Slides by Bibhudatta Sahoo -3-3

Pipeline ADC
- Review -

Slides by Bibhudatta Sahoo -4-

4
 Generic Pipelined ADC

Stage-1 Stage-2 Stage-M

·
+ ·
+ · · · ·
+ Flash
VIN 2 N1 2N2 2NM ADC
- - -

sub-ADC · sub-DAC sub-ADC · sub-DAC sub-ADC · sub-DAC

(N1+1)-bits (N2+1)-bits N(M+1)-bits

(NM+1)-bits
D2 DM
D1

-N1 -N2 -NM

2 2 2

Digital Combiner
(N1 + N2 + …+ NM)-bits
DOUT

 Each stage resolves a small number of bits (i.e. N1, N2, …, NM bits).
 The overall resolution of the ADC is P = (N1+N2+…+NM+NM+1).
 Output of stage-i (called “residue” ri) is digitized to (P- ij=1 Nj)-bits.
 The low resolution ADC digitizing ri is called the backend of stage-i.

Slides by Bibhudatta Sahoo -5-5

Switched-Capacitor (SC) Circuit – An Overview (1)

 Key building blocks:

 Switches
 Capacitors
 Op amp
 Two-phase non-overlapping
clock generator

 Sample/Reset phase  1 is high  Switches S1 to S4 are controlled by 1, i.e. S1 to S4

close when 1 is high.
 It is called sample-phase as input signal is sampled.
 It is also called reset-phase as opamp is reset (more later).
 Hold/Amplification phase 2 is high  Switches S5 to S7 are controlled by 2, i.e. S5
to S7 close when 2 is high.
 Vout is an amplified and held version of the sampled Vin.

Slides by Bibhudatta Sahoo -6-

6
 Switched-Capacitor (SC) Circuit – An Overview (2)

 Falling edge of 𝟏 samples the input, 𝑽𝒊𝒏𝟏 and 𝑽𝒊𝒏𝟐.

 In 2 the sampled values get amplified to give 𝑽𝒐𝒖𝒕𝟏 & 𝑽𝒐𝒖𝒕𝟐, respectively.
 During 𝟏 the sampled charge is 𝑸𝑺 = 𝑪𝑺 𝑽𝒊𝒏 .
 During 𝟐 the charge is 𝑸𝑯 = 𝑪𝑭 𝑽𝒐𝒖𝒕 .
𝑪𝑺
 Since charge is conserved, 𝑸𝑺 = 𝑸𝑯 ⟹ 𝑽𝒐𝒖𝒕 = 𝑽 .
𝑪𝑭 𝒊𝒏

 The gain of the circuit is the ratio of the sampling capacitor (𝑪𝑺 ) to feedback capacitor (𝑪𝑭 ).

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7
 Switched-Capacitor Comparator

𝚽𝟐

 During 1 the sampled charge 𝑸𝑺 = 𝑪𝒊𝑭 𝑽𝒊𝒏 .

 Since charge is conserved the charge during 2 is given by 𝑸𝑯 = 𝑪𝒊𝑭 𝑽𝑻𝑯𝒊 − 𝑽𝑿
resulting in 𝑽𝑿 = 𝑽𝒊𝒏 − 𝑽𝑻𝑯𝒊 .
 When the comparator is clocked with the falling edge of 2 it makes a decision
based on whether Vin > VTHi or Vin < VTHi.

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8
 Switched-Capacitor 4-bit Flash
 A 4-bit flash incorporates 15 switched capacitor
comparators.
 The threshold voltages VTH1 to VTH15 are generated by a
resistor ladder comprising of 16 equal resistors.
 The outputs of the comparator give a 15-bit wide
thermometer code which controls the DAC of the MDAC.
𝑻𝟏
 The thermometer code is converted to 4-bit binary code
𝑽𝑻𝑯𝟏
𝚽𝟐 using an on-chip look-up table, also called read-only-
memory (ROM).

Note: A switched capacitor N-bit flash would

𝑻𝟏𝟓 incorporate 2N-1 switched capacitor comparators and
a resistor ladder comprising 2N resistors to generate
𝚽𝟐 the 2N-1 threshold voltages, 𝑽𝑻𝑯𝟏 to 𝑽𝑻𝑯𝟐𝑵−𝟏 .
𝑽𝑻𝑯𝟏𝟓

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Switched-Capacitor MDAC (1)

 An M-bit MDAC incorporates 2M unit

capacitors (Ci , i=1 to 2M), feedback
capacitor CF, switches, and an op amp.
 This block does the following operations:
 1 is high (Sample phase/Reset phase):
 Sampling of input
 2 is high (Amplification phase):
 Digital-to-Analog Conversion (DAC)
 Subtraction  quantization noise generation
 Amplification (Multiplying)  scaling of the
quantization noise to the full-scale for the
later stages to digitize to relax the sensitivity
requirements of the later stage circuits.

Note: A switched capacitor 4-bit flash would incorporate 24

unit capacitors.

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Switched-Capacitor MDAC (2)

 During sample phase the sampled charge is,

𝟐𝑴

𝑸𝒔 = 𝑪𝒊 𝑽𝒊𝒏
𝒊=𝟏
 During amplification phase the charge is given
by,
𝟐𝑴 −𝟏

𝑸𝒂 = 𝑻𝒊 𝑪𝒊 𝑽𝑹 + 𝑪𝑭 𝑽𝒓𝒆𝒔
𝒊=𝟏

 By conservation of charge we get,

𝟐𝑴 𝟐𝑴 −𝟏
𝒊=𝟏 𝑪𝒊 𝑽𝒊𝒏 − 𝒊=𝟏 𝑩𝒊 𝑪𝒊 𝑽𝑹
𝑽𝒓𝒆𝒔 =
𝑪𝑭
where, Bi=1 if Ti=1 and Bi=1 if Ti=0.
 If CF = Ci then gain  2M, if CF = 2Ci then gain  2M-1.

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 Sources of Errors in Pipelined ADC
Stage-1 Stage-2 Stage-M

·
+ ·
+ · · · ·
+ Flash
VIN 2 N1 2N2 2NM ADC
- - -

sub-ADC · sub-DAC sub-ADC · sub-DAC sub-ADC · sub-DAC

(N1+1)-bits (N2+1)-bits N(M+1)-bits

(NM+1)-bits
D2 DM
D1

-N1 -N2 -NM

2 2 2

Digital Combiner
(N1 + N2 + …+ NM)-bits
DOUT

 Comparator Offset  Op Amp Nonlinearity

 Capacitor Mismatch  Op Amp Offset
 Op Amp Gain  Charge Injection Mismatch
 Op Amp Input Capacitance  Op Amp and kT/C Noise

Slides by Bibhudatta Sahoo -12-

12
 Comparator Offset

Missing
Levels
Missing
Codes
 Comparator offset saturates the later stage.
 Redundancy can overcome this.
Slides by Bibhudatta Sahoo -13-
13
Overcoming Comparator Offset (1)

CF = Ci , M=3  No redundancy

𝟐𝑴 𝟐𝑴 −𝟏
𝒊=𝟏 𝑪𝒊 𝑽𝒊𝒏 − 𝒊=𝟏 𝑩𝒊 𝑪𝒊 𝑽𝑹
𝑽𝒓𝒆𝒔 =
𝑪𝑭
If CF = 2Ci then gain  2M-1
resulting in comparator
offset tolerance of VREF/2M.
CF = 2Ci , M=3 Redundancy

Slides by Bibhudatta Sahoo -14-

14
Overcoming Comparator Offset1.5-bit Architecture
+VREF

V
 REF
2
VREF
´
4
Offset
0 Correction
Range
VREF
´ Flip-around Topology VOUT
4
V +VREF
 REF
2

𝑪𝑺 + 𝑪𝑭 𝑽𝑰𝑵 − 𝒌𝑪𝑺 𝑽𝑹𝑬𝑭

𝑽𝑶𝑼𝑻 = VIN
𝑪𝑭 -VREF +VREF
-VREF
where, 𝒌 = ±𝟏, 𝟎
𝑽𝑹𝑬𝑭 𝑽𝑹𝑬𝑭
− +
𝟒 𝟒
-VREF
Ref: S. Lewis et al, “A 10-b 20-MS/s Analog-to-Digital Converter,” IEEE JSSC., pp. 351-358, March 1992
Slides by Bibhudatta Sahoo -15-
15
Overcoming Comparator Offset1.5-bit Architecture
+VREF

V
 REF
2
VREF
´
4
Offset
0 Correction
Range
VREF
´ Non-Flip-around Topology VOUT
4
V +VREF
 REF
2

𝑪𝑺
𝑽𝑶𝑼𝑻 = 𝑽𝒊𝒏 − 𝒌𝑽𝑹𝑬𝑭
𝑪𝑭 VIN
-VREF where, 𝒌 = ±𝟏/𝟐, 𝟎 -VREF +VREF

𝑽𝑹𝑬𝑭 𝑽𝑹𝑬𝑭
− +
𝟒 𝟒
-VREF

Slides by Bibhudatta Sahoo -16-

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 Capacitor Mismatch

M=2, i.e., 2-bit stage

Missing
Capacitor Levels
mismatch Missing
𝟐𝑴 𝟐𝑴 −𝟏
𝒊=𝟏 𝑪𝒊 𝑽𝒊𝒏 − 𝒊=𝟏 𝑩𝒊 𝑪𝒊 𝑽𝑹𝑬𝑭 Codes
𝑽𝒓𝒆𝒔 =
𝑪𝑭
where, Bi=1 if Ti=1 and Bi=1 if Ti=0
17
Slides by Bibhudatta Sahoo -17-
 Finite Op amp Gain

M=2, i.e., 2-bit stage

𝟐𝑴 𝟐𝑴 −𝟏 Finite op Missing
𝒊=𝟏 𝑪𝒊 𝑽𝒊𝒏 + 𝒊=𝟏 𝑩𝒊 𝑪𝒊 𝑽𝑹𝑬𝑭
𝑽𝒓𝒆𝒔 = 𝑴
amp gain Codes
𝑪𝑭 + 𝑪𝑷 + 𝟐𝒊=𝟏 𝑪𝒊
𝑪𝑭 +
𝑨
where, Bi=1 if Ti=1 and Bi=1 if Ti=0
and A=

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 Op amp Nonlinearity (1)

• Weakly nonlinear op amp open-loop input-output

characteristic can be given by a 3rd order polynomial,
𝑽𝑶𝑼𝑻 = 𝜶𝟏 𝑽𝒊𝒏 + 𝜶𝟐 𝑽𝟐𝒊𝒏 + 𝜶𝟑 𝑽𝟑𝒊𝒏
• The inverse can be given by another polynomial
𝑽𝒊𝒏 = 𝜷𝟏 𝑽𝒐𝒖𝒕 + 𝜷𝟐 𝑽𝟐𝒐𝒖𝒕 + 𝜷𝟑 𝑽𝟑𝒐𝒖𝒕
𝟏 −𝜶𝟐 𝟐𝜶𝟐𝟐 𝜶𝟑
where, 𝜷𝟏 = , 𝜷𝟐 = , and 𝜷𝟑 = −
𝜶𝟏 𝜶𝟑𝟏 𝜶𝟓 𝜶𝟒𝟏
B. Sahoo and B. Razavi, IEEE JSSC, vol. 44, pp. 2366-2380, Jan. 2009.
19
Slides by Bibhudatta Sahoo -19-
 Op amp Nonlinearity (2)

M=2, i.e. 2-bit stage

Missing
Codes
 The input-output characteristic of the MDAC can be obtained by
solving the following non-linear equation:
𝟐𝑴 𝟐𝑴 −𝟏 𝟐𝑴
 𝒊=𝟏 𝑪𝒊 𝑽𝒊𝒏 = 𝒊=𝟏 𝑪𝒊 𝑽𝑹𝑬𝑭 + 𝑪𝑭 𝑽𝒓𝒆𝒔 − 𝜷𝟏 𝑽𝒐𝒖𝒕 + 𝜷𝟐 𝑽𝟐𝒐𝒖𝒕 + 𝜷𝟑 𝑽𝟑𝒐𝒖𝒕 𝑪𝑭 + 𝑪𝑷 + 𝒊=𝟏 𝑪𝒊

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20
Thermal Noise Consideration (1)

 Signal-to-noise ratio of an ADC is given by,

𝑷𝒔𝒊𝒈
𝑺𝑵𝑹 = 𝟏𝟎𝒍𝒐𝒈𝟏𝟎 𝑸𝑵 +𝑵𝑻
where,
𝑽𝟐𝒑−𝒑 𝑽𝒑−𝒑
 Psig = signal power = (for input 𝑽𝒊𝒏 = 𝒔𝒊𝒏 𝟐𝝅𝒇𝒕 )
𝟖 𝟐
𝜟𝟐
 𝑸𝑵 = ,
𝟏𝟐
 𝑵𝑻 = Input referred thermal noise power of the ADC
𝑽𝒑−𝒑
 𝜟 = 𝟐𝑵 , where N = ADC resolution.
 SNR of Semiconductor ADCs are limited by thermal noise of:
 Switches
 Op amps
 Switch thermal noise can be minimized by using large capacitors. The thermal noise of the
switches is given by “𝒌𝑻/𝑪”, where 𝒌 = 𝟏. 𝟑𝟖 × 𝟏𝟎−𝟐𝟑 , 𝑻 =Temperature in 𝑲, and 𝑪 is the sampling
capacitor.
 Op amp thermal noise can be minimized by burning more current.

Slides by Bibhudatta Sahoo -21-

21
 Thermal Noise Consideration (2)

 It is costly in terms of power, area, and speed to make input thermal noise smaller than
quantization noise for ADC resolution, 𝑵 > 𝟏𝟎bits.
 For example: If full-scale ADC input is 1 V, then for a 11-bit ADC the quantization noise
power is given by:
𝑽𝟐𝑳𝑺𝑩 𝟏 𝟏 𝟐 𝟐
 𝑸𝑵 = = = 𝟏𝟒𝟏𝝁𝑽𝒓𝒎𝒔
𝟏𝟐 𝟏𝟐 𝟐𝟏𝟎
 If thermal noise voltage power (𝑵𝑻) is same as quantization noise power then the SNR
takes a 𝟑 dB hit.
𝑸
 If SNR has to take < 𝟏 dB hit then the 𝑵𝑻 ≤ 𝑵 .
𝟏𝟎
 Size of the capacitor required to achieve this for 𝟏𝟏 −bit system is 𝟐 𝒑𝑭.
 For a 12-bit system the capacitor required would be 𝟖 𝒑𝑭 (a large value).
 For a 16-bit system the capacitor size would be 𝟐 𝒏𝑭 (almost physically unrealizable on
chip).

Slides by Bibhudatta Sahoo -22-

22
 Thermal Noise Consideration (3)

 Ignoring other noise sources if thermal noise is only modeled by

𝒌𝑻/𝑪 then the SNR if given by:
𝑷𝒔𝒊𝒈
𝑺𝑵𝑹 = 𝟏𝟎𝒍𝒐𝒈𝟏𝟎 𝒌𝑻
𝑸𝑵 +
𝑪

SNR Vs Capacitance (Full Swing = 2V) SNR Vs Capacitance (Full Swing = 1V)
100.00
95.00 100.00
90.00 95.00
85.00 90.00
8-bit

SNR (dB)
85.00
SNR (dB)

80.00
80.00 10-bit
75.00
75.00 12-bit
70.00 70.00 14-bit
65.00 65.00
60.00
16-bit
60.00
55.00 55.00
1.00E-13 1.00E-12 1.00E-11 1.00E-10 1.00E-09 1.00E-13 1.00E-12 1.00E-11 1.00E-10 1.00E-09
Capacitance Capacitance

Slides by Bibhudatta Sahoo -23-

23
 Distribution of Thermal Noise

 Each stage contributes to the thermal noise.

 How do we distribute the thermal noise so that the overall input-
referred thermal noise is minimized to maximize the SNR?
 Lets consider a pipelined ADC built using 1-bit stages (MDAC
gain = 2)

 Considering only 𝒌𝑻/𝑪 sampled noise the total input referred

noise power:
𝟏 𝟏 𝟏 𝟏
𝑵𝑻 ∝ 𝒌𝑻 + + + ⋯+
𝑪𝟏 𝑮𝟐𝟏 𝑪𝟐 𝑮𝟐𝟏 𝑮𝟐𝟐 𝑪𝟑 𝑮𝟐𝟏 ⋯𝑮𝟐𝑵−𝟏 𝑪𝑵

Slides by Bibhudatta Sahoo -24-

24
 Stage Scaling for Optimal Noise (1)

𝟏 𝟏 𝟏 𝟏
𝑵𝑻 ∝ 𝒌𝑻 + + + ⋯+
𝑪𝟏 𝑮𝟐𝟏 𝑪𝟐 𝑮𝟐𝟏 𝑮𝟐𝟐 𝑪𝟑 𝑮𝟐𝟏 ⋯𝑮𝟐𝑵−𝟏 𝑪𝑵
 If 𝑪𝟏 = 𝑪𝟐 = ⋯ 𝑪𝑵 then backend stages contribute very little noise
 Wasteful as power ∝ 𝑮𝒎 ∝ 𝑪
 How about scaling by 𝟐𝑴 where 𝑴 is the resolution of each stage.
 Same amount of noise from each stage.
 Power can be reduced.

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25
SHA-less Architecture

 Any mismatch between the “main

Main Sampling Path 1
sampling path” and “flash ADC
· · path” results in different voltages
1 C being sampled on “𝑪” and “𝑪/𝜶”.
· · ·

2 1  The mismatch can be translated to

VIN · time-constant mismatch ( ).
 For a signal of amplitude “𝑨” and
C/
· · frequency “𝒇𝒊𝒏” the difference in
2 1 voltage sampled on “𝑪” and “𝑪/”
is:
Flash ADC Path
Elements that
 𝑽 = 𝟐 𝒇𝒊𝒏 𝑨
can have mismatch
 Match the flash and MDAC paths.
[Mehr 2000]

Slides by Bibhudatta Sahoo 26

-26-
 Pipeline ADC
- Area, Power, Speed, Resolution
Optimization-

Slides by Bibhudatta Sahoo -27-

27
Pipeline ADC – Area, Power, Speed, Resolution Trade-off

Stage-1

·
+ ri Backend
VIN 2 N1 ADC
-

sub-ADC · sub-DAC

(P-N1)-bits
(N1+1)-bits
D1 DBE

-N1
2

Digital Combiner
P-bits
DOUT

 For a given ADC resolution, the number of stages and

number of bits resolved in each stage determines:
 power consumption
 area

Slides by Bibhudatta Sahoo 28

-28-
 1.5-bit Stage
2

+VREF 1 CF 1
· · ·
VIN · 1 CS VX
· · ·

V CX · VOUT
 REF 2 1
2
VREF
´ ±VREF,0
4
Offset
0
C S  C F VIN  kC SVREF
Correction

VOUT 
Range
VREF kC  C X C F 
´
4 C F   S 
V  A 
 REF
2  Feedback factor = ½.
 Offset correction range = ±VREF/4 (i.e. ±150 mV for VREF=0.6V).
 Settling Requirement on the op amp reduced by 1-bit.
-VREF  Input referred noise = ½ of output noise.

Slides by Bibhudatta Sahoo 29

-29-
 2.5-bit Stage
2
 Feedback factor =1/4.
1 C1 +VREF  Offset correction range
· · 2
· = ±VREF/8 (i.e. ±75 mV for
1 C2 1 VREF=0.6V).
· · · ·
1 VREF ´  Settling Requirement on
· ·
C3
·  the op amp reduced by
2 ´
b0 2
2-bits.
VX
±VREF ·
1 C4
·
CX
´ Offset  Input referred noise is ¼
· VOUT
VIN · · · 0 Correction
of output noise.
b1 2 ´ Range

 Input-Output transfer
±VREF V ´ function is:
·  REF 8 5
C 1 = C 2 = … C8
´
C V   Ci 3biVREF
· 2
1 · C8
i IN
· ·
VOUT  i 1 i 0
b52 C 1 C 2  C X
C1  C2 
1

-VREF
±VREF
A

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-30-
 3.5-bit Stage

2
 Feedback factor = 1/8.
1 C1 +VREF
· · 2  Offset correction range
· = ±VREF/16 (i.e. ±37.5 mV
´
1 1
· ·
C2
· · ´
for VREF=0.6V).
1 V ´  Settling Requirement on
· ·
C3
·  REF ´
2 the op amp reduced by
b0 2 ´
3-bits.
±VREF ·
VX
· ´
1 C4 CX
· VOUT ´ Offset
 Input referred noise is
· · · 0 Correction
VIN ´ Range 1/8 of output noise.
b1 2 ´
´  Input-Output transfer
±VREF V ´ function is:
·  REF
C1 = C2 = … C16 2 ´
· 16 13

1 · C
16
´
´
C V i IN   Ci 3biVREF
· · VOUT  i 1 i 0
C 1 C 2  C X
b132 1
C1  C2 
-VREF A
±VREF

Slides by Bibhudatta Sahoo 31

-31-
 Architecture Summary

Summary of ADC Stage Architectures

1.5-bit Stage 2.5-bit Stage 3.5-bit Stage Parameter effected
Feedback Factor 1 1 1 Speed and Power
2 4 8
Offset Correction  VREF 4  VREF 8  VREF 16 Linearity of ADC
Range
Reduction in Settling 1-bit 2-bits 3-bits Speed and Power
Requirement
Noise Scaling 1 1 1 SNR, Power, &
2 4 8 Area
Reduction in
Capacitor Matching 1-bit 2-bits 3-bits Power and Area
Requirement

 For resolutions more than 10-bits it is better to resolve more bits in the
first stage:
 relaxing op amp settling.
 capacitor matching.
 reducing capacitance  input referred noise is reduced.
 DOES NOT relax the op amp open loop DC gain requirement (more later).

Slides by Bibhudatta Sahoo 32

-32-
Why not resolve more bits in 1st Stage?

 Any mismatch between the “main sampling

Main Sampling Path 1 path” and “flash ADC path” results in
different voltages being sampled on “C” and
· · “C/”.
1 C  The mismatch can be translated to time-
· · ·
constant mismatch ( ).
2 1  The difference in voltage should be within
VIN · the offset correction range of the Flash ADC.
 Resolving more bits in the 1st stage reduces
C/ the offset-correction range and hence could
· ·
result in missing codes.
2 1
 Offset correction range should include:
 Comparator offsets in the flash.

Flash ADC Path  Time constant mismatch ( ).

Elements that  For a signal of amplitude “A” and frequency
can have mismatch “fin” the difference in voltage sampled on
“C” and “C/” is:
 V=2 fin A
Slides by Bibhudatta Sahoo 33
-33-
DC Gain Requirement of op amp in each stage

Stage-1
+ ri Backend
VIN ·
-
2 N1 ADC  Residue voltage Vri has to settle to LSB/2
of the backend-ADC.
sub-ADC · sub-DAC

(N1+1)-bits
(P-N1)-bits  Gain error:
D1 DBE
Ve 1 1
-N1    P  N1 1
Videal 1  ADC 2
2

Digital Combiner
P-bits
DOUT
 Resolution reduces but the feedback
factor also reduces by the same amount
 DC gain is defined by the resolution of
the ADC and not the resolution of the
backend ADC that follows.
Vri Ve
 The above holds true for the op amps in
the later stages of the pipeline.
t

Slides by Bibhudatta Sahoo 34

-34-
 Architecture Optimization (1)

 Some expressions used for architecture optimization i.e. number of pipeline

stages and number of bits/stage:
 Settling time for N-bit accuracy:
tsettle  N  1 · · ln 2
 Two stage op amp poles and unity gain bandwidths:
1 g g
 p1  ,  p 2  m 2 , u  m1 , and  p 2  5 · u
R1 g m 2 R2CC CL CC
 Variance of input referred sampled noise:

 kT N kT 1 
 2
IN  2·    2 
  op2   ref
2
  2jitter
 C1 i  2 Ci Gi 1 
where, Ci = sampling caps in each stage, and Gi = gain of each stage.
 2nd stage of the op amp is a common source stage. For maximum output swing at
the highest speed typical gain in the 2nd stage is  10.
 Overdrive voltage to maximize swing is chosen to be around VOV=150 mV and
hence current in each branch in the two stages are ID1 = gm1·VOV/2 and ID2 =
gm2·VOV/2.

Slides by Bibhudatta Sahoo -35-

35
Architecture Optimization (2)

 Signal swing = ±750 mV for 1.5 V supply

 Resolution = 12-bits (determines quantization noise)
 𝒇𝑴𝑨𝑿, 𝑰𝑵 = 100 MHz
 𝒇𝑺 = 200 MHz
 𝒕𝒔𝒍𝒆𝒘𝒊𝒏𝒈 = 0.5 ns
 𝒕𝒏𝒐𝒏 − 𝒐𝒗𝒆𝒓𝒍𝒂𝒑 = 0.2 ns
 𝒕𝒔𝒆𝒕𝒕𝒍𝒊𝒏𝒈 = 1.8 ns
 Noise Budget:
 Quantization Noise
 Sampled Thermal Noise
 Op amp Noise
 Reference Noise
 Jitter Noise
 Input signal buffer Noise
Slides by Bibhudatta Sahoo -36-
36
Architecture Optimization (3) Jitter Specification

 The variance of jitter voltage is given by:

 jitter  2  t j f in A
where, tj = variance of jitter.
fin= frequency of the input signal.
A = amplitude of the input signal.
 For maximum input frequency of 100 MHz and jitter limited SNR of 80 dB
the required rms jitter is 700 fs.

Slides by Bibhudatta Sahoo -37-

37
Architecture Optimization (4) Noise Budget

Noise Budget
LSB () V p p 1.5
 = 366 µV
212 212

Reference Noise 90 µV
Op Amp Noise 120 µV
Sampled Noise (kT/C) 64 µV (2 pF)
Jitter Noise
( 2t j f inV p  p / 2 ) 66 µV (200 fs RMS jitter)
Overall SNR 67.8 dB (in 100 MHz band)

Slides by Bibhudatta Sahoo -38-

38
Architecture Optimization (5)

Sl. No. Architecture Sampling Capacitance Power

Capacitor switching to (mW)
(pF) Reference
(pF)
1 9, 1.5-bit stages, 3-bit flash 3.0 4.0 138
2 4, 2.5-bit stages, 4-bit flash 1.5 2.5 120
3 3, 3.5-bit stages, 3-bit flash 1.0 2.0 140
4 2.5-bit 1st stage, 6, 1.5-bit 2.0 2.5 77
stages, and 4-bit flash
5 3.5-bit 1st stage, 5, 1.5-bit 1.0 1.5 50
stages, and 4-bit flash

 Optimization based on the following:

 Vin(p-p)(diff)=1.5 V
 Quantization noise is at 12-bit level.
 Thermal noise limited to 66 dB in 100MHz band.

 Architecture 5 is optimal.
Slides by Bibhudatta Sahoo -39-
39
Calibration : A Necessity

Slides by Bibhudatta Sahoo -40-

40
 Why Calibrate?

Basic Pipeline Stage

 As technology scales it is difficult to
get:
 get high op amp gain to
1. remove gain error
2. suppress nonlinearity
 low op amp offset.
 capacitor matching to remove DAC
nonlinearity.
31  2 ( N 1)   For example, op amp gain in a 12-bit
A1 
2( N 1) system should exceed 12000  81 dB.

Slides by Bibhudatta Sahoo -41-

41
 Current ADC Design Trends
 Choose capacitors to satisfy kT/C noise, not
matching.
 Choose op amp with high swing
 kT/C noise relaxed
 power consumption reduced.
 Relaxes op amp linearity requirement

 Choose best trade-off between speed, power, and

noise of op amp regardless of its gain.
 Digitally correct for everything!

Slides by Bibhudatta Sahoo -42-

42
 How to Calibrate?

 Inverse Operator estimation

can be done in:
 Background
 Foreground

Slides by Bibhudatta Sahoo -43-

43
Capacitor Mismatch
Calibration

Slides by Bibhudatta Sahoo -44-

44
Comparator Forcing Based Calibration

where,

and
B. Sahoo and B. Razavi, IEEE JSSC, vol. 48, pp. 1442-1452, Jan. 2013.

Slides by Bibhudatta Sahoo -45-

45
 Computation of 𝛽𝑗 (I)

In other words,

Slides by Bibhudatta Sahoo -46-

46
Computation of 𝛽𝑗 (II)

In other words,

’s can be calculated using adders and right shifts.

B. Sahoo and B. Razavi, “A 10-b 1-GHz 33-mW CMOS ADC“, IEEE Journal of Solid-
State Circuits, vol. 48, pp. 1442-1452, Jun. 2013.
A. Karanicolas, et. al., “A 15-b 1-Msample/s digitally self-calibrated pipeline ADC,
“, IEEE Journal of Solid-State Circuits, vol. 28, pp. 1207-1215, Dec. 1993.
Slides by Bibhudatta Sahoo -47-
47
 Capacitor Mismatch Calibration (1)
 The input output characteristic of a 4-bit stage is:
16 15

C V m IN   Cm Am , jVR
VOUT  m 1 m 1
16
C F C P   C m
CF  m 1
A
9 15

C m Am , jVR
 VOUT  VIN  m 1
16
C F C P   C m
CF  m 1
A
 VOUT  VIN   jVR ,
15 16

C m Am , jVR C m
where  j  m 1
16
and   i 1
16
.
 Dividing both sides by VR we get, C F C P   C m C F C P   C m
DBE=backend digital output DBE  DIN   j
CF  m 1
CF  m 1

DBEj A A
 DIN  
 

Slides by Bibhudatta Sahoo -48-

 Capacitor Mismatch Calibration (2)

C1  C2  · · ·  C15 
Region 15 : DBE  DIN 
C1  C2  · · ·  C14  C15 
 DIN  15
Region 1 : DBE  DIN  16
 DIN  1 16
C F  C P   Ci C F  C P   Ci
CF  i 1 CF  i 1

A A
C1  C2  · · ·  C15  Region 16 : DBE  DIN 
C1  C2  · · ·  C15   DIN  16
Region 2 : DBE  DIN   DIN   2 16
C F  C P   Ci
16
C F  C P   Ci
CF  i 1 CF  i 1

A A

Region 3 : DBE  DIN 

C1  C2  C3  · · ·  C15   DIN   3
16
C F  C P   Ci
CF  i 1
A
Slides by Bibhudatta Sahoo -49-
 Capacitor Mismatch Calibration (3)

 The digital output goes from 0 to 15 when the input changes from –VR to +VR.

 Apply Vj close to the comparator threshold and force the flash ADC output so that the
residue is once in region j and then in region (j+1).

 The redundancy/offset correction range in the architecture prevents the ADC from
clipping.

 The backend ADC gives two different codes for the same input voltage.

Slides by Bibhudatta Sahoo -50-

Capacitor Mismatch Calibration (4)


 Applying Vj to the ADC in region j we get,
D
D  
BE , j j

 
j

 Similarly applying Vj and forcing the flash ADC output to

be in region (j+1) we get,

DBE , j , f  j 1
D j, f  
 
 Since, same voltage is applied we can equate both of
them:

DBE , j , f  DBE , j   j   j 1
which is not dependent on gain error.
 Repeat the above steps for j=1 to 15.

Slides by Bibhudatta Sahoo -51-

 Capacitor Mismatch Calibration (5)
 Thus we end up with:
DBE ,1, f  DBE ,1  1   2 1  1 0 0 0 0 0 0 0 0 0 0 0 0 0   1   DBE ,1, f  DBE ,1 
DBE , 2, f  DBE , 2   2   3 0 1  1 0 0 0 0 0 0 0 0 0 0 0 0      D  DBE , 2 
   2   BE , 2, f
DBE ,3, f  DBE ,3   3   4 0 0 1  1 0 0 0 0 0 0 0 0 0 0 0    3   DBE ,3, f  DBE ,3 
DBE , 4, f  DBE , 4   4   5     
 0 0 0 1  1 0 0 0 0 0 0 0 0 0 0    4   DBE , 4, f  DBE , 4 
DBE ,5, f  DBE ,5   5   6 0 0 0 0 1  1 0 0 0 0 0 0 0 0 0    5   DBE ,5, f  DBE ,5 
    
DBE , 6, f  DBE , 6   6   7 0 0 0 0 0 1  1 0 0 0 0 0 0 0 0    6   DBE , 6, f  DBE , 6 
DBE , 7 , f  DBE , 7   7   8 0 0 0 0 0 0 1  1 0 0 0 0 0 0 0      DBE , 7 , f  DBE , 7 
  7   
DBE ,8, f  DBE ,8   8   9 0 0 0 0 0 0 0 1  1 0 0 0 0 0 0    8    DBE ,8, f  DBE ,8 
DBE ,9, f  DBE ,9   9  10 0 0 0 0 0 0 0 0 1  1 0 0 0 0 0      D  DBE ,9 
   9   BE ,9, f 
DBE ,10, f  DBE ,10  10  11 0 0 0 0 0 0 0 0 0 1  1 0 0 0 0   10   DBE ,10, f  DBE ,10 
     DBE ,11 

DBE ,11, f  DBE ,11  11  12 0 0 0 0 0 0 0 0 0 0 1  1 0 0 0   11   DBE ,11, f
DBE ,12, f  DBE ,12  12  13 0 0 0 0 0 0 0 0 0 0 0 1  1 0 0   12   DBE ,12, f  DBE ,12 
    
DBE ,13, f  DBE ,13  13  14  0 0 0 0 0 0 0 0 0 0 0 0 1  1 0   13   DBE ,13, f  DBE ,13 
DBE ,14, f  DBE ,14  14  15 0 0 0 0 0 0 0 0 0 0 0 0 0 1  1     DBE ,14, f  DBE ,14 
   14   
DBE ,15, f  DBE ,15  15  1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1   15   DBE ,15, f  DBE ,15 

 Solving for j is straight forward and does not require

multiplication.
Slides by Bibhudatta Sahoo -52-
 Capacitor Mismatch Calibration (6)
 Thus j can be obtained as follows without the need of multipliers:

 1  1 1 1 1 1 1 1 1 1 1 1 1 1 1  DBE ,1, f
1  DBE ,1 
   1 1   DBE , 2 
 2  1 1 1 1 1 1 1 1 1 1 1 1  DBE , 2, f
1
 3   1  1 1 1 1 1 1 1 1 1 1 1 1 1 1  DBE ,3, f  DBE ,3 
    
 4   1  1  1 1 1 1 1 1 1 1 1 1 1 1 1  DBE , 4, f  DBE , 4 
 5   1  1  1  1 1 1 1 1 1 1 1 1 1 1 1  DBE ,5, f  DBE ,5 
    
 6   1  1  1  1 1 1 1 1 1 1 1 1 1 1 1  DBE , 6, f  DBE , 6 
   1  1  1  1 1 1 1 1 1 1 1 1 1 1 1  DBE , 7 , f  DBE , 7 
  1
7
 
  8    1  1  1  1 1 1 1 1 1 1 1 1 1 1 1  DBE ,8, f  DBE ,8 
   2  1  1  1  1 1 1 1 1 1 1 1 1 1 1 1  DBE ,9, f  DBE ,9 

 9  
 10   1  1  1  1 1 1 1 1 1 1 1 1 1 1 1  DBE ,10, f  DBE ,10 
     DBE ,11 

 11   1  1  1  1 1 1 1 1 1 1 1 1 1 1 1  DBE ,11, f
 12   1  1  1  1 1 1 1 1 1 1 1 1 1 1 1  DBE ,12, f  DBE ,12 
    
 13   1  1  1  1 1 1 1 1 1 1 1 1 1 1 1  DBE ,13, f  DBE ,13 
   1  1  1  1 1 1 1 1 1 1  1  1  1 1 1  DBE ,14, f  DBE ,14 
 14    
 15   1  1  1  1 1 1 1 1 1 1  1  1  1  1 1  DBE ,15, f  DBE ,15 

 Combining the bits with appropriate j:

 Flash ADC output tells us which region the analog voltage is in.
 The above information can be used appropriately combine the bits.

Slides by Bibhudatta Sahoo -53-

Gain Calibration for Multi-bit
MDAC

Slides by Bibhudatta Sahoo -54-

54
 Computation of 

 Need to obtain C1 /Ceq, C2 /Ceq ,…, C16 /Ceq .

 Fortunately,

 We already have these values from previous measurements

Slides by Bibhudatta Sahoo -55-

55
 Computation of C16 /Ceq
 Swap C1 and
C16:

 

 Thus, is obtained.

Slides by Bibhudatta Sahoo -56-

56
 Gain Error Calibration (1)
 We can obtain a similar set of Region 1 : DBE  DIN 
C16  C2  · · ·  C15 
 DIN  1
16
measurements by connecting C16 to C F  C P   Ci
VR (controlled by A1) and C1 to CF  i 1
A
VCM.
C16  C2  · · ·  C15 
 Instead of 1 to 15 we can define Region 2 : DBE  DIN  16
 DIN   2
1 to 15 as shown on the side. C F  C P   Ci
CF  i 1
 Similarly we can solve for 1 to A
15 by matrix inversion. Region 3 : DBE  DIN 
C16  C2  C3  · · ·  C15   DIN  3
16
C F  C P   Ci
CF  i 1
A
·
·
·

Region 15 : DBE  DIN 

C16  C2  C3  · · ·  C15 
 DIN  15
16
C F  C P   Ci
CF  i 1
A
Region 16 : DBE  DIN 
C16  C2  C3  · · · C15   DIN  1
16
C F  C P   Ci
CF  i 1
A

Slides by Bibhudatta Sahoo -57-

 Gain Error Calibration (2)
 We can rewrite 1 to 15 in terms C1 to C16 as shown below:
 1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  C1   1 
 1 1 1
  1  1  1  1  1  1  1  1  1  1  1  1  C2    2 
 1 1 1  1  1  1  1  1  1  1  1  1  1  1  1  C3    3 
    
1 1 1  1  1  1  1  1  1  1  1  1  1  1  1  C4    4 
1 1 1 1  1  1  1  1  1  1  1  1  1  1  1  C5    5 
    
1 1 1 1 1  1  1  1  1  1  1  1  1  1  1  C6    6 
1 1 1 1 1 1  1  1  1  1  1  1  1  1  1  C7    7 
1     
1 1 1 1 1 1 1  1  1  1  1  1  1  1  1  C8     8 
 16

 C F  C P   Ci  1 1 1 1 1 1 1 1  1  1  1  1  1  1  1  C9    9 
C  i 1     
 F A 1 1 1 1 1 1 1 1 1  1  1  1  1  1  1 C10   10 
 1 1 1    
1 1 1 1 1 1 1  1  1  1  1  1 C11   11 
 
1 1 1 1 1 1 1 1 1 1 1  1  1  1  1 C12   12 
    
1 1 1 1 1 1 1 1 1 1 1 1  1  1  1 C13   13 
1 1 1 1 1 1 1 1 1 1 1 1 1  1  1 C14   14 
    
 1 1 1 1 1 1 1 1 1 1 1 1 1 1  1 C15   15 

 Similarly, we can rewrite 1 to 15 in terms C2 to C16.

16
C F CP   Ci
 Solving the two matrices we can obtain Ci/(CF-CX) where, CX  i 1

for i=1 to 16. A

16
Ci
 Gain error,  C
i 1  CX
F

Slides by Bibhudatta Sahoo -58-

 Gain Error Calibration – 1.5 bit stages
 Backend stages  need gain error calibration.

 Perturbation based calibration [1]:

 Applying VIN we get D0 and DBE0.
 Applying (VIN + ) we get D1 and DBE1.
 Applying  we get D0 and DBE.
 VIN and (VIN + ) should produce different
codes.
Thus, gain error  is obtained as follows:
VIN     VIN    0
 D1  DBE 1  D0  DBE 0  D0  DBE  0
D1
 
DBE 0  DBE  DBE 1
[1] B. Sahoo and B. Razavi, "A 12-Bit 200-MHz CMOS ADC,“ IEEE Journal of Solid-
State Circuits, vol. 44, pp. 2366-2380, Sept. 2009
Slides by Bibhudatta Sahoo -59-
Gain Calibration for 1.5-bit
Non-flip-around MDAC

Slides by Bibhudatta Sahoo -60-

60
1.5-Bit Stages

where, is the gain.

 CS and CF cannot be swapped to obtain gain as it would

lead to over-range.
Slides by Bibhudatta Sahoo -61-
61
Calibration Algorithm* (1.5-Bit Stages)

• Apply V10 mV
• Apply VREF/4
• Apply VREF/4+V
* B. Sahoo and B. Razavi, IEEE Journal of Solid-State Circuits, vol. 44, pp. 2366-2380, Sept. 2009

Slides by Bibhudatta Sahoo -62-

62
1.5-Bit Stages - Computing Inverse Gain (1/)
• Apply V

• Apply VREF/4, force comparator

output to be “0”

• Apply (VREF/4+V), force

comparator output to be “1”

Inverse Gain =

• Obtained using Newton-Raphson iterative method

instead of division.
Slides by Bibhudatta Sahoo -63-
63
Gain Calibration for 1.5-bit
Flip-around, 2.5-bit, etc.
MDAC

Slides by Bibhudatta Sahoo -64-

64
Gain Calibration for 1.5-bit Flip-around MDAC (1)

𝑪𝟏 +𝑪𝟐 𝑪𝟏
𝑽𝒐𝒖𝒕 = 𝑪 +𝑪 +𝑪 𝑽𝒊𝒏 − 𝑪𝟏 +𝑪𝟐 +𝑪𝑷 𝑲𝑽𝑹, where 𝑲 = ±𝟏, 𝟎
𝑪𝟐 + 𝟏 𝑨𝟐 𝑷 𝑪𝟐 +
𝑨
𝑪𝟏 +𝑪𝟐 𝑪𝟏
⟹ 𝑽𝒐𝒖𝒕 = 𝜶𝑽𝒊𝒏 − 𝑲𝜷𝑽𝑹 , where 𝜶 = 𝑪𝟏 +𝑪𝟐 +𝑪𝑷 , and 𝜷 = 𝑪 +𝑪 +𝑪
𝑪𝟐 + 𝑨
𝑪𝟐 + 𝟏 𝑨𝟐 𝑷
 𝜷 can be solved by applying 𝑽𝑻𝟏 or 𝑽𝑻𝟐 and forcing the corresponding
comparator to “1” or “0”.
 Unlike, an N-bit architecture as mentioned earlier we cannot swap the
capacitors here to solve for 𝜶.
𝑪 +𝑪 +𝑪 𝑪 +𝑪 +𝑪
 Swapping capacitors changes the denominator 𝑪𝟐 + 𝟏 𝑨𝟐 𝑷 to 𝑪𝟏 + 𝟏 𝑨𝟐 𝑷
* C. Ravi, V. Sarma, and B. Sahoo,“ IEEE NEWCAS, June 2015

Slides by Bibhudatta Sahoo -65-

65
Gain Calibration for 1.5-bit Flip-around MDAC (2)

𝑪𝟏 +𝑪𝟐 𝑪𝟏
𝑽𝒐𝒖𝒕 = 𝑪 +𝑪 +𝑪 𝑽𝒊𝒏 − 𝑪𝟏 +𝑪𝟐 +𝑪𝑷 𝑲𝑽𝑹, where 𝑲 = ±𝟏, 𝟎
𝑪𝟐 + 𝟏 𝑨𝟐 𝑷 𝑪𝟐 +
𝑨
𝑪𝟏 +𝑪𝟐 𝑪𝟏
⟹ 𝑽𝒐𝒖𝒕 = 𝜶𝑽𝒊𝒏 − 𝑲𝜷𝑽𝑹 , where 𝜶 = 𝑪𝟏 +𝑪𝟐 +𝑪𝑷 , and 𝜷 = 𝑪 +𝑪 +𝑪
𝑪𝟐 + 𝑨
𝑪𝟐 + 𝟏 𝑨𝟐 𝑷
 Applying 𝑽𝑹 the back-end ADC output can be given as:
𝑪𝟐 𝑪𝟐
𝑽𝒐𝒖𝒕 = 𝜶𝑽𝑹 − 𝜷𝑽𝑹 ⟹ 𝑽𝒐𝒖𝒕 = 𝑽𝑹 ⟹ 𝑫𝑩𝑬 =
𝑪 + 𝑪𝟐 + 𝑪𝑷 𝑪 + 𝑪𝟐 + 𝑪𝑷
𝑪𝟐 + 𝟏 𝑪𝟐 + 𝟏
𝑨 𝑨
 The 𝜷 obtained using the comparator forcing algorithm can be added to the
above 𝑫𝑩𝑬 measurement to obtain 𝜶
* C. Ravi, V. Sarma, and B. Sahoo,“ IEEE NEWCAS, June 2015
Slides by Bibhudatta Sahoo -66-
66
Gain Calibration for 2.5-bit Flip-around MDAC
 Comparator forcing based
calibration technique is used
to obtain 𝜷𝟏 to 𝜷𝟔 .
 Just as in 1.5-bit flip-around
topology swapping capacitor
changes the denominator
and hence cannot be used to
solve for the gain 𝜶.
 Applying the full-scale input
to the MDAC and digitizing
the output using the backend
we obtain,
𝑪𝟕 + 𝑪𝟖
𝑫𝑩𝑬 = 𝟖
𝒊=𝟏 𝑪𝒊 + 𝑪𝑷
𝟖 𝟔
𝒊=𝟏 𝑪𝒊 𝑽𝒊𝒏 𝒊=𝟏 𝑻𝒊 𝑪𝒊 𝑪𝟕 + 𝑪𝟖 +
𝑽𝒐𝒖𝒕 = 𝟖
− 𝟖
𝑽𝑹 𝑨
𝒊=𝟏 𝑪𝒊 + 𝑪𝑷 𝒊=𝟏 𝑪𝒊 + 𝑪𝑷 𝟔
𝒊=𝟏 𝑪𝒊
𝑪𝟕 + 𝑪𝟖 + 𝑪𝟕 + 𝑪𝟖 + Now, 𝜷𝟔 = .
𝑨 𝑨  𝟖 𝑪 +𝑪
⟹ 𝑽𝒐𝒖𝒕 = 𝜶𝑽𝒊𝒏 − 𝜷𝒊 𝑽𝑹 𝑪𝟕 +𝑪𝟖 + 𝒊=𝟏 𝑨 𝒊 𝑷
 𝜶 = 𝑫𝑩𝑬 + 𝜷𝟔
 Can be extended to 3.5-bit.
* C. Ravi, V. Sarma, and B. Sahoo,“ IEEE NEWCAS, June 2015
Slides by Bibhudatta Sahoo -67-
67
Calibration at Full-Speed

 Speed of existing calibration methods are limited by

 Circuitry which applies the calibration inputs
 Calibration at low speed doesn't capture the error in
residue
 Due to insufficient settling of the op amp at high
frequency
 Incorrect gain estimation
 In order to facilitate calibration at full-speed the
calibration voltages have to be generated using
capacitors switching to ±𝑽𝑹 .
 This eliminates the resistor ladder to generate the
calibration voltages.

* C. Ravi, V. Sarma, and B. Sahoo,“ IEEE NEWCAS, June 2015

68 Slides by Bibhudatta Sahoo -68-

Calibration Signal Generation for 1.5-bit Stage (1)

 Split the sampling capacitor and

the feedback capacitor into two
equal unit capacitors
 During normal operation
 Sampling phase: Input is
sampled onto all the capacitors
 Amplification phase: 2
capacitors are flipped around
 Remaining two capacitors
switch to 𝑲𝑽𝑹

* C. Ravi, V. Sarma, and B. Sahoo,“ IEEE NEWCAS, June 2015

69 Slides by Bibhudatta Sahoo -69-

Calibration Signal Generation for 1.5-bit Stage (2)

 During Calibration,
 Sampling phase: −𝑽𝑹 sampled
onto one sampling capacitors
 Remaining capacitors connected to
ground for applying 𝑽𝑻𝟏 = −𝑽𝑹/𝟒.
 Amplification phase: Two
capacitors connected to 𝑲𝑽𝑹
 Two capacitors flipped around
 Resulting residue voltage is
−𝑽𝑹 𝑪𝟏 + 𝑲𝑽𝑹 𝑪𝟏 + 𝑪𝟐
𝑽𝒐𝒖𝒕 =
𝑪 + 𝑪 𝟐 + 𝑪𝟑 + 𝑪𝟒
𝑪𝟑 + 𝑪𝟒 + 𝟏
𝑨
 This residue is same as if 𝑽𝑰𝑵 =
−𝑽𝑹/𝟒 is applied

* C. Ravi, V. Sarma, and B. Sahoo,“ IEEE NEWCAS, June 2015

70 Slides by Bibhudatta Sahoo -70-

Calibration Signal Generation for 1.5-bit Stage (3)

 Similarly, we can mimic the generation

of 𝑽𝑻𝟐 = 𝑽𝑹/𝟒 by
 Applying 𝑽𝑹 to one sampling
capacitor
 Remaining connected to ground

* C. Ravi, V. Sarma, and B. Sahoo,“ IEEE NEWCAS, June 2015

71 Slides by Bibhudatta Sahoo -71-

Background Gain Calibration
for Multi-bit, 1.5-bit, 2.5-bit,
etc. MDACs

Slides by Bibhudatta Sahoo -72-

72
Pipeline Stage I/O Characteristic
 The input output characteristic of a 4-bit stage is:
16 15

 CmVIN   Cm Am, jVR

VOUT  m 1 m 1
16
C F C P   C m
CF  m 1

9
A
15

C m Am , jVR
 VOUT  VIN  m 1
16
C F C P   C m
CF  m 1
A
 VOUT  VIN   jVR ,
15 16

 Cm Am, jVR C m
where  j  m 1
16
and   i 1
16
.
 Dividing both sides by VR we get, C F C P   C m C F C P   C m
CF  m 1
CF  m 1
A A
DBE  DIN   j
DBE
 DIN   j
where, 
 j is the capacitor mismatch  independent of op amp gain
  is the gain (G1) function of op amp gain.

Slides by Bibhudatta Sahoo -73-

73
Proposed Calibration Algorithm
 Initially estimate the gain (=G1) and the capacitor
mismatch (j) in the foreground using the calibration
technique in .
 Then estimate the inter-stage gain α, in the background.

B. Sahoo, and B. Razavi, ”A 10-bit 1-GHz 33-mW CMOS ADC,” IEEE JSSC, June 2013.

Slides by Bibhudatta Sahoo -74-

74
Pipelined Stage Residue Characteristic with MDAC
Gain Variation

2-bit MDAC residue characteristics 2-bit MDAC residue characteristics

Vres Vs Vin with Gain variation DBE Vs Vin with Gain variation

 MDAC gain (𝜶) changes  slope of the residue characteristic changes.

 Residue quantized by an ideal 𝑴-bit back-end to give a digital estimate,
𝑫𝑩𝑬,
𝑫𝑩𝑬, min= 2M-2 and 𝑫𝑩𝑬, max= 3´2M-2 -1
 Ideally  = 𝑫𝑩𝑬, max/𝑽𝑳𝑺𝑩/𝟐.
 Parameter drift changes 𝑫𝑩𝑬, min and 𝑫𝑩𝑬, max.
Slides by Bibhudatta Sahoo -75-
75
Calibration Algorithm
 Estimate the MDAC gain, α in the foreground mode using
technique in .
 Estimate DBE,max1 in the background mode, immediately after the
foreground calibration is done. Thus,  = DBE,max1/VLSB/2.
 Calibration engine keeps on estimating DBE,max. If the gain drifts a
new back-end maximum, DBE,max2 is obtained, resulting in new =
DBE,max2/VLSB/2.
 Thus,
 new
  Dmax 2
Dmax 1
 new   Dmax 2
Dmax 1

B. Sahoo, and B. Razavi, “A 10-bit 1-GHz 33-mW CMOS ADC,” IEEE JSSC, June 2013.

Slides by Bibhudatta Sahoo -76-

76
Effect of Non-Idealities

 The estimation of 𝑫𝑩𝑬, 𝑴𝑨𝑿 can be corrupted due

to the following non-idealities:
 Comparator Offset

 Capacitor mismatch

 Thermal Noise

Slides by Bibhudatta Sahoo -77-

77
Effect of Comparator Offset
 With comparator offset maximum back-
end code changes from region to
region, but slope in each region is the
same.
 Maximum in any one region gives the
accurate estimate of inter-stage gain
 The region should be such that the
calibration can work even with lower
signal swing
 For 2-bit MDAC, characteristic
corresponding to output code of 1 or 2
is chosen
 For 3-bit and 4-bit MDACs calibration would work for 1/4th and
1/8th of the signal swing.
Proposed calibration would thus require a minimum
swing that is either 12 dB or 18 dB below full scale.
Slides by Bibhudatta Sahoo -78-
78
Effect of Capacitor Mismatch

 Capacitor mismatch changes the

residue/back-end characteristic.
 Although the slope is the same in
each region the maximum in
each region is different.
 Calibration obtains the maximum
back-end code for a particular
region

Slides by Bibhudatta Sahoo -79-

79
Effect of Thermal Noise
 Thermal noise corrupts the measurement
of DBE,max.
 Histogram of the back-end code estimates
the true maximum code and eliminates the
absolute maximum code.
 For a noisy bin to have the same height as that of a noiseless bin,
the thermal noise should have a variance, σNTH > 10 LSB  SNR
degradation of approx. 30 dB.
 Noisy bins cannot be of the same height as noiseless bins

Slides by Bibhudatta Sahoo -80-

80
Multi-stage Gain Calibration

 Algorithm first calibrates the 2nd stage that has an ideal back-
end
 Consider the 2nd stage onwards as an ideal back-end and
calibrate the 1st stage
 Calibration starts from the later stages and moves to the 1st
stage

Slides by Bibhudatta Sahoo -81-

81
Digital Hardware Complexity
 Histogram requires counters and finding the maximum requires
comparators.
 For M-bit back-end, do we need 2M comparators and counters!No 

 Foreground calibration gives an initial estimate of DBE,max and noise

corrupts this by maximum of ±10 to ±20 back-end codes
 Hence maximum of 40 digital comparators and counters used
 Division operation is realized using Newton-Raphson technique,
which requires a multiplier and adder

Slides by Bibhudatta Sahoo -82-

82
 Survey of Digital
Calibration Techniques

Slides by Bibhudatta Sahoo -83-

83
Survey of Calibration Techniques
Sl. Author Type of Foreground/ Notes
No. (Year) MDAC Background
1. Lee Multi-bit Foreground Capacitor mismatch and gain error
(1992)
2. Karanicolas 1-bit Foreground Gain error
(1992)
3. Erdogan 1-bit Background Gain error
(1999)
4. Ming 1.5-bit non- Background Gain error
(2001) flip around
5. Li (2003) 1.5-bit flip- Background Gain error
around
6. Murmann 3-bit Background Capacitor mismatch, op amp
(2003) nonlinearity, and gain error
7. Wang 1.5-bit flip- Background Gain error and capacitor mismatch.
(2004) around
8. Verma 1.5-bit flip- Foreground Gain error, op amp nonlinearity,
(2009) around and capacitor mismatch
Slides by Bibhudatta Sahoo -84-
84
Calibration of Multistep ADC (1)

S-H. Lee and B-S. Song, IEEE JSSC, vol. 27, pp.
1679-1688, Dec. 1992.

Slides by Bibhudatta Sahoo -85-

85
Calibration of Multistep ADC (2)

 Error (𝑫𝒋) and Error (𝑫𝒋 + 𝟏) are the errors with digital codes
𝑫𝒋 and 𝑫𝒋 + 𝟏.

S-H. Lee and B-S. Song, IEEE JSSC, vol. 27, pp. 1679-1688, Dec. 1992.
Slides by Bibhudatta Sahoo -86-
86
Calibration of Multistep ADC (3)

 Measure the feedthrough voltage, i.e. offset, charge-injection, etc.

 Change the digital code by “1” and measure the output voltage.
 When digital code is changed by “1” then the change in the output
should be exactly ½ 𝑽𝑹𝑬𝑭.
 Thus the Error (Dj+1) can be obtained from the above measurement
and stored in memory.

S-H. Lee and B-S. Song, IEEE JSSC, vol. 27, pp. 1679-1688, Dec. 1992.
Slides by Bibhudatta Sahoo -87-
87
15-bit Self Calibrated Pipelined ADC (1)

𝟐+𝜶
𝑽𝒐𝒖𝒕 = 𝑽 − 𝑫𝑽𝒓𝒆𝒇
𝟏 + 𝜶 𝒊𝒏

where, 𝑪𝟐 = 𝟏 + 𝜶 𝑪𝟏

 Capacitor mismatch is merged with the gain term.

A. Karanicolas and H. S. Lee, IEEE JSSC, vol. 28, pp. 1207-1215, Dec. 1993.
Slides by Bibhudatta Sahoo -88-
88
15-bit Self Calibrated Pipelined ADC (2)
 Measure two quantities S1 and S2 by
applying Vin=0 and forcing D=0 and
D=1.
 Thus, the output can be given by,

𝒀 = 𝑿 if 𝑫 = 𝟎
= 𝑿 + 𝑺𝟏 − 𝑺𝟐 if 𝑫 = 𝟏.
 Calibration estimates only 𝑺𝟏 and 𝑺𝟐 for
each stage, stores them and then uses
them in the digital calibration logic.
 Calibration does not require
multiplication.
 Calibration starts from the later stages
and moves to the earlier stages.
 Difficult for a multi-bit stage.

A. Karanicolas and H. S. Lee, IEEE JSSC, vol. 28, pp. 1207-1215, Dec. 1993.
Slides by Bibhudatta Sahoo -89-
89
Queue Based Algorithmic ADC
Calibration (1)

 Queue based background gain error calibration.

 Having “n” sample-and-hold (SHA) and choosing fc > fs, time slots for
calibrating the ADC can be obtained without compromising the normal
operation of the ADC.
 The number of SHAs is given by:
𝑻𝒄𝒂𝒍
𝒏≥
𝑻𝑺
where, Tcal is the calibration time and Ts = 1/fs.
 Each of the SHA adds noise and degrades the SNR of the ADC.
 Also the additional SHA’s consume significant power.
 The paper demonstrates this for a Algorithmic ADC.
 It can also be extended to a pipelined ADC.

O. E. Erdogan, P. J. Hurst, and S. H. Lewis, IEEE JSSC, vol. 34, pp. 1812-1820, Dec. 1999.
Slides by Bibhudatta Sahoo -90-
90
Queue Based Algorithmic ADC
Calibration (2)

O. E. Erdogan, P. J. Hurst, and S. H. Lewis, IEEE JSSC, vol. 34, pp. 1812-1820, Dec. 1999.
Slides by Bibhudatta Sahoo -91-
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Queue Based Algorithmic ADC
Calibration (3)
 After the queue is empty the ADC goes into calibration mode.
 The ADC uses a 1-bit architecture just like in Karanicolas
1993.
 The nominal gain “m < 2” to make sure that there are no
missing levels.
 Since the actual value of “𝒎” is not known an initial estimate
of “𝒎” is used to obtain the digital output:

𝑫= 𝒎 𝒊 𝒅𝒊
𝒊=𝟏
 During calibration an input of 0 V is applied and the
comparator output is forced to “1” and “0” to obtain
respectively D1 and D0.
 LMS is used to estimate “𝒎” as per the following:
𝒎 𝒋 + 𝟏 = 𝒎 𝒋 + 𝝁 𝑫𝟏 − 𝑫𝟎 − 𝟏𝑳𝑺𝑩

O. E. Erdogan, P. J. Hurst, and S. H. Lewis, IEEE JSSC, vol. 34, pp. 1812-1820, Dec. 1999.
Slides by Bibhudatta Sahoo -92-
92
8-bit Pipelined ADC With Background
Calibration (1)
1.5-bit MDAC architecture

𝑪𝑺 𝟏
𝑽𝒐𝒖𝒕 = 𝑽𝒊𝒏 − 𝒌𝑽𝑹𝑬𝑭
𝑪𝑭 𝟏 + 𝟏 + 𝑪𝑺 + 𝑪𝑿
𝑨 𝑨𝑪𝑭
𝑽𝒐𝒖𝒕 = 𝑮𝑰 𝑮𝑬 𝑽𝒊𝒏 − 𝒌𝑽𝑹𝑬𝑭
𝑪 𝟏
where, 𝑮𝑰 = 𝑺 and 𝑮𝑬 = 𝟏 𝑪𝑺+𝑪𝑿
𝑪𝑭 𝟏+ +
𝑨 𝑨𝑪𝑭
𝑽𝑹𝟐
Adjust 𝑽𝑹𝟏 = to overcome the gain-error.
𝑮𝑬

J. Ming and S. H. Lewis, IEEE JSSC, vol. 36, pp. 1489-1497, Oct. 2001.
Slides by Bibhudatta Sahoo -93-
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8-bit Pipelined ADC With Background
Calibration (2)
 A pseudo-random generator
generates a  1 digital number.
 The random number is converted to
analog by DAC1.
 The output of DAC1 is digitized by the
back-end ADC and by a slow-but-
accurate ADC.
 The slow-but-accurate ADC output
should be subtracted from the back-
end ADC output to recover the digital
representation of Vin.
 The gain error of the stage can be
obtained if ei does not contain the
random input N(i). This is possible if:
𝑽𝒏 𝑮𝑫𝟏 𝑽𝒏 𝑽𝑹𝟐
− = 𝟎 → 𝑽𝑹𝟏 =
𝑽𝑹𝟐 𝑽𝑹𝟏 𝑮𝑫𝟏

J. Ming and S. H. Lewis, IEEE JSSC, vol.

Slides by Bibhudatta Sahoo -94-
94
36, pp. 1489-1497, Oct. 2001.
8-bit Pipelined ADC With Background
Calibration (3)
 Needs extensive analog hardware for
calibration.
 The DAC in the calibration system
should be accurate  difficult to
calibrate high resolution ADCs (> 10-
bits).
 Calibration technique can effectively
calibrate 1.5-bit/stage architecture
and not multi-bit architecture.
 Extension to multi-bit architecture is
very hardware intensive.

Multi-stage calibration
J. Ming and S. H. Lewis, IEEE JSSC, vol. 36, pp. 1489-1497, Oct. 2001.
Slides by Bibhudatta Sahoo -95-
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Radix Based Calibration (1)

𝟏 𝑪𝑺 + 𝑪𝑭 𝑪𝑺
𝑽𝑶 = 𝑽𝒊 − 𝑫𝑽𝒓𝒆𝒇
𝑪𝑺 + 𝑪𝑭 𝑪 𝑪
𝟏 + 𝑨𝑪 𝑭 𝑭 𝟐𝑪𝑺 𝟏 𝟏
𝑭 𝑽𝑶 = 𝑽𝒊 − 𝑫𝑽𝒓𝒆𝒇
𝟏+𝜷 𝑪𝑭 𝟏 + 𝟐𝑪𝑺 + 𝑪𝑭 𝟐
→ 𝑽𝑶 = 𝟏 + 𝜹 𝟐 + 𝜶 𝑽𝒊 − 𝑫𝑽𝒓𝒆𝒇 𝑨𝑪𝑭
𝟐+𝜶
𝟏 𝑪𝑺 +𝑪𝑭
→ 𝑽𝑶 = 𝟏 + 𝜹 𝟐 + 𝜶 𝑽𝒊 − 𝑫𝑽𝒓𝒆𝒇
where, 𝟏 + 𝜹 = 𝑪𝑺 +𝑪𝑭 , 𝟐 + 𝜶 = , 𝟏 𝑪𝑺 +𝑪𝑭
𝟏+ 𝑨𝑪 𝑪𝑭 where, 𝟏 + 𝜹 = 𝑪 +𝑪 𝐚𝐧𝐝 𝟐 + 𝜶 = 𝑪𝑭
,
𝑭 𝟏+ 𝑺 𝑨 𝑭
𝑪𝑺
and 𝟏+𝜷 =𝑪
𝑭

J. Li and Un-Ku Moon, IEEE TCAS-I, vol. 50, pp. 531-538, Sept. 2003.
Slides by Bibhudatta Sahoo -96-
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Radix Based Calibration (2)

Representation of the pipelined ADC with each stage using 1.5-bit non-flip
around topology.

 The digital output can be represented as:

𝑫𝑶 = 𝑫𝒏 + 𝑫𝒏 𝒓𝒂 + 𝑫𝒏 𝒓𝒂 𝟐 + ⋯ + 𝑫𝟏 𝒓𝒂 𝒏−𝟏
where, 𝒓𝒂 = 𝟏 + 𝜹 𝟐 + 𝜶 and reference voltage of each stage is scaled.
 Since the reference is scaled for each stage this is not attractive.
 However if each stage uses a non-flip-around topology then,
𝑫𝑶 = 𝑫𝒏 + 𝑫𝒏 𝒓𝒂 + 𝑫𝒏 𝒓𝒂 𝟐 + ⋯ + 𝑫𝟏 𝒓𝒂 𝒏−𝟏
where, 𝒓𝒂 = 𝟏 + 𝜹 𝟐 + 𝜶 and reference voltage of each stage is not scaled.
J. Li and Un-Ku Moon, IEEE TCAS-I, vol. 50, pp. 531-538, Sept. 2003.
Slides by Bibhudatta Sahoo -97-
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Radix Based Calibration (3)

𝟐+𝜶𝒊+𝟏
 The new radix is . 𝒓𝒂 = 𝟏 + 𝜷𝒊 𝟏 + 𝜹𝒊 𝟏+𝜷𝒊+𝟏
.
 The reference voltage is not scaled from stage-to-stage.

J. Li and Un-Ku Moon, IEEE TCAS-I, vol. 50, pp. 531-538, Sept. 2003.
Slides by Bibhudatta Sahoo -98-
98
Radix Based Calibration (4)



J. Li and Un-Ku Moon, IEEE TCAS-I, vol. 50, pp. 531-538, Sept. 2003.
Slides by Bibhudatta Sahoo -99-
99
Radix Based Calibration (5)
· Large convergence time as DBE has to be
correlated for a long time to guarantee
that PNDres vanishes.

· Generation of precise analog voltage

VPN whose digital value is PN.

· Reduction in dynamic range of the ADC

due to injection of pseudorandom
voltage VPN.

J. Li and Un-Ku Moon, IEEE TCAS-I, vol. 50, pp. 531-538, Sept. 2003.
Slides by Bibhudatta Sahoo -100-
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Open Loop Op amp Nonlinearity Calibration
(1)

B. Murmann and B. E.
Boser, IEEE JSSC, vol. 38,
pp. 2040-2050, Dec.
2003.

 The 12-bit pipelined ADC incorporates:

 3-bit stage-1 realized using open-loop amplifier.
 1-bit stage-2 (with 1 redundant bit to incorporate the signal injection for
calibration).
 Seven 1.5-bit stages
 3-bit flash ADC.
 Although 14-bits of raw data the last two bits are used for
calibration purpose.
 Only stage-1 is calibrated for linear gain error and non-
linearity.
 All other stages form an ideal Back-end ADC.
Slides by Bibhudatta Sahoo -101-
101
Open Loop Op amp Nonlinearity Calibration
(2)

Amplifier Model

 Stage-1 that incorporates an open-loop amplifier is modeled as

per the above block diagram with various error sources:
 VOS  op amp offset
   gain error  modeled by calibration parameter p1.
 a3  3rd order nonlinear term of the open-loop op amp.

B. Murmann and B. E. Boser, IEEE JSSC, vol. 38, pp. 2040-2050, Dec. 2003.

Slides by Bibhudatta Sahoo -102-

102
Open Loop Op amp Nonlinearity Calibration
(3)

Amplifier model with input Amplifier model with output

referred nonlinearity referred nonlinearity

𝟏 𝝅 𝟏 𝑽𝒓𝒆𝒔𝟏
𝒆 𝑽𝒓𝒆𝒔𝟏 = 𝑽𝒓𝒆𝒔𝟏 − 𝟐 − 𝒄𝒐𝒔 + 𝒄𝒐𝒔−𝟏
𝟑𝒑𝟐 𝟑 𝟑 𝟏
𝟐 −
𝟐𝟕𝒑𝟐
where, 𝑽𝒓𝒆𝒔𝟏 is digitized by the back-end ADC and
𝒂𝟑
𝒑𝟐 = 𝟑
𝟐 −∆ 𝟑
B. Murmann and B. E. Boser, IEEE JSSC, vol. 38, pp. 2040-2050, Dec. 2003.

Slides by Bibhudatta Sahoo -103-

103
Open Loop Op amp Nonlinearity Calibration
(4)

Digital
ADC Combiner
𝟏 𝝅 𝟏 𝑫𝒃
𝒆 𝑫𝒃 = 𝑫𝒃 − 𝟐 − 𝒄𝒐𝒔 + 𝒄𝒐𝒔−𝟏
𝟑𝒑𝟐 𝟑 𝟑 𝟏
𝟐 −
𝟐𝟕𝒑𝟐
where, 𝑫𝒃 is the back-end ADC output and the calibration engine
estimates p2.
B. Murmann and B. E. Boser, IEEE JSSC, vol. 38, pp. 2040-2050, Dec. 2003.

Slides by Bibhudatta Sahoo -104-

104
Open Loop Op amp Nonlinearity Calibration
(5)

 Vres1 can generate two curves based on the digital random-bit MODE.
 In order to accommodate the two transfer curves and not saturate the
back-end ADC stage-2 has 1-bit of redundancy.
 The residue characteristic with nonlinearity shows compression.
 Nonlinearity is overcome if h1 = h2 , i.e. the distance between the two
residue characteristic is constant at all points.
 Its sufficient to estimate the distance at the center and at the
extremes.
B. Murmann and B. E. Boser, IEEE JSSC, vol. 38, pp. 2040-2050, Dec. 2003.

Slides by Bibhudatta Sahoo -105-

105
Open Loop Op amp Nonlinearity Calibration
(6)

B. Murmann and B. E. Boser, IEEE JSSC, vol. 38, pp. 2040-2050, Dec. 2003.

Slides by Bibhudatta Sahoo -106-

106
Open Loop Op amp Nonlinearity Calibration
(7)

 Estimation of the gain error (p1) is similar to the method in Li2003.

 Estimation of nonlinearity (p2) is based on an LMS method which
minimizes the MSE of 𝑯𝟏 − 𝑯𝟐 .
 𝑯𝟏 − 𝑯𝟐 is a function of p2 as per
𝟏 𝝅 𝟏 𝑫𝒃
𝒆 𝑫𝒃 = 𝑫𝒃 − 𝟐 − 𝒄𝒐𝒔 + 𝒄𝒐𝒔−𝟏
𝟑𝒑𝟐 𝟑 𝟑 𝟏
𝟐 −
𝟐𝟕𝒑𝟐
B. Murmann and B. E. Boser, IEEE JSSC, vol. 38, pp. 2040-2050, Dec. 2003.
Slides by Bibhudatta Sahoo -107-
107
Open Loop Op amp Nonlinearity Calibration
(8)
 Requires that the inputs be sufficiently busy, i.e., the analog input to
the ADC be such that it exercises all the ADC levels. If the signal is
not full scale then the calibration cannot estimate the nonlinearity.
 As shown below in the residue characteristic of stage-1, if the signal
is within 1/16th of the full scale then also it exercises the full-scale of
the back-end ADC and hence estimates the nonlinearity.

 The open-loop amplifier is very susceptible to gain variation due to

temperature. If the LMS loop has a smaller time-constant as opposed
to the gain variation then the calibration works.

B. Murmann and B. E. Boser, IEEE JSSC, vol. 38, pp. 2040-2050, Dec. 2003.
Slides by Bibhudatta Sahoo -108-
108
Nested Digital Background Calibration (1)

 The algorithmic ADC and Pipelined ADC are realized using 1.5-
bit flip-around topology whose input-output characteristic is
given by,
𝟏 𝑪𝑺 + 𝑪𝑭 𝟏 𝑪𝑺
𝑽𝑶 = 𝑽𝒊 − 𝑫𝑽𝒓𝒆𝒇
𝑪𝑺 + 𝑪𝑭 𝑪 𝑭 𝑪𝑺 + 𝑪𝑭 𝑪𝑭
𝟏+ 𝟏+
𝑨𝑪𝑭 𝑨𝑪𝑭
→ 𝑽𝑶 = 𝟐 + 𝝐𝒈 𝑽𝒊 − 𝟏 + 𝝐𝑫𝑨𝑪 𝑫𝑽𝒓𝒆𝒇
𝟏 𝑪𝑺 +𝑪𝑭 𝟏 𝑪𝑺
where, 𝟐 + 𝝐𝒈 = 𝑪𝑺 +𝑪𝑭 𝑪 , and 𝟏 + 𝝐𝑫𝑨𝑪 = 𝑪 +𝑪
𝟏+ 𝑭 𝟏+ 𝑺 𝑭 𝑪𝑭
𝑨𝑪𝑭 𝑨𝑪𝑭

X. Wang, P. J. Hurst, and S. H. Lewis, IEEE JSSC, vol. 39, pp. 1799-1808, Nov. 2004.
Slides by Bibhudatta Sahoo -109-
109
Nested Digital Background Calibration (2)

 Digital output computation from the raw bits,

𝑽𝒊𝟏 = 𝑽𝑹 𝟎. 𝟓 𝟏 + 𝝐𝟏 𝒃𝟏 + 𝟎. 𝟓𝟐 𝟏 + 𝝐𝟐 𝒃𝟐 + 𝒒𝒂 𝟎. 𝟓𝟐 𝟏 + 𝝐𝟑
where, 𝝐𝟏 = 𝝐𝟏𝟐 , 𝝐𝟐 = 𝝐𝟏𝟏 + 𝝐𝟐𝟐 + 𝝐𝟏𝟏 𝝐𝟏𝟐, 𝝐𝟑 = 𝝐𝟏𝟏 + 𝝐𝟐𝟏 + 𝝐𝟏𝟏 𝝐𝟐𝟏 , and
𝒒𝒂 is the quantization noise.
 So 4 parameters are needed for a 2-stage pipeline
 Three (𝝐𝟏 , 𝝐𝟐 , and 𝝐𝟑 ) for the gain errors
 One more for the overall offset of the pipelined stages.
 For a K-stage ADC, (K+2) parameters need to be estimated,
including the offset term.
X. Wang, P. J. Hurst, and S. H. Lewis, IEEE JSSC, vol. 39, pp. 1799-1808, Nov. 2004.
Slides by Bibhudatta Sahoo -110-
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Nested Digital Background Calibration (3)
 Pipelined ADC core has 13-
stages.
 First 5-stages are calibrated.

 Digital output computation from the raw bits,

𝟏𝟑 𝟓

𝑫𝒑𝒊𝒑 (𝑽𝒊𝟏 ) = 𝟎. 𝟓𝒊 𝒃𝒊 + 𝟎. 𝟓𝒊 𝝐𝒊 𝒃𝒊 + 𝟎. 𝟓𝟓 𝒒 + 𝒐𝒇𝒇𝒔𝒆𝒕

𝒊=𝟏 𝒊=𝟏
 LMS optimization can be used to minimize the error,
𝒆 = 𝑫𝒑𝒊𝒑 − 𝑫𝒂𝒍𝒈
 The update equation is,
𝝏𝒆
𝝐𝒊 𝒎 + 𝟏 = 𝝐𝒊 𝒎 + 𝝁𝒑𝒊𝒑 𝒆
𝝏𝝐𝒊
X. Wang, P. J. Hurst, and S. H. Lewis, IEEE JSSC, vol. 39, pp. 1799-1808, Nov. 2004.
Slides by Bibhudatta Sahoo -111-
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Nested Digital Background Calibration (4)
 For 𝝐𝟏 to 𝝐𝟓 , the derivative of
MSE is zero,
𝝏𝑬 𝒆𝟐 𝝏𝒆 𝝏𝑫𝒑𝒊𝒑
= 𝑬 𝟐𝒆 = 𝑬 𝟐𝒆
𝝏𝝐𝒊 𝝏𝝐𝒊 𝝏𝝐𝒊
𝒊
= 𝟐 𝟎. 𝟓 𝑬 𝒆 ∙ 𝒃𝒊 = 𝟎 𝟏 ≤ 𝒊 ≤ 𝟓.

 For 𝝐𝟔 ,
𝝏𝑬 𝒆𝟐 𝝏𝒆 𝝏𝑫𝒑𝒊𝒑
= 𝑬 𝟐𝒆 = 𝑬 𝟐𝒆
𝝏𝝐𝟔 𝝏𝝐𝟔 𝝏𝝐𝟔
= 𝟐 𝟎. 𝟓 𝟓 𝑬 𝒆 ∙ 𝒒 = 𝟎
 For offset,
𝝏𝑬 𝒆𝟐 𝝏𝒆
= 𝑬 𝟐𝒆
𝝏(𝒐𝒔) 𝝏(𝒐𝒔)
𝝏𝑫𝒑𝒊𝒑
= 𝑬 𝟐𝒆 = 𝟐𝑬 𝟏 ∙ 𝒆 = 𝟎
𝝏(𝒐𝒔)

X. Wang, P. J. Hurst, and S. H. Lewis, IEEE JSSC, vol. 39, pp. 1799-1808, Nov. 2004.
Slides by Bibhudatta Sahoo -112-
112
Nested Digital Background Calibration (5)

 The algorithmic ADC is calibrated based on the

calibration technique proposed by Erdogan 1999.
 Erdogan used a 1-bit architecture for the stage.
Here 1.5-bit flip-around topology is used instead.
X. Wang, P. J. Hurst, and S. H. Lewis, IEEE JSSC, vol. 39, pp. 1799-1808, Nov. 2004.
Slides by Bibhudatta Sahoo -113-
113
10-bit 500 MHz 55 mW CMOS ADC (1)

A. Verma and B. Razavi, IEEE JSSC, vol.

44, pp. 3039-3050, Nov. 2009.

 All stages use 1.5-bit flip-around topology.

 Gain error, capacitor mismatch, and op amp nonlinearity correction done in
the 1st two stages.
 Gain error and capacitor mismatch calibration done in stage 3 to 6.
 No calibration for the remaining stages.
 LMS is used to do gain error and op amp nonlinearity calibration.

Slides by Bibhudatta Sahoo -114-

114
10-bit 500 MHz 55 mW CMOS ADC (2)
 Calibration requires a precision DAC.
 For the 10-bit system here the
reference DAC has to be 11-bit linear
 Calibration applies 𝑽𝑹/𝟐, 𝑽𝑹/𝟒, and 0
from the reference DAC to stage-𝒋 for
calibration.
 Stage-𝒋 is configured in multiply-by-𝟐
configuration.
 The digitized output of stage-𝒋 is given by
𝑫𝒕𝒐𝒕 = 𝜶𝟏 𝑫𝑩𝑲 + 𝜶𝟑 𝑫𝟑𝑩𝑲
 1 and 3 are updated using the following
LMS equation:
𝜶𝟏 𝒌 + 𝟏 = 𝜶𝟏 𝒌 + 𝝁 𝑫𝒄𝒂𝒍 − 𝑫𝒕𝒐𝒕 𝑫𝑩𝑲
𝜶𝟑 𝒌 + 𝟏 = 𝜶𝟑 𝒌 + 𝝁 𝑫𝒄𝒂𝒍 − 𝑫𝒕𝒐𝒕 𝑫𝟑𝑩𝑲

A. Verma and B. Razavi, IEEE JSSC, vol.

44, pp. 3039-3050, Nov. 2009.

Slides by Bibhudatta Sahoo -115-

115
10-bit 500 MHz 55 mW CMOS ADC (3)

A. Verma and B. Razavi, IEEE JSSC, vol. 44, pp. 3039-3050, Nov. 2009.
Slides by Bibhudatta Sahoo -116-
116
10-bit 500 MHz 55 mW CMOS ADC (5)
 Calibration requires a precision DAC.
 For a10-bit system the reference DAC has to be 11-bit linear
 For a 12-bit system the reference DAC has to be 13-bit linear
 Difficult to realize highly linear and precise DACs
 The calibration technique cannot be used to calibrate more
than 10-bit systems.
 Calibration applies signals from the resistor ladder 
calibration cannot be run at the full-speed of the ADC
because of the RC-settling issue.
 High frequency settling behavior of the op amps is not
captured.

A. Verma and B. Razavi, IEEE JSSC, vol. 44, pp. 3039-3050, Nov. 2009.
Slides by Bibhudatta Sahoo -117-
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Conclusion
 In the last 20 years various digital calibration techniques
have been developed.
 Goal is to overcome various circuit non-idealities like finite
op amp gain, op amp nonlinearity, and capacitor mismatch.
 Digital calibration techniques can be categorized as:
 Background
 Foreground
 Digital calibration technique calibrates for:
 Capacitor mismatch
 Linear Gain Error
 Op amp nonlinearity

Slides by Bibhudatta Sahoo -118-

118
 Thank You

Slides by Bibhudatta Sahoo -119-

119
 References
Scaling Trends:
[1] S. Borkar, “Design challenges of technology scaling,” IEEE Micro, vol. 19, no. 4, pp. 23–29, 1999.
[2] K. Bult, “The Effect of Technology Scaling on Power Dissipation in Analog Circuits,” in Analog
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