Interrupts

! Interrupts allow a device to change the flow of

control in the CPU
 Time

Main program (base level, foreground)

Program execution without interrupts

Interrupt ISR
ISR ISR
level execution

Base-level Main Main Main Main

execution
Interrupt (occurs asynchronously)
Return from interrupt instruction
 2

! Suppose a peripheral intermittently receives data,

which must be serviced by the processor
! The processor can poll the peripheral regularly to see if data
has arrived – wasteful
! The peripheral can interrupt the processor when it has data
! Requires an extra pin or pins: Int
! If INT is 1, processor suspends current program, jumps to an
Interrupt Service Routine, or ISR
! Known as interrupt-driven I/O
! Essentially, polling of the interrupt pin is built-into the
hardware, so no extra time!
 Interrupt Address Vector
3

(interrupt address vector) of the ISR

! Fixed interrupt
" Address built into microprocessor, cannot be changed
" Either ISR stored at address or a jump to actual ISR
stored if not enough bytes available
! Vectored interrupt
" Peripheralmust provide the address
" Common when microprocessor has multiple peripherals
connected by a system bus
! Compromise: interrupt address table
Interrupt-driven I/O using fixed ISR location
5
1(a): µP is executing its main program. 1(b): P1 receives input data in a
Time

register with address 0x8000.

2: P1 asserts Int to request

servicing by the microprocessor.
3: After completing instruction at 100, µP sees
Int asserted, saves the PC s value of 100,
and sets PC to the ISR fixed location of 16.

4(a): The ISR reads data from 0x8000, 4(b): After being read, P1 de-
modifies the data, and writes the resulting asserts Int.
data to 0x8001.

5: The ISR returns, thus restoring PC to

100+1=101, where µP resumes executing.
 Interrupt-driven I/O using fixed ISR location
6
1(a): µP is executing its main program
1(b): P1 receives input data in a register with address 0x8000.

Program memory µP Data memory

ISR
16: MOV R0, 0x8000
System bus
17: # modifies R0
18: MOV 0x8001, R0
19: RETI # ISR return
... P1 P2
Int
Main program
... PC 0x8000 0x8001
100: instruction
101: instruction
 Interrupt-driven I/O using fixed ISR location
7

2: P1 asserts Int to request servicing by the microprocessor

Program memory µP Data memory

ISR
16: MOV R0, 0x8000
System bus
17: # modifies R0
18: MOV 0x8001, R0
19: RETI # ISR return
... P1 P2
Int
Main program 1
... PC 0x8000 0x8001
100: instruction
101: instruction
 Interrupt-driven I/O using fixed ISR location
8

3: After completing instruction at 100, µP sees Int asserted, saves the PC s value of
100, and sets PC to the ISR fixed location of 16.

Program memory µP Data memory

ISR
16: MOV R0, 0x8000
System bus
17: # modifies R0
18: MOV 0x8001, R0
19: RETI # ISR return
... P1 P2
Int
Main program
... PC 1 0x8000 0x8001
100: instruction
101: instruction 100
 Interrupt-driven I/O using fixed ISR location
9

4(a): The ISR reads data from 0x8000, modifies the data, and writes the resulting
data to 0x8001.
4(b): After being read, P1 deasserts Int.

Program memory µP Data memory

ISR
16: MOV R0, 0x8000
17: # modifies R0 System bus
18: MOV 0x8001, R0
19: RETI # ISR return
... Int P1 P2
Main program
... PC 0x8000 0x8001
100: instruction
101: instruction
Interrupt-driven I/O using fixed ISR location
10

5: The ISR returns, thus restoring PC to 100+1=101, where µP resumes executing.

Program memory µP Data memory

ISR
16: MOV R0, 0x8000
17: # modifies R0 System bus
18: MOV 0x8001, R0
19: RETI # ISR return
... Int P1 P2
Main program
... PC
100: instruction 0x8000 0x8001
+1
101: instruction 100
 Interrupt-driven I/O using vectored interrupt
11

1(a): µP is executing its main program. 1(b): P1 receives input data in a

Time

register with address 0x8000.

2: P1 asserts Int to request servicing

3: After completing instruction at 100, µP sees by the microprocessor.
Int asserted, saves the PC s value of 100, and
asserts Inta. 4: P1 detects Inta and puts interrupt
address vector 16 on the data bus.

5(a): µP jumps to the address on the bus (16).

The ISR there reads data from 0x8000, modifies
the data, and writes the resulting data to 0x8001. 5(b): After being read, P1 deasserts
Int.

6: The ISR returns, thus restoring PC to

100+1=101, where µP resumes executing.
 Interrupt-driven I/O using vectored interrupt
12

1(a): P is executing its main program Program memory µP Data memory

ISR
1(b): P1 receives input data in a register 16: MOV R0, 0x8000
with address 0x8000. 17: # modifies R0 System bus
18: MOV 0x8001, R0
19: RETI # ISR return
... Inta P1 P2
Main program Int
... PC 16
100: instruction 0x8000 0x8001
101: instruction 100
 Interrupt-driven I/O using vectored interrupt
13

2: P1 asserts Int to request servicing by the Program memory µP Data memory

microprocessor ISR
16: MOV R0, 0x8000
17: # modifies R0 System bus
18: MOV 0x8001, R0
19: RETI # ISR return
... Inta P1 P2
Main program Int
... PC 1 16
100: instruction 0x8000 0x8001
101: instruction 100
 Interrupt-driven I/O using vectored interrupt
14

3: After completing instruction at 100, µP Program memory µP Data memory

sees Int asserted, saves the PC s value of ISR
100, and asserts Inta 16: MOV R0, 0x8000
17: # modifies R0 System bus
18: MOV 0x8001, R0
19: RETI # ISR return 1
... Inta P1 P2
Main program Int
... PC 16
100: instruction 0x8000 0x8001
101: instruction 100
 Interrupt-driven I/O using vectored interrupt
15

4: P1 detects Inta and puts interrupt Program memory µP Data memory

address vector 16 on the data bus ISR
16: MOV R0, 0x8000
17: # modifies R0 16 System bus
18: MOV 0x8001, R0
19: RETI # ISR return
... Inta P1 P2
Main program Int
... PC 16
100: instruction 0x8000 0x8001
101: instruction 100
 Interrupt-driven I/O using vectored interrupt
16

5(a): PC jumps to the address on the Program memory µP Data memory

bus (16). The ISR there reads data ISR
from 0x8000, modifies the data, and 16: MOV R0, 0x8000
17: # modifies R0 System bus
writes the resulting data to 0x8001.
18: MOV 0x8001, R0
19: RETI # ISR return
... Inta P1 P2
5(b): After being read, P1 deasserts Int. Int
Main program
... PC 0 16
100: instruction 0x8000 0x8001
101: instruction 100
 Interrupt-driven I/O using vectored interrupt
17

6: The ISR returns, thus Program memory µP Data memory

ISR
restoring the PC to 100+1=101, 16: MOV R0, 0x8000
where the µP resumes 17: # modifies R0 System bus
18: MOV 0x8001, R0
19: RETI # ISR return
... Int P1 P2
Main program
... PC 0x8000 0x8001
100: instruction +1
101: instruction 100
 Interrupt address table
18

! Compromise between fixed and vectored interrupts

! One interrupt pin

! Table in memory holding ISR addresses

" (maybe 256 words)
! Peripheral doesn t provide ISR address, but rather index
into table
" Fewer bits are sent by the peripheral
" Can move ISR location without changing peripheral
 Additional interrupt issues
19

! Maskable vs. non-maskable interrupts

! Maskable: programmer can set bit that causes processor to ignore
interrupt
" Important when in the middle of time-critical code
! Non-maskable: a separate interrupt pin that can t be masked
" Typically reserved for drastic situations, like power failure requiring
immediate backup of data to non-volatile memory
! Jump to ISR
! Some microprocessors treat jump same as call of any subroutine
" Complete state saved (PC, registers) – may take hundreds of cycles
! Others only save partial state, like PC only
" Thus, ISR must not modify registers, or else must save them first
" Assembly-language programmer must be aware of which registers stored
 AVR Interrupt Structure
20

! There are four (4) external interrupts associated with Atmel's ATMega8515
AVR microcontroller. Namely: RESET, External Interrupt 0 (INT0), External
Interrupt 1 (INT1) and External Interrupt 2 (INT2).The pins associated with
these interrupts are shown in the figure below.
AVR Interrupt Structure
21
Intel 8259 programmable priority controller
26
Signal Description
D[7..0] These wires are connected to the system bus and are used by the microprocessor to
write or read the internal registers of the 8259.
D[7..0] Intel 8259 IR0
A[0..0] This pin actis in cunjunction with WR/RD signals. It is used by the 8259 to decipher
A[0..0] IR1
RD IR2 various command words the microprocessor writes and status the microprocessor
WR IR3 wishes to read.
INT IR4
INTA IR5 WR When this write signal is asserted, the 8259 accepts the command on the data line, i.e.,
IR6 the microprocessor writes to the 8259 by placing a command on the data lines and
CAS[2..0] IR7 asserting this signal.
SP/EN
RD When this read signal is asserted, the 8259 provides on the data lines its status, i.e., the
microprocessor reads the status of the 8259 by asserting this signal and reading the data
lines.

INT This signal is asserted whenever a valid interrupt request is received by the 8259, i.e., it
is used to interrupt the microprocessor.

INTA This signal, is used to enable 8259 interrupt-vector data onto the data bus by a sequence
of interrupt acknowledge pulses issued by the microprocessor.

IR An interrupt request is executed by a peripheral device when one of these signals is

0,1,2,3,4,5,6,7 asserted.
CAS[2..0] These are cascade signals to enable multiple 8259 chips to be chained together.

SP/EN This function is used in conjunction with the CAS signals for cascading purposes.
 27

INT
CPU

PIC

RAM I/O (1)

ROM I/O (2)

I/O (N)

Fig: 7 Handling a number of interrupts

 Internal Architecture
28

INTA INT

DATA
D7-D0 BUS CONTROL LOGIC
BUFFER

IR0
RD READ/ IR1
WR WRITE IN- INTERRUPT IR2
A0 LOGIC SERVICE PRIORITY REQUEST IR3
REG RESOLVER REG IR4
(ISR) IR5
CS (IRR)
IR6
IR7
CAS 0 CASCADE
INTERRUPT MASK REG
CAS 1 BUFFER
(IMR)
CAS 2 COMPARATOR

SP/EN INTERNAL BUS

Fig: 9 The Functional Block Diagram

 29

Interrupt Request Register (IRR) and In-Service

Register (ISR)
! The interrupts at the IR input lines are handled by
two registers in cascade, the Interrupt Request
Register (lRR) and the In- Service Register (lSR).
The IRR is used to indicate all the interrupt levels
which are requesting service, and the ISR is used to
store all the interrupt levels which are currently
being serviced.
 30

Priority Resolver
! This logic block determines the priorities of the bits
set in the lRR. The highest priority is selected and
strobed into the corresponding bit of the lSR during
the INTA sequence.
Interrupt Mask Register (IMR)
! The lMR stores the bits which disable the interrupt
lines to be masked. The IMR operates on the output
of the IRR. Masking of a higher priority input will not
affect the interrupt request lines of lower priority.
 31

Data Bus Buffer

! This 3-state, bidirectional 8-bit buffer is used to interface the PIC to the
System Data Bus. Control words and status information are transferred
through the Data Bus Buffer.

Read/Write Control Logic

! The function of this block is to accept output commands from the CPU. It
contains the Initialization Command Word (lCW) registers and Operation
Command Word (OCW) registers which store the various control formats for
device operation. This function block also allows the status of the PIC to be
transferred onto the Data Bus. This function block stores and compares the
IDs of all PICs used in the system. The associated three I/O pins (CAS0- 2) are
outputs when the 8259 is used as a master and are inputs when the 8259 is
used as a slave. As a master, the 8259 sends the ID of the interrupting slave
device onto the CAS0 - 2 lines. The slave, thus selected will send its
preprogrammed subroutine address onto the Data Bus during the next one or
two consecutive INTA pulses.
 Daisy Chain
32

ADDRESS BUS (16)

CONTROL BUS
INT REQ
DATA BUS (8)

CS A0 D7 – D0 INTA INT CS A0 D7 – D0 INTA INT CS A0 D7 – D0 INTA INT

CAS 0 CAS 0 CAS 0
82C59A SLAVE A CAS 1 82C59A SLAVE B CAS 1 CAS 1 MASTER 82C59A
CAS 2 CAS 2 CAS 2
SP/EN 7 6 5 4 3 2 1 0 SP/EN 7 6 5 4 3 2 1 0 SP/EN 7 6 5 4 3 2 1 0

GND 7 6 5 4 3 2 1 0 GND 7 6 5 4 3 2 1 0 VCC 7 6 5 4 3 2 1 0

INTERRUPT REQUESTS

Fig: 10 Nested Connection of Interrupts