Major Assignment - General Major Assignment - Presentation

• Excellent effort – Average mark was 17/20. • Report structure:

• Most p
people
p reached 14% efficiency.y – Executive summary (optional);
– Some vpl files appeared a little more frequently than they – Introduction;
should have... – Report body containing a section for each optimised process;
• Some variation between markers inevitable. – Conclusion;
• Explanation – References (if necessary).
– Most people lost marks because they didn’t provide enough • All figures and graphs should be labelled with a caption.
supporting information. • Graph axes were often poorly labelled – must include
• Some tried to exploit the reflectance problem. units. E.g., Time (min).
– Not penalised
li d on efficiency
ffi i bbut penalised
li d iin explanation.
l i • Graphsh “tell
ll a story” – you don’t
d need
d to explain
l i what
h
• Minority lifetime bug meant that the Al screen printing the graph shows in the text.
setup was not critical.
– Why?
– Marks were not deducted if you chose not to optimise that
process.

Major Assignment – Presentation Major Assignment – Written Expression

• When listing results of a batch don’t list individual wafer • Use complete sentences.
values - report mean ± SD. • Avoid note style.
y E.g.,
g , →.
– SD provides information about the spread of the parameter –
this is very important for manufacturing. • Use spelling/gramma checkers!
– Significant figures? × 269.4 ± 2.87 μm • Bullet points are ok but with the correct punctuation.
E.g.
√ 269 ± 3 μm The following processes were optimised:
• Saw damage etch;
• Texturing;
• Etc.; and
• Cofiring.
• The text should always refer to any figures. E.g.,
By varying the texturing temperature (see Figure 3),
it was found that the pyramid coverage could be
increased to 99% using a temperature of 90 ºC.

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 Major Assignment – Explanation Major Assignment – Explanation
• Many proposed an optimisation without justifying it • Didn’t need to explain the general theory behind the
with simulation results. process.
• Should include graphs that shows how the parameter • Should try and relate factors to their impact on cell
being optimised varies with a process parameter. parameters (Voc, Isc and FF) and not just directly link
• Texturing example: them to cell efficiency.
• In general the summary/conclusion was not done well.
– Most just included a table of parameters before and after
optimisation.
– Very few provided a justification of their sampling method.

Major Assignment - Optimisations Major Assignment – Saw Damage Etch

• Problem: Too little Si etched. Initial thickness ~ 270
μm - need to etch at least 20 μm each side for wire-
1. Saw damageg etch sawn wafers
wafers.
2. Texturing • Defects remain on surface → can be propagated into the
3. Diffusion bulk during processing → ↓minority carrier lifetimes.
4. Edge isolation • Methodology: Show how you can vary process to
5. Antireflection coating increase the amount of Si etched.
• Graph Si etched vs etching time/temperature .
6. Ag screen printing • Show the benefit of the optimisation by graphing either
7. Al screen printing average efficiency, VOC as a function of etching temp/Si
8. Cofiring etched.
t h d
• Solution: Etch at least 40-50 μm by increasing etching
temperature/time
• No point increasing [NaOH] because maximum etching rate
is ~ 30% (w/v) [NaOH].
• Best to choose a solution which keeps time short – Why?

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 Major Assignment – Texturing Major Assignment – Diffusion
• Problem: Coverage only ~ 30% and pyramid size < • Problem: Emitter sheet resistance ~ 70 Ω/ (too
3 μm → higher reflectance.
reflectance high) and junction is too shallow (290 nm).
nm)
• Reduced JSC • Low lateral conductance
• Methodology: Show how you can vary process • High contact resistance
parameters to improve above parameters. • High series resistance due to shallow junction.
• Graph “% coverage” and “pyramid size” against • Methodology: Show how you can vary process to
time/temperature. improve above parameters.
• Show reflectance curve before and after optimisation • Graph sheet resistance and junction depth against belt
without ARC – Why? speed
p and/or Zone 2 temperature.
p
• Solution: Increase etching temperature/time to get ~ • Show doping profile before and after optimisation.
5 μm pyramids and ~ 100% coverage. Final • Solution: Decrease sheet resistance to 45-50 Ω/
reflectance should be 10-11%. and increase junction depth to ~ 500 nm by
• Best to choose a solution which keeps time short – Why? increasing diffusion temperature or reducing belt
speed.

Major Assignment – Diffusion Major Assignment – Edge Isolation

• Problem: Emitter sheet resistance ~ 70 Ω/ (too • Problem: Plasma power is too high
high) and junction is too shallow (~
( 290 nm).
nm) • J
Junction
i ddamage → high
hi h ideality
id li factor
f → reduced
d d FF,
FF
• Low lateral conductance efficiency.
• High contact resistance • Methodology: Show how you can vary process to
• High series resistance due to shallow junction. improve above parameters.
• Methodology: Show how you can vary process to • Graph plasma power vs FF/efficiency to show lower power
improve above parameters. is beneficial.
• Graph sheet resistance and junction depth against belt • Demonstrate that even though the shunt resistance is
speed
p and/or Zone 2 temperature.
p decreased, the emitter is still isolated (e.g., Voc contour
map)
• Show doping profile before and after optimisation.
• Solution: Decrease plasma power to 300-400 W and
• Solution: Decrease sheet resistance to 45-50 Ω/ increase time.
and increase junction depth to ~ 500 nm by • Shunt resistance should remain > 250 Ω.
increasing diffusion temperature or reduce belt
speed.

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 Major Assignment – ARC Major Assignment – ARC (cont)
• Problem: Refractive index is too low (1.75) and
layer too thick (~ 89 nm).
• R fl ti it is
Reflectivity i increased
i d → reduced
d d JSC.
• Methodology: Show how you can vary process to
improve above parameters.
• Graph deposition time vs thickness.
• Graph gas ratio vs refractive index.
• Show reflectance/spectral response before and after
optimisation.
• Solution: Ratio of gas flows should be ~11 to get a
refractive index ~ 2 and time should be decreased to
get a layer thickness of 75 nm (for 600 nm).
• Can also increase temperature to make the layer harder so
you can cofire at a higher temperature.

Major Assignment – Ag Screen Printing Major Assignment – Al Screen Printing

• Problem: Fingers aren’t thick enough and are spaced
too far apart. • Problem: Aluminium layer is too thin (5 um).
• Hi h fi
High finger andd lateral
l t l resistance
it → high
hi h series
i resistance.
it • Poor BSF → poor long wavelength spectral response.
• Al can all be consumed in the firing process.
• Methodology: Show how you can vary process to
improve above parameters. • Methodology: Show how you can vary process to
• Graph emulsion thickness & finger width vs finger resistance.
improve above parameters.
• Graph finger spacing vs series resistance. • Graph emulsion thickness vs Voc (very little change).
• Show spectral response before and after optimisation
• Solution: Increase emulsion height (thicker fingers) (slight improvement in long wavelength response).
increase finger width to get more conductive fingers, • Solution: Increase emulsion thickness to > 20 μm to
and decrease finger spacing to reduce lateral ensure sufficiently
ffi i l thick
hi k Al layer.
l
resistance.
• Screen design not that critical if printing a solid layer.
• Can also reduce mesh density to get more paste through.
• Make sure squeegee pressure not too high else hard to get a
• Finger width should be ≥ 4 × strand diameter. thick layer.
• Finger width should be ≥ 2 × mesh spacing. • All given full marks for this section because simulation was
not sensitive to these parameters because of mcl bug.

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 Major Assignment – Cofiring Major Assignment – Conclusion
• Problem: Cofiring temperature is not optimised for • List table with before and after parameters.
Solar Magic’s diffusion and ARC. Depending on your • Describe your sampling approach.
ARC hardness the firing temperature may have needed • Does a batch size of only 5 accurately represent the
to be reduced/increased. yield?
• If firing temp too high → Ag pentetrates too far → high series
resistance due to current crowding. • Show before and after IV curves and spectral response
• If firing temp too low → Ag does not penetrate the ARC. curves and generally discuss improvements with
• Methodology: Show how you can vary process to reference to these VPL outputs.
improve above parameters.
• Graph series resistance vs Z2 temperature/belt speed.
• Solution: Change firing temperature/belt speed to
minimise series resistance.
• Z1 and Z3 should be 150 ºC < Z2 temperature. Why?

Frequently-Asked Questions Photoluminescence (PL)

• Why are the regions of high lifetime bright?

Conduction Band
PL ∝ ne nh
• Minority carrier lifetimes in Si are dominated
by recombination via traps (defects).
• PL detects radiative recombination (i.e.,
Absorbed
Emitted Emitted emitted photons).
Energy
phonon photon • Proportionality to ne and nh comes from
(a) (b) (c) aanalysis
a ys s of
o radiative
ad a ve recombination
eco b a o – not o
covered in this course.
• PL signal can be recorded in decay mode and
in QSS mode (e.g., like PCD).
Energy

Valence Band • PL imaging is recorded under steady-state

(SS) conditions.

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 Photoluminescence (PL) - Cont PL with Current Extraction (PLCE)
• PL Imaging: What about reflected laser light?

• Laser is directed at an angle to minimise capture of • Bright areas – higher series resistance. Why?
reflected light. • Carriers (e.g., electrons) are not removed by contacts
• PL camera has filters for laser light. therefore np increases.

Efficiency in Low Light Efficiency of c-Si Cells in Low Light

• Outdoor: 50-1000 W/m2: Indoor: ~ 0.1 W/m2
• Why y do manyy thin film technologies
g experience
p less
efficiency loss than c-Si cells at low lighting levels?
• Quite complicated because of quite different (thin film)
technologies involved.
• When edges are plasma etched for c-Si cells this is
probably true because junction defects result in ideality • Voc drops logarithmically with light level.
factors > 1. • But at low light Voc increases in c-Si cells due to temperature
– At low light these defects result in ↑SRH recombination in the coefficient (-2.2 mV/ºC).
d l ti region.
depletion i • So as long as edge defects are minimised (and hence n ~ 1 at
• Comparison is further complicated because some thin MPP), for c-Si cells loss of efficiency can be comparable with that
film cells have high Rs. of thin film technologies.
– Lower currents result is reduced voltage loss. • E.g., Pluto cells keep the same efficiency at 1-sun and 0.2 suns
because the lower T at 0.2 suns (that gives higher Voc)
– If Rs is very high then efficiency can actually increase in low- compensates for the loss in Voc due to the lower current density
light! (i.e. they approx balance).

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Other Questions