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The document outlines a timing analysis for a clock path from 'clk_cpu' to 'iram_blk_idc_dirty_ram_dc_dirty_ram0/u_mem'. It details the incremental path delays at various points in the circuit, indicating the timing characteristics of each component involved. The analysis focuses on the maximum path type and recovery checks against the rising edge of the clock signal.

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2 views

Default_S

The document outlines a timing analysis for a clock path from 'clk_cpu' to 'iram_blk_idc_dirty_ram_dc_dirty_ram0/u_mem'. It details the incremental path delays at various points in the circuit, indicating the timing characteristics of each component involved. The analysis focuses on the maximum path type and recovery checks against the rising edge of the clock signal.

Uploaded by

chia wei liu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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Startpoint: clk_cpu (clock source 'clk_cpu')

Endpoint: iram_blk_idc_dirty_ram_dc_dirty_ram0/u_mem
(rising-edge recovery check against clock clk_cpu)
Path Group: default
Path Type: max

Point
Incr Path

-----------------------------------------------------------------------------------
--------------------------------------------------------------
clock clk_cpu (rise edge)
0.0 0.0
clk_cpu (in)
0.0 @ 0.0 r
CTSSTL_INV_S_2_G1B35I1/A (STL_INV_S_12) <-
0.0 @ 0.0 r
CTSSTL_INV_S_2_G1B35I1/X (STL_INV_S_12) <-
0.0 @ 0.0 f
CTSSTL_INV_S_12_G1B34I1/A (STL_INV_S_12) <-
0.0 @ 0.0 f
CTSSTL_INV_S_12_G1B34I1/X (STL_INV_S_12) <-
0.0 @ 0.1 r
CTSSTL_INV_S_12_G1B24I1/A (STL_INV_S_12) <-
0.0 @ 0.1 r
CTSSTL_INV_S_12_G1B24I1/X (STL_INV_S_12) <-
0.0 @ 0.1 f
CTSSTL_INV_S_6_G1B23I1/A (STL_INV_S_12) <-
0.0 @ 0.1 f
CTSSTL_INV_S_6_G1B23I1/X (STL_INV_S_12) <-
0.0 @ 0.1 r
CTSSTL_INV_S_12_G1B20I1/A (STL_INV_S_4) <-
0.0 @ 0.1 r
CTSSTL_INV_S_12_G1B20I1/X (STL_INV_S_4) <-
0.0 @ 0.1 f
CTSSTL_INV_S_8_G1B19I1/A (STL_INV_S_8) <-
0.0 @ 0.1 f
CTSSTL_INV_S_8_G1B19I1/X (STL_INV_S_8) <-
0.0 @ 0.1 r
CTSSTL_INV_S_8_G1B12I1/A (STL_INV_S_12) <-
0.0 @ 0.1 r
CTSSTL_INV_S_8_G1B12I1/X (STL_INV_S_12) <-
0.0 @ 0.2 f
CTSSTL_INV_S_8_G1B11I2/A (STL_INV_S_12) <-
0.0 @ 0.2 f
CTSSTL_INV_S_8_G1B11I2/X (STL_INV_S_12) <-
0.0 @ 0.2 r
CTSSTL_INV_S_12_G1B10I1/A (STL_INV_S_4) <-
0.0 @ 0.2 r
CTSSTL_INV_S_12_G1B10I1/X (STL_INV_S_4) <-
0.0 @ 0.2 f
CTSSTL_INV_S_12_G1B9I1/A (STL_INV_S_6) <-
0.0 @ 0.2 f
CTSSTL_INV_S_12_G1B9I1/X (STL_INV_S_6) <-
0.0 @ 0.3 r
CTSSTL_INV_S_6_G1B4I17/A (STL_INV_S_8) <-
0.0 @ 0.3 r
CTSSTL_INV_S_6_G1B4I17/X (STL_INV_S_8) <-
0.0 @ 0.3 f
CTSSTL_INV_S_4_G1B3I6/A (STL_INV_S_6) <-
0.0 @ 0.3 f
CTSSTL_INV_S_4_G1B3I6/X (STL_INV_S_6) <-
0.0 @ 0.4 r
CTS_CTS_clk_cpu_CTO_delay3573/A (STL_BUF_S_4) <-
0.0 @ 0.4 r
CTS_CTS_clk_cpu_CTO_delay3573/X (STL_BUF_S_4) <-
0.0 @ 0.4 r
CTSSTL_INV_S_8_G1B2I15/A (STL_INV_S_6) <-
0.0 @ 0.4 r
CTSSTL_INV_S_8_G1B2I15/X (STL_INV_S_6) <-
0.0 @ 0.4 f

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