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The report provides timing analysis for the design 'cpu_isle' with a focus on maximum rise delay. It indicates that 99.50% of delays are based on Arnoldi methods, with a detailed breakdown of clock and data arrival times. The report also includes specific timing metrics related to clock propagation and recovery times.

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chia wei liu
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1 views

5

The report provides timing analysis for the design 'cpu_isle' with a focus on maximum rise delay. It indicates that 99.50% of delays are based on Arnoldi methods, with a detailed breakdown of clock and data arrival times. The report also includes specific timing metrics related to clock propagation and recovery times.

Uploaded by

chia wei liu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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****************************************

Report : timing
-path ful
-delay max_rise

////
/
/
/
/
/
############################
##########################
-sort_by group
Design : cpu_isle
Version: U-2022.12-SP6
Date : Tue Sep 17 16:06:12 2024
****************************************

* Some/all delay information is back-annInformation: Percent of Arnoldi-based


delays = 99.50%

Information: Percent of CCS-based delays = 0.13%

Startpoint: clk_cpcpu')
Endpoint: iram_blk_idc_dirty_ram_dc_dirty_ram (rising-edge recovery check against
clock clk_cpu)
Path Group: default
Path Type: max

Point
Incr Path

-----------------------------------------------------------------------------------
--------------------------------------------------------------
clock clk_cpu (rise edge)
0.0 0.0
clk_cpu (in)
0.0 @ 0.0 r
CTSSTL_INV_S_2_G1B35I1/A (STL_INV_S_12) <-
0.0 @ 0.0 r
CTSSTL_INV_S_2_G1B35I1/X (STL_INV_S_12) <-
0.0 @ 0.0 f
CTSSTL_INV_S_12_G1B34I1/A (STL_INV_S_12) <-
0.0 @ 0.0 f
CTSSTL_INV_S_12_G1B34I1/X (STL_INV_S_12) <-
0.0 @ 0.1 r
CTSSTL_INV_S_12_G1B24I1/A (STL_INV_S_12) <-
0.0 @ 0.1 r
CTSSTL_INV_S_12_G1B24I1/X (STL_INV_S_12) <-
0.0 @ 0.4 f
CTSSTL_INV_S_8_G1B1I5/A (STL_INV_S_6) <-
0.0 @ 0.4 f
CTSSTL_INV_S_8_G1B1I5/X (STL_INV_S_6) <-
0.0 @ 0.5 r
iram_blk_idc_dirty_ram_dc_dirty_ram0/CLKB
(mem_ts45nkkb2p11sadrl32ksa18p7_512x8_cm4_bk2_cdfalse_bwe1_byes_rno_wrapper) <-
0.0 0.5 r
iram_blk_idc_dirty_ram_dc_dirty_ram0/u_mem/CLKB
(mem_ts45nkkb2p11sadrl32ksa18p7_512x8_cm4_bk2_cdfalse_bwe1_byes_rno) 0.0
@ 0.5 r
data arrival time
0.5

clock clk_cpu (rise edge)


1.0 1.0
clock network delay (propagated)
0.4 1.4
clock reconvergence pessimism
0.0 1.4
inter-clock uncertainty
-0.1 1.3
iram_blk_idc_dirty_ram_dc_dirty_ram0/u_mem/CLKA
(mem_ts45nkkb2p11sadrl32ksa18p7_512x8_cm4_bk2_cdfalse_bwe1_byes_rno) 0.0
1.3 r
library recovery time
-0.9 0.4
data required time
0.4

-----------------------------------------------------------------------------------
--------------------------------------------------------------
data required time

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