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20EVE23

This document outlines the structure and content of the Second Semester M.Tech. Degree Examination for System Verilog, including instructions for answering questions and guidelines to avoid malpractice. It consists of five modules, each containing two questions, from which students must choose one. The examination covers various topics such as verification processes, simulation phases, array methods, test bench design, randomization, threading concepts, and coverage techniques.

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Prajwal UG
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0% found this document useful (0 votes)
9 views

20EVE23

This document outlines the structure and content of the Second Semester M.Tech. Degree Examination for System Verilog, including instructions for answering questions and guidelines to avoid malpractice. It consists of five modules, each containing two questions, from which students must choose one. The examination covers various topics such as verification processes, simulation phases, array methods, test bench design, randomization, threading concepts, and coverage techniques.

Uploaded by

Prajwal UG
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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USN 20EVE23

Second Semester M.Tech. Degree Examination, July/August 2022


System Verilog
Time: 3 hrs. Max. Marks: 100
Note: Answer any FIVE full questions, choosing ONE full question from each module.
2. Any revealing of identification, appeal to evaluator and /or equations written eg, 42+8 = 50, will be treated as malpractice.

Module-1
1 a. Explain the verification process of system verilog. (10 Marks)
b. Explain the different phases of simulation. (10 Marks)

OR
2 a. Explain different types of array methods used in unpacked arrays. (10 Marks)
b. Discuss the guidelines associated to choose a storage type. (10 Marks)
Important Note : 1. On completing your answers, compulsorily draw diagonal cross lines on the remaining blank pages.

Module-2
3 a. Describe C-style routine arguments, argument direction, advanced argument types and
default argument values with system verilog program example. (10 Marks)
b. Write a program for automatic storage. Explain the process. (10 Marks)

OR
4 a. Discuss the steps required to connect an RTL block to a test bench with suitable codes.
(10 Marks)
b. Describe test bench-design race condition. Write system verilog code for race condition
between test bench and design. (10 Marks)

Module-3
5 a. Explain the concept of randomization in system verilog with an example. (10 Marks)
b. Explain valid constraints and In-line constraints with an example. (10 Marks)

OR
6 a. Describe the solution probabilities in system verilog with example. (10 Marks)
b. Explain “Building a bathtub distribution” with system verilog code. (10 Marks)

Module-4
7 a. Write a short note on dynamic threads and automatic variables in threads. (10 Marks)
b. Explain the concept of fork….join, fork….join_none and fork….join_any statement. Explain
these statements with example. (10 Marks)

OR
8 a. Describe with a suitable code, how single thread and multiple threads are disabled. (10 Marks)
b. Write a mail box program with a generator and driver exchanging transactions. (10 Marks)

Module-5
9 a. What is coverage? Explain different types of coverage techniques. (10 Marks)
b. What is cross coverage? Write the code for basic cross coverage and give the coverage
summary report for basic cross coverage. (10 Marks)

OR
10 a. Describe various functional coverage strategies. (10 Marks)
b. Describe various coverage options with example. (10 Marks)
*****

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