GYAN GANGA INSTITUTE OF TECHNOLOGY & SCIENCES

Computer Science Engineering

Sr.
No Topics/Sub Topics Date Grade Signature Remark
.
To study and verify the Truth Tables
of AND, OR, NOT, NAND, NOR
1
EXOR and EXNOR logic gates for
positive logic

Design all basic logic gates using NOR

2 universal gate.

Design all basic logic gates using NAND

3
universal gate.

4 To verify the Demorgan’s theorems.

Construction and verification of half

5
adder and full adder.

Construction and verification of half

6 subtractor and full subtractor circuits

To design and implement a binary to

7
gray and gray to binary converter.

To design BCD to Excess 3 code

8
converter.
Design and verification of Multiplexer
9 circuit.

Design and verification of De-

10 Multiplexer circuit.
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Experiment No:-1

Aim: To study and verify the Truth Tables of AND, OR, NOT, NAND, NOR, EXOR and EXNOR
logic gates for positive logic.

Software: MULTISIM

Theory:

AND gate (IC 7408): A multi-input circuit in which the output is 1 only if all inputs are 1.The
symbolic representation of the AND gate is:

The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A dot
(.) is used to show the AND operation i.e. A.B .

OR gate (IC 7432): A multi-input circuit in which the output is 1 when any input is 1.
The symbolic representation of the OR gate is shown:

The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high.
A plus (+) is used to show the OR operation.
NOT gate( IC 7404): The output is 0 when the input is 1, and the output is 1 when the
input is 0. The symbolic representation of an inverter is :

The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It is
also known as an inverter. If the input variable is A, the inverted output is known as NOT A. This is
also shown as A', or A with a bar over the top, as shown at the outputs.
NAND gate (IC 7400): followed by INVERT. It is also known as universal gate.The symbolic
representation of the NAND gate is:
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This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of all
NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on
the output. The small circle represents inversion.

NOR gate (IC 7402 ): followed by inverter. It is also known as universal gate.The symbolic
representation is:

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all
NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on the
output. The small circle represents inversion.

EXOR gate (IC 7486): The output of the Exclusive –OR gate, is 0 when it’s two inputs are
the same and it’s output is 1 when its two inputs are different.It is also known as Anti-coincidence
gate.

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of its two
inputs are high. An encircled plus sign ( ) is used to show the EOR operation.

EXNOR gate (IC 747266)

The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a low output if
either, but not both, of its two inputs are high. The symbol is an EXOR gate with a small circle on the
output. The small circle represents inversion

Table 2 is a summary truth table of the input/output combinations for the NOT gate together with all
possible input/output combinations for the other gate functions. Also note that atruth table with 'n'
inputs has 2n rows. You can compare the outputs of different gates.

Table 2: Logic gates representation using the Truth table

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Results and Analysis:

NOT Gate: When logic 1 is applied to one of NOT gate of 7404 IC, then output becomes zero.
When input LED is ON (RED), the output LED become OFF (Green) vice versa.

OR Gate: The output of an OR gate is a 1 if one or the other or both of the inputs are 1, but a 0 if
both inputs are 0. When One or the other or Both of the input LEDS are ON (RED Light), then
output LED is ON(RED) otherwise Output LED is OFF(Green Light)

AND Gate: The output of an AND gate is only 1 if both its inputs are 1. For all other possible inputs
the output is 0.When both the LEDS are On, then output LED is ON (RED Light) otherwise Output
LED is OFF.

NOR Gate: The output of the NOR gate is a 1 if both inputs are 0 but a 0 if one or the other or both
the inputs are 1.
NAND Gate: The output of the NAND gate is a 0 if both inputs are 1 but a 1 if one or the other or
both the inputs are 0.

EXOR gate: The output of the XOR gate is a 1 if either but not both inputs are 1 and a 0 if the inputs
are both 0 or both 1.

Result: Truth Table of different logic gates are verified on MULTISIM

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VIVA QUESTIONS
Q.1 What is a logic gate?
Q.2 Draw symbol of OR, NOT, AND , NAND, NOR, EX-OR and EX-NOR gate?
Q.3 What are the Universal gates? Why they are called so?
Q.4 Implement all the logic gates using NOR gate.
Q.5 Implement all the logic gates using NAND gate.
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EXPERIMENT NO:-2

Aim: Design all basic logic gates using NOR universal gate.

Software: MULTISIM
Theory:
NAND gate is actually a combination of two logic gates: AND gate followed by NOT gate.
So its output is complement of the output of an AND gate.

This gate can have minimum two inputs, output is always one. By using only NAND gates,
we can realize all logic functions: AND, OR, NOT, X-OR, X-NOR, NOR. So this gate is also called
universal gate.

NAND gates as NOT gate

A NOT produces complement of the input. It can have only one input, tie the inputs of a NAND gate
together. Now it will work as a NOT gate. Its output is
Y = (A.A)’
=> Y = (A)’

---------------------------------------------------------------------------------------------------
NAND gates as AND gate

A NAND produces complement of AND gate. So, if the output of a NAND gate is inverted, overall
output will be that of an AND gate.
Y = ((A.B)’)’
=> Y = (A.B)

---------------------------------------------------------------------------------------------------
NAND gates as OR gate
From DeMorgan’s theorems: (A.B)’ = A’ + B’
=> (A’.B’)’ = A’’ + B’’ = A + B
So, give the inverted inputs to a NAND gate, obtain OR operation at output.

---------------------------------------------------------------------------------------------------
NAND gates as X-OR gate
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The output of a to input X-OR gate is shown by: Y = A’B + AB’. This can be achieved with the logic
diagram shown in the left side.

Gate No. Inputs Output

1 A, B (AB)’
2 A, (AB)’ (A (AB)’)’
3 (AB)’, B (B (AB)’)’
4 (A (AB)’)’, (B (AB)’)’ A’B + AB’
Now the ouput from gate no. 4 is the overall output of the configuration.
Y = ((A (AB)’)’ (B (AB)’)’)’
= (A(AB)’)’’ + (B(AB)’)’’
= (A(AB)’) + (B(AB)’)
= (A(A’ + B)’) + (B(A’ + B’))
= (AA’ + AB’) + (BA’ + BB’)
= ( 0 + AB’ + BA’ + 0 )
= AB’ + BA’
=> Y = AB’ + A’B
---------------------------------------------------------------------------------------------------
NAND gates as X-NOR gate

X-NOR gate is actually X-OR gate followed by NOT gate. So give the output of X-OR gate to a
NOT gate, overall ouput is that of an X-NOR gate.
Y = AB+ A’B’

---------------------------------------------------------------------------------------------------
NAND gates as NOR gate

A NOR gate is an OR gate followed by NOT gate. So connect the output of OR gate to a NOT gate,
overall output is that of a NOR gate.
Y = (A + B)’
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---------------------------------------------------------------------------------------------------

Result: Truth Table of different logic gates are verified using NAND gates on MULTSIM
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VIVA QUESTIONS

Q 1. What do you mean by universal gate?

Q 2. Give the name of universal gates?
Q 3. Implement XOR and XNOR gate using NAND gates
Q 4. What are the minimum number of NAND gates needed to implement Half adder.
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EXPERIMENT NO:-3

Aim: Realization of logic functions with the help of universal gates-NOR Gate.
Software: MULTISIM
Theory:
NOR gate is actually a combination of two logic gates: OR gate followed by NOT gate. So its
output is complement of the output of an OR gate.

This gate can have minimum two inputs, output is always one. By using only NOR gates, we
can realize all logic functions: AND, OR, NOT, X-OR, X-NOR, NAND. So this gate is also called
universal gate.

---------------------------------------------------------------------------------------------------
NOR gates as NOT gate

A NOT produces complement of the input. It can have only one input, tie the inputs of a NOR gate
together. Now it will work as a NOT gate. Its output is
Y = (A+A)’
=> Y = (A)’

---------------------------------------------------------------------------------------------------
NOR gates as OR gate

A NOR produces complement of OR gate. So, if the output of a NOR gate is inverted, overall output
will be that of an OR gate.
Y = ((A+B)’)’
=> Y = (A+B)

---------------------------------------------------------------------------------------------------
NOR gates as AND gate

From DeMorgan’s theorems: (A+B)’ = A’B’

=> (A’+B’)’ = A’’B’’ = AB
So, give the inverted inputs to a NOR gate, obtain AND operation at output.

---------------------------------------------------------------------------------------------------
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NOR gates as X-NOR gate

The output of a two input X-NOR gate is shown by: Y = AB + A’B’. This can be achieved with the
logic diagram shown in the left side.

Gate No. Inputs Output

1 A, B (A + B)’
2 A, (A + B)’ (A + (A+B)’)’
3 (A + B)’, B (B + (A+B)’)’
4 (A + (A + B)’)’, (B + (A+B)’)’ AB + A’B’

Now the ouput from gate no. 4is the overall output of the configuration.
Y = ((A + (A+B)’)’ (B +( A+B)’)’)’
= (A+(A+B)’)’’.(B+(A+B)’)’’
= (A+(A+B)’).(B+(A+B)’)
= (A+A’B’).(B+A’B’)
= (A + A’).(A + B’).(B+A’)(B+B’)
= 1.(A+B’).(B+A’).1
= (A+B’).(B+A’)
= A.(B + A’) +B’.(B+A’)
= AB + AA’ +B’B+B’A’
= AB + 0 + 0 + B’A’
= AB + B’A’
=> Y = AB + A’B’
---------------------------------------------------------------------------------------------------
NOR gates as X-OR gate

X-OR gate is actually X-NOR gate followed by NOT gate. So give the output of X-NOR gate to a
NOT gate, overall ouput is that of an X-OR gate.
Y = A’B+ AB’

---------------------------------------------------------------------------------------------------
NOR gates as NAND gate
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A NAND gate is an AND gate followed by NOT gate. So connect the output of AND gate to a NOT
gate, overall output is that of a NAND gate.
Y = (AB)’

---------------------------------------------------------------------------------------------------

Result: Truth Table of different logic gates are verified using NOR gates on MULTISIM

VIVA QUESTIONS
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Q.1 What is Bubbled OR and Bubbled AND ?

Q.2 What are the minimum number of NOR gates needed to implement Half adder.
Q.3 Implement XOR and XNOR gate using NOR gates.

EXPERIMENT NO:-4
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Aim: To verify the Demorgan’s theorems.

Software: MULTISIM

Theory:
De Morgan has suggested two theorems which are extremely useful in Boolean Algebra. The
two theorems are discussed below.

Theorem 1

 The left hand side (LHS) of this theorem represents a NAND gate with inputs A and B, whereas
the right hand side (RHS) of the theorem represents an OR gate with inverted inputs.

 This OR gate is called as Bubbled OR.

Table showing verification of the De Morgan's first theorem

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Theorem 2
 The LHS of this theorem represents a NOR gate with inputs A and B, whereas the RHS
represents an AND gate with inverted inputs.

 This AND gate is called as Bubbled AND.

Table showing verification of the De Morgan's second theorem −

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Result: -Thus, De Morgan’s theorem is verified on MULTISIM

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VIVA QUESTIONS

Q 1. What is De Morgans law?

Q 2. Prove the De Morgans law ?
Q 3. Define Distribution theorem
Q 4. With n variable what are the maximum possible min terms and maximum logical
expressions that can be created ?
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EXPERIMENT NO:-5
Aim: - Construction and verification of half adder and full adder circuits.

Software: MULTISIM

Theory:

Half Adder
It is combinational circuits that perform addition of two bits. This circuit has two inputs A and B
(augend and added) and two outputs- Sum (S) and Carry (C).The sum is a 1 when A and B are
different and carry is a 1when A and B are 1.The truth table for a half adder can be constructed using
the addition table for binary numbers
Truth Table
INPUTS OUTPUTS
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
From the truth table, we can write logical expression for S and C outputs as

S = AB + AB = A exor B
C = AB

From the equation it is clear that this 1-bit adder can be easily implemented with the help of EXOR
Gate for the output ‘SUM’ and an AND Gate for the carry. Take a look at the implementation below.

Fig:1 Logic Circuit Diagram of Implementation of Half Adder

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For complex addition, there may be cases when you have to add two 8-bit bytes together. This can be
done only with the help of full-adder logic.

Full Adder
This type of adder is a little more difficult to implement than a half-adder. The main difference
between a half-adder and a full-adder is that the full-adder has three inputs and two outputs. The first
two inputs are A and B and the third input is an input carry designated as CIN. When a full adder
logic is designed we will be able to string eight of them together to create a byte-wide adder and
cascade the carry bit from one adder to the next.
The output carry is designated as COUT and the normal output is designated as S. Take a look at the
truth-table.
INPUTS OUTPUTS
A B CIN COUT S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
From the above truth-table, the full adder logic can be implemented. We can see that the output S is
an EXOR between the input A and the half-adder SUM output with B and CIN inputs. We must also
note that the COUT will only be true if any of the two inputs out of the three are HIGH.

S=A EXOR B EXOR Cin

Cout = AB + ACin + BCin

Thus, we can implement a full adder circuit with the help of two half adder circuits. The first will
half adder will be used to add A and B to produce a partial Sum. The second half adder logic can be
used to add CIN to the Sum produced by the first half adder to get the final S output. If any of the
half adder logic produces a carry, there will be an output carry. Thus, COUT will be an OR function
of the half-adder Carry outputs.
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.
Fig 2 Full Adder using Half Adder.
Single Bit full Adder
With this type of symbol, we can add two bits together taking a carry from the next lower order of
magnitude, and sending a carry to the next higher order of magnitude. In a computer, for a multi-bit
operation, each bit must be represented by a full adder and must be added simultaneously. Thus, to
add two 8-bit numbers, you will need 8 full adders which can be formed by cascading two of the 4-
bit blocks. The addition of two 4-bit numbers is shown below.

Result:- Thus ,we have verified the truth table of Half and Full Adder on MULTISIM.
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VIVA QUESTIONS

Q 1. Draw circuit diagram of Half Adder using NAND gate?

Q 2. Draw circuit diagram of Full Adder using NOR gate?
Q 3. Draw Full Adder circuit by using Half Adder circuit and minimum no. of logic
gates?
Q 4. Write application of Half Adder?
Q 5. Write application of Full Adder?
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EXPERIMENT NO:-6

Aim: Construction and verification of half subtractor and full subtractor circuits.

Software: MULTISIM
.

Theory

The arithmetic operation, subtraction of two binary digits has four possible elementary operations,
namely,

0-0=0
0 - 1 = 1 with 1 borrow
1-0=1
1-1=0

In all operations, each subtrahend bit is subtracted from the minuend bit. In case of the second
operation the minuend bit is smaller than the subtrahend bit, hence 1 is borrowed.

Half Subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The
input variables designate the minuend and the subtrahend bit, whereas the output variables produce
the difference and borrow bits. Half subtractor

The half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It has
two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow).

INPUTS OUTPUTS
A B Diff Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Full Subtractor
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A combinational circuit which performs the subtraction of three input bits is called full
subtractor. The three input bits include two significant bits and a previous borrow bit. A full
subtractor circuit can be implemented with two half subtractors and one OR gate. As in the case of
the addition using logic gates, a full subtractor is made by combining two half-subtractors and an
additional OR-gate. A full subtractor has the borrow in capability (denoted as BIN in the diagram
below) and so allows cascading which results in the possibility of multi-bit subtraction. The circuit
diagram for a full subtractor is given below.
Inputs Outputs

Minuend Subtrahend Borrow in Difference Borrow out

X Y Bin D Bout

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Result:- Thus ,we have verified the truth table of Half and Full Subtractor
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VIVA QUESTIONS
Q 1. Draw logic diagram of half subtractor circuit using NAND gate?
Q 2. Draw logic diagram of full subtractor circuit using NAND gate?
Q 3. Draw full subtractor circuit by using half subtractor circuit and minimum no. of
logic gates?
Q 4. Write application of half subtractor?

Q 5. Write application of full subtractor

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EXPERIMENT NO:-7
Aim:
To design and implement a binary to gray and gray to binary converter.

Software: MULTISIM

Theory:
The reflected binary code, also known as Gray code after Frank Gray, is a binary numeral system
where two successive values differ in only one bit. The reflected binary code was originally designed
to prevent spurious output from electromechanical switches. Today Gray codes are widely used to
facilitate error correction in digital communications such as digital terrestrial television and some
cable TV systems.

Forming gray code:

The binary-reflected Gray code list for n bits can be generated recursively from the list for n-1 bits by
reflecting the list (i.e. listing the entries in reverse order), concatenating the original list with the
reversed list prefixing the entries in the original list with a binary 0, ang then prefixing the entries in
the reflected list with a binary 1. For example, generating the n = 3 list from the n = 2 list:

Truth Table for Binary to Gray code converter

Decimal Binary Input Gray Output

Decimal B2 B1 B0 G2 G1 G0
0 0 0 0 0 0 0
1 0 0 1 0 0 1
2 0 1 0 0 1 1
3 0 1 1 0 1 0
4 1 0 0 1 1 0
5 1 0 1 1 1 1
6 1 1 0 1 0 1
7 1 1 1 1 0 0

Logical Equations:

G2 = B2B1'B0' + B2B1'B1 + B2B1B0' + B2B1B0

G1 = B2'B1B0' + B2'B1B0 + B2B1'B0' + B2B1'B0
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G0 = B2'B1'B0 + B2'B1B0' + B2B1'B0 + B2B1B0'

Simplification:

G2 = B2B1'(B0' + B0) + B2B1(B0' + B0)

= B2B1' + B2B1
= B2(B1' +B1)
= B2
G1 = B2'B1B0' + B2'B1B0 + B2B1'B0' + B2B1'B0
= B2'B1(B0' + B0) + B2B1'(B0' + B0)
= B2'B1 + B2B1'
= B2 XOR B1
G0 = B2'B1'B0 + B2'B1B0' + B2B1'B0 + B2B1B0'
= B2'(B1'B0 + B1B0') + B2(B1'B0 + B1B0')
= (B1'B0 + B1B0') (B2' + B2)
= (B1'B0 + B1B0')
= B1 XOR B0

Logic Design:-

Gray to Binary Code Converter

Truth Table for Binary to Gray code converter

Decimal Gray Input Binary Output

Decimal G2 G1 G0 B2 B1 B0
0 0 0 0 0 0 0
1 0 0 1 0 0 1
2 0 1 0 0 1 1
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3 0 1 1 0 1 0
4 1 0 0 1 1 0
5 1 0 1 1 1 1
6 1 1 0 1 0 1
7 1 1 1 1 0 0

Logic Equations:

B2 = G2G1G0' + G2G1G0 + G2G1'G0 + G2G1'G0'

B1 = G2'G1G0 + G2'G1G0' + G2G1'G0 + G2G1'G0'
B0 = G2'G1'G0 + G2'G1G0' + G2G1G0 + G2G1'G0'

Simplification:

B2 = G2G1G0' + G2G1G0 + G2G1'G0 + G2G1'G0'

= G2G1(G0' + G0) + G2G1'(G0 + G0')
= G2G1 + G2G1'
= G2(G1+G1')
= G2
B1 = G2'G1(G0 + G0') + G2G1'(G0 + G0')
= G2'G1 + G2G1'
= G2 XOR G1
B0 = G2'G1'G0 + G2'G1G0' + G2G1G0 + G2G1'G0'
= G2'(G1'G0 + G1G0') + G2(G1G0 + G1'G0')
= G2'(G1 XOR G0) + G2(G1 XNOR G0) this is of the form A’B+AB’
= G2 XOR G1 XOR G0

Logic Diagram:
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Result:- the circuit is tested and verified with the truth table
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VIVA QUESTIONS
Q 1. What is a code converter?
Q 2. What is the gray code?
Q 3. What is Excess 3 code?
Q 4. Write name of any 5 code converters?
Q 5. Write the gray code and Binary code for the following representation 1110001
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EXPERIMENT NO:-8
Aim:
To design BCD to Excess 3 code converter.

Apparatus required:
Trainer kit or Bread Board, EX-OR Gate IC-7486, +5v Power Supply and Connecting leads or
Hookup

Theory:
Code converters, more specifically encoders and decoders, have been used by children and adults
alike to protect private information In digital system it is quite often required to convert coded
number to some another system. The term BCD refers to representing the ten decimal digits in binary
forms; which simply means to count in binary. The Excess-3 system simply adds 3 to each number
to make the codes look different. We will not venture to discuss the importance of the Excess-3 BCD
system because the discussion would serve too great a distraction from our present purpose and the
cost would outweigh the benefit. Suffice it to say that the Excess-3 BCD system has some properties
that made it useful in early computers

TRUTH TABLE:-

Using K map following equations are obtained

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Figure : BCD to Excess 3 code converter

Result:- Thus operation of BCD to Excess 3code Converter is verified.

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VIVA QUESTIONS
Q 1. What is the gray code?
Q 2. What is Excess 3 code?
Q 3. Write the gray code and Excess-3 code for the following representation 1110001
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EXPERIMENT NO:- 09

Aim:
Design and verification of Multiplexer circuit

Software: MULTISIM
Theory:
A multiplexer is a circuit which has a number of inputs but only 1 output or we can say multiplexer
is a circuit which transmits a large number of information signals(inputs) over a small number of
signal lines(output).Digital multiplexer is a combinational logic circuit and its function is to select
information in binary from one of many inputs and outputs the information along a single selected
output. These circuits are especially useful when a complex logic circuit is to be shared by a number
of input signals. The information to be outputted is selected by the address line.
In case of 4:1 multiplexer, it has four input lines having a signals as I0,I1,I2 AND I3.For selecting
one of the four input signals we require address which can be a two bit word. The address lines are
designated as S1 and S2. For each combination of selection signals (S1 and S0) one of the inputs is
outputted.

Truth Table:

SELECTION INPUT OUTPUT

S.No
S1 S2 Y
1. 0 0 I0
2. 0 1 I1
3. 1 0 I2
4. 1 1 I3

Circuit Diagram:

Result:- Thus ,we have designed and verified the operation of …………… multiplexer.
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VIVA QUESTIONS
Q 1. Explain the Multiplexer?
Q 2. Draw a circuit diagram of 4:1 MUX?
Q 3. What are the advantages and disadvantages of MUX?
Q 4. Write application of MUX?
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EXPERIMENT NO:-10

Aim:
Design and verification of De-multiplexer circuit

Apparatus required:
Trainer kit or Bread Board, NOT Gate IC-7404,AND Gate IC – 7408, and Connecting leads
or Hookup wires

Theory:
Demultiplexer as t he name indicates, it has only data input D with 4 outputs namely Y0,Y1Y2 Y3 It
has two data selector inputs namely S0,S1, at which control bits are applied.

The data bit is transmitted to the data bit Y0,Y1Y2 Y3 of the output lines. Which particular output
line will be chosen will depend on the value of S3,S2,S1,S0 the control input. Consider the case when S1
S0=00 now the upper AND gate is enable while all other AND gate are disabled. Hence it is not possible to
activate any output other than Y0. Thus Y0=D, if D is low Y0 will be low and if D is high, Y0 will be high.
Considering another case,S1,S0=01. We find that Y1 is activated because second AND gate is enable.
Similarly if S1 S0=11. The sixteenth AND gate will be enabled and Y15 Will be activated. Thus if D is high
then all values other then the correct value of activated Y output, will be low.

1X4 DEMULTIPLEXER

Logic Symbol:

Truth Table:
Data Select Outputs
Input Inputs

D S1 S0 Y3 Y2 Y1 Y0

D 0 0 0 0 0 D
D 0 1 0 0 D 0

D 1 0 0 D 0 0
D 1 1 D 0 0 0
 GYAN GANGA INSTITUTE OF TECHNOLOGY & SCIENCES

Computer Science Engineering

From the truth table ,it is clear that the data input is connected to output Y0 when S1=0 and
S0=0and the data input is connected to output Y1 when S1=0 and S0=1. Similarly the data
input is connected to output Y2 when S1=1 and S0=0 and when S1=1 and S0=1,
respectively.The expressions for outputs can be written as follows:

Here , the input data line is connected to all the AND gates. The two select lines S1S0 enable
only one gate at a time and the data that appears on the input line passes through the selected
gate to the associated output line.

Circuit Diagram:

Result:- Thus ,we have verified the operation of 1:4 Demultiplexer.

VIVA QUESTIONS
 GYAN GANGA INSTITUTE OF TECHNOLOGY & SCIENCES

Computer Science Engineering

Q 1. Explain about Demultiplexer?

Q 2. What is the difference between Multiplexer and Demultiplexer?

Q 3. Write application of Demultiplexer?

Q 4. Draw a logic diagram of 1:4 Demultiplexer?
Q 5. What are the applications of Demultiplexer?