International Journal of Computer Applications (0975 – 8887)

International Conference on Quality Up-gradation in Engineering Science and Technology, 2016

Design and Implementation of HDLC Transmitter using

VHDL

Ku. Rupal P. Bende A. P. Bagade S. R. Salwe

Student M.Tech (V.L.S.I) Assit.Professor, EXTC Dept. Asst. Professor, EXTC Dept.
B.D.C.E, Sewagram B.D.C.E, Sewagram B.D.C.E, Sewagram

ABSTRACT (1)Flag- Every frame starts and ends with flag sequence
Data communication over the network is efficiently carried 01111110. At any time, the transmission of frame can be
out with the help of protocol. Protocol is set of rules that aborted by sending the abort flag which is bit sequence of
define the format of frame, packet or message that are 01111111. Flags are continuously transmitted on the link
exchanged between devices. HDLC i.e. High level data link between frames to keep the link active.
control protocol is one of the protocol defined by International (2)Address- It is an 8 Bit or 16 bit field. It consists of the
Organization for Standardization (ISO) for data link layer of address of the receiver.
OSI reference model. HDLC is bit oriented protocol and (3)Control field- It control the communications process.
widely used in the network. It is used to send the data in This field contains the commands, responses and sequences
proper frame format. This paper discusses the design of numbers used to maintain the data flow accountability of the
HDLC transmitter coded in VHDL and its simulation in link, defines the functions of the frame and initiates the logic
Modelsim software. to control the movement of traffic between sending and
receiving stations.
Keywords- (4)Data or Information-It consists of data i.e. number of
HDLC, VHDL, FCS, FPGA, Verilog HDL, Xilinx. bits; the sender actually wants to transmit to the receiver.
(5)FCS-This field contains a 16-bit, or 32-bit cyclic
1. INTRODUCTION redundancy check bits. It is used for error detection. The
High level data link control (HDLC) protocol is developed by fields are transmitted from left to right, least significant bit
the ISO for data link layer of OSI reference model. It specifies first.
a packetization standard for serial links. It is mostly used as it HDLC uses a technique called bit-stuffing to differentiate
supports half duplex, full duplex communication lines, point bit sequence from a flag field. Every time the user wants to
and multi-point networks. The procedures outlined in HDLC send a bit sequence having more than 5 consecutive 1s, it
are designed to permit synchronous, code-transparent data inserts (stuffs) one redundant 0 after the fifth 1. This extra
transmission. In HDLC protocol, the control information is zero is inserted regardless of whether the sixth bit is another
always in the same position, which reduces the chance of one or not. Its presence tells the receiver that the current
errors. HDLC is bit orientated protocol as it sends information sequence is not a flag. Once the receiver has seen the stuffed
as a sequence of bits. It has also capability of error detection. 0, it is dropped from the data and the original stream is
It is suitable for Frame Relay switches, Video conferencing on restored. This paper aims to design and implement the HDLC
ISDN, SONET Termination, X.25 layer-2 protocol, Cable transmitter using VHDL. Here the transmitter is designed and
Modem, Private packet data networks & switches. design of receiver is proposed.
HDLC is a specification for the Data Link layer and lies
between the Physical layer and the Network layer. The 2. PROPOSED SYSTEM
Network layer is responsible for passing a packet of data From the study of related work [1], it has been seen that
through an internetwork, which can consist of many HDLC transceiver is designed using VHDL and it is
individual local area networks and even wide area links. The designed to operate at different rate of frequency. When the
Data Link layer, of which HDLC is a part of, is responsible transceiver is designed at maximum frequency, it can be used
for passing the data between two nodes on the same network. in many applications. Thus the research work aims to design
HDLC takes packets from the Network layer and attaches and Enhanced HDLC protocol using VHDL which includes the
address, control, and data integrity information to them. Once design of transmitter and receiver operating at maximum
formatted, the packets are sent "down the wire" using the frequency.
Physical layer. Thus in HDLC protocol, the data is arranged in
proper frame.
2.1 Proposed Model for transmitter
The proposed diagram of transmitter includes blocks of
1.1 HDLC frame structure address insertion, FCS generation, Zero insertion block. The
In this protocol, data is encapsulated in frame which block diagram is shown in figure 2.
includes address field, control field and FCS. The frame
format is shown below- 8 bit Address FCS Zero
register insertion generation insertion
Flag Address Control Data FCS Flag
Fig. 1 HDLC frame format.
Fig. 2 Proposed transmitter diagram

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 International Journal of Computer Applications (0975 – 8887)
International Conference on Quality Up-gradation in Engineering Science and Technology, 2016

As seen in figure 2, the data to be transmitted is given to 4. Zero insertion- When the bit sequence having more than 5
register and parallel to serial conversion is done .Then, consecutive 1s is detected, this block inserts (stuffs) one
address of receiver is added in the data. Address may be 8 bits redundant 0 after the fifth 1.
or 16 bits. After this, FCS bits are added in frame which is 5. Transmit control -HDLC Transmitter controller is
used for error detection. In order to avoid the confusion responsible for generating all the necessary internal control
between data and flag bits, zero bits are stuffed when five signals.
consecutive ones are detected in data. Then, flag bits 0111110 When the system is initialised, the data and address is
are added at beginning and end of the frame. In this way, loaded on rising edge of the clock signal and reset signal is
actual data is transmitted after arranging it in frame format. high. After the loading of whole data, the FCS bits are
included the frame data. FCS i.e Frame Check Sequence is
2.2 Proposed Model for receiver sequence of bits that are appended in data for error detection.
The design of receiver is proposed and shown in figure It is calculated by using 16/32 bit Cyclic Redundancy Check
(CRC) method. Extra zeros are inserted by the bit stuffer into
3. It can be implemented in future work. the bit stream to avoid transmission of the control flag
sequences within the frame data. This method of adding the
Flag Zero FCS Address zeros is called bit stuffing or transparency. This operation
detection detection detection checker involves inserting a zero after any sequence of 5 consecutive
ones in the transmitted data stream. Its presence tells the
receiver that the current sequence is not a flag. Once the
Fig. 3 Proposed receiver diagram receiver has seen the stuffed 0, it is dropped from the data and
the original stream is restored. In this way, the data is
When the frame data is received at receiver, the flag transmitted. Each module of the HDLC transmitter is
sequence is detected. After that, extra zeros are detected modelled, simulated and synthesized using VHDL. Finally all
which are added in bit insertion process. After detection of the blocks were integrated using port mapping technique in
extra zeros, they are removed from the bit sequence. Then VHDL in order to get the complete HDLC Transmitter. The
FCs bits are detected and receiver will calculate its own FCS design is successfully implemented in Modelsim SE 6.2c
bits. When FCS bit sequence are equal, it indicates that software.
transmission is error free. In this way, the error is detected.
Then the address is detected and verified. In this way, the 4. SIMULATION RESULT AND
whole data is retrieved. The proposed work aims to design
protocol at maximum the bit rate thereby making the design ANALYSIS
more flexible and efficient. The simulation result of implemented HDLC transmitter is
shown in figure 5. The design is coded in VHDL and
successfully implemented in ModelSim SE 6.2c software.
3. DESIGN AND IMPLEMENTATION This software from Mentor Graphics is the tool used for pre-
The proposed work includes the design of transmitter and
synthesis and post-synthesis simulation. VHDL language is
receiver for HDLC protocol. Out of the two main modules,
used as it can describe the behaviour and structure of
transmitter is designed and implemented. Following figure 4
electronic systems, but is particularly suited as a language to
shows the basic block diagram of HDLC transmitter. The
describe the structure and behaviour of digital electronic
main blocks of transmitter are-1. 8-bit register- Transmit
hardware designs, such as ASICs and FPGAs as well as
register module is responsible for capturing the data on the
conventional digital circuit.
rising edge of clock signal.
2. Address insertion-This block contains the address of the
destination, which can be either of 8 bits or 16 bits address.
This can be any arbitrary address, or the broadcast or “All-
Stations” Address, which are all one.
3. FCS generation-FCS is performed for detecting errors in
the received data by grouping the bytes of data into a block
and calculating a Cyclic Redundancy Check (CRC). The CRC
is calculated by performing a modulo 2 division of the data by
a generator polynomial and recording the remainder after
division and that remainder is FCS. In software, it is basically
performed using a shift register and X-OR gates. This method
is used for generating the FCS bits in design of the
Fig. 5- Simulation result of transmitter
transmitter.
As seen from figure 5, initially the input data 01111111
and address 11011111 is loaded on rising edge of clock signal
8-bit Address FCS and reset signal is high. When reset becomes zero, the whole
Zero
register insertion generation inserti data including input data, address, FCS bits and flag sequence
on starts transmitting. The out_data line indicates the flow of bits
that are transmitting. The busy line indicates whether the
transmission is completed or not. When busy line is 1, the
Transmit control transmission is going on and when it is 0, the transmission is
completed. At the transmitter side, the bits of frame that are
transmitted is 11111 0 11 11111 0 110 000001100001100.
Fig. 4 Block Diagram of transmitter.

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 International Journal of Computer Applications (0975 – 8887)
International Conference on Quality Up-gradation in Engineering Science and Technology, 2016

5. RESULT HDLC protocol transceiver using Verilog”, International

The design is coded in VHDL and successfully implemented Journal of Computer Science Issues, Vol. 9, Issue 2, No
in Modelsim SE 6.2c. The transmitter is found to be running 2, March 2012.
at 31.25Mbps. The final implementation of proposed HDLC [6] Armaan Hasan Nagpurwala,Sundaresan C, Chaitanya
transceiver will be done on Xilinx software by selecting the CVS, ”Implementation of HDLC Controller Design
suitable family of FPGA. using Verilog HDL “, International Conference on
Electrical, Electronics and System Engineering,2013.
6. CONCLUSION [7] Gaurav Chandil, Priyanka Mishra,”Design and
The transmitter for HDLC protocol has been successfully
Implementation of HDLC Controller by Using Crc-16”,
implemented in Modelsim SE 6.2c software. The coding for
International Journal of Modern Engineering Research
transmitter is done in VHDL language. Each module of the
(IJMER) Jan.-Feb. 2013.
transmitter is thoroughly simulated before and after synthesis.
For increasing the efficiency of transmitter, it can be [8] Jai Karan Singh1, Mukesh Tiwari, Mohd Firoz
implemented in Xilinx suit of software. Thus this paper Warsi,”Implementation of HDLC Protocol Based DDR-
describes the design and implementation of HDLC transmitter RAM Radar Processing System”, International Journal of
using VHDL. This project can be used in MODEMS where VLSI and Embedded Systems-IJVES -May - June 2013.
error detection part is performed by this HDLC controller and
also it can be used in other communication network. [9] Shubham Fadnavis,”An HVD Based Error Detection and
Correction Code in HDLC Protocol Used for
Communication”, International Journal of Advanced
7. FUTURE SCOPE Research in Computer and Communication Engineering,
As the proposed work involves the design of transmitter and Vol. 2, Issue 6, June 2013.
receiver, receiver can be designed in this paper. Both
transmitter and receiver can be designed to operate at higher [10] Shashank Rampelly, Santhosh Rao Seri, Gnaneshwara
Chary, Krishanm Raju, “Data Communication Using
frequency to achieve the aim of research work. By increasing
HDLC Protocol”, International Journal of Innovative
the bit rate, its efficiency will be increased and it can be used
in more application. Thus making the HDLC controller more Research in Electrical, Electronics, Instrumentation and
efficient, flexible and upgradable. control engineering ,Vol. 2, Issue 5, May 2014.
[11] Gao, Zhen-bin and Jian-Fei Liu,"FPGA implementation
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