Introduction to VHDL :

The United States Department of Defense as part of its Very High-Speed Itegrated Circuit (VHSIC)
program developed VHSIC HDL (VHDL) in 1982. It is based on programming language ada. The
development of VHDL was originated by IBM, Texas Instruments and Intermetrics in 1983. The
result contributed by many participating Electronics Design Automation (EDA) groups. It includes
many hardware specific constructs. This language has constructs that enable to express the concurrent
or sequential behaviour of digital system with or without timing, it also allows interconnecting
component. Very High-Speed Integrated Circuit (VHSIC) HDL (VHDL) is a programming language
for describing the behavior of digital systems. This language has constructs that enable to express the
concurrent or sequential behavior of digital system with or without timing, it also allows
interconnecting component. VHDL is one of a few HDLs in widespread use today. VHDL is
recognized as a standard HDL by the Institute of Electrical and Electronics Engineers (IEEE Standard
1076, ratified in 1987). VHDL has many features appropriate for describing the behavior of electronic
components ranging from simple logic gates to complete microprocessors and custom chips. VHDL
allows the behavior of complex electronic circuits to be captured into a design system for automatic
circuit synthesis or for system simulation. One of the most important applications of VHDL is to
capture the performance specification for a circuit, in the form of what is commonly referred to as a
test bench.

Features of VHDL :
(1) World wide Popularity.
(2) VHDL supports different types of modeling.
(3) Also VHDL can be used at different complexity levels-from single transistor up to complete
systems and everything remains in the same simulation environment.
(4) The language supports flexible design methodologies top down, bottom up or mixed.
(5) The language can be used as communication medium between different CAD and CAE tools.
(6) The language supports hierarchy that is digital system can be modeled as a set of interconnected
components or subcomponents.
(7) It supports both synchronous and asynchronous timing models.
(8) Test benches can be written using the same language to test other VHDL models

VHDL Program Format :

The various sections used in VHDL program are shown in figure below. These sections are,
1) LIBRARY declaration which contains the list of libraries used in the program.
e.g. : ieee, std, work, etc.
2) ENTITY which declares the I/O pins of the circuit and
3) ARCHITECTURE which describes the detailed logical design aspects of the IC.
LIBRARY Declarations :
LIBRARY is a set of functions which are used in the program. The structure of the library is shown in
figure. The LIBRARY code is normally written in the form of FUNCTIONS, PROCEDURES, or
COMPONENTS and kept in the form of PACKAGES. To declare the LIBRARY two lines are
required in the program, one is the name of the library and second is the USE clause, as shown in the
syntax.
LIBRARY library_name;

USE

Library_name_package_name.package_parts;

The packages required in the program are,

1) ieee.std_logic_1164 (from the ieee library),
2) standard (from the std library) and
3) work (work library).
The declarations of the libraries are as follows,
LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY std;

USE std.standard.all;

LIBRARY work;

USE work.all;

Since the libraries std and work are by default libraries, these libraries are need not to be declared. In
the program the ieee library must be declared along with the STD_LOGIC (or STD_ULOGIC) data
type used in the design.
Structure of VHDL Program :
Every VHDL program consists of at least one entity/architecture pair. In a large design, you will
typically write many entity/architecture pairs and connect them together to form a complete circuit.
An entity declaration describes the circuit as it appears from the “outside” - from the perspective of its
input and output interfaces. The second part of a minimal VHDL design description is the architecture
declaration.
ENTITY :
ENTITY is the list with specifications of all input and output pins of the circuit. Its syntax is shown
below :
ENTITY name IS

PORT (

port_name : signal_mode signal_type;

port_name : signal_mode signal_type;

...

);

END name;

The mode of the signal used may be IN, OUT, INOUT or BUFFER. IN and OUT are unidirectional
pins, while INOUT is bidirectional. BUFFER, is used when the output signal is used internally in the
design. The type of the signal may be BIT, STD_LOGIC, INTEGER, etc. The name of the entity
should be not use the VHDL reserved words.
ARCHITECTURE :
The ARCHITECTURE is the description of how the circuit of design works. Its syntax is as follows,
ARCHITECTURE architecture_name OF entity_name IS

[declarations]

BEGIN

(code)

END architecture_name;

As shown in above syntax, architecture has two parts, 1) A declarative part where signals and
constants are declared and 2) The code part. The name of architecture is any name except VHDL
reserved words.
The architecture indicates that the circuit is performing NAND operation between the two input
signals a and b and assigning the result to the output pin (x).
Figure below shows the detailed description of entity and architecture declarations in the VHDL
program.

Modeling styles in VHDL coding are used to specify the architectural body of the design. The
modeling styles can be selected depending upon the complexity of the digital design.
The modeling styles are categorized as :
1. Data flow modeling (Concurrent code)
 2. Behavioral modeling (Sequential code)
3. Structural modeling
4. Mixed modeling.

Data Types :
A set of values and a set of operations is called as Data Types. There are nine classes of types in
VHDL .
(1) Scalar types (values of these types have no elements),
(2) Composite types (values of these types consist of element values),
(3) Access types (provide access to objects of a given type)
(4) Files (provide access to objects that contain a sequence of values of a given type)
(5) Array Types
(6) Record Types
(7) Predefined VHDL Data Types
(8) Unsupported Data Types
(9) Subtypes
(10) Physical Type
The Syntax of data type is :
type type_name_specify is type_define;

type type_name_specify;

1) Scalar Type :
Scalar type is a type whose values have no elements. The scalar type values cannot contain any
composite elements. The Syntax of Scalar Type is :
scalar_type ::= enumeration_type

integer_type

floating_type

physical_type

2) Composite Type :
An object of a composite type is a collection of other objects, called elements. The Syntax of
Composite type is,
composite_type ::= array_type | record_type

3) Access Types :
Access type allows to manipulate data, which are created dynamically during simulation.The syntax
of access type is :
access_type::=access

subtype_indication

incomplete_type_declation::=type

identifier

4) Array Types :
The array is a composite object, which elements are of the same subtype. The Syntax of Array Type is,
type type_name_define is array (range) of element_type_specify

type type_name_define is array (type range <>) of element_type_specify

5) Physical Type:
A physical type allows defining measurement units for some physical quantity, like length, time,
pressure, capacity, etc. The Syntax of Physical Type is :
type type_name_specify is range left_bound_specify downto right_bound_specify

units primary_unit_name_specify

secondary_unit_name_specify = number primary_unit_name_specify

secondary_unit_name_specify = number primary_unit_name_specify

...

end units type_name_specify

type type_name_specify is range left_bound_specify downto right_bound_specify

units primary_unit_name_specify

secondary_unit_name_specify = number primary_unit_name_specify

secondary_unit_name_specify = number primary_unit_name_specify

...

end units type_name_specify

6) Subtypes :
Subtype declarations are used to define subsets of a type. The Syntax of Subtype is :
subtype_declaration_specify ::= subtype identifier is subtype_indication_specify ;

subtype_indication_specify ::= [ resolution_function_name ] type_mark [ constraint ]

type_mark_specify ::= type_name_specify | subtype_name_specify

constraint_specify ::= range_constraint_specify | index_constraint_specify

7) Predefined VHDL Data Types :
VHDL describes specific packages which contain standard set of types and operations.

1 Bit :
The Bit type is from the Standard package has two allowable values: '0' and '1'.

Bit_Vector :
The Bit_Vector type is from the Standard package and has Bit type elements.

Boolean :
The Boolean type is from the Standard package which has false and true values.

Identifiers :
Identifiers are probably the most common operand. An identifier in VHDL is a user-defined name for
any of this : Constant, Variable, Function, Signal, Entity, port, Subprogram, Parameter, And
Instantance
There are two types of identifiers : basic identifiers and extended identifiers.

Data Objects :
A data objects hold a value of specified type, which is created by means of an object declaration. In
the following example signal is one of the type of data object. e.g. signal sl: std- logic
Type of data objects :
1) Constant :
A constant is an object whose value may never be changed during the simulation process. The
constant declaration contains one or more identifiers. The Syntax of constant is,
constant constant_name : type := value;

2) File :
A sequence of value called file. The value can be read or write to file using read procedures and write
procedures respectively. The Syntax of file is :
file identifier : subtype_indication [ file_open_information ];

3) Variables :
A variable is an object with single current value. A signal value of given type having different values
assigned to different times called as variable. The Syntax of variable is,:
variable variable_name : type;

variable variable_name : type := initial_value;

4) Signal :
Signal is an object with a past history of values. The term signal refers to objects declared by signal
declarations and port declarations. The Syntax of signal is :
signal signal_name : type;
signal signal_name : type := initial_value;
 ➢ Data Flow Modeling :
The view of data as flowing through a design, from input to output. A dataflow model specifies the
functionality of the entity without explicitly specifying its structure. This functionality shows the flow
of information through the entity, which is expressed primarily using concurrent signal assignment
statements and block statements. VHDL code is inherently concurrent (parallel). Concurrent code is
also called dataflow code.

Example 1 : Two input NAND gate

architecture DATAFLOW of NAND2 is
begin

X <= a nand b;

end DATAFLOW;

In above NAND gate code is described using single concurrent signal assignment statement. A signal
assignment is identified by the symbol " <=".
Example 2 : Decoder
architecture Dataflow of Decoder is
begin

led(3) <= bcd(0) and bcd(1);

led(2) <= bcd(0) and (not bcd(1));

led(1) <= (not bcd(0)) and bcd(1);

led(0) <= (not bcd(0)) and (not bcd(1));

end Dataflow;

All the four statements here are executed concurrently and each of them is activated individually
when any of its input signals changes its value.
 ➢ Behavioral Modeling:
In behavioral modeling sequential execution statements are used. The statements used in this
modeling style allowed only inside PROCESSES, FUNCTIONS, or PROCEDURES. Describing a
circuit at the behavioral level is very similar to writing a computer program. You have all the standard
high-level programming language constructs (like C, BASIC), such as the FOR LOOP, WHILE
LOOP, IF THEN ELSE, CASE, and variable assignments. The statements are enclosed in a
PROCESS block, and are executed sequentially. When creating a behavioral description of a circuit,
you will describe your circuit in terms of its operation over time. Let us take the example of simple
NAND2 logic gate as shown in following Fig.4.9.1. In behavioral modeling we must require the
behavior of design or simply truth table of design. No need of logical circuit diagram.

Example 1 : Example of Behavioral style architecture for Entity NAND2.

architecture behave of NAND2 is
begin

process(A, B)

begin

if (A = '1') and (B = '1') then Z <= '0';

else Z <= '1';

end if;

end process;
 end behave;

In above example, NAND gate has output z is low if both inputs A and B are high. Otherwise output
is high for any other combination of inputs. This behavior of NAND gate is described using if
statement. The architecture contains only one statement, called a process statement. It starts at the line
beginning with the keyword process and ends with the line that contains end process. All the
statements between these two lines are considered part of the process statement
Example 2: 2:4 Decoder
architecture behavioral of Decoder is

signal S: bit_vector (3 downto 0);

begin

P1: process (bcd, S)

begin

case bcd is

when "00" => S <= "0001"

when "01" => S <= "0010"

when "10" => S <= "0100"

when "11" => S <= "1000"

end case;

led <= S;

end process P1;

end behavioral;

Example 3 : Half-adder

Architecture behave of Half-adder is

begin

process(A,B)

begin

if A = 0 and B = 0 then sum <= '0'; carry <= '0';

elseif A = 0 and B = 1 then sum <='1'; carry <= '0';

elseif A = 1 and B = 0 then sum <= '1'; carry <= '0';

else sum <== '0'; carry <= '1'

endif

end process;

end behave;
 ➢ Structural Modelling :
In structural modeling the components of the system are listed and the interconnections between them
are specified. In this modeling the designs are described in the form of block diagrams. Components
represented by blocks are interconnected by lines representing signals.
VHDL Structural modeling code should have 1) ability to define the list of components, 2) definition
of a set of signals, 3) ability to uniquely label the component and 3) ability to specify signals to ports.
COMPONENT :
COMPONENT linked with, LIBRARY declarations, ENTITY, ARCHITECTURE. However, by
declaring COMPONENT, it can be used within another system. The syntaxes are as follows,
COMPONENT declaration :
COMPONENT component_name IS

PORT (

port_name : signal_mode signal_type;

port_name : signal_mode signal_type;

...);

END COMPONENT;

COMPONENT instantiation :

label: component_name PORT MAP (port_list);

From the syntax it can be seen that, the declaration is similar to that of an ENTITY. To instantiate the
component a label is mandatory, followed by the name of component and PORT MAP declaration.
There are two ways to declare a COMPONENT. 1) designed and placed in the destination LIBRARY
2) declared in the main code or declared using a PACKAGE. Figure below show the component
declarations.
 ➢ The Mixed Style Modeling :
The mixed style modeling is any combination of behavior, data flow, and structural modeling in a
single architecture body. In mixed style of modeling we could use component instantiation statements,
concurrent signal assignment statements, sequential signal assignment statement. The most popular
method to modeling large system is mixed style containing structural plus behavioral. For example if
you want to write code for any microprocessor. First make the code for each block (register, ALU,
control etc.) in behavioral format and then join them by structural method. Let take the one example
shown in figure below. First divide it in parts as shown in the figure. We divide them in two part one
is structural and other is dataflow.

library ieee;

use ieee.std_logic_1164.all;

entity example is

port (A,B,C,D,E : in std_logic;

Y : out std_logic);

end example;

architecture mixed of example is

component nand2 is -- component declaration

port (p1,p2 : in std_logic;

0 : out std_logic);

end component;

component xor2 is

port (x1,x2 : in std_logic;

0 : out std_logic);

end component;

signal s:std_logic_vector (0 to 3); -- signal s assigns internal connections

begin

N1 : nand2 port map (A,B,s0); -- component instantiation

N2 : nand2 port map (s0,s1,s3);

X1 : xor2 port map (C,D,s1);

S2<=D and E; -- data flow statement

Y<= s3 or s2;

end mixed;