Computer Organization

UNIT III
Computer Processing Unit Organization

Introduction to CPU

The operation or task that must perform by CPU is:

• Fetch Instruction: The CPU reads an instruction from memory.
• Interpret Instruction: The instruction is decoded to determine what action is
required.
• Fetch Data: The execution of an instruction may require reading data from memory
or I/O module.
• Process data: The execution of an instruction may require performing some arithmetic
or logical operation on data.
• Write data: The result of an execution may require writing data to memory or an I/O
module.

To do these tasks, it should be clear that the CPU needs to store some data temporarily.
It must remember the location of the last instruction so that it can know where to get the
next instruction. It needs to store instructions and data temporarily while an instruction
is being executed. In other words, the CPU needs a small internal memory. These
storage locations are generally referred as registers.

The major components of the CPU are an arithmetic and logic unit (ALU) and a control
unit (CU). The ALU does the actual computation or processing of data. The CU controls
the movement of data and instruction into and out of the CPU and controls the operation
of the ALU.

The CPU is connected to the rest of the system through system bus. Through system
bus, data or information gets transferred between the CPU and the other component of
the system. The system bus may have three components:

Data Bus: Data bus is used to transfer the data between main memory and CPU.
Address Bus: Address bus is used to access a particular memory location by putting the
address of the memory location.
Control Bus: Control bus is used to provide the different control signal generated by
CPU to different part of the system.
As for example, memory read is a signal generated by CPU to indicate that a memory
read operation has to be performed. Through control bus this signal is transferred to
memory module to indicate the required operation.

Figure 1: CPU with the system bus.

There are three basic components of CPU: register bank, ALU and Control Unit. There

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are several data movements between these units and for that an internal CPU bus is
used. Internal CPU bus is needed to transfer data between the various registers and the
ALU.

Figure 2 : Internal Structure of CPU

Stack Organization:

A useful feature that is included in the CPU of most computers is a stack or last in, first
out (LIFO) list. A stack is a storage device that stores information in such a manner that
the item stored last is the first item retrieved. The operation of a stack can be compared
to a stack of trays. The last tray placed on top of the stack is the first to be taken off.

The stack in digital computers is essentially a memory unit with an address register that
can only( after an initial value is loaded in to it).The register that hold the address for the
stack is called a stack pointer (SP) because its value always points at the top item in
stack. Contrary to a stack of trays where the tray it self may be taken out or inserted, the
physical registers of a stack are always available for reading or writing.

The two operation of stack are the insertion and deletion of items. The operation of
insertion is called PUSH because it can be thought of as the result of pushing a new item
on top. The operation of deletion is called POP because it can be thought of as the result
of removing one item so that the stack pops up. However, nothing is pushed or popped
in a computer stack. These operations are simulated by incrementing or decrementing
the stack pointer register.

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Register stack:

A stack can be placed in a portion of a large memory or it can be organized as a

collection of a finite number of memory words or registers. Figure X shows the
organization of a 64-word register stack. The stack pointer register SP contains a binary
number whose value is equal to the address of the word that is currently on top of the
stack. Three items are placed in the stack: A, B, and C in the order. item C is on the top
of the stack so that the content of sp is now 3. To remove the top item, the stack is
popped by reading the memory word at address 3 and decrementing the content of SP.
Item B is now on top of the stack since SP holds address 2. To insert a new item, the
stack is pushed by incrementing SP and writing a word in the next higher location in the
stack. Note that item C has read out but not physically removed. This does not matter
because when the stack is pushed, a new item is written in its place.

In a 64-word stack, the stack pointer contains 6 bits because 26 =64. since SP has only
six bits, it cannot exceed a number grater than 63(111111 in binary). When 63 is
incremented by 1, the result is 0 since 111111 + 1 =1000000 in binary, but SP can
accommodate only the six least significant bits. Similarly, when 000000 is decremented
by 1, the result is 111111. The one bit register Full is set to 1 when the stack is full, and
the one-bit register EMTY is set to 1 when the stack is empty of items. DR is the data
register that holds the binary data to be written in to or read out of the stack.

Figure 3: Block Diagram Of A 64-Word Stack

Initially, SP is cleared to 0, Emty is set to 1, and Full is cleared to 0, so that SP points to

the word at address o and the stack is marked empty and not full. if the stack is not full ,
a new item is inserted with a push operation. the push operation is implemented with the
following sequence of micro-operation.

SP ←SP + 1 (Increment stack pointer)

M(SP) ← DR (Write item on top of the
stack) if (sp=0) then (Full ← 1) (Check if stack is full)
Emty ← 0 ( Marked the stack not empty)

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The stac pointer is incremented so that it points to the address of the next-higher word.
A memory write operation inserts the word from DR into the top of the stack. Note that
SP holds the address of the top of the stack and that M(SP) denotes the memory word
specified by the address presently available in SP, the first item stored in the stack is at
address 1. The last item is stored at address 0, if SP reaches 0, the stack is full of item,
so FULLL is set to 1. This condition is reached if the top item prior to the last push was
in location 63 and after increment SP, the last item stored in location 0. Once an item is
stored in location 0, there are no more empty register in the stack. If an item is written in
the stack, Obviously the stack can not be empty, so EMTY is cleared to 0.

DR← M[SP] Read item from the top of stack

SP ← SP-1 Decrement stack
Pointer if( SP=0) then (Emty ← 1) Check if stack is
empty FULL ← 0 Mark the stack not full

The top item is read from the stack into DR. The stack pointer is then decremented. if its
value reaches zero, the stack is empty, so Emty is set to 1. This condition is reached if
the item read was in location 1. once this item is read out , SP is decremented and
reaches the value 0, which is the initial value of SP. Note that if a pop operation reads
the item from location 0 and then SP is decremented, SP changes to 111111, which is
equal to decimal 63. In this configuration, the word in address 0 receives the last item in
the stack. Note also that an erroneous operation will result if the stack is pushed when
FULL=1 or popped when EMTY =1.

Memory Stack :

A stack can exist as a stand-alone unit as in figure 4 or can be implemented in a

random access memory attached to CPU. The implementation of a stack in the CPU is
done by assigning a portion of memory to a stack operation and using a processor
register as a stack pointer. Figure shows a portion of computer memory partitioned in to
three segment program, data and stack. The program counter PC points at the address of
the next instruction in the program. The address register AR points at an array of data.
The stack pointer SP points at the top of the stack. The three register are connected to a
common address bus, and either one can provide an address for memory. PC is used
during the fetch phase to read an instruction. AR is used during the execute phase to
read an operand. SP is used to push or POP items into or from the stack.

As show in figure :4 the initial value of SP is 4001 and the stack grows with
decreasing addresses. Thus the first item stored in the stack is at address 4000, the
second item is stored at address 3999, and the last address hat can be used for the stack
is 3000. No previous are available for stack limit checks. We assume that the items in
the stack communicate with a data register DR. A new item is inserted with the push
operation as follows.

SP← SP-1
M[SP] ← DR
The stack pointer is decremented so that it points at the address of the next word. A
Memory write operation insertion the word from DR into the top of the stack. A new
item is deleted with a pop operation as follows.
DR← M[SP]
SP←SP + 1
The top item is read from the stack in to DR. The stack pointer is then incremented to
point at the next item in the stack.
Most computer do not provide hardware to check for stack overflow (FULL) or
underflow (Empty). The stack limit can be checked by using two prossor register :

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one to hold upper limit and other hold the lower limit. after the pop or push operation SP
is compared with lower or upper limit register.

Figure 4: computer memory with program, data and stack segments

INSTRUCTION FORMATS:

We know that a machine instruction has an opcode and zero or more operands.
Encoding an instruction set can be done in a variety of ways. Architectures are
differentiated from one another by the number of bits allowed per instruction (16, 32,
and 64 are the most common), by the number of operands allowed per instruction, and
by the types of instructions and data each can process. More specifically, instruction sets
are differentiated by the following features:
1. Operand storage in the CPU (data can be stored in a stack structure or in registers)
2. Number of explicit operands per instruction (zero, one, two, and three being the most
common)
3. Operand location (instructions can be classified as register-to-register, register-to-
memory or memory-to-memory, which simply refer to the combinations of operands
allowed per instruction)
4. Operations (including not only types of operations but also which instructions can
access memory and which cannot)
5. Type and size of operands (operands can be addresses, numbers, or even characters)
Number of Addresses:

One of the characteristics of the ISA(Industrial Standard Architecture) that shapes the
architecture is the number of addresses used in an instruction. Most operations can be
divided into binary or unary operations. Binary operations such as addition and

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multiplication require two input operands whereas the unary operations such as the
logical NOT need only a single operand. Most operations produce a single result. There
are exceptions, however. For example, the division operation produces two outputs: a
quotient and a remainder. Since most operations are binary, we need a total of three
addresses: two addresses to specify the two input operands and one to specify where the
result should go.

Three-Address Machines:
In three-address machines, instructions carry all three addresses explicitly. The RISC
processors use three addresses. Table X1 gives some sample instructions of a three-
address machine.

In these machines, the C statement

A=B+C*D-E+F+A
is converted to the following code:
mult T,C,D ; T = C*D
add T,T,B ; T = B + C*D
sub T,T,E ; T = B + C*D - E
add T,T,F ; T = B + C*D - E + F
add A,T,A ; A = B + C*D - E + F + A

Table :T1 Sample three-address machine instructions

Instruction Semantics
add dest,src1,src2 Adds the two values at src1 and src2 and
stores the result in dest
M(dest) = [src1] + [src2]
sub dest,src1,src2 Subtracts the second
source operand at src2 from the first at
src1 and stores the result in dest
M(dest) = [src1] - [src2]
mult dest,src1,src2 Multiplies the two values at src1
and src2 and stores the result in dest
M(dest) = [src1] * [src2]

We use the notation that each variable represents a memory address that stores the value
associated with that variable. This translation from symbol name to the memory address
is done by using a symbol table.

As you can see from this code, there is one instruction for each arithmetic operation.
Also notice that all instructions, barring the first one, use an address twice. In the middle
three instructions, it is the temporary T and in the last one, it is A. This is the motivation
for using two addresses, as we show next.

Two-Address Machines :

In two-address machines, one address doubles as a source and destination. Usually, we

use dest to indicate that the address is used for destination. But you should note that this
address also supplies one of the source operands. The Pentium is an example processor
that uses two addresses. Sample instructions of a two-address machine

On these machines, the C statement

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A=B+C*D-E+F+A
is converted to the following code:
load T,C ; T = C
mult T,D ; T = C*D
add T,B ; T = B + C*D
sub T,E ; T = B + C*D - E
add T,F ; T = B + C*D - E +
F
add A,T ; A = B + C*D - E + F + A
Table :T2 Sample Two-address machine instructions:

Instruction Semantics

load dest,src Copies the value at src to

dest M(dest) = [src]

add dest,src Adds the two values at src and dest and
stores the result in dest
M(dest) = [dest] + [src]
sub dest,src Subtracts the second source operand at
src from the first at dest and
stores the result in dest
M(dest) = [dest] - [src]
mult dest,src Multiplies the two values at src and dest and
stores the result in dest
M(dest) = [dest] * [src]

Since we use only two addresses, we use a load instruction to first copy the C value into
a temporary represented by T. If you look at these six instructions, you will notice that
the operand T is common. If we make this our default, then we don‟t need even two
addresses: we can get away with just one address.

One-Address Machines :

In the early machines, when memory was expensive and slow, a special set of registers
was used to provide an input operand as well as to receive the result from the ALU.
Because of this, these registers are called the accumulators. In most machines, there is
just a single accumulator register. This kind of design, called accumulator machines,
makes sense if memory is expensive.

In accumulator machines, most operations are performed on the contents of the

accumulator and the operand supplied by the instruction. Thus, instructions for these
machines need to specify only the address of a single operand. There is no need to store
the result in memory: this reduces the need for larger memory as well as speeds up the
computation by reducing the number of memory accesses. A few sample accumulator
machine instructions are shown in Table X3.
In these machines, the C statement
A=B+C*D-E+F+A
is converted to the following code:

load C ; load C into the accumulator

mult D ; accumulator = C*D
add B ; accumulator = C*D+B
sub E ; accumulator = C*D+B-E
add F ; accumulator = C*D+B-E+F

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add A ; accumulator = C*D+B-E+F+A
store A ; store the accumulator contents in A

Table :T3 Sample ONE-address machine instructions

Instruction Semantics
load addr Copies the value at address addr into the
accumulator accumulator = [addr]
store addr Stores the value in the accumulator at the
memory address addr
M(addr) = accumulator
add addr Adds the contents of the accumulator and
value at address addr
accumulator = accumulator + [addr]
sub addr Subtracts the value at memory address
addr from the contents of the accumulator
accumulator = accumulator - [addr]
mult addr Multiplies the contents of the
accumulator and value at address
addr
accumulator = accumulator * [addr]

Zero-Address Machines :
In zero-address machines, locations of both operands are assumed to be at
a default location. These machines use the stack as the source of the input operands
and the result goes back into the stack. Stack is a LIFO (last-in-first-out) data
structure that all processors support, whether or not they are zero-address
machines. As the name implies, the last item placed on the stack is the first item to
be taken out of the stack. A good analogy is the stack of trays you find in a
cafeteria.
All operations on this type of machine assume that the required input
operands are the top two values on the stack. The result of the operation is placed
on top of the stack. Table X4 gives some sample instructions for the stack
machines.

Table :T4 Sample Zero-address machine instructions

Instruction Semantics
push addr Places the value at address addr on top of the stack
push([addr])
pop addr Stores the top value on the stack at memory address addr
M(addr) = pop
add Adds the top two values on the stack and pushes the result
onto the stack
push(pop + pop)
sub Subtracts the second top value from the top value of the stack
and pushes the result onto the stack
push(pop – pop)
mult Multiplies the top two values in the stack and pushes the result
onto the stack
push(pop * pop)

Notice that the first two instructions are not zero-address instructions. These

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two are special instructions that use a single address and are used to move data
between memory and stack.
All other instructions use the zero-address format. Let‟s see how the stack
machine translates the arithmetic expression we have seen in the previous
subsections. In these machines, the C statement
A=B+C*D-E+F+A
is converted to the following code:
push E ; <E>
push C ; <C, E>
push D ; <D, C, E>
mult ; <C*D, E>
push B ; <B, C*D, E>
add ; <B+C*D, E>
sub ; <B+C*D-E>
push F ; <F, B+D*C-E>
add ; <F+B+D*C-E>
push A ; <A, F+B+D*C-E>
add ; <A+F+B+D*C-E>
pop A ;<>

On the right, we show the state of the stack after executing each instruction.
The top element of the stack is shown on the left. Notice that we pushed E early
because we need to subtract it from (B+C*D).
Stack machines are implemented by making the top portion of the stack
internal to the processor. This is referred to as the stack depth. The rest of the stack
is placed in memory. Thus, to access the top values that are within the stack depth,
we do not have to access the memory. Obviously, we get better performance by
increasing the stack depth.

INSTRUCTION TYPES

Most computer instructions operate on data; however, there are some that do
not. Computer manufacturers regularly group instructions into the following
categories:
• Data movement
• Arithmetic
• Boolean
• Bit manipulation (shift and rotate)
• I/O
• Transfer of control
• Special purpose
Data movement instructions are the most frequently used instructions. Data
is moved from memory into registers, from registers to registers, and from registers
to memory, and many machines provide different instructions depending on the
source and destination. For example, there may be a MOVER instruction that
always requires two register operands, whereas a MOVE instruction allows one
register and one memory operand.

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Some architectures, such as RISC, limit the instructions that can move data
to and from memory in an attempt to speed up execution. Many machines have
ariations of load, store, and move instructions to handle data of different sizes. For
example, there may be a LOADB instruction for dealing with bytes and a LOADW
instruction for handling words.
Arithmetic operations include those instructions that use integers and
floating point numbers. Many instruction sets provide different arithmetic
instructions for various data sizes. As with the data movement instructions, there are
sometimes different instructions for providing various combinations of register and
memory accesses in different addressing modes.
Boolean logic instructions perform Boolean operations, much in the same
way that arithmetic operations work. There are typically instructions for performing
AND, NOT, and often OR and XOR operations.
Bit manipulation instructions are used for setting and resetting individual bits
(or sometimes groups of bits) within a given data word. These include both arithmetic
and logical shift instructions and rotate instructions, both to the left and to the right.
Logical shift instructions simply shift bits to either the left or the right by a specified
amount, shifting in zeros from the opposite end. Arithmetic shift instructions, commonly
used to multiply or divide by 2, do not shift the leftmost bit, because this represents the
sign of the number. On a right arithmetic shift, the sign bit is replicated into the bit
position to its right. On a left arithmetic shift, values are shifted left, zeros are shifted in,
but the sign bit is never moved. Rotate instructions are simply shift instructions that shift
in the bits that are shifted out. For example, on a rotate left 1 bit, the leftmost bit is
shifted out and rotated around to become the rightmost bit.
I/O instructions vary greatly from architecture to architecture. The basic
schemes for handling I/O are programmed I/O, interrupt-driven I/O, and DMA
devices. These are covered in more detail in Chapter 5.
Control instructions include branches, skips, and procedure calls. Branching
can be unconditional or conditional. Skip instructions are basically branch
instructions with implied addresses. Because no operand is required, skip
instructions often use bits of the address field to specify different situations (recall
the Skipcond instruction used by MARIE). Procedure calls are special branch
instructions that automatically save the return address. Different machines use
different methods to save this address. Some store the address at a specific location
in memory, others store it in a register, while still others push the return address on a
stack. We have already seen that stacks can be used for other purposes.
Special purpose instructions include those used for string processing, high
level language support, protection, flag control, and cache management. Most
architectures provide instructions for string processing, including string
manipulation and searching.

Addressing Modes
We have examined the types of operands and operations that may be
specified by machine instructions. Now we have to see how is the address of an
operand specified, and how are the bits of an instruction organized to define the
operand addresses and operation of that instruction.

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Addressing Modes: The most common addressing techniques are

• Immediate
• Direct
• Indirect
• Register
• Register Indirect
• Displacement
• Stack
All computer architectures provide more than one of these addressing modes.
The question arises as to how the control unit can determine which addressing mode
is being used in a particular instruction. Several approaches are used. Often,
different opcodes will use different addressing modes. Also, one or more bits in the
instruction format can be used as a mode field. The value of the mode field
determines which addressing mode is to be used.

What is the interpretation of effective address. In a system without virtual

memory, the effective address will be either a main memory address or a register. In
a virtual memory system, the effective address is a virtual address or a register. The
actual mapping to a physical address is a function of the paging mechanism and is
invisible to the programmer.

To explain the addressing modes, we use the following notation:

A = contents of an address field in the instruction that refers to a

memory
R = contents of an address field in the instruction that refers to a
register
actual (effective) address of the location containing the
EA = referenced operand
(X) = contents of location X

Immediate Addressing:
The simplest form of addressing is immediate addressing, in which the
operand is actually present in the instruction:
OPERAND = A
This mode can be used to define and use constants or set initial values of
variables. The advantage of immediate addressing is that no memory reference other
than the instruction fetch is required to obtain the operand. The disadvantage is that
the size of the number is restricted to the size of the address field, which, in most
instruction sets, is small compared with the world length.

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Figure 4.1: Immediate Addressing Mod

The instruction format for Immediate Addressing Mode is shown in the Figure 4.1.
Direct Addressing:
A very simple form of addressing is direct addressing, in which the address
field contains the effective address of the operand:
EA = A
It requires only one memory reference and no special calculation.

Figure 4.2: Direct Addressing Mode

Indirect Addressing:
With direct addressing, the length of the address field is usually less than the
word length, thus limiting the address range. One solution is to have the address
field refer to the address of a word in memory, which in turn contains a full-length
address of the operand. This is know as indirect addressing:
EA = (A)

Figure 4.3: Indirect Addressing Mode

Register Addressing:
Register addressing is similar to direct addressing. The only difference is that
the address field refers to a register rather than a main memory address:
EA = R

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The advantages of register addressing are that only a small address field is
needed in the instruction and no memory reference is required. The disadvantage of
register addressing is that the address space is very limited.

Figure 4.4: Register Addressing Mode.

The exact register location of the operand in case of Register Addressing

Mode is shown in the Figure 34.4. Here, 'R' indicates a register where the operand is
present.

Register Indirect Addressing:

Register indirect addressing is similar to indirect addressing, except that the
address field refers to a register instead of a memory location. It requires only one
memory reference and no special calculation.
EA = (R)
Register indirect addressing uses one less memory reference than indirect
addressing. Because, the first information is available in a register which is nothing
but a memory address. From that memory location, we use to get the data or
information. In general, register access is much more faster than the memory access.

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Diaplacement Addressing:
A very powerful mode of addressing combines the capabilities of direct
addressing and register indirect addressing, which is broadly categorized as
displacement addressing:
EA = A + (R)
Displacement addressing requires that the instruction have two address fields, at
least one of which is explicit. The value contained in one address field (value = A) is
used directly. The other address field, or an implicit reference based on opcode, refers to
a register whose contents are added to A to produce the effective address. The general
format of Displacement Addressing is shown in the Figure 4.6.
Three of the most common use of displacement addressing are:
• Relative addressing
• Base-register addressing
• Indexing

Figure 4.6: Displacement Addressing

Relative Addressing:
For relative addressing, the implicitly referenced register is the program
counter (PC). That is, the current instruction address is added to the address field to
produce the EA. Thus, the effective address is a displacement relative to the address
of the instruction.
Base-Register Addressing:
The reference register contains a memory address, and the address field
contains a displacement from that address. The register reference may be explicit or
implicit. In some implementation, a single segment/base register is employed and is
used implicitly. In others, the programmer may choose a register to hold the base
address of a segment, and the instruction must reference it explicitly.
Indexing:
The address field references a main memory address, and the reference
register contains a positive displacement from that address. In this case also the
register reference is sometimes explicit and sometimes implicit.
Generally index register are used for iterative tasks, it is typical that there is a
need to increment or decrement the index register after each reference to it. Because

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this is such a common operation, some system will automatically do this as part of the same instruction cycle.
This is known as auto-indexing. We may get two types of auto-indexing: -one is auto-incrementing and the other one
is - auto-decrementing.
If certain registers are devoted exclusively to indexing, then auto-indexing can be invoked implicitly and
automatically. If general purpose register are used, the auto index operation may need to be signaled by a bit in the
instruction.

Auto-indexing using increment can be depicted as follows:

EA = A + (R)
R = (R) + 1

Auto-indexing using decrement can be depicted as follows:

EA = A + (R)
R = (R) - 1

In some machines, both indirect addressing and indexing are provided, and it is possible to employ both in the
same instruction. There are two possibilities: The indexing is performed either before or after the indirection.
If indexing is performed after the indirection, it is termed post indexing

EA = (A) + (R)

First, the contents of the address field are used to access a memory location containing an address. This address is
then indexed by the register value.

With pre indexing, the indexing is performed before the indirection:

EA = ( A + (R)

An address is calculated, the calculated address contains not the operand, but the address of the operand.

Stack Addressing:
A stack is a linear array or list of locations. It is sometimes referred to as a pushdown list or last-in- first-out
queue. A stack is a reserved block of locations. Items are appended to the top of the stack so that, at any given time,
the block is partially filled. Associated with the stack is a pointer whose value is the address of the top of the stack.
The stack pointer is maintained in a register. Thus, references to stack locations in memory are in fact register
indirect addresses.
n have a large impact on the number of page faults that occur.

Input-Output Organization: Peripheral Devices, Input-Output Interface, Asynchronous data

transfer Modes of Transfer, Priority Interrupt Direct memory Access, Input –Output Processor (IOP)
Pipeline And Vector Processing: Parallel Processing, Pipelining, Arithmetic Pipeline, Instruction
Pipeline, Dependencies, Vector Processing.

Introduction:
The I/O subsystem of a computer provides an efficient mode of communication between the central
system and the outside environment. It handles all the input-output operations of the computer
system.

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Peripheral Devices
Input or output devices that are connected to computer are called peripheral devices. These devices
are designed to read information into or out of the memory unit upon command from the CPU and are
considered to be the part of computer system. These devices are also called peripherals.
For example: Keyboards, display units and printers are common peripheral devices.
There are three types of peripherals:

1. Input peripherals : Allows user input, from the outside world to the computer. Example:
Keyboard, Mouse etc.
2. Output peripherals: Allows information output, from the computer to the outside world.
Example: Printer, Monitor etc
3. Input-Output peripherals: Allows both input(from outised world to computer) as well as,
output(from computer to the outside world). Example: Touch screen etc.

Interfaces
Interface is a shared boundary btween two separate components of the computer system which can be
used to attach two or more components to the system for communication purposes.
There are two types of interface:

1. CPU Inteface
2. I/O Interface

Let's understand the I/O Interface in details,

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Input-Output Interface
Peripherals connected to a computer need special communication links for interfacing with CPU. In
computer system, there are special hardware components between the CPU and peripherals to control
or manage the input-output transfers. These components are called input-output interface
units because they provide communication links between processor bus and peripherals. They
provide a method for transferring information between internal system and input-output devices.

Asynchronous Data Transfer

We know that, the internal operations in individual unit of digital system are synchronized by means
of clock pulse, means clock pulse is given to all registers within a unit, and all data transfer among
internal registers occur simultaneously during occurrence of clock pulse.Now, suppose any two units
of digital system are designed independently such as CPU and I/O interface.

And if the registers in the interface(I/O interface) share a common clock with CPU registers, then
transfer between the two units is said to be synchronous.But in most cases, the internal timing in
each unit is independent from each other in such a way that each uses its own private clock for its
internal registers.In that case, the two units are said to be asynchronous to each other, and if data
transfer occur between them this data transfer is said to be Asynchronous Data Transfer.

But, the Asynchronous Data Transfer between two independent units requires that control signals be
transmitted between the communicating units so that the time can be indicated at which they send
data.

This asynchronous way of data transfer can be achieved by two methods:

1. One way is by means of strobe pulse which is supplied by one of the units to other
unit.When transfer has to occur.This method is known as “Strobe Control”.
2. Another method commonly used is to accompany each data item being transferred
with a control signal that indicates the presence of data in the bus.The unit receiving the
data item responds with another signal to acknowledge receipt of the data.This method of
data transfer between two independent units is said to be “Handshaking”.

The strobe pulse and handshaking method of asynchronous data transfer are not restricted to I/O
transfer.In fact, they are used extensively on numerous occasion requiring transfer of data between
two independent units.So, here we consider the transmitting unit as source and receiving unit as
destination.
As an example: The CPU, is the source during an output or write transfer and is the destination unit
during input or read transfer.

And thus, the sequence of control during an asynchronous transfer depends on whether the transfer is
initiated by the source or by the destination.

So, while discussing each way of data transfer asynchronously we see the sequence of control in
both terms when it is initiated by source or when it is initiated by destination.In this way, each way
of data transfer, can be further divided into parts, source initiated and destination initiated.

We can also specify, asynchronous transfer between two independent units by means of a timing
diagram that shows the timing relationship that exists between the control and the data buses.

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Now, we will discuss each method of asynchronous data transfer in detail one by one.

1. Strobe Control:

The Strobe Control method of asynchronous data transfer employs a single control line to time
each transfer .This control line is also known as strobe and it may be achieved either by source or
destination, depending on which initiate transfer.

Source initiated strobe for data transfer:

The block diagram and timing diagram of strobe initiated by source unit is shown in figure below:

In block diagram we see that strobe is initiated by source, and as shown in timing diagram, the
source unit first places the data on the data bus.After a brief delay to ensure that the data settle to a
steady value, the source activates a strobe pulse.The information on data bus and strobe control signal
remain in the active state for a sufficient period of time to allow the destination unit to receive the
data.Actually, the destination unit, uses a falling edge of strobe control to transfer the contents of
data bus to one of its internal registers.The source removes the data from the data bus after it disables
its strobe pulse.New valid data will be available only after the strobe is enabled again.

Destination-initiated strobe for data transfer:

The block diagram and timing diagram of strobe initiated by destination is shown in figure below:

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In block diagram, we see that, the strobe initiated by destination, and as shown in timing diagram,
the destination unit first activates the strobe pulse, informing the source to provide the data.The
source unit responds by placing the requested binary information on the data bus.The data must be
valid and remain in the bus long enough for the destination unit to accept it.The falling edge of strobe
pulse can be used again to trigger a destination register.The destination unit then disables
the strobe.And source removes the data from data bus after a per determine time interval.

Now, actually in computer, in the first case means in strobe initiated by source - the strobe may be
a memory-write control signal from the CPU to a memory unit.The source, CPU, places the word on
the data bus and informs the memory unit, which is the destination, that this is a write operation.

And in the second case i.e, in the strobe initiated by destination - the strobe may be a memory read
control from the CPU to a memory unit.The destination, the CPU, initiates the read operation to
inform the memory, which is a source unit, to place selected word into the data bus.

2. Handshaking:

The disadvantage of strobe method is that source unit that initiates the transfer has no way of
knowing whether the destination has actually received the data that was placed in the
bus.Similarly, a destination unit that initiates the transfer has no way of knowing whether
the source unit, has actuallyplaced data on the bus.

This problem can be solved by handshaking method.

Hand shaking method introduce a second control signal line that provides a replay to the unit that
initiates the transfer.

In it, one control line is in the same direction as the data flow in the bus from the source to
destination.It is used by source unit to inform the destination unit whether there are valid data
in the bus.The other control line is in the other direction from destination to the source.It is
used by the destination unit to inform the source whether it can accept data.And in it
also, sequence of control depends on unit that initiate transfer.Means sequence of control depends
whether transfer is initiated by source and destination.Sequence of control in both of them are
described below:

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Source initiated Handshaking:

The source initiated transfer using handshaking lines is shown in figure below:

In its block diagram, we se that two handshaking lines are "data valid", which is generated by the
source unit, and "data accepted", generated by the destination unit.

The timing diagram shows the timing relationship of exchange of signals between the two
units.Means as shown in its timing diagram, the source initiates a transfer by placing data on the bus
and enabling its data valid signal.The data accepted signal is then activated by destination unit after it
accepts the data from the bus.The source unit then disable its data valid signal which invalidates the
data on the bus.After this, the destination unit disables its data accepted signal and the system goes
into initial state.The source unit does not send the next data item until after the destination unit shows
its readiness to accept new data by disabling the data accepted signal.

This sequence of events described in its sequence diagram, which shows the above sequence in
which the system is present, at any given time.

Destination initiated handshaking:

The destination initiated transfer using handshaking lines is shown in figure below:

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In its block diagram, we see that the two handshaking lines are "data valid", generated by the
source unit, and "ready for data" generated by destination unit.Note that the name of signal data
accepted generated by destination unit has been changed to ready for data to reflect its new meaning.

In it, transfer is initiated by destination, so source unit does not place data on data bus until it
receives ready for data signal from destination unit.After that, hand shaking process is some as that of
source initiated.

The sequence of event in it are shown in its sequence diagram and timing relationship between
signals is shown in its timing diagram.

Thus, here we can say that, sequence of events in both cases would be identical.If we consider
ready for data signal as the complement of data accept.Means, the only difference between source
and destination initiated transfer is in their choice of initial state.

Modes of I/O Data Transfer

Data transfer between the central unit and I/O devices can be handled in generally three types of
modes which are given below:
1. Programmed I/O
2. Interrupt Initiated I/O
3. Direct Memory Access

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Programmed I/O
Programmed I/O instructions are the result of I/O instructions written in computer program. Each
data item transfer is initiated by the instruction in the program.
Usually the program controls data transfer to and from CPU and peripheral. Transferring data under
programmed I/O requires constant monitoring of the peripherals by the CPU.

Interrupt Initiated I/O

In the programmed I/O method the CPU stays in the program loop until the I/O unit indicates that
it is ready for data transfer. This is time consuming process because it keeps the processor busy
needlessly.
This problem can be overcome by using interrupt initiated I/O. In this when the interface determines that
the peripheral is ready for data transfer, it generates an interrupt. After receiving the interrupt signal, the
CPU stops the task which it is processing and service the I/O transfer and then returns back to its
previous processing task.

Direct Memory Access

Removing the CPU from the path and letting the peripheral device manage the memory buses
directly would improve the speed of transfer. This technique is known as DMA.
In this, the interface transfer data to and from the memory through memory bus. A DMA controller
manages to transfer data between peripherals and memory unit.
Many hardware systems use DMA such as disk drive controllers, graphic cards, network cards and sound
cards etc. It is also used for intra chip data transfer in multicore processors. In DMA, CPU would initiate
the transfer, do other operations while the transfer is in progress and receive an interrupt from the DMA
controller when the transfer has been completed.

Priority Interrupt
A priority interrupt is a system which decides the priority at which various devices, which
generates the interrupt signal at the same time, will be serviced by the CPU. The system has authority to
decide which conditions are allowed to interrupt the CPU, while some other interrupt is being serviced.
Generally, devices with high speed transfer such as magnetic disks are given high priority and slow
devices such as keyboards are given low priority.
When two or more devices interrupt the computer simultaneously, the computer services the device with the
higher priority first.

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DIRECT MEMORY ACCESS

Block of data transfer from high speed devices, Drum, Disk, Tape

CPU bus signals for DMA transfer


ABUS Address bus High-impedence
Bus request
BR DBUS Data bus (disabled)
Bus granted CPU RD when BG is
Read
BG
WR Write enabled
Block diagram of DMA controller
Address bus
Data bus
Data bus buffers Address bus
buffers

DMA select
DS Internal Bus
Register select Address register
RS
Read
RD Word count register
Write Control
WR
Bus request logic
BR Control register
Bus grant
BG
Interrupt Interrupt DMA request
DMA acknowledge to I/O device

* DMA controller - Interface which allows I/O transfer directly

between Memory and Device, freeing CPU for other tasks
* CPU initializes DMA Controller by sending memory
address and the block size(number of words)

DMA TRANSFER

Interrupt
Random-access
BG
CPU memory unit (RAM)
BR
RD WR Addr Data RD WR Addr Data
Read control
Write control
Data bus
Address bus

Address
select

RD WR Addr Data
DS DMA ack.

RS I/O
DMA
Peripheral
BR Controller
device
BG DMA request
Interrupt

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Input/output Processor
An input-output processor (IOP) is a processor with direct memory access capability. In this, the
computer system is divided into a memory unit and number of processors.
Each IOP controls and manage the input-output tasks. The IOP is similar to CPU except that it
handles only the details of I/O processing. The IOP can fetch and execute its own instructions. These
IOP instructions are designed to manage I/O transfers only.
Block Diagram Of I/O Processor:
Below is a block diagram of a computer along with various I/O Processors. The memory unit occupies the
central position and can communicate with each processor.
The CPU processes the data required for solving the computational tasks. The IOP provides a path for
transfer of data between peripherals and memory. The CPU assigns the task of initiating the I/O program.
The IOP operates independent from CPU and transfer data between peripherals and memory.

The communication between the IOP and the devices is similar to the program control method of transfer.
And the communication with the memory is similar to the direct memory access method.
In large scale computers, each processor is independent of other processors and any processor can initiate
the operation.
The CPU can act as master and the IOP act as slave processor. The CPU assigns the task of initiating
operations but it is the IOP, who executes the instructions, and not the CPU. CPU instructions
provide operations to start an I/O transfer. The IOP asks for CPU through interrupt.
Instructions that are read from memory by an IOP are also called commands to distinguish them from
instructions that are read by CPU. Commands are prepared by programmers and are stored in memory.
Command words make the program for IOP. CPU informs the IOP where to find the commands in
memory.

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Pipelining and vector processing

Parallel processing
Execution of Concurrent Events in the computing process to achieve faster Computational Speed
Levels of Parallel Processing
- Job or Program level
- Task or Procedure level
- Inter-Instruction level
- Intra-Instruction level
PARALLEL COMPUTERS
Architectural Classification
Flynn's classification

» Based on the multiplicity of Instruction Streams and Data Streams

» Instruction Stream
Sequence of Instructions read from memory

» Data Stream
Operations performed on the data in the processor

What is Pipelining?
Pipelining is the process of accumulating instruction from the processor through a pipeline. It
allows storing and executing instructions in an orderly process. It is also known as pipeline
processing.
Pipelining is a technique where multiple instructions are overlapped during execution. Pipeline is
divided into stages and these stages are connected with one another to form a pipe like structure.
Instructions enter from one end and exit from another end.
Pipelining increases the overall instruction throughput.
In pipeline system, each segment consists of an input register followed by a combinational circuit.
The register is used to hold data and combinational circuit performs operations on it. The output
of combinational circuit is applied to the input register of the next segment.

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Pipeline system is like the modern day assembly line setup in factories. For example in a car
manufacturing industry, huge assembly lines are setup and at each point, there are robotic arms to
perform a certain task, and then the car moves on ahead to the next arm.

Types of Pipeline
It is divided into 2 categories:

1. Arithmetic Pipeline
2. Instruction Pipeline

Arithmetic Pipeline
Arithmetic pipelines are usually found in most of the computers. They are used for floating point
operations, multiplication of fixed point numbers etc. For example: The input to the Floating Point Adder
pipeline is:
X = A*2^a

Y = B*2^b

Here A and B are mantissas (significant digit of floating point numbers), while a and b are exponents.
The floating point addition and subtraction is done in 4 parts:

1. Compare the exponents.

2. Align the mantissas.
3. Add or subtract mantissas
4. Produce the result.

Registers are used for storing the intermediate results between the above operations.

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Instruction Pipeline
In this a stream of instructions can be executed by overlapping fetch, decode and execute phases of an
instruction cycle. This type of technique is used to increase the throughput of the computer system.
An instruction pipeline reads instruction from the memory while previous instructions are being executed
in other segments of the pipeline. Thus we can execute multiple instructions simultaneously. The
pipeline will be more efficient if the instruction cycle is divided into segments of equal duration.

Advantages of Pipelining
1. The cycle time of the processor is reduced.
2. It increases the throughput of the system
3. It makes the system reliable.

Disadvantages of Pipelining
1. The design of pipelined processor is complex and costly to manufacture.
2. The instruction latency is more.

Vector(Array) Processing
There is a class of computational problems that are beyond the capabilities of a conventional
computer. These problems require vast number of computations on multiple data items, that will take a
conventional computer(with scalar processor) days or even weeks to complete.
Such complex instructions, which operates on multiple data at the same time, requires a better way of
instruction execution, which was achieved by Vector processors.
Scalar CPUs can manipulate one or two data items at a time, which is not very efficient. Also, simple
instructions like ADD A to B, and store into C are not practically efficient.
Addresses are used to point to the memory location where the data to be operated will be found, which
leads to added overhead of data lookup. So until the data is found, the CPU would be sitting ideal,
which is a big performance issue.
Hence, the concept of Instruction Pipeline comes into picture, in which the instruction passes through
several sub-units in turn. These sub-units perform various independent functions, for example:
the first one decodes the instruction, the second sub-unit fetches the data and the thirdsub-unit performs
the math itself. Therefore, while the data is fetched for one instruction, CPU does not sit idle, it rather
works on decoding the next instruction set, ending up working like an assembly line.
Vector processor, not only use Instruction pipeline, but it also pipelines the data, working on multiple
data at the same time.
A normal scalar processor instruction would be ADD A, B, which leads to addition of two operands, but
what if we can instruct the processor to ADD a group of numbers(from 0 to n memory location) to another
group of numbers(lets say, n to k memory location). This can be achieved by vector processors.
In vector processor a single instruction, can ask for multiple data operations, which saves time, as
instruction is decoded once, and then it keeps on operating on different data items.

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Applications of Vector Processors

Computer with vector processing capabilities are in demand in specialized applications. The following are
some areas where vector processing is used:

1. Petroleum exploration.
2. Medical diagnosis.
3. Data analysis.
4. Weather forecasting.
5. Aerodynamics and space flight simulations.
6. Image processing.
7. Artificial intelligence.

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