Instruction Cycle

A program residing in the memory unit of a computer consists of a sequence of

instructions. These instructions are executed by the processor by going through
a cycle for each instruction. In a basic computer, each instruction cycle consists
of the following phases:
1. Fetch instruction from memory.
2. Decode the instruction.
3. Read the effective address from memory.
4. Execute the instruction.

Input-Output Configuration
In computer architecture, input-output devices act as an interface between the
machine and the user.

Instructions and data stored in the memory must come from some input device.
The results are displayed to the user through some output device.

The following block diagram shows the input-output configuration for a basic
computer.
 o The input-output terminals send and receive information.
o The amount of information transferred will always have eight bits of an
alphanumeric code.
o The info generated on the keyboard is shifted to an input register 'INPR.
The information for the printer is stored in the output register 'OUTR'.
o Registers INPR and OUTR communicate with a communication interface
serially and with the AC in parallel.
o The transmitter interface receives info from keyboard and transmits to
INPR. The receiver interface receives info from OUTR and sends to the
printer serially.

Design of a Basic Computer

A basic computer consists of the following hardware components.

1. A memory unit with 4096 words of 16 bits each

2. Registers: AC (Accumulator), DR (Data register), AR (Address register),
IR (Instruction register), PC (Program counter), TR (Temporary register),
SC (Sequence Counter), INPR (Input register), and OUTR (Output
register).
3. Flip-Flops: I, S, E, R, IEN, FGI and FGO
4. Two decoders: a 3 x 8 operation decoder and 4 x 16 timing decoder
5. A 16-bit common bus
6. Control Logic Gates
7. The Logic and Adder circuits connected to the input of AC.
Note: FGI and FGO are corresponding input and output flags which are considered as
control flip-flops.

Design of Control Unit

Control Unit: The Control Unit of a computer system controls the operations of
components like ALU, memory and input/output devices.

The Control Unit consists of a program counter that contains the address of the
instructions to be fetched and an instruction register into which instructions are
fetched from memory for execution.

The Control Unit is classified into two major categories(organizations):

1. Hardwired Control
2. Microprogrammed Control

Hardwired Control
The Hardwired Control organization involves the control logic to be implemented
with gates, flip-flops, decoders, and other digital circuits.

The following image shows the block diagram of a Hardwired Control

organization.
 opcode (3 bit) = what operation it is to perform. From 000 –
110;
I = addressing mode; if
I = 0 i.e direct addressing;
I = 1 indirect addressing mode

o A Hard-wired Control consists of two decoders, a sequence counter, and a

number of logic gates.
o An instruction fetched from the memory unit is placed in the instruction
register (IR).
o The component of an instruction register includes; I bit, the operation code,
and bits 0 through 11.
o The operation code in bits 12 through 14 are coded with a 3 x 8 decoder.
o The outputs of the decoder are designated by the symbols D0 through D7.
o The operation code at bit 15 is transferred to a flip-flop designated by the
symbol I.
o The operation codes from Bits 0 through 11 are applied to the control logic
gates.
o The Sequence counter (SC) can count in binary from 0 through 15.

Micro-programmed Control
The Microprogrammed Control organization is implemented by using the
programming approach.

In Microprogrammed Control, the micro-operations are performed by executing

a program consisting of micro-instructions.
The following image shows the block diagram of a Microprogrammed Control
organization.

o The Control memory address register specifies the address of the micro-
instruction.
o The Control memory is assumed to be a ROM, within which all control
information is permanently stored.
o The control register holds the microinstruction fetched from the memory.
o The micro-instruction contains a control word that specifies one or more
micro-operations for the data processor.
o While the micro-operations are being executed, the next address is
computed in the next address generator circuit and then transferred into the
control address register to read the next microinstruction.
o The next address generator is often referred to as a micro-program
sequencer, as it determines the address sequence that is read from control
memory.

Some Other differences between Micro-programmed

control unit and Hardwire control unit
Now we will describe these differences on the basis of some parameters, such as
speed, cost, modification, instruction decoder, control memory, etc. These
differences are described as follows:

Speed

In the hardwired control unit, the speed of operations is very fast. In contrast, the
micro-programmed control unit needs frequent memory access. So the speed of
operation of a micro-programmed control unit is slow.
Modification

If we want to do some modifications to the Hardwired control unit, we have to

redesign the entire unit. In contrast, if we want to do some modification in the
micro-programmed control unit, we can do that just by changing the
microinstructions in the control memory. In this case, the more flexible control
unit is a micro-programmed control unit.

Cost

The implementation of a Hardwire control unit is very much compared to the

Micro-programmed control unit. In this case, the micro-programmed control unit
will save our money at the time of implementation.

Handling Complex Instructions

If we try to handle the complex instructions with the help of a hardwired control
unit, it will be very difficult for us to handle them. But if we try to handle the
complex instructions with the help of micro-programmed control unit, it will be
very easy for us to handle them. In this case also, the Micro-programmed control
unit is better.

Instruction decoding

In the hardwired control unit, if we want to perform instruction decoding, it will

be very difficult. But if we do the same thing in a micro-programmed control unit,
it will be very easy for us.

Instruction set size

A small instruction set is used by the hardwired CU. On the other hand, a large
instruction set is used by the micro-programmed control unit.

Control Memory

The hardwired control unit does not use the control memory to generate the
control signals, but the micro-programmed CU needs to use the control memory
to generate the control signals.

Applications

The hardwired control unit is used in those types of processors that basically use
a simple instruction set. This set is called a Reduced Instruction Set Computer.
On the other hand, a micro-programmed control unit is used in those types of
processors that basically use a complex instruction set. This set is called a
Complex Instruction Set Computer.

Hardwired Control Unit Micro-programmed Control Unit

With the help of a hardware circuit, we can While with the help of programming, we can
implement the hardwired control unit. In other implement the micro-programmed control unit.
words, we can say that it is a circuitry approach.

The hardwired control unit uses the logic circuit The micro-programmed CU uses
so that it can generate the control signals, which microinstruction so that it can generate the
are required for the processor. control signals. Usually, control memory is
used to store these microinstructions.

In this CU, the control signals are going to be It is very easy to modify the micro-programmed
generated in the form of hard wired. That's why control unit because the modifications are going
it is very difficult to modify the hardwired to be performed only at the instruction level.
control unit.

In the form of logic gates, everything has to be The micro-programmed control unit is less
realized in the hardwired control unit. That's costly as compared to the hardwired CU
why this CU is costlier as compared to the because this control unit only requires the
micro-programmed control unit. microinstruction to generate the control signals.

The complex instructions cannot be handled by The micro-programmed control unit is able to
a hardwired control unit because when we handle the complex instructions.
design a circuit for this instruction, it will
become complex.

Because of the hardware implementation, the The micro-programmed control unit is able to
hardwired control unit is able to use a limited generate control signals for many instructions.
number of instructions.

The hardwired control unit is used in those types The micro-programmed control unit is used in
of computers that also use the RISC (Reduced those types of computers that also use the CISC
instruction Set Computers). (Complex instruction Set Computers).

In the hardwired control unit, the hardware is In this CU, the microinstructions are used to
used to generate only the required control generate the control signals. That's why this CU
signals. That's why this control unit is faster as is slower than the hardwired control unit.
compared to the micro-programmed control
unit.
 Combinational Circuits
A combinational circuit comprises of logic gates whose outputs at any time are
determined directly from the present combination of inputs without any regard to
previous inputs.

A combinational circuit performs a specific information-processing operation

fully specified logically by a set of Boolean functions.

The basic components of a combinational circuit are:

a) input variables,
b) logic gates,
c) and output variables.

The 'n' input variables come from an external source whereas the 'm' output
variables go to an external destination. In many applications, the source or
destination are storage registers.

Examples
1. Adders & subtractor
2. Decoders
3. Code converters
4. Comparators
5. Rom
6. Programmable logic array

Design procedure of a Combinational Circuit

The design procedure of a combinational circuit involves the following steps:

1. Find the required number of input variables and outputs from given
specifications.
 2. Formulate the Truth table. If there are ‘n’ input variables, then there
will be 2n possible combinations. For each combination of input, find
the output values.
3. Find the Boolean expressions for each output. If necessary, simplify
those expressions.
4. Implement the above Boolean expressions corresponding to each output
by using Logic gates.

Digital Arithmetic Circuits

The basic arithmetic circuits like Binary adder and Binary subtractor. These
circuits can be operated with binary values 0 and 1.

Binary Adder
The most basic arithmetic operation is addition. The circuit, which performs the
addition of two binary numbers is known as Binary adder. First, let us implement
an adder, which performs the addition of two bits.

The combinational circuit that performs the addition of two bits is called a half
adder and the one that performs the addition of three bits (two significant bits and
a previous carry) is a full adder.

Half Adder
Half adder is a combinational circuit, which performs the addition of two binary
numbers A and B are of single bit. It produces two outputs sum, S & carry, C.
The Truth table of Half adder is shown below.

Inputs Outputs

A B C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0
When we do the addition of two bits, the resultant sum can have the values
ranging from 0 to 2 in decimal. We can represent the decimal digits 0 and 1 with
single bit in binary. But, we can’t represent decimal digit 2 with single bit in
binary. So, we require two bits for representing it in binary.
Let, sum, S is the Least significant bit and carry, C is the Most significant bit of
the resultant sum. For first three combinations of inputs, carry, C is zero and the
value of S will be either zero or one based on the number of ones present at the
inputs. But, for last combination of inputs, carry, C is one and sum, S is zero,
since the resultant sum is two.
From Truth table, we can directly write the Boolean functions for each output as
S=A⊕B
C=AB
We can implement the above functions with 2-input Ex-OR gate & 2-input AND
gate. The circuit diagram of Half adder is shown in the following figure.

In the above circuit, a two input Ex-OR gate & two input AND gate produces
sum, S & carry, C respectively. Therefore, Half-adder performs the addition of
two bits.
Full Adder
Full adder is a combinational circuit, which performs the addition of three
bits A, B and Cin. Where, A & B are the two parallel significant bits and Cin is the
carry bit, which is generated from previous stage. This Full adder also produces
two outputs sum, S & carry, Cout, which are similar to Half adder.
The Truth table of Full adder is shown below.

Inputs Outputs

A B Cin Cout S

0 0 0 0 0
 0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

When we do the addition of three bits, the resultant sum can have the values
ranging from 0 to 3 in decimal. We can represent the decimal digits 0 and 1 with
single bit in binary. But, we can’t represent the decimal digits 2 and 3 with single
bit in binary. So, we require two bits for representing those two decimal digits in
binary.
Let, sum, S is the Least significant bit and carry, Cout is the Most significant bit of
resultant sum. It is easy to fill the values of outputs for all combinations of inputs
in the truth table. Just count the number of ones present at the inputs and write
the equivalent binary number at outputs. If Cin is equal to zero, then Full adder
truth table is same as that of Half adder truth table.
We will get the following Boolean functions for each output after simplification.
S=A⊕B⊕Cin
cout=AB+(A⊕B)cin
The sum, S is equal to one, when odd number of ones present at the inputs. We
know that Ex-OR gate produces an output, which is an odd function. So, we can
use either two 2input Ex-OR gates or one 3-input Ex-OR gate in order to produce
sum, S. We can implement carry, Cout using two 2-input AND gates & one OR
gate. The circuit diagram of Full adder is shown in the following figure.
This adder is called as Full adder because for implementing one Full adder, we
require two Half adders and one OR gate. If Cin is zero, then Full adder becomes
Half adder. We can verify it easily from the above circuit diagram or from the
Boolean functions of outputs of Full adder.

Integrated Circuits
An integrated circuit (IC) is manufactured using silicon material and mounted in
a ceramic or plastic container (known as Chip). The basic components of an IC
consist of electronic circuits for the digital gates. The various gates are
interconnected inside an IC to form the required circuit.

The following categories can broadly classify an Integrated Circuit (IC):

SSI (Small Scale Integration Devices)
These types of devices contain several independent gates in a single package. The
inputs and outputs of these gates are connected directly to the pins in the package.
The number of logic gates are usually less than 10 and are limited by the number
of pins available in the IC.

MSI (Medium Scale Integration Devices)

These types of devices have a complexity of approximately 10 to 200 gates in a
single package. The basic components include decoders, adders, and registers.

LSI (Large Scale Integration Devices)

LSI devices contain about 200 to a few thousand gates in a single package. The
basic components of an LSI device include digital systems, such as processors,
memory chips, and programmable modules.

VLSI (Very Large Scale Integration Device)

This type of devices contains thousands of gates within a single package. The
most common example of a VLSI device is a complex microcomputer chip.

Digital integrated circuits are also classified by their specific circuit technology
to which they belong. The circuit technology is often referred to as Digital Logic
Family. Each technology has its own basic electronic circuit and functions to
perform.

The most common component in each technology is either a NAND, a NOR, or

an inverter gate.

Decoders
A Decoder can be described as a combinational circuit that converts binary
information from the 'n' coded inputs to a maximum of 2^n different outputs.
Note: A binary code of n bits is capable of representing up to 2^n distinct elements of the
coded information.

The most preferred or commonly used decoders are n-to-m decoders, where m<=
2^n.

An n-to-m decoder has n inputs and m outputs and is also referred to as an n * m

decoder.

The following image shows a 3-to-8-line decoder with three input variables
which are decoded into eight output, each output representing one of the
combinations of the three binary input variables.

The three inverter gates provide the complement of the inputs corresponding to
which the eight AND gates at the output generates one binary combination for
each input.

The most common application of this decoder is binary-to-octal conversion.

The truth table for a 3-to-8 line decoder can be represented as:

x y z D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0
 0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

Let us consider an example of 2-to-4 line NAND Gate Decoder which uses
NAND Gates instead of AND gate in the central logic.

The following image shows a 2-to-4-line decoder with NAND gates.

The truth table for a 2-to-4 line decoder can be represented as:

E A1 A0 D0 D1 D2 D3
 0 0 0 0 1 1 1

0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0

1 0 0 1 1 1 1

It is also possible to combine two or more decoders to form a large decoder

whenever needed. For instance, we can construct a 3 * 8 decoder by combining
two 2 *4 decoders.

The following image shows a 3 * 8 decoder constructed with two 2 * 4 decoders.

Encoders
An encoder can also be described as a combinational circuit that performs the
inverse operation of a decoder. An encoder has a maximum of 2^n (or less) input
lines and n output lines.

In an Encoder, the output lines generate the binary code corresponding to the
input value.

The following image shows the block diagram of a 4 * 2 encoder with four input
and two output lines.

The truth table for a 4-to-2 line encoder can be represented as:

A3 A2 A1 A0 D1 D0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

From the truth table, we can write the Boolean function for each output as:
D1 = A3 + A2
D0 = A3 + A1

The circuit diagram for a 4-to-2 line encoder can be represented by using two
input OR gates.
The most common application of an encoder is the Octal-to-Binary encoder.
Octal to binary encoder takes eight input lines and generates three output lines.

The following image shows the block diagram of an 8 * 3 line encoder.

The truth table for an 8 * 3 line encoder can be represented as:

 D7 D6 D5 D4 D3 D2 D1 D0 x y z

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

From the truth table, we can write the Boolean function for each output as:
x = D4 + D5 + D6 + D7
y = D2 + D3 + D6 + D7
z = D1 + D3 + D5 + D7

The circuit diagram for an 8 * 3 line encoder can be represented by using two
input OR gates.
Multiplexers
A Multiplexer (MUX) can be described as a combinational circuit that receives
binary information from one of the 2^n input data lines and directs it to a single
output line.

The selection of a particular input data line for the output is decided on the basis
of selection lines. Backward 10s

The multiplexer is often called as data selector since it selects only one of many
data inputs.

Note: A 2^n-to-1 multiplexer has 2^n input data lines and n input selection lines whose bit
combinations determine which input data are selected for the output.

The following image shows the block diagram of a 4 * 1 Multiplexer.

Out of these four input data lines, a particular input data line will be connected to
the output based on the combination of inputs present at these two selection lines.

Note: A truth table describing the circuit needs 64 rows since six input variables can have
2^n binary combinations. This will result in an excessively long table. Therefore, a more
convenient way to describe the operation of multiplexers is using a function table.

The function table for a 4 * 1 Multiplexer can be represented as:

S1 S0 y

0 0 I0

0 1 I1

1 0 I2

1 1 13

From the function table, we can write the Boolean function for the output (y) as:
y = S1'S0'I0 + S1' S0'I1 + S1S0'I2 + S1S0I3

The above equation for output 'y' can be implemented using inverters, three-input
AND gates and an OR gate.
We can also implement higher order multiplexers using lower order multiplexers.
For instance, let us implement an 8 *1 multiplexer using two 4*1 multiplexers
and a 2*1 multiplexer.

The two 4*1 multiplexers are required in the first stage to get the eight input data
lines.

A 2*1 multiplexer is required in the second stage to converge the outputs

generated at first stage into a single output.

The following image shows the block diagram of an 8*1 multiplexer designed
using two 4*1 multiplexers and a single 2*1 multiplexer.
A set of common selection lines (S1 and S2) are applied to both of the 4*1
multiplexers.

The output generated by both of the 4*1 multiplexers is applied as inputs of the
2*1 multiplexer.

The function table for an 8*1 multiplexer can be represented as:

S2 S1 S0 y

0 0 0 10

0 0 1 I1

0 1 0 I2

0 1 1 I3

1 0 0 I4

1 0 1 I5

1 1 0 I6

1 1 1 17
De-Multiplexers
A De-multiplexer (De-Mux) can be described as a combinational circuit that
performs the reverse operation of a Multiplexer.

A De-multiplexer has a single input, 'n' selection lines and a maximum of 2^n
outputs.

The following image shows the block diagram of a 1 * 4 De-multiplexer.

The function table for a 1 * 4 De - Multiplexer can be represented as:

S1 S0 y3 y2 y1 y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0

From the above function table, we can write the Boolean function for each output
as:
y3 = S1S0 I, y2 = S1S0' I, y1 = S1' S0 I, y0 = S1'S0' I

The above equations can be implemented using inverters and three-input AND
gates.
We can also implement higher order De-multiplexers using lower order De-
multiplexers. For instance, let us implement a 1 * 8 De-multiplexer using 1 * 2
De-multiplexer in the first stage followed by two 1 * 4 De-multiplexers in the
second stage.

The function table for a 1 * 8 De-multiplexer can be represented as:

S2 S1 S0 y7 y6 y5 y4 y3 y2 y1 y0

0 0 0 0 0 0 0 0 0 0 I

0 0 1 0 0 0 0 0 0 I 0

0 1 0 0 0 0 0 0 I 0 0

0 1 1 0 0 0 0 I 0 0 0

1 0 0 0 0 0 I 0 0 0 0

1 0 1 0 0 I 0 0 0 0 0

1 1 0 0 I 0 0 0 0 0 0
 1 1 1 I 0 0 0 0 0 0 0

The block diagram for a 1 * 8 De-multiplexer can be represented as:

The Selection lines 'S1' and 'S0' are common for both of the 1 * 4 De-
multiplexers.

Registers
o A Register is a fast memory used to accept, store, and transfer data and
instructions that are being used immediately by the CPU.
o A Register can also be considered as a group of flip-flops with each flip-
flop capable of storing one bit of information.
o A register with n flip-flops is capable of storing binary information of n-
bits.
 o The flip-flops contain the binary information whereas the gates control the
flow of information, i.e. when and how the information’s are transferred
into a register.
o Different types of registers are available commercially. A simple register
consists of only flip-flops with no external gates.
o The transfer of new data into a register is referred to as loading the register.

o The above figure shows a register constructed with four D-type flip-flops
and a common clock pulse-input.
o The clock pulse-input, CP, enables all flip-flops so that the information
presently available at the four inputs can be transferred into the four-bit
register.

Shift - Registers
Shift - Registers are capable of shifting their binary information in one or both
directions. The logical configuration of a Shift - Register consists of a series of
flip-flops, with the output of one flip-flop connected to the input of the next flip-
flop.

Note: To control the flow of shifts, i.e. the flow of binary information from one register to
the next, a common clock is connected to all of the registers connected in series. This clock
generates a clock pulse which initiates the shift from one stage to the next.

The following image shows the block diagram of a Shift - Register and its
configuration.
The basic configuration of a Shift - Register contains the following points:

o The most general Shift - Registers are often referred to as Bidirectional

Shift Register with parallel load.
o A common clock is connected to each register in series to synchronize all
operations.
o A serial input line is associated with the left-most register, and a serial
output line is associated with the right-most register.
o A control state is connected which leaves the information in the register
unchanged even though clock pulses are applied continuously

Register Transfer Language

A digital computer system exhibits an interconnection of digital modules such as
registers, decoders, arithmetic elements, and Control logic.

These digital modules are interconnected with some common data and control
paths to form a complete digital system.

Moreover, digital modules are best defined by the registers and the operations
that are performed on the data stored in them.

The operations performed on the data stored in registers are called Micro-
operations.
The internal hardware organization of a digital system is best defined by
specifying:

o The set of registers and the flow of data between them.

o The sequence of micro-operations performed on the data which are stored
in the registers.
o The control paths that initiates the sequence of micro-operation

The Register Transfer Language is the symbolic representation of notations

used to specify the sequence of micro-operations.

In a computer system, data transfer takes place between processor registers and
memory and between processor registers and input-output systems. These data
transfer can be represented by standard notations given below:

o Notations R0, R1, R2..., and so on represent processor registers.

o The addresses of memory locations are represented by names such as LOC,
PLACE, MEM, etc.
o Input-output registers are represented by names such as DATA IN, DATA
OUT and so on.
o The content of register or memory location is denoted by placing square
brackets around the name of the register or memory location.

Register Transfer
The term Register Transfer refers to the availability of hardware logic circuits
that can perform a given micro-operation and transfer the result of the operation
to the same or another register.

Most of the standard notations used for specifying operations on various registers
are stated below.

o The memory address register is designated by MAR.

o Program Counter PC holds the next instruction's address.
o Instruction Register IR holds the instruction being executed.
o R1 (Processor Register).
o We can also indicate individual bits by placing them in parenthesis. For
instance, PC (8-15), R2 (5), etc.
 o Data Transfer from one register to another register is represented in
symbolic form by means of replacement operator. For instance, the
following statement denotes a transfer of the data of register R1 into
register R2.

1. R2 ← R1
o Typically, most of the users want the transfer to occur only in a
predetermined control condition. This can be shown by following if-then
statement:
If (P=1) then (R2 ← R1); Here P is a control signal generated in the control
section.
o It is more convenient to specify a control function (P) by separating the
control variables from the register transfer operation. For instance, the
following statement defines the data transfer operation under a specific
control function (P).

1. P: R2 ← R1

The following image shows the block diagram that depicts the transfer of data
from R1 to R2.

Here, the letter 'n' indicates the number of bits for the register. The 'n' outputs of
the register R1 are connected to the 'n' inputs of register R2.

A load input is activated by the control variable 'P' which is transferred to the
register R2.
 Memory Organisation
Memory Hierarchy
A memory unit is an essential component in any digital computer since it is
needed for storing programs and data.

Typically, a memory unit can be classified into two categories:

1. The memory unit that establishes direct communication with the CPU is
called Main Memory. The main memory is often referred to as RAM
(Random Access Memory).
2. The memory units that provide backup storage are called Auxiliary
Memory. For instance, magnetic disks and magnetic tapes are the most
commonly used auxiliary memories.

Apart from the basic classifications of a memory unit, the memory hierarchy
consists all of the storage devices available in a computer system ranging from
the slow but high-capacity auxiliary memory to relatively faster main memory.

The following image illustrates the components in a typical memory hierarchy.

Auxiliary Memory
Auxiliary memory is known as the lowest-cost, highest-capacity and slowest-
access storage in a computer system. Auxiliary memory provides storage for
programs and data that are kept for long-term storage or when not in immediate
use. The most common examples of auxiliary memories are magnetic tapes and
magnetic disks.

A magnetic disk is a digital computer memory that uses a magnetization process

to write, rewrite and access data. For example, hard drives, zip disks, and floppy
disks.

Magnetic tape is a storage medium that allows for data archiving, collection,
and backup for different kinds of data.

Main Memory
The main memory in a computer system is often referred to as Random Access
Memory (RAM). This memory unit communicates directly with the CPU and
with auxiliary memory devices through an I/O processor.

The programs that are not currently required in the main memory are transferred
into auxiliary memory to provide space for currently used programs and data.

I/O Processor
The primary function of an I/O Processor is to manage the data transfers
between auxiliary memories and the main memory.
Cache Memory
The data or contents of the main memory that are used frequently by CPU are
stored in the cache memory so that the processor can easily access that data in a
shorter time. Whenever the CPU requires accessing memory, it first checks the
required data into the cache memory. If the data is found in the cache memory,
it is read from the fast memory. Otherwise, the CPU moves onto the main
memory for the required data.

We will discuss each component of the memory hierarchy in more detail later in
this chapter.

Main Memory
The main memory acts as the central storage unit in a computer system. It is a
relatively large and fast memory which is used to store programs and data during
the run time operations.
The primary technology used for the main memory is based on semiconductor
integrated circuits. The integrated circuits for the main memory are classified into
two major units.

1. RAM (Random Access Memory) integrated circuit chips

2. ROM (Read Only Memory) integrated circuit chips

RAM integrated circuit chips

The RAM integrated circuit chips are further classified into two possible
operating modes,

1. static RAM
2. dynamic RAM.

The primary compositions of a static RAM are flip-flops that store the binary
information. The nature of the stored information is volatile, i.e. it remains valid
as long as power is applied to the system. The static RAM is easy to use and takes
less time performing read and write operations as compared to dynamic RAM.

The dynamic RAM exhibits the binary information in the form of electric charges
that are applied to capacitors. The capacitors are integrated inside the chip by
MOS transistors. The dynamic RAM consumes less power and provides large
storage capacity in a single memory chip.

RAM chips are available in a variety of sizes and are used as per the system
requirement. The following block diagram demonstrates the chip interconnection
in a 128 * 8 RAM chip.
 o A 128 * 8 RAM chip has a memory capacity of 128 words of eight bits
(one byte) per word. This requires a 7-bit address and an 8-bit bidirectional
data bus.
o The 8-bit bidirectional data bus allows the transfer of data either from
memory to CPU during a read operation or from CPU to memory during
a write operation.
o The read and write inputs specify the memory operation, and the two chip
select (CS) control inputs are for enabling the chip only when the
microprocessor selects it.
o The bidirectional data bus is constructed using three-state buffers.
o The output generated by three-state buffers can be placed in one of the
three possible states which include a signal equivalent to logic 1, a signal
equal to logic 0, or a high-impedance state.

Note: The logic 1 and 0 are standard digital signals whereas the high-impedance state
behaves like an open circuit, which means that the output does not carry a signal and has
no logic significance.

The following function table specifies the operations of a 128 * 8 RAM chip.

From the functional table, we can conclude that the unit is in operation only when
CS1 = 1 and CS2 = 0. The bar on top of the second select variable indicates that
this input is enabled when it is equal to 0.
ROM integrated circuit
The primary component of the main memory is RAM integrated circuit chips, but
a portion of memory may be constructed with ROM chips.

A ROM memory is used for keeping programs and data that are permanently
resident in the computer.

Apart from the permanent storage of data, the ROM portion of main memory is
needed for storing an initial program called a bootstrap loader. The primary
function of the bootstrap loader program is to start the computer software
operating when power is turned on.

ROM chips are also available in a variety of sizes and are also used as per the
system requirement. The following block diagram demonstrates the chip
interconnection in a 512 * 8 ROM chip.

o A ROM chip has a similar organization as a RAM chip. However, a ROM

can only perform read operation; the data bus can only operate in an output
mode.
o The 9-bit address lines in the ROM chip specify any one of the 512 bytes
stored in it.
o The value for chip select 1 and chip select 2 must be 1 and 0 for the unit to
operate. Otherwise, the data bus is said to be in a high-impedance state.
Cache Memory
The data or contents of the main memory that are used frequently by CPU are
stored in the cache memory so that the processor can easily access that data in a
shorter time. Whenever the CPU needs to access memory, it first checks the cache
memory. If the data is not found in cache memory, then the CPU moves into the
main memory.

Cache memory is placed between the CPU and the main memory. The block
diagram for a cache memory can be represented as:

The cache is the fastest component in the memory hierarchy and approaches the
speed of CPU components.

Cache memory is organised as distinct set of blocks where each set contains a
small fixed number of blocks.
As shown in the above sets are represented by the rows. The example contains N
sets and each set contains four blocks. Whenever an access is made to cache, the
cache controller does not search the entire cache in order to look for a match.
Rather, the controller maps the address to a particular set of the cache and
therefore searches only the set for a match.

If a required block is not found in that set, the block is not present in the cache
and cache controller does not search it further. This kind of cache organisation is
called set associative because the cache is divided into distinct sets of blocks. As
each set contains four blocks the cache is said to be four way set associative.

The basic operation of a cache memory is as follows:

o When the CPU needs to access memory, the cache is examined. If the word
is found in the cache, it is read from the fast memory.
 o If the word addressed by the CPU is not found in the cache, the main
memory is accessed to read the word.
o A block of words one just accessed is then transferred from main memory
to cache memory. The block size may vary from one word (the one just
accessed) to about 16 words adjacent to the one just accessed.
o The performance of the cache memory is frequently measured in terms of
a quantity called hit ratio.
o When the CPU refers to memory and finds the word in cache, it is said to
produce a hit.
o If the word is not found in the cache, it is in main memory and it counts as
a miss.
o The ratio of the number of hits divided by the total CPU references to
memory (hits plus misses) is the hit ratio.

Auxiliary Memory
An Auxiliary memory is known as the lowest-cost, highest-capacity and slowest-
access storage in a computer system. It is where programs and data are kept for
long-term storage or when not in immediate use. The most common examples of
auxiliary memories are magnetic tapes and magnetic disks.

Magnetic Disks
A magnetic disk is a type of memory constructed using a circular plate of metal
or plastic coated with magnetized materials. Usually, both sides of the disks are
used to carry out read/write operations. However, several disks may be stacked
on one spindle with read/write head available on each surface.

The following image shows the structural representation for a magnetic disk.
 o The memory bits are stored in the magnetized surface in spots along the
concentric circles called tracks.
o The concentric circles (tracks) are commonly divided into sections called
sectors.

Magnetic Tape
Magnetic tape is a storage medium that allows data archiving, collection, and
backup for different kinds of data. The magnetic tape is constructed using a
plastic strip coated with a magnetic recording medium.

The bits are recorded as magnetic spots on the tape along several tracks. Usually,
seven or nine bits are recorded simultaneously to form a character together with
a parity bit.

Magnetic tape units can be halted, started to move forward or in reverse, or can
be rewound. However, they cannot be started or stopped fast enough between
individual characters. For this reason, information is recorded in blocks referred
to as records.
 Pipelining
The term Pipelining refers to a technique of decomposing a sequential process
into sub-operations, with each sub-operation being executed in a dedicated
segment that operates concurrently with all other segments.

The most important characteristic of a pipeline technique is that several

computations can be in progress in distinct segments at the same time. The
overlapping of computation is made possible by associating a register with each
segment in the pipeline. The registers provide isolation between each segment so
that each can operate on distinct data simultaneously.

The structure of a pipeline organization can be represented simply by including

an input register for each segment followed by a combinational circuit.

Let us consider an example of combined multiplication and addition operation to

get a better understanding of the pipeline organization.

The combined multiplication and addition operation is done with a stream of

numbers such as:
Ai* Bi + Ci for i = 1, 2, 3, ......., 7

The operation to be performed on the numbers is decomposed into sub-operations

with each sub-operation to be implemented in a segment within a pipeline.

The sub-operations performed in each segment of the pipeline are defined as:
R1 ← Ai, R2 ← Bi Input Ai, and Bi
R3 ← R1 * R2, R4 ← Ci Multiply, and input Ci
R5 ← R3 + R4 Add Ci to product

The following block diagram represents the combined as well as the sub-
operations performed in each segment of the pipeline.
Registers R1, R2, R3, and R4 hold the data and the combinational circuits operate
in a particular segment.

The output generated by the combinational circuit in a given segment is applied

as an input register of the next segment. For instance, from the block diagram, we
can see that the register R3 is used as one of the input registers for the
combinational adder circuit.

In general, the pipeline organization is applicable for two areas of computer

design which includes:

1. Arithmetic Pipeline
2. Instruction Pipeline

We will discuss both of them in our later sections.

Arithmetic Pipeline
Arithmetic Pipelines are mostly used in high-speed computers. They are used to
implement floating-point operations, multiplication of fixed-point numbers, and
similar computations encountered in scientific problems.

To understand the concepts of arithmetic pipeline in a more convenient way, let

us consider an example of a pipeline unit for floating-point addition and
subtraction.

The inputs to the floating-point adder pipeline are two normalized floating-point
binary numbers defined as:
X = A * 2a = 0.9504 * 103
Y = B * 2b = 0.8200 * 102

Where A and B are two fractions that represent the mantissa and a and b are the
exponents.

The combined operation of floating-point addition and subtraction is divided into

four segments. Each segment contains the corresponding suboperation to be
performed in the given pipeline. The suboperations that are shown in the four
segments are:

1. Compare the exponents by subtraction.

2. Align the mantissas.
3. Add or subtract the mantissas.
4. Normalize the result.

We will discuss each suboperation in a more detailed manner later in this section.

The following block diagram represents the suboperations performed in each

segment of the pipeline.
Note: Registers are placed after each suboperation to store the intermediate results.
1. Compare exponents by subtraction:
The exponents are compared by subtracting them to determine their difference.
The larger exponent is chosen as the exponent of the result.
The difference of the exponents, i.e., 3 - 2 = 1 determines how many times the
mantissa associated with the smaller exponent must be shifted to the right.

2. Align the mantissas:

The mantissa associated with the smaller exponent is shifted according to the
difference of exponents determined in segment one.
X = 0.9504 * 103
Y = 0.08200 * 103

3. Add mantissas:
The two mantissas are added in segment three.
Z = X + Y = 1.0324 * 103

4. Normalize the result:

After normalization, the result is written as:
Z = 0.1324 * 104

Instruction Pipeline
Pipeline processing can occur not only in the data stream but in the instruction
stream as well.

Most of the digital computers with complex instructions require instruction

pipeline to carry out operations like fetch, decode and execute instructions.

In general, the computer needs to process each instruction with the following
sequence of steps.

1. Fetch instruction from memory.

2. Decode the instruction.
3. Calculate the effective address.
4. Fetch the operands from memory.
5. Execute the instruction.
6. Store the result in the proper place.

Each step is executed in a particular segment, and there are times when different
segments may take different times to operate on the incoming information.
Moreover, there are times when two or more segments may require memory
access at the same time, causing one segment to wait until another is finished with
the memory.

The organization of an instruction pipeline will be more efficient if the instruction

cycle is divided into segments of equal duration. One of the most common
examples of this type of organization is a Four-segment instruction pipeline.

A four-segment instruction pipeline combines two or more different segments

and makes it as a single one. For instance, the decoding of the instruction can be
combined with the calculation of the effective address into one segment.

The following block diagram shows a typical example of a four-segment

instruction pipeline. The instruction cycle is completed in four segments.
Segment 1:

The instruction fetch segment can be implemented using first in, first out (FIFO)
buffer.

Segment 2:

The instruction fetched from memory is decoded in the second segment, and
eventually, the effective address is calculated in a separate arithmetic circuit.

Segment 3:

An operand from memory is fetched in the third segment.

Segment 4:

The instructions are finally executed in the last segment of the pipeline
organization.