Design Implementation

Array Multiplier
Full Adder

module fulladder(
input a,
input b,
input cin,
output s,
output cout
);
//Assigning sum and carryout
assign s=a+b+cin;
assign cout=(a&b)|(a&cin)|(b&cin);

endmodule

16 Bit Adder

module fulladder16bit(
input [15:0] a,
input [15:0] b,
output [15:0] s,
output cout
);

// Declaring Signal
wire [14:0] c;
// Structural model of 16 bit adder
fulladder A01 (.a(a[0]),.b(b[0]),.cin(1'b0),.s(s[0]),.cout(c[0]));
fulladder A02 (.a(a[1]),.b(b[1]),.cin(c[0]),.s(s[1]),.cout(c[1]));
fulladder A03 (.a(a[2]),.b(b[2]),.cin(c[1]),.s(s[2]),.cout(c[2]));
fulladder A04 (.a(a[3]),.b(b[3]),.cin(c[2]),.s(s[3]),.cout(c[3]));
fulladder A05 (.a(a[4]),.b(b[4]),.cin(c[3]),.s(s[4]),.cout(c[4]));
fulladder A06 (.a(a[5]),.b(b[5]),.cin(c[4]),.s(s[5]),.cout(c[5]));
fulladder A07 (.a(a[6]),.b(b[6]),.cin(c[5]),.s(s[6]),.cout(c[6]));
 fulladder A08 (.a(a[7]),.b(b[7]),.cin(c[6]),.s(s[7]),.cout(c[7]));
fulladder A09 (.a(a[8]),.b(b[8]),.cin(c[7]),.s(s[8]),.cout(c[8]));
fulladder A10 (.a(a[9]),.b(b[9]),.cin(c[8]),.s(s[9]),.cout(c[9]));
fulladder A11 (.a(a[10]),.b(b[10]),.cin(c[9]),.s(s[10]),.cout(c[10]));
fulladder A12 (.a(a[11]),.b(b[11]),.cin(c[10]),.s(s[11]),.cout(c[11]));
fulladder A13 (.a(a[12]),.b(b[12]),.cin(c[11]),.s(s[12]),.cout(c[12]));
fulladder A14 (.a(a[13]),.b(b[13]),.cin(c[12]),.s(s[13]),.cout(c[13]));
fulladder A15 (.a(a[14]),.b(b[14]),.cin(c[13]),.s(s[14]),.cout(c[14]));
fulladder A16 (.a(a[15]),.b(b[15]),.cin(c[14]),.s(s[15]),.cout(cout));

endmodule

16 Bit Array Multiplier

module array_multiplier16bit(
input [15:0] a,
input [15:0] b,
output [31:0] m
);

//Declaring signals
wire [15:0] a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15;
wire [15:0] s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14;
wire [14:0] c;
// assigning Partial Product results of inputs
assign a0[15:0]=a[15:0]&{16{b[0]}};
assign a1[15:0]=a[15:0]&{16{b[1]}};
assign a2[15:0]=a[15:0]&{16{b[2]}};
assign a3[15:0]=a[15:0]&{16{b[3]}};
assign a4[15:0]=a[15:0]&{16{b[4]}};
assign a5[15:0]=a[15:0]&{16{b[5]}};
assign a6[15:0]=a[15:0]&{16{b[6]}};
assign a7[15:0]=a[15:0]&{16{b[7]}};
assign a8[15:0]=a[15:0]&{16{b[8]}};
assign a9[15:0]=a[15:0]&{16{b[9]}};
assign a10[15:0]=a[15:0]&{16{b[10]}};
assign a11[15:0]=a[15:0]&{16{b[11]}};
assign a12[15:0]=a[15:0]&{16{b[12]}};
assign a13[15:0]=a[15:0]&{16{b[13]}};
assign a14[15:0]=a[15:0]&{16{b[14]}};
 assign a15[15:0]=a[15:0]&{16{b[15]}};
// Structural model of 16 BIT ARRAY MULTIPLIER
// First layer of 16 bit adder
fulladder16bit A01 (.a({1'b0,a0[15:1]}),.b(a1[15:0]),.s(s0[15:0]),.cout(c[0]));
// Second layer of 16 bit adder
fulladder16bit A02 (.a({c[0],s0[15:1]}),.b(a2[15:0]),.s(s1[15:0]),.cout(c[1]));
// Third layer of 16 bit adder
fulladder16bit A03 (.a({c[1],s1[15:1]}),.b(a3[15:0]),.s(s2[15:0]),.cout(c[2]));
// Fourth layer of 16 bit adder
fulladder16bit A04 (.a({c[2],s2[15:1]}),.b(a4[15:0]),.s(s3[15:0]),.cout(c[3]));
// Fifth layer of 16 bit adder
fulladder16bit A05 (.a({c[3],s3[15:1]}),.b(a5[15:0]),.s(s4[15:0]),.cout(c[4]));
// Sixth layer of 16 bit adder
fulladder16bit A06 (.a({c[4],s4[15:1]}),.b(a6[15:0]),.s(s5[15:0]),.cout(c[5]));
// Seventh layer of 16 bit adder
fulladder16bit A07 (.a({c[5],s5[15:1]}),.b(a7[15:0]),.s(s6[15:0]),.cout(c[6]));
// Eight layer of 16 bit adder
fulladder16bit A08 (.a({c[6],s6[15:1]}),.b(a8[15:0]),.s(s7[15:0]),.cout(c[7]));
// Ninth layer of 16 bit adder
fulladder16bit A09 (.a({c[7],s7[15:1]}),.b(a9[15:0]),.s(s8[15:0]),.cout(c[8]));
// Tenth layer of 16 bit adder
fulladder16bit A10 (.a({c[8],s8[15:1]}),.b(a10[15:0]),.s(s9[15:0]),.cout(c[9]));
// Eleventh layer of 16 bit adder
fulladder16bit A11 (.a({c[9],s9[15:1]}),.b(a11[15:0]),.s(s10[15:0]),.cout(c[10]));
// Twelfth layer of 16 bit adder
fulladder16bit A12 (.a({c[10],s10[15:1]}),.b(a12[15:0]),.s(s11[15:0]),.cout(c[11]));
// Thirteen layer of 16 bit adder
fulladder16bit A13 (.a({c[11],s11[15:1]}),.b(a13[15:0]),.s(s12[15:0]),.cout(c[12]));
// Fourteen layer of 16 bit adder
fulladder16bit A14 (.a({c[12],s12[15:1]}),.b(a14[15:0]),.s(s13[15:0]),.cout(c[13]));
// Fifteen layer of 16 bit adder
fulladder16bit A15 (.a({c[13],s13[15:1]}),.b(a15[15:0]),.s(s14[15:0]),.cout(c[14]));
//assigning to the multiplier output
assign m[31:15]={c[14],s14[15:0]};
assign m[14:8]={s13[0],s12[0],s11[0],s10[0],s9[0],s8[0],s7[0]};
assign m[7:0]={s6[0],s5[0],s4[0],s3[0],s2[0],s1[0],s0[0],a0[0]};

endmodule
RTL Schematic of 16 Bit Array Multiplier
Vedic Multiplier
Full Adder

module fulladder(
input a,
input b,
input cin,
output s,
output cout
);

//Assigning sum and carry out

assign s=a+b+cin;
assign cout=(a&b)|(a&cin)|(b&cin);

endmodule

2 Bit Vedic Multiplier

module vedic_multiplier2bit(
input [1:0] a,
input [1:0] b,
output [3:0] m
);

//Declaring Signals
wire [3:0] c;
wire [1:0] d;
wire [1:0] e;
// assigning Partial product results of inputs
assign c[0]=a[0]&b[0];
assign c[1]=a[0]&b[1];
assign c[2]=a[1]&b[0];
assign c[3]=a[1]&b[1];
assign d[0]=c[1]^c[2];
assign d[1]=c[1]&c[2];
assign e[0]=d[1]^c[3];
assign e[1]=d[1]&c[3];
 //assigning to the multiplier output
assign m[3:0]={e[1:0],d[0],c[0]};

endmodule

4 Bit Adder

module vedic_adder4bit(
input [3:0] a,
input [3:0] b,
output [3:0] s,
output cout
);

//Declaring signals
wire [2:0] c;
// Structural model of 4 bit adder
fulladder A01 (.a(a[0]),.b(b[0]),.cin(1'b0),.s(s[0]),.cout(c[0]));
fulladder A02 (.a(a[1]),.b(b[1]),.cin(c[0]),.s(s[1]),.cout(c[1]));
fulladder A03 (.a(a[2]),.b(b[2]),.cin(c[1]),.s(s[2]),.cout(c[2]));
fulladder A04 (.a(a[3]),.b(b[3]),.cin(c[2]),.s(s[3]),.cout(cout));

endmodule

4 Bit Vedic Multiplier

module vedic_multiplier4bit(
input [3:0] a,
input [3:0] b,
output [7:0] m
);

// Declaring signals
wire [3:0] w1,w2,w3,w4,w5,w6,w7;
wire c0,c1,c2;
// Structural model of 4 BIT VEDIC MULTIPLIER
//first layer 2 bit multipliers
vedic_multiplier2bit M1 (.a(a[1:0]),.b(b[1:0]),.m(w1[3:0]));
vedic_multiplier2bit M2 (.a(a[1:0]),.b(b[3:2]),.m(w2[3:0]));
vedic_multiplier2bit M3 (.a(a[3:2]),.b(b[1:0]),.m(w3[3:0]));
 vedic_multiplier2bit M4 (.a(a[3:2]),.b(b[3:2]),.m(w4[3:0]));
// second layer of 4 bit adder
vedic_adder4bit A1 (.a(w2[3:0]),.b(w3[3:0]),.s(w5[3:0]),.c(c0));
// third layer of 4 bit adder
vedic_adder4bit A2 (.a({2'b00,w1[3:2]}),.b(w5[3:0]),.s(w6[3:0]),.c(c1));
// fourth layer of 4 bit adder
vedic_adder4bit A3 (.a({
({1'b0,c0}+{1'b0,c1}),w6[3:2]}),.b(w4[3:0]),.s(w7[3:0]),.c(c2));
//assigning to the multiplier output
assign m={w7[3:0],w6[1:0],w1[1:0]};

endmodule

8 Bit Adder

module vedic_adder8bit(
input [7:0] a,
input [7:0] b,
output [7:0] s,
output cout
);

// Declaring signal
wire [6:0] c;
//Structural model of 8 bit adder
fulladder A01 (.a(a[0]),.b(b[0]),.cin(1'b0),.s(s[0]),.cout(c[0]));
fulladder A02 (.a(a[1]),.b(b[1]),.cin(c[0]),.s(s[1]),.cout(c[1]));
fulladder A03 (.a(a[2]),.b(b[2]),.cin(c[1]),.s(s[2]),.cout(c[2]));
fulladder A04 (.a(a[3]),.b(b[3]),.cin(c[2]),.s(s[3]),.cout(c[3]));
fulladder A05 (.a(a[4]),.b(b[4]),.cin(c[3]),.s(s[4]),.cout(c[4]));
fulladder A06 (.a(a[5]),.b(b[5]),.cin(c[4]),.s(s[5]),.cout(c[5]));
fulladder A07 (.a(a[6]),.b(b[6]),.cin(c[5]),.s(s[6]),.cout(c[6]));
fulladder A08 (.a(a[7]),.b(b[7]),.cin(c[6]),.s(s[7]),.cout(cout));

endmodule
8 Bit Vedic Multiplier

module vedic_multiplier8bit(
input [7:0] a,
input [7:0] b,
output [15:0] m
);

// Declaring signals
wire [7:0] w1,w2,w3,w4,w5,w6,w7;
wire c0,c1,c2;
// Structural model of 8 BIT VEDIC MULTIPLIER
//first layer 4 bit multipliers
vedic_multiplier4bit M1 (.a(a[3:0]),.b(b[3:0]),.m(w1[7:0]));
vedic_multiplier4bit M2 (.a(a[3:0]),.b(b[7:4]),.m(w2[7:0]));
vedic_multiplier4bit M3 (.a(a[7:4]),.b(b[3:0]),.m(w3[7:0]));
vedic_multiplier4bit M4 (.a(a[7:4]),.b(b[7:4]),.m(w4[7:0]));
// second layer of 8 bit adder
vedic_adder8bit A1 (.a(w2[7:0]),.b(w3[7:0]),.s(w5[7:0]),.c(c0));
// third layer of 8 bit adder
vedic_adder8bit A2 (.a({4'b0000,w1[7:4]}),.b(w5[7:0]),.s(w6[7:0]),.c(c1));
// fourth layer of 8 bit adder
vedic_adder8bit A3 (.a({({3'b0,c0}+{3'b0,c1}),w6[7:4]}),.b(w4[7:0]),.s(w7[7:0]),.c(c2));
//assigning to the multiplier output
assign m={w7[7:0],w6[3:0],w1[3:0]};

endmodule

16 Bit Adder

module vedic_adder16bit(
input [15:0] a,
input [15:0] b,
output [15:0] s,
output cout
);

// Declaring signals
wire [14:0] c;
// Structural model of 16 bit adder
 fulladder A01 (.a(a[0]),.b(b[0]),.cin(1'b0),.s(s[0]),.cout(c[0]));
fulladder A02 (.a(a[1]),.b(b[1]),.cin(c[0]),.s(s[1]),.cout(c[1]));
fulladder A03 (.a(a[2]),.b(b[2]),.cin(c[1]),.s(s[2]),.cout(c[2]));
fulladder A04 (.a(a[3]),.b(b[3]),.cin(c[2]),.s(s[3]),.cout(c[3]));
fulladder A05 (.a(a[4]),.b(b[4]),.cin(c[3]),.s(s[4]),.cout(c[4]));
fulladder A06 (.a(a[5]),.b(b[5]),.cin(c[4]),.s(s[5]),.cout(c[5]));
fulladder A07 (.a(a[6]),.b(b[6]),.cin(c[5]),.s(s[6]),.cout(c[6]));
fulladder A08 (.a(a[7]),.b(b[7]),.cin(c[6]),.s(s[7]),.cout(c[7]));
fulladder A09 (.a(a[8]),.b(b[8]),.cin(c[7]),.s(s[8]),.cout(c[8]));
fulladder A10 (.a(a[9]),.b(b[9]),.cin(c[8]),.s(s[9]),.cout(c[9]));
fulladder A11 (.a(a[10]),.b(b[10]),.cin(c[9]),.s(s[10]),.cout(c[10]));
fulladder A12 (.a(a[11]),.b(b[11]),.cin(c[10]),.s(s[11]),.cout(c[11]));
fulladder A13 (.a(a[12]),.b(b[12]),.cin(c[11]),.s(s[12]),.cout(c[12]));
fulladder A14 (.a(a[13]),.b(b[13]),.cin(c[12]),.s(s[13]),.cout(c[13]));
fulladder A15 (.a(a[14]),.b(b[14]),.cin(c[13]),.s(s[14]),.cout(c[14]));
fulladder A16 (.a(a[15]),.b(b[15]),.cin(c[14]),.s(s[15]),.cout(cout));

endmodule

16 Bit Vedic Multiplier

module vedic_multiplier16bit(
input [15:0] a,
input [15:0] b,
output [31:0] m
);

// Declaring signals
wire [15:0] w1,w2,w3,w4,w5,w6,w7;
wire c0,c1,c2;
//Structural model of 16 BIT VEDIC MULTIPLIER
//first layer 8 bit multipliers
vedic_multiplier8bit M1 (.a(a[7:0]),.b(b[7:0]),.m(w1[15:0]));
vedic_multiplier8bit M2 (.a(a[7:0]),.b(b[15:8]),.m(w2[15:0]));
vedic_multiplier8bit M3 (.a(a[15:8]),.b(b[7:0]),.m(w3[15:0]));
vedic_multiplier8bit M4 (.a(a[15:8]),.b(b[15:8]),.m(w4[15:0]));
// second layer of 16 bit adder
vedic_adder16bit A1 (.a(w2[15:0]),.b(w3[15:0]),.s(w5[15:0]),.c(c0));
// third layer of 16 bit adder
vedic_adder16bit A2 (.a({8'b0,w1[15:8]}),.b(w5[15:0]),.s(w6[15:0]),.c(c1));
 // fourth layer of 16 bit adder
vedic_adder16bit A3
(.a({({7'b0,c0}+{7'b0,c1}),w6[15:8]}),.b(w4[15:0]),.s(w7[15:0]),.c(c2));
//assigning to the multiplier output
assign m[31:0] = {w7[15:0],w6[7:0],w1[7:0]};

endmodule

RTL Schematic of 16 Bit Vedic Multiplier

Vedic Multiplier Using Reversible Gates
Reversible Gates

BME Gate

module bmegate(
input a,
input b,
input c,
input d,
output p,
output q,
output r,
output s
);

//Assigning outputs with the combination of inputs

assign p=a;
assign q=(a&b)^c;
assign r=(a&d)^c;
assign s=(~a&b)^c^d;

endmodule

PERES Gate

module peresgate(
input a,
input b,
input c,
output p,
output q,
output r
);

//Assigning outputs with the combination of inputs

 assign p=a;
assign q=a^b;
assign r=(a&b)^c;

endmodule

FEYNMENN Gate

module fenmenngate(
input a,
input b,
output p,
output q
);

//Assigning outputs with the combination of inputs

assign p=a;
assign q=a^b;

endmodule

DKG Gate

module dkggate(
input a,
input b,
input c,
input d,
input p,
input q,
input r,
input s
);

//Assigning outputs with the combination of inputs

assign p=b;
assign q=(~a&c)|(a&~d);
assign r=(a^b)&(c^d)^(c&d);
assign s=b^c^d;
endmodule

4 Bit DKG Gate (For easy implementation of adders using Reversible Gates)

module dkg_4(
input [3:0] a,
input [3:0] b,
input d,
output [3:0] s,
output c
);

// Declaring signals
wire [2:0] w;
wire [7:0] g;
// structural model of 4 bit DKG GATE using reversible gate
dkggate M1 (.a(1'b0),.b(a[0]),.c(b[0]),.d(d),.p(g[0]),.q(g[1]),.r(w[0]),.s(s[0]));
dkggate M2 (.a(1'b0),.b(a[1]),.c(b[1]),.d(w[0]),.p(g[2]),.q(g[3]),.r(w[1]),.s(s[1]));
dkggate M3 (.a(1'b0),.b(a[2]),.c(b[2]),.d(w[1]),.p(g[4]),.q(g[5]),.r(w[2]),.s(s[2]));
dkggate M4 (.a(1'b0),.b(a[3]),.c(b[3]),.d(w[2]),.p(g[6]),.q(g[7]),.r(c),.s(s[3]));

Endmodule

Implementation of Vedic Multiplier Using Reversible Gates

2 Bit Vedic Multiplier Using Reversible Gates

module reversible_multiplier2bit(
input [1:0] a,
input [1:0] b,
output [3:0] m
);

//Declaring signals
wire w1,w2,w3,w4;
wire [4:0] g;
//structural model of 2 bit multiplier using reversible gates
bmegate M1 (.a(a[0]),.b(b[0]),.c(1'b0),.d(b[1]),.p(g[0]),.q(m[0]),.r(w1),.s(g[1]));
 bmegate M2 (.a(a[1]),.b(b[0]),.c(1'b0),.d(b[1]),.p(g[2]),.q(w2),.r(w3),.s(g[3]));
peresgate M3 (.a(w1),.b(w2),.c(1'b0),.p(g[4]),.q(m[1]),.r(w4));
fenmenngate M4 (.a(w4),.b(w3),.p(m[3]),.q(m[2]));

endmodule

4 Bit Adder Using Reversible Gates

module reversible_adder4bit(
input [3:0] a,
input [3:0] b,
output [3:0] s,
output c
);

// Structural model of 4 bit adder using reversible gate

dkg_4 A1 (.a(a),.b(b),.d(1'b0),.s(s),.c(c));

endmodule

4 Bit Vedic Multiplier Using Reversible Gates

module reversible_multiplier4bit(
input [3:0] a,
input [3:0] b,
output [7:0] m
);

// Declaring signals
wire [3:0] w1,w2,w3,w4,w5,w6,w7;
wire c0,c1,c2;
// Structural model of 4 BIT VEDIC MULTIPLIER USING REVERSIBLE GATES
//first layer 2 bit multipliers
reversible_multiplier2bit M1 (.a(a[1:0]),.b(b[1:0]),.m(w1[3:0]));
reversible_multiplier2bit M2 (.a(a[1:0]),.b(b[3:2]),.m(w2[3:0]));
reversible_multiplier2bit M3 (.a(a[3:2]),.b(b[1:0]),.m(w3[3:0]));
reversible_multiplier2bit M4 (.a(a[3:2]),.b(b[3:2]),.m(w4[3:0]));
// second layer of 4 bit adder
reversible_adder4bit A1 (.a(w2[3:0]),.b(w3[3:0]),.s(w5[3:0]),.c(c0));
// third layer of 4 bit adder
 reversible_adder4bit A2 (.a({2'b00,w1[3:2]}),.b(w5[3:0]),.s(w6[3:0]),.c(c1));
// fourth layer of 4 bit adder
reversible_adder4bit A3 (.a({
({1'b0,c0}+{1'b0,c1}),w6[3:2]}),.b(w4[3:0]),.s(w7[3:0]),.c(c2));
//assigning to the multiplier output
assign m={w7[3:0],w6[1:0],w1[1:0]};

endmodule

8 Bit Adder Using Reversible Gates

module reversible_adder8bit(
input [7:0] a,
input [7:0] b,
output [7:0] s,
output c
);
// Declaring signals
wire e;
// structural model of 8 bit adder using reversible gate
dkg_4 A1 (.a(a[3:0]),.b(b[3:0]),.d(1'b0),.s(s[3:0]),.c(e));
dkg_4 A2 (.a(a[7:4]),.b(b[7:4]),.d(e),.s(s[7:4]),.c(c));

endmodule

8 Bit Vedic Multiplier Using Reversible Gates

module reversible_multiplier8bit(
input [7:0] a,
input [7:0] b,
output [15:0] m
);

// Declaring signals
wire [7:0] w1,w2,w3,w4,w5,w6,w7;
wire c0,c1,c2;
//Structural model of 8 BIT MULTIPLIER USING REVERSIBLE GATES
//first layer 4 bit multipliers
reversible_multiplier4bit M1 (.a(a[3:0]),.b(b[3:0]),.m(w1[7:0]));
reversible_multiplier4bit M2 (.a(a[3:0]),.b(b[7:4]),.m(w2[7:0]));
 reversible_multiplier4bit M3 (.a(a[7:4]),.b(b[3:0]),.m(w3[7:0]));
reversible_multiplier4bit M4 (.a(a[7:4]),.b(b[7:4]),.m(w4[7:0]));
// second layer of 8 bit adder
reversible_adder8bit A1 (.a(w2[7:0]),.b(w3[7:0]),.s(w5[7:0]),.c(c0));
// third layer of 8 bit adder
reversible_adder8bit A2 (.a({4'b0,w1[7:4]}),.b(w5[7:0]),.s(w6[7:0]),.c(c1));
// fourth layer of 8 bit adder
reversible_adder8bit A3
(.a({({3'b0,c0}+{3'b0,c1}),w6[7:4]}),.b(w4[7:0]),.s(w7[7:0]),.c(c2));
//assigning to the multiplier output
assign m={w7[7:0],w6[3:0],w1[3:0]};

endmodule

16 Bit Adder Using Reversible Gates

module reversible_adder16bit(
input [15:0] a,
input [15:0] b,
output [15:0] s,
output c
);

// Declaring signals
wire e,f,g;
// Structural model of 16 bit adder using reversible gates
dkg_4 A1 (.a(a[3:0]),.b(b[3:0]),.d(1'b0),.s(s[3:0]),.c(e));
dkg_4 A2 (.a(a[7:4]),.b(b[7:4]),.d(e),.s(s[7:4]),.c(f));
dkg_4 A3 (.a(a[11:8]),.b(b[11:8]),.d(f),.s(s[11:8]),.c(g));
dkg_4 A4 (.a(a[15:12]),.b(b[15:12]),.d(g),.s(s[15:12]),.c(c));

endmodule

16 Bit Vedic Multiplier Using Reversible Gates

module reversible_vedic_multiplier16bit(
input [15:0] a,
input [15:0] b,
output [31:0] m
);
 // Declaring signals
wire [15:0] w1,w2,w3,w4,w5,w6,w7;
wire c0,c1,c2;
//Structural model of 16 BIT MULTIPLIER USING REVERSIBLE GATES
//first layer 8 bit multipliers
reversible_multiplier8bit M1 (.a(a[7:0]),.b(b[7:0]),.m(w1[15:0]));
reversible_multiplier8bit M2 (.a(a[7:0]),.b(b[15:8]),.m(w2[15:0]));
reversible_multiplier8bit M3 (.a(a[15:8]),.b(b[7:0]),.m(w3[15:0]));
reversible_multiplier8bit M4 (.a(a[15:8]),.b(b[15:8]),.m(w4[15:0]));
// second layer of 16 bit adder
reversible_adder16bit A1 (.a(w2[15:0]),.b(w3[15:0]),.s(w5[15:0]),.c(c0));
// third layer of 16 bit adder
reversible_adder16bit A2 (.a({8'b0,w1[15:8]}),.b(w5[15:0]),.s(w6[15:0]),.c(c1));
// fourth layer of 16 bit adder
reversible_adder16bit A3
(.a({({7'b0,c0}+{7'b0,c1}),w6[15:8]}),.b(w4[15:0]),.s(w7[15:0]),.c(c2));
//assigning to the multiplier output
assign m[31:0] = {w7[15:0],w6[7:0],w1[7:0]};

endmodule
RTL Schematic of 16 Bit Vedic Multiplier using Reversible Gates