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712 Chap. 13 Output Stages and Power Amplifiers

Many other classes of PAs have been invented and used in various applications. Examples
include classes C, D, E, and F. The reader is referred to more advanced texts [1].

13.10 Chapter Summary

 Power amplifiers deliver high power levels and large signal swings to relatively low load
impedances.
 Both the distortion and efficiency of power amplifiers are critical parameters.
 While providing a low small-signal output impedance, emitter followers operate poorly under
large-signal conditions.
 A push-pull stage consists of an npn follower and a pnp follower. Each device conducts for
about half of the input cycle, improving the efficiency.
 A simple push-pull stage suffers from a dead zone, across which the neither transistor con-
ducts and the small-signal gain falls to zero.
 The crossover distortion resulting from the dead zone can be reduced by biasing the push-pull
transistors for a small quiescent current.
 With two diodes placed between the bases of the push-pull transistors and a CE amplifier
preceding this stage, the circuit can provide a high output power with moderate distortion.
 The output pnp transistors is sometimes replaced with a composite pnp-npn structure that
provides a higher current gain.
 In low-distortion applications, the output stage may be embedded in a negative feedback loop
to suppress the nonlinearity.
 A push-pull stage operating at high temperatures may suffer from thermal runaway, whereby
the elevated temperatures allow the output transistors to draw higher currents, which in turn
makes them dissipate even more.
 The power efficiency of emitter followers rarely reaches 25%, whereas it can approach 79%
for push-pull stages.
 Power amplifiers can operate in different classes depending on across what fraction of the
input cycle the transistor conducts. These classes include class A, class B, and class C.

Problems
Unless otherwise stated, assume VCC = +5 V, VEE = ,5V, VBE;on = 0:8 V,
IS = 6  10,17 ; VA = 1; RL = 8 , and  1 in the following problems.
1. consider the emitter follower shown in Fig. 13.30. We wish to deliver a power of 0.5 W to
RL = 8 .
VCC
V in Q1
Vout
I1 RL
VEE
Figure 13.30

(a) Determine I1 for a small-signal voltage gain of 0.8.

(b) Writing gm = IC =VT , calculate the voltage gain as Vin reaches its positive peak value.
The change in voltage gain represents nonlinearity.
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Sec. 13.10 Chapter Summary 713

2. For the emitter follower of Fig. 13.30, we can express the voltage gain as

Av = I RIC R+L V : (13.67)

C L T
Recall from Section 13.2 that I1  VP =RL , where VP denotes the peak voltage delivered to
RL .
(a) Assuming I1 = VP =RL and VP  VT , determine an expression for AV if the swings
are small.
(b) Now assume the output reaches a peak of VP . Calculate the small-signal voltage gain in
this region and obtain the change with respect to the result in part (a).
3. A student designs the emitter follower of Fig. 13.30 for a small-signal voltage gain of 0.7
and a load resistance of 4 . For a sinusoidal input, estimate the largest average power that
can be delivered to the load without turning Q1 off.
4. Suppose the follower of Fig. 13.30 is designed for a small-signal voltage gain of Av . Deter-
mine the maximum power that can be delivered to the load without turning Q1 off.
5. Due to a manufacturing error, the load of an emitter follower is tied between the output and
VCC (Fig. 13.31). Assume IS1 = 5  10,17 A, RL = 8 and I1 = 20 mA.
VCC

V in Q1 RL
Vout
I1
VEE
Figure 13.31

(a) Calculate the bias current of Q1 for Vin = 0.

(b) For what value of Vin does Q1 carry only 1% of I1 ?
6. The emitter follower of Fig. 13.30 senses a sinusoidal input with a peak amplitude of 1 V.
Assume IS 1 = 6  10,17 A, RL = 8 and I1 = 25 mA.
(a) Calculate VBE for Vin = +1 V and Vin = ,1 V. (This change is a measure of the
nonlinearity.)
(b) Noting that Vout = Vin , VBE , sketch the output waveform.
7. In the circuit of Problem 6, determine the maximum input swing for which VBE changes by
less than 10 mV from the positive peak to the negative peak. Determine the ratio of
VBE
and peak-to-peak output swing as a measure of the nonlinearity.
8. For the push-pull stage of Fig. 13.3(a), sketch the base current of Q1 as a function of Vin .
9. Consider the push-pull stage depicted in Fig. 13.32, where a current source, I1 , is tied from
the output node to ground.

VCC
Q1

V in Vout

Q2 I 1 RL
VEE
Figure 13.32
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714 Chap. 13 Output Stages and Power Amplifiers

(a) Suppose Vin = 0. Determine a relationship between I1 and RL to guarantee that Q1 is

on, i.e., VBE 1  800 mV.
(b) With the condition obtained in (a), calculate the input voltage at which Q2 turns on, i.e.,
VBE2  800 mV.
10. Explain how I1 in Fig. 13.32 alters the input/output characteristic and the dead zone.
11. The circuit shown in Fig. 13.33 precedes the output npn device with an emitter follower.
Sketch the input/output characteristic and estimate the width of the dead zone.
VCC
VCC
V in Q3
Q1
I1
VEE Vout

RL
Q2

VEE
Figure 13.33

12. Repeat Problem 11 for the stage depicted in Fig. 13.34.

VCC

Q1

VCC
Vout

RL
Q2
V in Q3 VEE
VEE
Figure 13.34

13. Figure 13.35 a CMOS realization of the push-pull stage.

VCC

M1

V in Vout

RL
M2

VEE
Figure 13.35

(a) Sketch the input/output characteristic of the circuit.

(b) Determine the small-signal voltage gain for the positive and negative inputs outside the
dead zone.
14. A large sinusoidal input is applied to the circuit of Fig. 13.33. Sketch the output waveform.
15. Repeat Problem 14 for the circuit of Fig. 13.34.
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Sec. 13.10 Chapter Summary 715

16. Consider the push-pull stage illustrated in Fig. 13.36, where VB  VBE (rather than 2VBE ).
VCC

Q1

VB
Vout

V in RL
Q2

VEE
Figure 13.36

(a) Sketch the input/output characteristic.

(b) Sketch the output waveform for a sinusoidal input.
17. In the push-pull stage of Fig. 13.36, IS 1 = 5  10,17 A and IS 2 = 8  10,17 A. Calculate
the value of VB so as to establish a bias current of 5 mA in Q1 and Q2 (for Vout = 0).
18. Suppose the design in Problem 17 operates with a peak input swing of 2 V and RL = 8 .
(a) Calculate the small-signal voltage gain for Vout  0.
(b) Use the gain obtained in (a) to estimate the output voltage swing.
(c) Estimate the peak collector current of Q1 assuming that Q2 still carries 5 mA.
19. The stage of Fig. 13.36 is designed with VB  2VBE to suppress crossover distortion. Sketch
the collector currents of Q1 and Q2 as a function of Vin .
20. Consider the circuit shown in Fig. 13.37, where VB is placed in series with the emitter of
Q1 . Sketch the input/output characteristic.
VCC

Q1

VB
V in Vout

RL
Q2

VEE
Figure 13.37

21. In the circuit of Fig. 13.11(b), we have VBE 1 + jVBE 2 j = VD1 + VD2 . Under what condition
can we write IC 1 IC 2 = ID1 ID2 ?
22. The circuit of Fig. 13.11(b) is designed with I1 = 1 mA and IS;Q1 = IS;Q2 = 16IS;D1 =
16IS;D2. Calculate the bias current of Q1 and Q2 (for Vout = 0). (Hint: VBE1 + jVBE2 j =
VD1 + VD2 .)
23. The stage of Fig. 13.11(b) must be designed for a bias current of 5 mA in Q1 and Q2 (for
Vout = 0). If IS;Q1 = IS;Q2 = 8IS;D1 = 8IS;D2 , determine the required value of I1 . (Hint:
VBE1 + jVBE2 j = VD1 + VD2 .)
24. In the output stage of Fig. 13.11(b), I1 = 2 mA, IS;Q1 = 8IS;D1 , and IS;Q2 = 16IS;D2 .
Determine the bias current of Q1 and Q2 (for Vout = 0). (Hint: VBE 1 + jVBE 2 j = VD1 +
VD2 .)
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716 Chap. 13 Output Stages and Power Amplifiers

25. A critical problem in the design of the push-pull stage shown in Fig. 13.11(b) is the tem-
perature difference between the diodes and the output transistors because the latter consume
much greater power and tend to rise to a higher temperature. Noting that VBE 1 + jVBE 2 j =
VD1 + VD2 , explain how a temperature difference introduces an error in the bias currents of
Q1 and Q2 .
26. Determine the small-signal voltage gain of the stage depicted in Fig. 13.38. Assume I1 is an
VCC

I1
Q1
D1
Vout
D2
V in RL
Q2

VEE
Figure 13.38

ideal current source. Neglect the incremental resistance of D1 and D2 .

27. Repeat Problem 26 but do not neglect the incremental resistance of D1 and D2 .
28. The output stage of Fig. 13.38 must achieve a small-signal voltage gain of 0.8. Determine
the required bias current of Q1 and Q2 . Neglect the incremental resistance of D1 and D2 .
29. Compute the small-signal input impedance of the output stage depicted in Fig. 13.38 if the
incremental resistance of D1 and D2 is not neglected. From the result, determine the condi-
tion under which this resistance is neglected.
30. The stage of Fig. 13.15(b) is designed with a bias current of 1 mA in Q3 and Q4 and 10
mA in Q1 and Q2 . Assuming 1 = 40, 2 = 20, and RL = 8 , calculate the small-signal
voltage gain if the incremental resistance of D1 and D2 is neglected.
31. Noting that gm1  gm2 in Fig. 13.15(b), prove that Eq. (13.23) reduces to

vout = , 2 1 2 g R :
vin m4 L (13.68)
1+ 2

Interestingly, the gain remains independent of the bias current of Q1 and Q2 .

32. The output stage of Fig. 13.15(b) must provide a small-signal voltage gain of 4. Assuming
1 = 40, 2 = 20, and RL = 8 , determine the required bias current of Q3 and Q4 .
Neglect the incremental resistance of D1 and D2 .
33. Consider Eq. (13.27) and note that gm1  gm2 = gm . Prove that the output impedance can
be expressed as

vX  1 + rO3 jjrO4 ( + ):
iX 2gm 2 1 2 1 2 (13.69)

34. The push-pull stage of Fig. 13.15(b) employs a bias current of 1 mA in Q3 and Q4 and 8 mA
in Q1 and Q2 . If Q3 and Q4 suffer from the Early effect and VA3 = 10 V and VA4 = 15 V,
(a) Calculate the small-signal output impedance of the circuit if 1 = 40 and 2 = 20.
(b) Using the result obtained in (a), determine the voltage gain if the stage drives a load
resistance of 8 .
35. The circuit of Fig. 13.15(b) employs a bias current of 1 mA in Q3 and Q4 . If 1 = 40 and
2 = 20, calculate the maximum current that Q1 and Q2 can deliver to the load.
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Sec. 13.10 Chapter Summary 717

36. We wish to deliver a power of 0.5 W to an 8- load. Determine the minimum required bias
current of Q3 and Q4 in Fig. 13.15(b) if 1 = 40 and 2 = 20.
37. The push-pull stage of Fig. 13.15 delivers an average power of 0.5 W to RL = 8 with
VCC = 5 V. Compute the average power dissipated in Q1 .
38. The push-pull stage of Fig. 13.15 incorporates transistors with a maximum power rating of
0.75 W. If VCC = 5 V, what is the largest power that the circuit can deliver to an 8- load?
39. Repeat Problem 38 but assume that VCC can be chosen freely.
40. Consider the composite stage shown in Fig. 13.39. Assume I1 = 5 mA, 1 = 40, and
2 = 50. Calculate the base current of Q2 .

VCC

I1

Vout
V in
Q2
Q1

VEE
Figure 13.39

41. In Problem 40, Vin = 0:5 V. Determine the output voltage if IS 2 = 6  10,17 A.
42. In Problem 40, calculate the input and output impedances of the circuit.
43. In the circuit of Fig. 13.39, determine the value of I1 so as to obtain an output impedance of
1 . Assume 1 = 40 and 2 = 50.
44. An emitter follower delivers a peak swing of 0.5 V to an 8- load with VCC = 2 V. If the
bias current is 70 mA, calculate the power efficiency of the circuit.
45. In a realistic emitter follower design, the peak swing reaches only VCC , VBE . Determine
the efficiency in this case.
46. Repeat Problem 45 for a push-pull stage.
47. A push-pull stage is designed to deliver a peak swing of VP to a load resistance of RL . What
is the efficiency if the circuit delivers a swing of only VP =2?
48. A push-pull stage operating from VCC = 3 V delivers a power of 0.2 W to an 8- load.
Determine the efficiency of the circuit.
Design Problems
49. We wish to design the emitter follower of Fig. 13.30 for a power of 1 W delivered to RL =
8 . Determine I1 and the power rating of Q1 .
50. The emitter follower of Fig. 13.30 must be designed to drive RL = 4 with a voltage gain
of 0.8. Determine I1 , the maximum output voltage swing, and the power rating of Q1 .
51. Consider the push-pull stage shown in Fig. 13.38. Determine the bias current of Q1 and Q2
so as to obtain a voltage gain of 0.6 with RL = 8 . Neglect the incremental resistance of
D1 and D2 .
52. The push-pull stage of Fig. 13.38 must deliver a power of 1 W to RL = 8 . Determine
the minimum allowable supply voltage if jVBE j  0:8 V and the minimum value of I1 if
1 = 40.
53. Suppose the transistors in the stage of Fig. 13.38 exhibit a maximum power rating of 2 W.
What is the largest power that the circuit can deliver to an 8- load?
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718 Chap. 13 Output Stages and Power Amplifiers

54. Repeat Problem 53 for a 4- load.

55. We wish to design the push-pull amplifier for Fig. 13.15(b) for a small-signal voltage gain
of 4 with RL = 8 . If 1 = 40 and 2 = 20, compute the bias current of Q3 and Q4 . What
is the maximum current that Q1 can deliver to RL ?
56. Repeat Problem 55 with RL = 4 and compare the results.
57. The push-pull stage of Fig. 13.15(b) must be designed for an output power of 2 W and
RL = 8 . Assume jVBE j  0:8 V, 1 = 40, and 2 = 20.
(a) Determine the minimum required supply voltage if Q3 and Q4 must remain in the active
region.
(b) Calculate the minimum required bias current of Q3 and Q4 .
(c) Determine the average power dissipated in Q1 while the circuit delivers 2 W to the load.
(d) Compute the overall efficiency of the circuit, taking into account the bias current of Q3
and Q4 .
58. A stereo system requires a push-pull stage similar to that in Fig. 13.15(b) with a voltage gain
of 5 and an output power of 5 W. Assume RL = 4 , 1 = 40, and 2 = 20.
(a) Calculate the bias current of Q3 and Q4 to achieve the required voltage gain. Does the
result satisfy the required output power?
(b) Determine the bias current of Q3 and Q4 to achieve the required output power. What is
the resulting voltage gain?
SPICE Problems
In the following problems, use the MOS device models given in Appendix A. For bipolar
transistors, assume IS;npn = 5  10,16 A, npn = 100, VA;npn = 5 V, IS;pnp = 8  10,16
A, pnp = 50, VA;pnp = 3:5 V. Also, SPICE models the effect of charge storage in the base
by a parameter called F = Cb =gm . Assume F (tf ) = 20 ps.
59. The emitter follower shown in Fig. 13.40 must deliver a power of 50 mW to an 8- speaker
at a frequency of 5 kHz.

VCC = +2.5 V

V in Q1
50 µ F
Vout
Vb 8Ω
Q2

Figure 13.40

(a) Determine the minimum required supply voltage.

(b) Determine the minimum bias current of Q2 .
(c) Using the values obtained in (a) and (b) and a current mirror to bias Q2 , examine the
output waveform. What supply voltage and bias current yield a relatively pure sinusoid?
60. Repeat Problem 59 for the source follower of Fig. 13.41, where (W=L)1,2 =
300 m=0:18 m and compare the results.
61. Plot the input/output characteristic of the circuit shown in Fig. 13.42 for ,2 V < Vin < +2
V. Also, plot the output waveform for an input sinusoid having a peak amplitude of 2 V. How
are these results changed if the load resistance is raised to 16 .
62. In the push-pull stage of Fig. 13.43, Q3 and Q4 operate as diodes.
(a) Select I1 so that the circuit can deliver a peak swing of 1.5 V to the load.
(b) Under these conditions, examine the output waveform and explain what happens.
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References 719

M1 VDD = 1.8 V
V in
50 µ F
M2 Vout
Vb 8Ω

Figure 13.41

VCC = +2.5 V

Q1
V in Vout

8Ω
Q2

VEE = −2.5 V

Figure 13.42
VCC = +2.5 V

I1
Q1
Q3
Vout
Q4
V in 8Ω
Q2

VEE = −2.5 V
Figure 13.43

(c) SPICE allows scaling of bipolar transistors as follows: q1 col bas emi sub
bimod m=16, where m = 16 denotes a 16-fold increase in the size of the transistor (as if
16 unit transistors are placed in parallel). Using m = 16 for Q1 and Q6 , repeat part (b).
63. The feedback push-pull stage of Fig. 13.44 must deliver a peak swing of 1.5 V to an 8-
load. (a) What is the minimum required value of I1 ?
(b) Using an input dc level of ,1:7 V and a scaling factor of 16 for Q1 and Q2 (as in Problem
62), examine the output waveform.

References
1. B. Razavi, RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998.
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720 Chap. 13 Output Stages and Power Amplifiers

VCC = +2.5 V

I1
Q1
Q3
Vout
Q4
8Ω
Q2
V in Q0
1 kΩ −2.5 V

10 k Ω

Figure 13.44