From Transistors to MEMS: Throughput-Aware Power Gating in CMOS Circuits

Michael B. Henry and Leyla Nazhandali

AbstractIn this paper we study the effectiveness of two power gating methods transistor switches and MEMS switches in reducing the power consumption of a design with a certain target throughput. Transistor switches are simple, but have fundamental limitations in their effectiveness. MEMS switches, with zero leakage in the off state, have achieved much focus over the past decade in the RF eld, but have only very recently been explored in the context of power gating. In this paper we study both methods in conjunction with voltage scaling and show that MEMS switches are the superior choice over a wide range of target throughputs, especially low-throughput applications such as wireless sensor networks and biomedical implants. We also show that the architectural choices and operating conditions in a throughput-aware design can be profoundly different when using MEMS switches as opposed to transistor switches. For instance, while transistor switches favor smaller and slower architectures, the MEMS switches favor larger and faster designs when the target throughput is low. Moreover, while the optimal operating voltage of a transistor-switched design resides in the subthreshold region, that of a MEMS-switched design can be above or near the threshold voltage. To prove this, we provide both a mathematical analysis and experimental results from four different FFT architectures.

I. I NTRODUCTION In throughput-aware design, the goal is to optimize the power consumption by selecting the appropriate architecture and operating conditions for the target throughput of an embedded application. Consider, for example, a biomedical implant that must collect and process information once a day. Since the device has all day to process, the target throughput is very low and the performance constraints are very relaxed. The device will spend very little time active and a lot of time idle, so the leakage power of the device is especially important. Common techniques for reducing the leakage of low-throughput devices include choosing a low-complexity design, and reducing the supply voltage. Another popular technique is power gating, whereby the power source to the circuit is shut off by means of a switch. The most common switch is a transistor between the circuit and the power network (header), or more commonly, the ground network (footer). Transistor switches are easy to implement and can yield a large leakage reduction, but there are some drawbacks. First, the transistors themselves leak current, so even when the transistor is switched off, there is still leakage power. Second, all of the current must drain through the transistor switches, and the switches have an effective resistance, so a voltage drop is created across them.

This voltage drop lowers the effective supply voltage of the attached circuit, thereby reducing its speed. A larger transistor creates a smaller voltage drop, but also leaks more; therefore, a tradeoff exists. For low-throughput embedded applications, a very small transistor switch is desirable because speed is not a factor, and leakage power must be kept to a minimum. If the switch is too small, however, a large voltage drop may be created which would render the circuit inoperable. Hence, there is a fundamental limit to the size of the footer. On-die switches that use Microelectromechanical Systems (MEMS) techniques have been proposed, whereby a lever bends from electrostatic, piezoelectric, thermal or magnetic force and forms an ohmic contact. These switches have received much attention in the RF community due to their ideal switching characteristics, including near perfect isolation when off, and almost no resistance when on. These characteristics also make MEMS switches good candidates for power switches. The low resistance when the switch is on means that there is a negligible voltage drop across it and therefore no performance penalty. The complete isolation means that when the circuit is idle and the switch is off, there is no standby leakage power. There are some drawbacks, including packaging and reliability issues, but these have mainly been investigated with respect to RF switches, and further study is needed for digital logic power switches. As for related work, [9] studies the leakage reduction and delay penalty associated with transistor switches in the presence of ultra-low voltage operation, which is relevant to this paper. [6] is the rst and so far only paper that investigates the use of a MEMS switch as a power switch and looks into packaging issues. Our paper builds upon [6] by providing a mathematical and experimental analysis of MEMS switches in the presence of supply voltage scaling. The contributions of this paper are as follows: A mathematical analysis is developed that provides the impact of transistor and MEMS switches on the average power consumption and optimal supply voltage of a circuit for a given target throughput. An experimental validation is presented for four different FFT architectures across a wide range of target throughputs. It is shown that for low throughputs, transistor switches reach a fundamental limit of effectiveness, while MEMS switches continue to be effective and consume many orders of magnitude less power consumption.

978-3-9810801-6-2/DATE10 2010 EDAA

II. P RELIMINARIES This Section provides the preliminaries on common power gating and leakage reduction techniques that are relevant to this paper. We also provide a brief description of the FFT architectures that are used as examples throughout this paper. Transistor Switches: High threshold-voltage footers have commonly been used along with Multi-Threshold CMOS (MTCMOS) processes for power gating. However, it has been shown that high threshold voltages can be effectively mimicked in a single threshold voltage process using nonminimal length transistors [2]. We adopt this technique to be used in this paper. In our experimental analysis, we will use a single footer transistor. In a physical design, parallel and stacked transistors may be used, but simulations with single footer provides a close approximation[9]. MEMS Switches : While there are many varieties of MEMS switches, this paper will focus on the thermally actuated switch presented in [6], due its low activation voltage, 0.5V, relatively low power consumption, 100 W , and small size (10m 30m). The thermal switch operates by using an electric current to heat up and bend a bi-material Ti-SiO2 beam. When bent, a gold contact on the beam contacts two gold contacts on the substrate and closes the switch. With MEMS switches, packaging and reliability are still ongoing issues. For RF switches, a very clean contact is required, which means the ohmic contacts must be a high quality material such as gold or platinum. Also, any contamination might degrade the contact quality, so the switch must be hermetically sealed. This means that MEMS switches are not CMOS compatible and must be manufactured separately and bonded to the CMOS die. While these issues are relevant for RF switches, reliability and quality requirements for power switches have not been determined yet. It may be the case that power gating MEMS switches have more relaxed requirements. Supply Voltage Scaling: Reducing the supply voltage has long been a popular method for reducing the power consumption of digital circuits, due to the fact that reducing the supply voltage decreases the power consumption quadratically while only increasing critical timing linearly. Voltage scaling can be used in conjunction with power gating techniques for some low-throughput applications [8] and we will study the effectiveness of this technique in this paper. Voltage scaling has been traditionally limited to above the threshold voltage, which is the voltage that turns the transistor on. However, in order to achieve maximum power reduction, several subthreshold voltage prototypes have been successfully built and tested [5], [3]. Subthreshold operation has the potential to greatly reduce the idle-state leakage power, so it will be included as a possible option in this paper. FFT Architectures: Four FFT architectures that vary in complexity and speed will be investigated. They each perform a 1024-point radix-2 FFT with 32-bit complex numbers. The low- and medium-complexity implementations use a single real valued 16-bit ALU with a multiplier and an adder, a register bank, and a very simple microprogram to implement the FFT. The low-complexity design uses a 16-bit add/shift

multiplier that takes 16 clock cycles, while the mediumcomplexity design uses a high speed Booth multiplier that takes a single clock cycle. The high-complexity implementation takes advantage of the repetitive nature of the signal ow of an FFT, and contains 9 adders and 3 Booth multipliers. Finally, a parallel architecture with 16 high-complexity cores is implemented. All of the designs are optimally pipelined with respect to energy per FFT[7]. The designs require a memory bank to hold the 1024 input points, and the same memory bank also holds intermediate values and the nal result. A ROM bank is also required to store the constant coefcients (sometimes called twiddle factors) used in the FFT. Data retention is an important concept with power gating, because a powered down memory bank loses its data. As is the case with a lot of signal processing applications, the raw data does not need to be kept after it is processed using the FFT. Therefore, data retention is not necessary. More general purpose architectures, on the other hand, may require a data retention plan.
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Figure 1 shows the total energy per FFT of the four different designs with respect to supply voltage (the designs are running at their respective maximum clock rate). As the complexity of the designs increase, the energy per FFT decreases, mainly due to the fact that the smaller designs must save intermediate operands in registers and have lower activity factor. However, the parallel design is not more energy efcient than its scalar counterpart, because parallelization in general does not decrease the energy per operation or task[7]. III. T HROUGHPUT-AWARE P OWER R EDUCTION The goal of throughput-aware power reduction is to maximize power efciency of a design for a certain target throughput. In this section, we study the effectiveness of using transistor and MEMS switches in conjunction with voltage scaling to achieve this goal. We, rst, pay attention to the fact that voltage scaling and power gating are not two independent knobs for throughput-aware power reduction. For example, if a design at nominal voltage is four times faster than the required throughput, it should spend 75% of the time power gated. If

we use voltage scaling to reduce its speed by half, it should spend 50% of the time power gated. Therefore, depending on the efciency of power gating and the amount of gain from voltage scaling, any of these solutions might be superior. The purpose of this section is to derive mathematical formulas that describes the relationship between switch characteristics, power, supply voltage and target throughput. Let us dene target throughput, RT , as the desired number of tasks performed per second (for example, FFTs per second). Also, let us dene energy, E, as energy per task. Average power consumption, P , can be determined by RT E. For any given design, active energy, EA , leakage power, PL , and maximum throughput, RM , are all dependant on supply voltage and can be considered functions of V . Using these denitions, the average power consumption P of a nonswitched, i.e. not power-gated, circuit with respect to RT and supply voltage V , is dened in (1): P (V, RT ) = RT EA (V ) + PL (V ) (1)

B. MEMS Switch When using MEMS switches, the circuit leaks only when the switch is on. However, when the circuit is on, the MEMS switch consumes additional power, PSW . Equation (1) can be rewritten for MEMS-switched circuits as follows: RT [PL (V ) + PSW ] (4) P (V, RT ) = RT EA (V ) + RM (V ) Rearranging (4) gives (5): P (V, RT ) = RT [EA (V ) + PL (V ) + PSW ] RM (V ) (5)

Let EM IN be the minimum energy of a circuit, across all supply voltages, as shown in (6) and Vopt be the voltage where EM IN is achieved: EM IN = min[EA (V ) +
V

PL (V ) + PSW ] RM (V )

(6)

As long as RM (Vopt ) is equal or more than RT , which holds for lower-throughput applications, (5) becomes: P (RT ) = RT EM IN (7)

It should be noted that with non-switched circuits, as RT approaches 0, the average power consumption approaches PL , meaning the least complex designs would consume the least amount of power. A. Transistor Switch When transistor switches (footers) are used, they affect both the critical delay and idle leakage power of a circuit. To examine this, we use the methodology from [9]. [9] identies two effects that footers have on a circuit: KD is the delay penalty, and is the factor by which a circuit slows down due to the voltage drop across the footer. KL is the leakage reduction, and is the factor by which the leakage is reduced when the power switch is off. KD and KL are dependent on the relative footer width, W , which is dened as the width of the footer divided by the sum of the widths of the NFETS of the circuit. The duty cycle, D, of the circuit is the the ratio between the time the switch has to be on and the total time per cycle. Equation (2) provides the equation for duty cycle with respect to V , RT , and W .
D(V, RT , W ) = RT RM (V )/KD (W ) (2)

Comparing (7) and (3) shows several important distinctions between the behavior of a transistor switched circuit versus a MEMS switched one: In MEMS switched circuits, the average power consumption approaches 0 as RT approaches 0. The supply voltage that minimizes energy of MEMS switched circuits is no longer dependent on the target throughput, and can be determined separately. The most suitable architecture for low-throughput applications when using MEMS switches is the one that has the least EM IN , which unlike transistor-switched designs, is not necessarily the least complex architecture. C. Optimal Supply Voltage It is important to study the effect of switch choice on the optimal operating voltage since it can affect other aspects of the design. For example, if the optimal voltage is in subthreshold region, it will require the use of custom RAM cells and special considerations against process variation and coupling noise. Therefore, we provide a mathematical analysis of optimal supply voltage. As can be seen in Figure 1, the optimal voltage of the four architectures in terms of energy is nearly the same, around 250mV. This is due to the fact that the designs are all optimally pipelined, in terms of energy, according to the methodology in [7]. Equation (8) provides the optimal supply voltage of a non-switched circuit, (VoptN S ), where n is the subthreshold slope of the process, VT H is the thermal voltage, is the activity factor, CL is the total load capacitance, WEF F is the sum of the widths of the transistors, k is a tting parameter, CG is the typical capacitance of a gate, and LCP is the logical delay (gate depth) of the critical path[3]. VoptN S = nVT H [2 lambertW ( 2CL e2 )] (8) WEF F kCG LCP

Furthermore, by modifying (1), we can get ( 3) that provides the average power equation for transistor switched circuit:
P (V, RT , W ) = RT EA (V ) + (1 D)PL (V ) + D PL (V ) (3) KL (W )

As the target throughput approaches zero, the power consumption does not go to zero, but instead consumes PL /KL (W ) watts. In [8], it was shown that it is possible to target very low-throughput architectures by using a very small footer. However, if the footer is too small, the effective voltage of the circuit may be below the minimum operational voltage of the circuit, rendering the circuit inoperable. Once this footer size limit is reached, KL (W ) reaches its maximum value and no matter how low the throughput goes, the power consumption will always be at PL (V )/KL (W ).

As the FFT architectures become more complex, CL increases almost at the same rate as the WEF F , so they have very little effect on VoptN S . Likewise, the architectures are optimally pipelined, which means LCP and end up being similar for the different architectures. The major difference between the architectures is the number of clock cycles it takes to complete an FFT, which has no affect on the optimal V according to (8). It is also noteworthy that, according to (8), threshold voltage (VT ) has no effect on the optimal V . (8) does not take into account the presence of a MEMS switch, so a new equation has to be derived for the optimal voltage of a MEMS switched circuit, VoptM S . It will be assumed that the power consumption of the MEMS switch dominates the leakage power of the circuit. For the technology used in this paper and a 100 W MEMS switch, this is a reasonable assumption for circuits with less than half a million gates, especially since unlike leakage power, MEMS power does not decrease with lower voltages. Let tT ASK be the time it takes to complete a task (for example, an FFT). Then the total energy from the MEMS switch is ESW = PSW tT ASK . Let tGAT E be the typical delay of a gate and LT be the logical delay of the task, with LT = tT ASK /tGAT E . (9) gives the well-known equation for tGAT E using the Shockley model, where CG is the capacitance of the gate. It is assumed that the optimal V is in the superthreshold region. If it is not, another equation must be used [3]. tGAT E = kCG V (V VT )2 (9)

MEMS switch results in a higher optimal voltage compared to a non-switched design. 1

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(10) gives the active energy in terms of effective capacitance, CEF F = CL . EA = CEF F V 2 (10) Let be the non-controllable process dependant parameters, = PSW kCG (note that CG varies along with VT , so is not constant over different VT s). Then the total energy, ET , of the circuit per task is given in (11), where ESW is the energy consumption of the MEMS switch.
ET = EA + ESW = CEF F V 2 + V LT (V VT )2 (11)

VoptM S can be found by setting the derivative of ET to zero, which is shown in (12). 2CEF F VoptM S (VoptM S VT )3 LT (VoptM S +VT ) = 0 (12) (12) is a quartic equation that has a real positive, real negative, and complex solution, with the real positive solution being VoptM S . Like many quartic solutions, the solution to (12) is extremely long with many terms and is not shown in this paper, but can be easily found using symbolic math tools such as MATLAB. Figure 2 presents VoptM S with respect to CEF F and LT , and includes the range occupied by the FFT architectures (PSW = 100W , k = 3.1 105 , and CG is determined for each threshold voltage). The solid mesh shows the lowest threshold voltage while two mesh outlines are shown for the regular and high threshold voltage available with the technology used. It can be seen that employing the

In summary, Figure 2 shows that if the total energy is more dominated by MEMS switch energy, the optimal voltage grows higher in a natural attempt to reduce the MEMS energy, which is wasted energy, i.e. not spent toward completing tasks. This can be seen in the gure from three different perspectives: 1) Increasing the threshold voltage slows down the design, which increases the MEMS switch energy and therefore, increases optimal voltage. This is in direct contrast to non-switched circuits, where changing VT does not affect the optimal voltage [3]. 2) Increasing the logical delay of the design per task, which is effectively slowing down the design have a similar effect. This means a parallel design will have a lower optimal voltage compared to a scalar design, which again is a different behavior from non-switched or transistor-switched designs. 3) Decreasing the effective capacitance while keeping other parameters constant, means lowering active energy while keeping MEMS switch energy constant. This has a similar effect of increasing the optimal voltage. IV. M ETHODOLOGY A. Synthesis and Simulation
TABLE I EDA T OOLS

Technology & Cell Library Synthesis Dynamic Power Meas. SRAM ROM

Industry 130nm, Regular VT Synopsys Design Compiler Synopsys PrimeTime & HSPICE Custom Sub-VT design[1] Industry ROM Compiler

Table I gives a summery of the synthesis and simulation techniques used to measure the critical timing and power con1 It is not possible for the MEMS switch to push V optM S lower than VoptN S because that would mean the assumption that MEMS power dominates leakage power is false.

Average Power Consumption (W)

sumption of the various circuits. An older 130nm technology was chosen because of its balance between speed and leakage. Newer technologies such as 90nm and 45nm have considerably higher leakage currents and can often consume more energy per operation than older deep-submicron technologies [8]. The SRAM is custom robust SRAM design that can operate down to 300 mV[1]. B. Exhaustive Search For the transistor-switched circuits, we performed an exhaustive search to nd the optimal supply voltage and footer size in order to minimize power consumption for each target throughput, which ranged from one FFT per s to one FFT per day. In our search, we varied the supply voltage from nominal voltage down to 100mV. As for the footer size, we used the methodology from [9], whereby KL and KD are determined for various relative widths, ranging from one down to the minimum size(where the circuit is inoperable at nominal voltage). We selected the length of the footer as 500 nm in order to achieve a good tradeoff between KD and KL [8]. In addition, we employed the methodology from [4] to speed up the voltage scaling simulation. We repeated this process for each of the four FFT architectures. Similarly, we performed an exhaustive search for the MEMS-switched designs. However, the only varying parameter for this case is the operating voltage as we study only one MEMS switch in this paper. Since the MEMS switch has a certain activation time of 1 ms [6], we assumed the switch was left constantly on if the activation time was too slow to meet the throughput requirement. V. R ESULTS A. Transistor Switch Figure 3 presents the results for transistor switch experiment. For any given target throughput(horizontal axis), the best combination of supply voltage (chart C) and relative footer width (chart B) that yields the minimum average power consumption (chart A) is shown. As the target throughput reduces, due to the relaxed performance requirements, the footer can be made smaller. As was mentioned in Section 1, if the footer is too small, then the voltage drop across the footer would render the circuit inoperable. Figure 3.B shows shows the fundamental limit to the relative size of the footer, where the optimal relative footer width approaches 5 102 with an optimal supply voltage of 150mV. This brings up another limitation of transistor switches: for a digital logic design with 50,000 transistors, a relative width of 5 102 would require 2500 transistor switches (or a smaller number of larger transistors), which can add signicant area overhead of around 5%, not to mention the fact that a signal must be routed to these switch transistors to activate them. A common solution is to use a higher (and non-optimal) supply voltage, which would allow for smaller (or less) transistor switches. In [8], for example, a 500mV supply voltage is used at the cost of increasing power consumption.

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It also can be seen that with target throughputs higher than an FFT every second, the parallel architecture is the most power efcient. The reason is that the parallel architecture is much faster than the others, so the supply voltage can be set lower, thereby reducing power [7]. At lower throughputs, where the relative width starts to reach a limit, the the average power consumption approaches PL /KL . In this region the least complex architectures become the most power efcient. This implies that even in the presence of transistor switches, the target throughput is an important consideration when selecting an architecture. B. MEMS Switch Figure 4.A presents the average power consumption of the 4 architectures using a MEMS switch for power gating. With the exception of very high throughputs, where the supply

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voltage must be raised to meet the throughput requirement, the power consumption forms a linear relationship with target throughput, as predicted by the mathematical analysis, namely Equation (7). With the transistor-switched designs, there would be very little difference in power consumption if an FFT was performed once an hour or once a month because the power curve approaches a nite value. With a MEMS-switched design, there would be a substantial decrease in power. In order to compare MEMS switches with transistor switches, the curves for the parallel architecture and the low-complexity architecture using the transistor switches are also shown using dashed lines on the same gure. It can be seen that, with a very small exception in the high throughput region, the MEMS-switched parallel architecture is the clear winner in terms of power consumption. This is signicant because it implies that one can design a circuit without considering the target throughput, and it would be a good selection for a range of high-throughput and low-throughput applications. Figure 4.B presents the optimal supply voltage of the different architectures. As the mathematical analysis predicted, unlike their transistor-switched counterparts, the optimal supply voltages of MEMS-switched circuits vary greatly and are in the superthreshold region. As the designs get faster and more complex, the optimal supply voltage decreases and the energy efciency increases. With the parallel design, the optimal supply voltage is pushed even further lower and power is reduced by 40% across all throughputs, compared to the single core design. With transistor-switched design, parallelization only decreased power in the high throughput range and greatly increases power at low throughputs. VI. C ONCLUSION AND F UTURE W ORK In this paper, we compared the older method of transistor switches with new method of MEMS switches in terms of their effectiveness in power reduction of throughput-aware applications. We showed the fundamental limits of transistor switches for extremely low-throughput applications. We also compared four different FFT designs with varying complexity in terms of their suitability for throughput-aware design. We showed that when using transistor switches, low-complexity designs are

more suitable for low-throughput applications. However, the trend is completely different when using MEMS switches. Our experimental results showed that an FFT architecture with 16 parallel units is able to cut the power almost in half compared to a non parallel architecture, when using MEMS switches in low-throughput applications. We also showed that, while the optimal operating voltage of low-throughput applications using transistor switches is in subthreshold region, this is may not be the case with MEMS switches. Future work would include a physical implementation of the experimental simulations presented in this paper. Further work is needed to determine the requirements of a MEMS switch for power gating applications. It may be the case that the high reliability and expensive packaging requirements that currently plague RF MEMS switches are more relaxed with respect to power switches. Further work is also needed to determine how well both transistor switches and MEMS switches scale with decreasing technology sizes. R EFERENCES
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