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apb

The document provides an overview of the Advanced Peripheral Bus (APB) protocol, which is part of the AMBA architecture introduced by ARM in 1996. APB is designed for low-cost, low-power peripheral connectivity and features a simple, non-pipelined interface that requires at least two cycles for each transfer. Key aspects include signal descriptions, operating states, and the protocol's role in system-on-chip (SoC) designs, emphasizing its efficiency and ease of integration.

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3 views

apb

The document provides an overview of the Advanced Peripheral Bus (APB) protocol, which is part of the AMBA architecture introduced by ARM in 1996. APB is designed for low-cost, low-power peripheral connectivity and features a simple, non-pipelined interface that requires at least two cycles for each transfer. Key aspects include signal descriptions, operating states, and the protocol's role in system-on-chip (SoC) designs, emphasizing its efficiency and ease of integration.

Uploaded by

lurecartsuppourt
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© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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APB PROTOCOL

ADVANCED PERIPHERAL BUS PROTOCOL

BY SIREESHA DEVI
VERIFICATION TRAINER
INDEX

• INTRODUCTION OF AMBA
• AMBA EVOLUTION
• AMBA ARCHITECTURE
• INTRODUCTION OF APB PROTOCOL
• SIGNAL DESCRIPTIONS
• MASTER-SLAVE COMMUNICATION
• STATE MACHINE
• TIMING DIAGRAMS
INTRODUCTION OF AMBA

• AMBA(Advanced micro control Bus Architecture) is


introduced byARM(Advanced RISC Machine) in 1996.
• AMBA is a family for all protocols. Like as ASB,APB,AHB, AXI….,etc.
• AMBA is a set of interconnect protocols
AMBA EVOLUTION
AMBA BUS ARCHITECTURE
APB PROTOCOL

• APB protocol is a part of AMBA family. APB protocol is low-cost


interface that optimized for minimal power consumption.
• It is reduced interface complexity. It is not pipelined and is a
simple.
• Every transfer takes at least two cycles to complete.
• All the singles transitions are only related to the rising edge of the
clock to enable the integration of APB peripherals
KEY FEATURES OF APB PROTOCOL

• Simple and Low Power

• Fixed Transfer Size

• Low Bandwidth and High Latency


THE APB PROTOCOL IS A CRUCIAL COMPONENT OF
SOC DESIGN FOR SEVERAL REASONS:

1. Peripheral Connectivity: It provides a standardized way to connect and


communicate with a variety of peripheral devices within the same system.
2. Power Efficiency: APB's low-power characteristics make it an excellent choice for
battery-powered devices, where energy efficiency is paramount.
3. Simplicity: APB's simplicity makes it easier to implement and verify, reducing
development time and cost.
4. Integration: As it is part of the ARM AMBA specification, APB can be seamlessly
integrated into ARM-based SoC designs, ensuring compatibility with ARM
processors and other IP cores
APB SIGNALS
SIGNAL DESCRIPTIONS IN APB

• PCLK – Generally System clock is directly connected to this

• PRESETn – Active Low Asynchronous Reset

• PSELx – Slave select signal, there will be one PSEL signal for each slave connected to
master. If master connected to ‘n’ number of slaves, PSELn is the maximum number of
signals present in the system. (Eg: PSEL1,PSEL2,..,PSELn)

• PENABLE – Indicates the second and subsequent cycles of transfer. When PENABLE is
asserted, the ACCESS phase in the transfer starts.
• PADDR[31:0] – Address bus from Master to Slave, can be up 32 to bit wide

• PWRITE – Indicates Write when HIGH, Read when LOW

• PWDATA[31:0] – Write data bus from Master to Slave, can be up to 32 bit wide

• PRDATA[31:0] – Read data us from Slave to Master, can be up to 32 bit wide

• PREADY – It is used by the slave to include wait states in the transfer. i.e. whenever slave
is not ready to complete the transaction, it will request the master for some time by de-
asserting the PREADY.

• PSLVERR – Indicates the Success or failure of the transfer. HIGH indicates failure and
LOW indicates Success
• PSTRB[3:0] : The PSTRB signal is only present if DATA_WIDTH is greater than 8. Each
bit of PSTRB corresponds to a write enable for the byte lane on PWDATA.
There is one write strobe for each eight bits of the write data bus.
Therefore, PSTRB[n] corresponds to PWDATA[(8n + 7):(8n)].“

PPROT[2:0]
• To support complex system designs, it is often necessary for both the interconnect and
other devices in the system to provide protection against illegal transactions. It is
provided by Protection Unit in APB Protocol.
PPROT[2:0] : Protection type. This signal indicates the normal, privileged, or secure
protection level of the transaction and whether the transaction is a data access or
an instruction access.
OPERATING STATES

• IDLE : This is the default state of APB.


• SETUP : When transfer is required, PSELx is asserted
then the bus moves in setup state. Bus only remains in
SETUP for only one clock cycle and always moves to
ACCESS state on next rising edge of clock. So, the slave
must be able to sample the Address and control
information in the SETUP cycle itself.
• ACCESS : PENABLE is asseted to enter into the ACCESS
state. The PADDR, PWRITE, PSELx and PWDATA
signals must remain stable during ACCESS state.
WRITE AND READ TRANSFERS IN APB
PROTOCOL

WRITE Transfer – Without Wait States


• At T1, a write transfer with address PADDR,PWDATA,PWRITE and PSEL starts.
• This is Setup Phase of Transfer.
• After T2, PENABLE and PREADY are registered at the rising edge of PCLK.
• When asserted, PENABLE indicates starting of ACCESS Phase
• When asserted, PREADY indicates that slave can complete the transfer at the next rising
edige of PCLK.
• PADDR, PDATA and control signals all should remain valid till the transfer completes at
T3.
• PENABLE signal will be de-asserted at the end of transfer.
• PSEL is also de-asserted, if next transfer is not to the same slave.
READ Transfer – Without Wait States
• At T1, a READ transfer with address PADDR, PWRITE and PSEL starts.
• They will be registered at rising edge of PCLK.
• This is SETUP Phase of the transfer.
• After T2, PENABLE and PREADY are registered at the rising edge of PCLK.
• When asserted, PENABLE indicates the starting of ACCESS phase.
• When asserted, PREADY indicates that slave can complete the transfer at next rising
edge of PCLK by providing the data on PRDATA.
• Slave must provide the data before the end of read transfer. i.e. before T3.
WRITE Transfer – With Wait States
• During the ACCESS Phase, when PENABLE is high, the slave extends the transfer by
driving PREADY low.
• The PADDR, PWRITE, PSEL, PENABLE, PWDATA, PSTRB, PPROT signals should
remain unchanged while PREADY is low
• PREADY can take any value when PENABLE is low.
• It is recommended that the address and write signals are not changed immediately after
a transfer, but remain stable until another access occurs.
•During the ACCESS Phase, when PENABLE is high, the slave extends the transfer by
driving PREADY low.

•The PADDR, PWRITE, PSEL, PENABLE, PPROT signals should remain unchanged while
PREADY is low
ERROR RESPONSE

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