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Jan-22 IO interfacing MM class (1)

The document outlines the interfacing of the 8085 microprocessor with I/O devices, detailing the steps for accessing memory and identifying I/O devices through memory-mapped and peripheral I/O. It explains the process of device selection and data transfer between the microprocessor and I/O devices, including the necessary control signals and operations for both input and output data transfers. Additionally, it describes the decoding of the address bus to generate unique pulses for device selection.

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6 views

Jan-22 IO interfacing MM class (1)

The document outlines the interfacing of the 8085 microprocessor with I/O devices, detailing the steps for accessing memory and identifying I/O devices through memory-mapped and peripheral I/O. It explains the process of device selection and data transfer between the microprocessor and I/O devices, including the necessary control signals and operations for both input and output data transfers. Additionally, it describes the decoding of the address bus to generate unique pulses for device selection.

Uploaded by

archana.singh804
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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8085 interfacing with I/O Devices

Interfacing memory…recap…

•Accessing memory can be summarized into the following three steps:


•Select the chip.
•Identify the memory register.
•Enable the appropriate buffer.

•Translating this to microprocessor domain:


•The microprocessor places a 16-bit address on the address bus.
•Part of the address bus will select the chip and the other part will go through the
address decoder to select the register.
•The signals IO/M and RD combined indicate that a memory read operation is in
progress. The MEMR signal can be used to enable the RD line on the memory
chip.
8085 Machine Cycle Status and Control Signals
8085 interfacing with I/O Devices

• Microprocessor need to Identify


I/O devices with binary number.
IO devices can be interfaced:
• Memory-Mapped I/O (using
addresses from memory space)
– Device is identified by
16-bit address (Space ranges
from 0000H – FFFF

• Standard I/O mapped or


isolated I/O mapping
/Peripheral Mapped I/O
– has separate numbering
scheme for I/O devices
– Instructions IN/OUT are
used for data transfer
– Device is identified by 8-bit
address (Space ranges from
00H –FFH)
Memory Mapping Vs Peripheral
Memory mapped I/O interfacing
Peripheral I/O Instructions
Device Selection and Data Transfer

Steps are summarized as:

•Decode the address bus to generate unique pulse corresponding to device address on
the bus called device address bus or I/O address pulse.

•Combine the device address pulse with the control signal to generate a device select
pulse(I/O select) that is generated only when both signals are asserted.

•Use the I/O select pulse to activate interfacing device(I/O port)


Data
Transfer
For data transfer from input device to processor the following operations are
performed.
•The input device will load the data to the port.
•When the port receives a data, it sends message to the processor to read the data.
The processor will read the data from the port.
•After a data have been read by the processor the input device will load the next data
into the port.

For data transfer from processor to output device the following operations are
performed.
•The processor will load the data to the port.
•The port will send a message to the output device to read the data.
•The output device will read the data from the port.
•After the data have been read by the output device the processor can load the next
data to the port.
A7 A6 A5 A4 A3 A2 A1 A0
Decoder i/p
1 1 0 1 0 1 0 0 D4 =101 =>5
1 1 0 1 0 1 0 1 D5
Chip select
1 1 0 1 0 1 1 0 D6
connected to
1 1 0 1 0 1 1 1 D7 o/p pin5
END

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