Microprocessor-

 Microprocessor is an electronic circuit that functions as the central

processing unit(CPU)of a computer,providing computational
control.
 Microprocessor are also used in other electronic system such as
computer,printer,automobiles,jet airlines etc

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 Evaluation of Microprocessors-

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 Chapter 1-
8086 16-bit Microprocessor
 8086 Microprocessor is an enhanced version of 8085Microprocessor
that was designed by Intel in 1976.
 It is a 16-bit Microprocessor having 20 address lines and16 data lines
that provides up to 1MB storage.
 It consists of powerful instruction set, which provides operations like
multiplication and division easily.
 It supports two modes of operation, i.e. Maximum mode and Minimum
mode.
 Maximum mode is suitable for system having multiple processors and
Minimum mode is suitable for system having a single processor.

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 Features of 8086
 It has an instruction queue, which is capable of storing six instruction bytes
from the memory resulting in faster processing.
 It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal
data bus, and 16-bit external data bus resulting in faster processing.
 It is available in 3 versions based on the frequency of operation −
 8086 → 5MHz
 8086-2 → 8MHz
 (c)8086-1 → 10 MHz
 It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which
improves performance.
 Fetch stage can prefetch up to 6 bytes of instructions and stores them in the
queue.
 Execute stage executes these instructions.
 It has 256 software vectored interrupts.
 It consists of 29,000 transistors
 Supports Multiprogramming

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 Supports 24 operand addressing modes
 Provide separate instructions for string manipulation
Software Model of the 8086 Microprocessors

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 Block diagram of 8086

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 As shown in fig ,the 8086 CPU is divided into two independent
functional parts i.e

 Executoin Unit(EU)
 Bus interface Unit(BIU)
Functions of Execution Unit(EU)-
1. To tell BIU where to fetch instruction or data from
2. To decode the instuction
3. To execute the instruction

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 8086 Registers
Ge ne ral Purpose Inde x
AH AL
BP
AX

SP
BH BL
BX
SI

CH CL
DI
CX

DH DL
DX Segme nt

CS

Status and Control SS

Flags DS

IP ES

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 General Purpose Registers

AX - the Accumulator
BX - the Base Register
CX - the Count Register
DX - the Data Register

 Normally used for storing temporary results

 Each of the registers is 16 bits wide (AX, BX, CX, DX)
 Can be accessed as either 16 or 8 bits AX, AH, AL
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 General Purpose Registers
• AX
– Accumulator Register
– Preferred register to use in arithmetic, logic and data transfer
instructions because it generates the shortest Machine Language
Code
– Must be used in multiplication and division operations
– Must also be used in I/O operations

• BX
– Base Register
– Also serves as an address register

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 General Purpose Registers
• CX
– Count register
– Used as a loop counter
– Used in shift and rotate operations

• DX
– Data register
– Used in multiplication and division
– Also used in I/O operations

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 Pointer and Index Registers

• All 16 bits wide, L/H bytes are not accessible

• Used as memory pointers

– Example: MOV AH, [SI]
• Move the byte stored in memory location whose address is contained in register SI to register
AH

• IP is not under direct control of the programmer

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 Flag Register

Overflow Carry
Direction Parity

Interrupt enable Auxiliary Carry

Trap Zero
6 are status flags
Sign
3 are control flag
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 FLAG Register-
 Carry Flag(CF)-It is set to 1 at MSB position
 Auxiliary carry flag(AF)-If an operation performed in ALU
generates a carry /barrow from lower nibble to upper nibble
 Parity flag(PF)-This flag indicates the Parity of result.
If result contains even number of ‘1’ s,then parity flag is set
 Zero Flag(ZF)-If result of arithmetic & logical operation is zero
then it is set to 1 otherwise 0
 Sign Flag(SF)-If result of operation is negative then sign flag is set
 Overflow Flag(OF)-If result is too large to fit in the number of
available bits.
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 FLAG Register-
 Trap Flag(TF)-
-Single step control flag
 Interrupt Flag(IF)-
-interrupt enable/disable flag
 Direction Flag(DF)-
-used for string operation

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 BIU-
 The functions of BIU is to send address to:
1. Fetch the instruction or data from memory
2. Write the data to memory
3. Write the data to the port
4. Read the data from the port
 Segment Registers-
CS,DS,SS,ES
 Instruction Queue IQ(Queue)

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 8086 Programmer’s Model
ES Extra Segment
CS Code Segment
BIU registers
(20 bit adder) SS Stack Segment
DS Data Segment
IP Instruction Pointer

EU registers AX AH AL Accumulator
BX BH BL Base Register
CX CH CL Count Register
DX DH DL Data Register
SP Stack Pointer
BP Base Pointer
SI Source Index Register
DI Destination Index Register
FLAGS

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 The Stack
• The stack is used for temporary storage of information such as
data or addresses.

• When a CALL is executed, the 8086 automatically PUSHes the

current value of CS and IP onto the stack.

 Other registers can also be pushed

 Before return from the subroutine, POP instructions can be

used to pop values back from the stack into the corresponding
registers.
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 INTEL 8086 - Pin Diagram

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 INTEL 8086 - Pin Details

Power Supply
5V  10%
Ground

Reset
Registers, seg
regs, flags
CS: FFFFH, IP:
0000H
If high for
minimum 4
Clock clks
Duty cycle: 33%
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 INTEL 8086 - Pin Details

Address/Data Bus:
Contains address Address Latch Enable:
bits A15-A0 when ALE
is 1 & data bits D15 – When high,
D0 when ALE is 0. multiplexed
address/data bus
contains address
information.

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 INTEL 8086 - Pin Details

INTERRUPT

Non - maskable
interrupt

Interrupt
acknowledge

Interrupt request
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 INTEL 8086 - Pin Details

Direct
Memory
Access

Hold

Hold
acknowledge

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 INTEL 8086 - Pin Details

Address/Status Bus
Address bits A19 –
A16 & Status bits S6
– S3

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 INTEL 8086 - Pin Details

BHE#, A0: Bus High Enable/S7

0,0: Whole word Enables most
(16-bits)
significant data bits
0,1: High byte D15 – D8 during read
to/from odd address or write operation.
1,0: Low byte S7: Always 1.
to/from even address

1,1: No selection

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 INTEL 8086 - Pin Details

Min/Max mode
Minimum Mode: +5V
Maximum Mode: 0V

Minimum Mode Pins

Maximum Mode
Pins

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 Minimum Mode- Pin Details

Read Signal

Write Signal

Memory or I/0

Data
Transmit/Receiv
e

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Data Bus Enable
 Maximum Mode - Pin Details

S2 S1 S0
000: INTA
001: read I/O port
010: write I/O port
011: halt
100: code access Status Signal
101: read memory
110: write memory Inputs to 8288 to
111: none -passive generate eliminated
signals due to max
mode.

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 Maximum Mode - Pin Details

Lock Output
Used to lock peripherals
off the system
DMA
Activated by using the Request/Grant
LOCK: prefix on any
instruction
Lock Output

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 Maximum Mode - Pin Details

QS1 QS0
00: Queue is idle
01: First byte of opcode
10: Queue is empty
11: Subsequent byte of
opcode
Queue Status
Used by numeric
coprocessor (8087)

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 Memory Segmentation in 8086
 Segmentation is the process in which the main memory of the
computer is logically divided into different segments and each
segment has its own base address.
 It is basically used to enhance the speed of execution of the
computer system, so that the processor is able to fetch and execute
the data from the memory easily and fast.

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 Memory Segmentation in 8086
 Need for Segmentation –
The Bus Interface Unit (BIU) contains four 16 bit special purpose
registers (mentioned below) called as Segment Registers.
 Code segment register (CS): is used for addressing memory
location in the code segment of the memory, where the executable
program is stored.
 Data segment register (DS): points to the data segment of the
memory where the data is stored.
 Extra Segment Register (ES): also refers to a segment in the
memory which is another data segment in the memory.
 Stack Segment Register (SS): is used for addressing stack
segment of the memory. The stack segment is that segment of
memory which is used to store stack data.

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 Memory Segmentation in 8086

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 Advantages of the Segmentation
 The main advantages of segmentation are as follows:
 It provides a powerful memory management mechanism.
 Data related or stack related operations can be performed in different
segments.
 Code related operation can be done in separate code segments.
 It allows to processes to easily share data.
 It allows to extend the address ability of the processor, i.e.
segmentation allows the use of 16 bit registers to give an addressing
capability of 1 Megabytes. Without segmentation, it would require 20
bit registers.
 It is possible to enhance the memory size of code data or stack
segments beyond 64 KB by allotting more than one segment for each
area.

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 Benefits
 Segmentation allows memory capacity to be 1 MB.
 It allows placing of code, data and stack portions of same program
into different segments. It helps protection of code and data.
 Segmentation allows multiprogramming.
 Allows data sharing between two or more programs.
 Segmentation makes it possible to create relocatable programs.
 It allows creating multi-user and time-shared systems.

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 Pipelining:
 Fetching next instruction while the current instruction executes is
called pipelining.
 In a non-pipelined processor, the instruction is fetched, decoded
and executed.
 Unless one instruction is completely executed, next instruction is
not fetched.
 In a pipelined processor, the operations instruction fetch (IF),
Instruction decode (ID) and execute(E), are performed in parallel
i.e. while one instruction is being decode, at the same time
microprocessor can fetch the next instruction, thus speeding up
execution.
 Figure below shows execution of 3 instructions I1, I2, I3 in a non-
pipelined processor and in a pipelined processor:

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 Pipelining:

IF ID E IF ID E IF ID E

I1 I1 I1 I2 I2 I2 I3 I3 I3

1 2 3 4 5 6 7 8 9

Clock cycles
 Fig.(a) Execution of 3 instructions on a non-pipelined processor

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 Pipelining:
IF

ID

1 2 3 4 5
Clock cycles

Fig.(b) Execution of 3 instructions on a pipelined processor

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 Pipelining:
 From the above two figures it is clear that pipeline processors take
less time to execute same number of instructions as compared to
non-pipelined processors.
 In the above example, to execute 3, instructions non-pipelined
processor takes 9 clock cycles while pipelined processor takes only
5 clock cycles.
 In 8086, pipelining is implemented by dividing the processor into 2
functional units: Bus Interface Unit (BIU) and Execution Unit (EU)
 Bus Interface Unit fetches next instructions and stores them in
prefetch queue while current instruction is executed by Execution
Unit

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 Physical Address generation:
 In order to access any memory location, 8086 microprocessor generates 20 bit
address.
 Memory of 8086 based systems is divided into segments.
 To access a location in a particular segment, 8086 uses segment register.
 The content of segment register is shifted to left by 4 bit position.
 An offset value is added to this shifted content and the result is placed on address
bus.

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
 Physical Address generation:

 For example, if contents of CS=2000H and IP=1234H then

in order to fetch instruction from memory:
1. Shift contents of CS by 4 bit position:
2000 20000
 Add offset value (contents of IP) to this:
20000
1234
21234H
 21234H will be placed on address bus

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 Physical Address generation:

 Calculate the Physical Address for given

i)DS=73A2H SI=3216H
ii)CS=7370H IP=561EH
iii)4370:561E
iv)7A32:0028

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 7 3 A 2 0 DS
+ 3 2 1 6 SI
P.A 7 6 C 3 6

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 Difference 8085 AND 8086
Serial
8085 microprocessor 8086 microprocessor
No.

1 The data bus is of 8 bits. The data bus is of 16 bits.

2 The address bus is of 16 bits. The address bus is of 20 bits.

The memory capacity is 64 KB.Also 8085

Can Perform Operation Upto 2^8 ie. 256 The memory capacity is 1 MB.Also 8086 Can Perform
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numbers. A number greater than this is to Operation upto 2^16 ie. 65,536 numbers.
taken multiple times in 8 bit data bus.

The input/output port addresses are of 8

4 The input/output port addresses are of 8 bits.
bits.

5 The operating frequency is 3.2 MHz. The operating frequency is 5 MHz, 8MHZ,10MHZ.

8086 MP has Two Modes Of Operation.

5 8085 MP has Single Mode Of Operation. 1. Minimum Mode = SingLe CPU PROCESSOR
2. Maximum Mode = Multiple CPU PROCESSOR.

It not have multiplication and division

6 It have multiplication and division instructions.
instructions.

It supports pipe-lining as it has two independent units

7 It does not support pipe-lining.
Execution Unit (EU) and Bus Interface Unit (BIU).

8 It does not support instruction queue. It supports instruction queue.

9 Memory space is not segmented. Memory space is segmented.

44 It consists of 5 flags(Sign Flag, Zero Flag, It consists of 9 flags(Overflow Flag, Direction Flag,
10 Auxiliary Carry Flag, Parity Flag, Carry Interrupt Flag, Trap Flag, Sign Flag, Zero Flag, Auxiliary
 Differentiate between minimum mode and
maximum mode of 8086 microprocessor

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