Scribd
Upload
21 views16 pages

Lecture-3-07.01.2025

The document provides an overview of MIPS instruction encoding, detailing the structure of R, I, and J type instructions, and their respective fields. It outlines the MIPS32 implementation, instruction cycle, and execution phases, including instruction fetch, decode, execution, memory access, and write-back. Additionally, it discusses the speculative approach for operand fetching and the design of the register bank for improved performance.

Uploaded by

Munesh Meena
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
21 views16 pages

Lecture-3-07.01.2025

The document provides an overview of MIPS instruction encoding, detailing the structure of R, I, and J type instructions, and their respective fields. It outlines the MIPS32 implementation, instruction cycle, and execution phases, including instruction fetch, decode, execution, memory access, and write-back. Additionally, it discusses the speculative approach for operand fetching and the design of the register bank for improved performance.

Uploaded by

Munesh Meena
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 16

LECTURE 3: REVIEWING MIPS

DATAPATH-1
MIPS Instruction Encoding
Name Fields Comments
Field size 6 bits 5 bits 5 bits 5bits 5bits 6 bits All instruction =32 bit long
R Type op rs rt rd shamt funct Arithmetic instruction
I Type op rs rt Address/ immediate data Transfer, Branch, Imm
J Type op Target address Jump

◦ MIPS fields have names to make them easier to discuss:


◦ op – basic operation of the instruction, traditionally called the opcode
◦ rs – the first register source operand
◦ rt – the second register source operand
◦ rd – the register destination operand, which gets the result of the operation
◦ shamt – shift amount to be used in shift instructions, zero otherwise
◦ funct – often called the function code, selects the specific variant of the operation in
the opcode field
MIPS32: Simple Implementation
◦ We consider the integer instructions and datapath of MIPS32.
◦ Basic idea:
◦ Different instructions require different number of register operands and immediate data (16
bits or 26bits).
◦ Relative positions of register encodings and immediate data are the same across instructions.
◦ A Naïve Approach:
◦ After fetching and decoding an instruction, identify the exact register(s) and/or immediate
operands to use, and handle them accordingly.
◦ The number of register fetches and immediate operand processing will vary from instruction to
instruction.
◦ We do not utilize the possible overlapping of operations to make instruction execution faster.
◦ Before instruction decoding is complete, fetch the register operands and immediate data in case
they are required later.
Assumption
◦An instruction can have up to two source operands:
ADD R1, R5, R10
LW R5, 100(R6)
◦There are 32 32-bit integer registers, R0 to R31.
◦ We design the register bank in such a way that two registers can be
read simultaneously (i.e. there are 2 read ports).
◦ We shall later see that performance can be improved by adding a write
port (i.e. 2 reads and 1 write operations are possible per cycle).
Src Reg 1
Read (5 bits) Dest Reg
Port 1 Reg Data (5 bits)
(32 bits) Write
REGISTER Reg Data
Port
BANK (32 bits)

Read Src Reg 2


(5 bits)
Port 2
Reg Data
(32 bits)
◦A Speculative Approach:
◦ Here we try to eliminate the time required to fetch the register
operands and process the immediate data.
◦ When an instruction is decoded, at the same time we fetch the
register operands and also process the immediate data (i.e. sign
extend).
◦ Possible because their locations in the instruction word are fixed.
◦ If the operands are required, they are already available (no extra time
required).
◦ If the operands are not required, they are ignored.
MIPS32 Instruction Cycle
◦We divide the instruction execution cycle into five steps:
a) IF : Instruction Fetch
b) ID : Instruction Decode or Register Fetch
c) EX : Execution or Effective Address Calculation
d) MEM : Memory Access or Branch Completion
e) WB : Register Write-back
◦ We now show the generic micro-instructions carries out in the
various steps.
Execution Cycle
◦Instruction Fetch
◦ Instruction Decode
◦ Execution
◦ Memory
◦Write Back
Instruction Fetch
◦ Instruction Fetch
◦ Get the next instruction from memory. The instruction pointed to by
PC is fetched from memory, and also the next value of PC is
computed.
◦ Every MIPS32 instruction is of 32 bits (i.e. 4 bytes).
◦ For a branch instruction, new value of the PC may be the target
address. So PC is not updated in this stage; new value is stored in a
register NPC.

IF : IR <- Mem [PC]


NPC <- PC + 4
Instruction Decode
◦The instruction already fetched in IR is decoded.
◦ Opcode is 6-bits: bits 31..26, with optional function specifier: bits 5..0
◦ First source operand rs: bits 25..21, second source operand rt: bits
20..16
◦ 16-bit immediate data: bits 15..0
◦ 26-bit immediate data: bits 25..0
◦Decoding is done in parallel with reading the register
operands rs and rt.
◦ Possible because these fields are in a fixed location in the instruction
format.
◦In a similar way, the immediate data can be sign-extended.
ID A ← Reg [rs];
B ← Reg [rt];
Imm ← (IR15)16 ## IR15..0 // sign extend 16-bit immediate field
Imm1 ← IR25..0 ## 00 // pad 2 0’s to 26-bit immediate field

A, B, Imm, Imm1 are temporary registers.


Execute/ Effective Address Calculation
◦In this step, the ALU is used to perform some calculation.
◦ The exact operation depends on the instruction that is already
decoded.
◦ The ALU operates on operands that have been already made ready in
the previous cycle.
◦We show the micro-instructions corresponding to the type of
instruction.
Memory Reference:
Example: LW R3, 100(R8)
ALUOut ← A + Imm;

Register-Register ALU Instruction:


Example: SUB R2, R5, R12
ALUOut ← A func B;
[operation specified by func field (bits 5..0)]

Register-Immediate ALU Example: SUBI R2, R5, 524


Instruction: [operation specified by func field (bits
ALUOut ← A func Imm; 5..0)]

Branch: Example: BEQZ R2, Label


ALUOut ← NPC + (Imm << 2); [op is ==]
cond ← (A op 0);
MEM: Memory Access or Branch Completion

◦ The only instructions that make use of this step are loads,
stores, and branches.
◦ The load and store instructions access the memory.
◦ The branch instruction updates PC depending upon the outcome of
the branch condition.
Load instruction: Branch instruction:
PC ← NPC; if (cond) PC ← ALUOut;
LMD ← Mem [ALUOut]; else PC ← NPC;

Store instruction:
PC ← NPC; Other instructions:
Mem [ALUOut] ← B; PC ← NPC;
WB: Register Write Back
◦ In this step, the result is written back into the register file.
◦ Result may come from the ALU.
◦ Result may come from the memory system (viz. a LOAD instruction).
◦ The position of the destination register in the instruction word depends on the
instruction → already known after decoding has been done.

R Type op rs rt rd shamt funct


I Type op rs rt immediate

Register-Register ALU Instruction: Register-Immediate ALU Instruction:


Reg [rd] ← ALUOut; Reg [rt] ← ALUOut;

Load Instruction:
Reg [rt] ← LMD;
Thank You

You might also like