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AN-9750
High-Power Factor Flyback Converter for LED Driver with
FL7732 PSR Controller
efficiency and simple design. FL7732 provides protection
Introduction functions such as open-LED, short-LED and over-
temperature protection. The current-limit level is
This highly integrated PWM controller, FL7732, provides automatically reduced to minimize the output current and
several features to enhance the performance of low-power protect external components in short-LED condition.
flyback converters. The proprietary topology enables
simplified circuit design for LED lighting applications. By This application note presents practical design consideration
using single-stage topology with primary-side regulation, a for an LED driver employing Fairchild Semiconductor
LED lighting board can be implemented with few external PWM PSR controller FL7732. It includes designing the
components and minimized cost, without requiring an input transformer, selecting the components, and implementing
bulk capacitor and feedback circuitry. To implement high constant current regulation. The step-by-step design
power factor and low THD, constant on-time control procedure helps engineers design a power supply. The
utilizes an external capacitor connected at the COMI pins. design procedure is verified through an experimental
prototype converter. Figure 1 shows the typical application
Precise constant-current control regulates accurate output circuit of primary-side controlled flyback converter using
current across changes in input voltage and output voltage. FL7732 created in the design example.
The operating frequency is proportionally changed by the
output voltage to guarantee DCM operation with higher

Bridge-Diode
D
L

RSN CSN
C1 NP NS
CO
N RSTART
DSN

DVDD

CVDD NA

FL7732 QMOSFET
7 COMI VDD 4

5 2 RVS1
NC Gate
8 GND VS 6

3 GND CS 1

CCOMI
RSENSE RVS2 CVS

Figure 1. Typical Application Circuit

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.4 • 4/17/13
AN-9750 APPLICATION NOTE

ID D
VIN.peak n:1
Basic Operation
- VD + +
Generally, Discontinuous Conduction Mode (DCM) Lm
operation is preferred for primary-side regulation because it CO VOUT
allows better output regulation. The operation principles of IM
DCM flyback converter are as follows: -
IDS
Q +
Mode I
VDS
During the MOSFET turn-on time (tON), input voltage -
(VIN.pk) is applied across the primary-side inductor (Lm).
Then, drain current (IDS) of the MOSFET increases linearly
from zero to the peak value (Ipk), as shown in Figure 2. Figure 3. Mode I: Q[ON], D[OFF]
During this time, the energy is drawn from the input and
stored in the inductor.

Mode II ID D
VIN.peak n:1

When the MOSFET (Q) is turned off, the energy stored in - VD + +

the inductor forces the rectifier diode (D) to be turned on. Lm
While the diode is conducting, output voltage (VOUT), together CO VOUT
IM
with diode forward-voltage drop (VF), is applied across the
secondary-side inductor and diode current (ID) decreases IDS
-
linearly from the peak value (Ipk NP/NS) to zero. At the end of Q +
inductor current discharge time (tDIS), all energy stored in the
VDS
inductor has been delivered to the output.
-

MODE I MODE II MODE III

VGate Figure 4. Mode II: Q[OFF], D[ON]

VDS
nVOUT ID D
VIN.peak n:1

VIN - VD + +
Lm
CO VOUT
IM IM
IDS ID
IDS -
Q +
IDS VDS
-

ID Figure 5. Mode III: Q[OFF], D[OFF]

IO

Mode III
VA NA
 VO
NS When the diode current reaches zero, the transformer
auxiliary winding voltage begins to oscillate by the
resonance between the primary-side inductor (Lm) and the
effective capacitor loaded across MOSFET (Q).
tDIS
tS

Figure 2. Basic Function of DCM Mode Flyback

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.4 • 4/17/13 2
AN-9750 APPLICATION NOTE

Constant Current Regulation Output voltage is detected by the auxiliary winding and
resistive divider connected to the VS pin, as shown in
The output current (IO) can be estimated by using the peak Figure 7.
drain current (Ipk) of MOSFET and discharging time (tDIS) of
inductor current because output current (IO) is same as the OSC
average of the diode current (ID) in steady state. The output
current estimator identifies the peak value of the drain VOUT
current with a peak-detection circuit and calculates the Linear Frequency
output current using the inductor discharging time and Controller
switching period (tS). This output information is compared Freq. 6
VS
with an internal precise reference to generate error voltage
(VCOMI), which determines the duty cycle of the MOSFET in VS
Constant Current Mode. With Fairchild’s innovative
TRUECURRENT® technique, the constant output current
can be precisely controlled.
Figure 8. Linear Frequency Control
1 t N 1
I o   DIS  VCS  P  (1)
2 tS N S RSENSE
When output voltage decreases, secondary diode conduction
TRUECURRENT ®
calculation makes a precise output time is increased and the linear frequency control lengthens
current prediction. the switching period, which retains DCM operation in the
wide output voltage range, as shown in Figure 8. The
frequency control also lowers primary rms current with
7 COMI better power efficiency in full-load condition.
1 CS

Peak Primary Secondary

Error Detector Current Current
Amp. nVo
Lm
+
-

VO =
VREF TrueCurrent® VO.nom
Calculation
t DIS T

3
tDIS n VO
6 VS 4
VO = Lm
Detector
75% VO.nom

Figure 6. Detection for TRUECURRENT® Calculation 4

4 T
t 3
DIS
3
3
n VO
VCS VO = 5
Ipk = ID.pk 60% VO.nom Lm
RS

IO
5
5 T
t DIS 3
3
IDS ID
t Figure 9. Primary and Secondary Current
tDIS
tS

Figure 7. TRUECURRENT® Calculation Principle BCM Control

The end of secondary diode conduction time is possibly over
Linear Frequency Control
a switching period set by linear frequency control. In this
As mentioned above, DCM should be guaranteed for high case, FL7732 doesn’t allow CCM and the operation mode
power factor in flyback topology. To maintain DCM in the changes from DCM to BCM. Therefore, FL7732 originally
wide range of output voltage, frequency is linearly changed eliminates sub-harmonic distortion in CCM.
by the output voltage in linear frequency control.

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.4 • 4/17/13 3
AN-9750 APPLICATION NOTE

LED Open !
Protections VDD

The FL7732 have several self-protection functions, such as VDD_OVP

over-voltage protection, over-temperature protection, and
pulse-by-pulse current limit. All the protections are
VDD_ON
implemented as Auto-Restart Mode.

VDD_OFF
Open-LED Protection
FL7732 protects external components, such as diode and VOUT
capacitor at secondary side, in open-LED condition. During
switch-off, the VDD capacitor is charged up to the auxiliary VDD_OVP
winding voltage, which is applied as the reflected output x NS/NA
voltage. Because the VDD voltage has output voltage
information, the internal voltage comparator at the VDD pin
can trigger output over-voltage protection (OVP), as shown
in Figure 9. When at least one LED is open-circuited, output GATE
load impedance becomes very high and output capacitor is
quickly charged up to VOVP x NS / NA. Then switching is shut
down and the VDD block goes into “Hiccup Mode” until the
open-LED condition is removed, as shown in Figure 10.
Figure 11. Waveforms at Open-LED Condition

Internal
Bias Short-LED Protection (OCP)
In case of short-LED condition, the switching MOSFET and
secondary diode are usually stressed by the high powering
VDD good
current. However, FL7732 changes the OCP level in the
VDD 4 + short LED condition. When VS voltage is lower than 0.4 V,
VOVP - OCP level changes to 0.2 V from 0.7 V, as shown in Figure
12 so that powering is limited and external components
current stress is relieved.
+
-

S Q Shutdown Gate Driver -

LEB 1 CS
+
VOCP
VDD good R
At VS < 0.4V
Figure 10. Internal OVP Block
VOCP = 0.2V.
6 VS
At VS > 0.6V
Under Voltage Lockout (UVLO) VOCP = 0.7V.
The turn-on and turn-off thresholds are fixed internally at
16 V and 7.5 V, respectively. During startup, the VDD Figure 12. Internal OCP Block
capacitor must be charged to 16 V. The VDD capacitor
continues to supply VDD until power can be delivered from
the auxiliary winding of the main transformer. VDD is not
Figure 13 shows operational waveforms at short-LED
allowed to drop below 7.5 V during this startup process.
condition. Output voltage is quickly lowered to 0 V right
This UVLO hysteresis window ensures that VDD capacitor
after the LED-short event. Then, the reflected auxiliary
properly supplies VDD during startup.
voltage is also 0 V making VS voltage less than 0.4 V. 0.2 V
OCP level limits primary-side current and VDD hiccups up
and down in between UVLO hysteresis.

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.4 • 4/17/13 4
AN-9750 APPLICATION NOTE

LED Short ! Over-Voltage Protection (OVP)

The OVP prevents damage in over-voltage conditions. If the
VDD voltage exceeds 23 V at open-loop feedback condition,
VIN the OVP is triggered and the PWM switching is disabled. At
open-LED condition, VDD reaches VDD_OVP. Then, auto-
restart sequence causes a delay, limiting output voltage.

VCS
Over-Temperature Protection (OTP)
0.2V The built-in temperature-sensing circuit shuts down PWM
output if the junction temperature exceeds 150°C. There is
hysteresis of 10°C.
VDD
VDD_ON

VDD_OFF

Figure 13. Waveforms at Short-LED Condition

At short-LED condition, VS is low due to low output voltage.

Then, OCP level is changed to 0.2 V to reduce output current.

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.4 • 4/17/13 5
AN-9750 APPLICATION NOTE

then IIN.pk and VIN.min.pk can be expressed as:

Design Procedure
In this section, a design procedure a of single-stage flyback
I IN . pk  2  I IN .rms (4)
using FL7732 is presented using the schematic of Figure 1
as a reference. An offline LED driver with 16.8 W
VIN . min . pk  2 VIN .rms (5)
(24 V/0.7 A) output has been selected as a design example. where the IIN.rms and VIN.rms are rms line input current and
The design specifications are as follows: voltage, respectively.
 Input voltage range: 90 ~ 264 VAC and 50 ~ 60 Hz tON is required to calculate reasonable Lm value. With
 Nominal output voltage and current: 24 V/0.7 A Equation (2) ~ (5), the turn-on time, tON, is obtained as:
 Minimum efficiency: 87%
2 Lm  I IN .rms
tON 
2
 Maximum switching frequency: 65 kHz (6)
VI N .rms  f s
Step 1. Inductor Selection (Lm)
FL7732 operates with constant turn-on and turn-off time, as The input power is given as:
shown Figure 14. When MOSFET turn-on time (tON) and
switching period (tS) are constant, IIN is proportional to VIN PO
and can implement high power factor. PIN  I IN .rms  (7)

With Equation (6) and (7), the Lm value is obtained as:
Max. Peak Switch Current
(ISW.PK) Input Voltage (Vin)

  (VIN .rms ) 2  f s  tON 2

Switch Current (ISW)

Peak Input Current Input Current

(Iin)
Lm  (8)
(Iin.pk)
2 PO

(Design Example) Since the minimum input voltage is

Constant On-Time
Constant Off-Time 90VAC, the maximum tON occurs at full-load condition.
(tON) tS
Assuming the maximum tON is 7.4 µs at 65 kHz of the
Figure 14. Theoretical Waveform maximum frequency, the magnetizing inductance is
obtained as:

0.87  90 2  65  10 3  (7.4  10 6 ) 2
The single-stage flyback using FL7732 is assumed to Lm   743µH
operate in DCM due to constant tON and tS. Input voltage is 2  16.8
applied across the magnetizing inductance (Lm) during tON,
charging the magnetic energy in Lm. Therefore, the The maximum peak current of MOSFET at nominal output
maximum peak switch current (ISW.pk) of MOSFET occurs at power is calculated as:
peak point of line voltage, as shown Figure 14. The peak
input current (IIN.pk) is also shown at the peak input voltage
of one line cycle. Once the maximum tON is decided, ISW.pk of 7.4 106  2  90
I SW . pk   1.26 A
MOSFET is obtained at the minimum line input voltage and 743 106
full-load condition as:

tON VIN .min pk

I SW . pk  (2)
Lm Step 2. Sensing Resistor and nPS Selection
where VIN.min.pk and tON are the peak input voltage and Since FL7732 adopts TRUECURRENT® Calculation
the maximum turn-on time at the minimum line input method to regulate constant output current (IO), as defined in
voltage, respectively. equation (1). The output current is proportional to turn ratio
Using equation (2), the peak input current is obtained by: nps between the primary and secondary windings of the
transformer and inversely proportional to sensing resistor
V (RS). The FL7732 also implements cycle-by-cycle current
1
I IN . pk   (t ON )( IN . min . pk  t ON )  f s (3) limitation by detecting VCS to protect system from output
2 Lm short or overload. Therefore, VCS level to handle rated
system power without the current limitation should be
considered. It is typical to set the cycle-by-cycle limit level
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.0.4 • 4/17/13 6
AN-9750 APPLICATION NOTE

(typical: 0.67 V) at 20~30% higher than CS peak voltage link capacitor, auxiliary winding voltage cannot be clamped
(VCS.pk) at full-load condition. MOSFET peak current (ISW.pk) to reflected output voltage due to the small Lm current,
is converted into VCS,pk as: which induces VS voltage sensing error. Then, frequency
decreases rapidly at the zero-crossing point of line voltage,
VCS. pk  I SW . pk  RS (9) which can cause flicker. To maintain constant frequency
over the whole sinusoidal line voltage, FL7732 has VS
blanking to disable sampling of VS voltage at less than a
According to Equation (1), the transformer turn ratio is particular line voltage by sensing the auxiliary winding.
determined by the sensing resistor and nominal output
current as: Considering the maximum switching frequency at rated
power and VS blanking level, RVS1 and RVS2 are obtained as:
n ps 10.5  I O  RS (10)
where10.5 is a constant.
(VO  VF )n AS  VVS .max
1 t DIS 1 RVS  (13)
  VCS  (11) VVS .max
2 tS 10.5
RVS 1  rVS  RVS 2 (14)

(Design Example) Once VCS,pk is set as 0.5 V, the sensing where VVS.max is the VS value to set the maximum
resistor value is obtained as: switching frequency for constant output current in rated
power and VF is secondary diode forward voltage.
VCS. pk 0.5
RS    0.396
I SW .PK 1.26
1 VVS .bnk  VIN bnk  n AP (15)
RVS 2   (VVS .bnk  )
I VS .bnk RVS
n ps  10.5  0.7  0.396  2.91
where VIN.bnk and nAP are the blanking level of input
voltage and the turn ratio of auxiliary to primary,
respectively. The nAP can be calculated as the ratio of
Step 3. nAS Selection nAS to nPS. IVS.bnk and VVS.bnk are decided internally at
1 µA and 0.545 V.
When VDD voltage is 23 V, FL7732 stops switching
operation due to over-voltage protection (OVP). So nAS can
be determined as follows:
(Design Example) The voltage divider network is
VDD.OVP 23 determined as:
nAS   (12)
VO.OVP VO.OVP (24  0.7)  0.77  2.35
RVS   7.06
where (nAS=NA/NS) is the turns ratio the of secondary to 2.35
auxiliary of transformer. Therefore, VO.OVP can be set by
changing the nAS value. Once VIN.bnk level is set to 50 V, RVS2 is obtained as.

0.77
0.545  50 
1 2.91 )
(Design Example) Once output over-voltage level is set as RVS 2   (0.545 
30 V, nAS is obtained as: 100 10  6 7.06
23  24.86k
n AS   0.77
30 Then RVS1 is determined to be 175.5 kΩ.

Step 4. Resistor Selection (RVS1 and RVS2) It is recommended to place a bypass capacitor of 10 ~ 30 pF
closely between the VS pin and the GND pin to bypass the
The first consideration for RVS1 and RVS2 selection is that VS switching noise and keep the accuracy of the VS sensing for
is 2.35 V at the end of diode current conduction time to CC regulation. The value of the capacitor affects constant-
operate at maximum switching frequency at rated power. current regulation. If a high value of VS capacitor is selected,
The second consideration is VS blanking, as explained the discharge time tDIS becomes longer and the output
below. The output voltage is detected by auxiliary winding current is lower, compared to small VS capacitor.
and a resistive divider connected to the VS pin, as shown in
Figure 7. However, in a single-stage flyback without DC
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.0.4 • 4/17/13 7
AN-9750 APPLICATION NOTE

Step 5. Design the Transformer

The number of primary turns is determined by Faraday’s VOS VRO = (VO + VF )NP /NS

law. Np,min is fixed by the peak value of the minimum line

input voltage across the primary winding and the maximum VRO
on time. The minimum number of turns for the transformer
primary side to avoid the core saturation is given by:

VIN . min . pk  tON VIN.max

N p ,min  (16)
Bsat  Ae
where Ae is the cross-sectional area of the core in m2
VDS in DCM
and Bsat is the saturation flux density in Tesla.
Since the saturation flux density decreases as the Figure 15. Drain Voltage of MOSFET
temperature rises, the high-temperature characteristics
NP
should be considered when it is used in an enclosed case. VDS (max)  VIN . max . pk  (Vo  VF )  VOS (17)
NS
where Vin.max.pk is the maximum line peak voltage.
(Design Example) An RM8 core is selected for the
transformer and the minimum number of turns for the
The rms current (ISW.rms) though the MOSFET is given as:
transformer primary side to avoid the core saturation is
given by:

2  90  7.4  10 6 tON  f S
N p ,min   54.5T I SW .rms  I pk  (18)
0.27  64  10 6 6
Considering the tolerance of the transformer and high
ambient temperature, NP should be selected with a margin (Design Example) Assuming that drain voltage
about 5% ~ 10% to avoid core saturation: overshoot is the same as the reflected output voltage, the
N p  54.5 1.1  59.95T maximum drain voltage across the MOSFET is calculated
as:
Once the turn number of the primary side (NP) is 60
determined as 60 T, the turn number of the secondary side VDS (max)  374   (24  0.7)  2  522V
20
(NS) is obtained by:
The rms current though the MOSFET is
N S  60  2.91  20.5T 7.4  0.065
I SW .rms  1.26   0.357 A
6
Once the turn number of the secondary side (NS) is
determined as 20 T, the auxiliary winding turns (NA) is
Secondary-Side Diode: The maximum reverse voltage and
obtained by:
rms current of the rectifier diode are obtained as:
N A  20  0.77  15.4T NS
VD  VO   Vin. max . pk (19)
NA is determined to be 15 T. NP
Vin. min . pk N P
I D.rms  I SW .rms   (20)
2  VRO N S
Step 6. Calculate the Voltage and Current of
the Switching Devices (Design Example) The diode voltage and current are
obtained as:
Primary-Side MOSFET: The voltage stress of the
MOSFET was discussed when determining the transformer 20
turns ratio. Assuming the drain voltage overshoot is the VD  24   374  148.7V
60
same as the reflected output voltage, the maximum drain
voltage is given as: 127 60
I D.rms  0.357    0.991A
2  74.1 20

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.4 • 4/17/13 8
AN-9750 APPLICATION NOTE

Snubber capacitor voltage at full-load condition is given as:

Step 7. Design RCD Snubber in Primary Side
When the power MOSFET is turned off, there is a high-
VSN  VRO  VOS (21)
voltage spike on the drain due to the transformer leakage
The power dissipated in the snubber network is obtained as:
inductance. This excessive voltage on the MOSFET may
lead to an avalanche breakdown and eventually failure of the 2
V 1 VSN
PSN  SN  Llk  I PK   fS
2
device. Therefore, it is necessary to use an additional (22)
network to clamp the voltage. The RCD snubber circuit and RSN 2 VSN  VRO
its waveform are shown in Figure 16 and Figure 17, where Llk is leakage inductance, VSN is the
respectively. The RCD snubber network absorbs the current snubber capacitor voltage at full load, and RSN is the
in the leakage inductance by turning on the snubber diode snubber resistor.
(DSN) once the MOSFET drain voltage exceeds the cathode
voltage of snubber diode. In the analysis of snubber network,
it is assumed that the snubber capacitor is large enough that The leakage inductance is measured at the switching
its voltage does not change significantly during one frequency on the primary winding with all other windings
switching cycle. The snubber capacitor should be ceramic or shorted. Then, the snubber resistor with proper rated wattage
a material that offers low ESR. Electrolytic or tantalum should be chosen based on the power loss. The maximum
capacitors are unacceptable for these reasons. ripple of the snubber capacitor voltage is obtained as:

VSN
VSN  (23)
VIN.peak n:1 D CSN  RSN  f S
-
+
VSN RSN CSN
Lm
CO In general, 5 ~ 20% ripple of the selected capacitor voltage
+ VOUT
is reasonable. In this snubber design, neither the lossy
- discharge of the inductor nor stray capacitance is considered.
DSN
Llk
(Design Example) Since the voltage overshoot of drain
voltage has been determined to be the same as the
+
reflected output voltage, the snubber voltage is:
VGate VDS
- VSN  VRO  VOS  150V

The leakage inductance is measured as 10 µH. Then the

loss in snubber networking is given as:
Figure 16. Snubber Circuit
1 150
PSN  10 10 6 1.26 2   65 10 3
2 150  75
VDS 1.03W
VOS
VSN
150 2
VRO RSN   21.84k
1.03
To allow 7% ripple on the snubber voltage (150 V):
VIN
150
CSN   10.06nF
0.07 150  21.84 103  65 103

Figure 17. Snubber Waveforms

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.4 • 4/17/13 9
AN-9750 APPLICATION NOTE

Lab Notes
1. Before modifying or soldering/desordering the power 2. In case of LED-short condition, VDD voltage charged
supply, discharge the primary capacitors through the at VDD capacitor should touch VDD off level rapidly to
external bleeding resistor. Otherwise, the PWM IC may stop switching. Therefore, VDD capacitor value is
be destroyed by external high-voltage during the process. recommended under 22 µF.
This device is sensitive to electrostatic discharge (ESD).
To improve the yield, the production line should be ESD
protected as required by ANSI ESD S1.1, ESD S1.4, ESD
S7.1, ESD STM 12.1, and EOS/ESD S6.1 standards.

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.4 • 4/17/13 10
AN-9750 APPLICATION NOTE

Schematic of Design example

Figure 18 shows the schematic of the 16.8 W LED driver design example. RM8 core is used for the transformer. Figure 19
shows the transformer information.

BD1 RM8 Do1

LF1 RS1 RS2
L Vo

CS1
MOV1 CF1 CF2 C1 R1 Np Ns
R2
Co1 Ro1 24V/0.7A
N Co2

F1 DS1
R3
D1

R6
C3 C2 Na CY1

U1
7 COMI VDD 4
RG1 Q1 R4
5
NC Gate 2
C5 8 GND VS 6
3 GND CS 1
R5 C4

RCS1 RCS2

Figure 18. Schematic of the FL7732 17 W Design Example

NA(6 à5)

NP2(1 à2)

NS (7 à8)

NP1(12 à1)

Figure 19. Transformer Winding Structure

No. Winding Pin (S → F) Wire Turns Winding Method

1 NP1 12 à 1 0.25φ 30 Ts Solenoid Winding
2 Insulation: Polyester Tape t = 0.025 mm, 3-Layer
3 NS 7- à 8 0.5φ (TIW) 20 Ts Solenoid Winding
4 Insulation: Polyester Tape t = 0.025 mm, 3-Layer
5 NP2 1à2 0.25φ 30 Ts Solenoid Winding
6 Insulation: Polyester Tape t = 0.025 mm, 3-Layer
7 NA 6à5 0.25φ 15 Ts Solenoid Winding
8 Insulation: Polyester Tape t = 0.025 mm, 3-Layer

Pin Specification Remark

Inductance 12 – 2 750 µH ± 10% 60 kHz, 1 V
Leakage 1–2 6 µH 60 kHz, 1 V Short All Output Pins

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.4 • 4/17/13 11
AN-9750 APPLICATION NOTE

Bill of Materials
Item Part
Part Number Qty. Description Manufacturer
No. Reference
Fairchild
1 BD1 DF06S 1 1.5 A / 600 V Bridge Diode
Semiconductor
2 CF1 MPX AC275V 104K 1 104 / AC275V X-Capacitor Carli
3 CF2 MPX AC275V 473K 1 473 / AC275V X-Capacitor Carli
4 CS1 C1206C103KDRACTU 1 103 / 1 kV SMD Capacitor 3216 Kemet
5 CY1 SCFz2E472M10BW 1 472 / 250V Y-Capacitor Samwha
6 Co1, Co2 KMG 470 µF / 35 V 2 470 µF / 35 V Electrolytic Capacitor Samyoung
7 C1 MPE 630V104K 14S 1 104 / 630 V MPE film Capacitor Sungho
8 C2 KMG 22 µF / 50 V 1 22 µF / 35V Electrolytic Capacitor Samyoung
9 C3 C0805C104K5RACTU 1 104 / 50 V SMD Capacitor 2012 Kemet
10 C4 C0805C200J5GACTU 1 200 / 50V SMD Capacitor 2012 Kemet
11 C5 C0805C225Z3VACTU 1 225 / 25V SMD Capacitor 2012 Kemet
Fairchild
12 DS1 RS1M 1 1000 V / 1 A Ultra Fast recovery Diode
Semiconductor
Fairchild
13 Do1 ES3D 1 200 V / 3 A, Fast Rectifier
Semiconductor
Fairchild
14 D1 1N4003 1 200 V / 1 A, General Purpose Rectifier
Semiconductor
15 F1 SS-5-1A 1 250 V / 1 A Fuse Bussmann
16 LF1 R10402KT00 1 4 mH Inductor, 10Ø Bosung
17 MOV1 SVC 471 D-07A 1 Metal Oxide Varistor Samwha
Fairchild
18 Q1 FDD5N60NZ 1 600 V / 4 A, N-Channel MOSFET
Semiconductor
19 RG1, R6 RC1206JR-0710L 2 10 Ω SMD Resistor 3216 Yageo
20 RS1, RS2 RC1206JR-07100KL 2 100 kΩ SMD Resistor 3216 Yageo
21 Rcs1, Rcs2 RC1206JR-071RL 2 1 Ω SMD Resistor 3216 Yageo
22 Rcs3 RC1206JR-072R4L 1 2.4 Ω SMD Resistor 3216 Yageo
23 Ro1 RC1206JR-0720KL 1 20 KΩ SMD Resistor 3216 Yageo
24 R4 RC1206JR-07150KL 1 150 KΩ SMD Resistor 3216 Yageo
25 R1, R2, R3 RC1206JR-0768KL 3 68 KΩ SMD Resistor 3216 Yageo
26 R5 RC1206JR-0724KL 1 24 KΩ SMD Resistor 3216 Yageo
27 T1 RM8 Core 1 12-Pin, Transformer TDK
Fairchild
28 U1 FL7732M_F116 1 Main PSR Controller
Semiconductor

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.4 • 4/17/13 12
AN-9750 APPLICATION NOTE

Related Datasheets
FL7732 — Single-Stage PFC Primary-Side-Regulation Offline LED Driver
Reference Designs— http://www.fairchildsemi.com/referencedesign/

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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:

1. Life support devices or systems are devices or systems 2. A critical component is any component of a life support
which, (a) are intended for surgical implant into the body, or device or system whose failure to perform can be reasonably
(b) support or sustain life, or (c) whose failure to perform expected to cause the failure of the life support device or
when properly used in accordance with instructions for use system, or to affect its safety or effectiveness.
provided in the labeling, can be reasonably expected to
result in significant injury to the user.

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.4 • 4/17/13 13