RM0432

Reference manual
STM32L4+ Series advanced Arm®-based
32-bit MCUs

Introduction
This reference manual targets application developers. It provides complete information on
how to use the STM32L4+ Series microcontrollers memory and peripherals.
The STM32L4+ Series are families of microcontrollers with different memory sizes,
packages and peripherals.
For ordering information, mechanical and electrical device characteristics, refer to the
corresponding datasheets.
For information on the Arm® Cortex®-M4 core, refer to the Cortex®-M4 Technical Reference
Manual.

Related documents
• Cortex®-M4 Technical Reference Manual, available from: http://infocenter.arm.com
• STM32L4S5xx STM32L4S7xx STM32L4S9xx datasheet
• STM32L4R5xx STM32L4R7xx STM32L4R9xx datasheet
• STM32L4Q5xx datasheet
• STM32L4P5xx datasheet
• STM32F3, STM32F4, STM32L4 and STM32L4+ Series Cortex®-M4 (PM0214)

December 2019 RM0432 Rev 6 1/2301

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Contents RM0432

Contents

1 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
1.1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
1.2 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
1.3 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
1.4 Availability of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

2 System and memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

2.1 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.1.1 I-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
2.1.2 D-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
2.1.3 S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
2.1.4 DMA-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
2.1.5 DMA2D-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
2.1.6 LCD-TFT controller DMA bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
2.1.7 SDMMC1 controller DMA bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
2.1.8 SDMMC2 controller DMA bus (only for STM32L4P5xx and
STM32L4Q5xx devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
2.1.9 GFXMMU-bus (only for STM32L4Rxxx and STM32L4Sxxx devices) . . 89
2.1.10 BusMatrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
2.2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
2.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
2.2.2 Memory map and register boundary addresses . . . . . . . . . . . . . . . . . . 92
2.3 Bit banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
2.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
2.4.1 SRAM2 parity check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
2.4.2 SRAM2 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
2.4.3 SRAM2 Read protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
2.4.4 SRAM2 Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
2.5 Flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
2.6 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
2.6.1 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

3 Embedded Flash memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

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3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

3.2 FLASH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
3.3 FLASH functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
3.3.1 Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
3.3.2 Error code correction (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
3.3.3 Read access latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
3.3.4 Adaptive real-time memory accelerator (ART Accelerator . . . . . . . . . . 122
3.3.5 Flash program and erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . 125
3.3.6 Flash main memory erase sequences . . . . . . . . . . . . . . . . . . . . . . . . . 126
3.3.7 Flash main memory programming sequences . . . . . . . . . . . . . . . . . . . 127
3.3.8 Read-while-write (RWW) available only in Dual-bank mode
(DBANK=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
3.4 FLASH option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
3.4.1 Option bytes description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
3.4.2 Option bytes programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
3.5 FLASH memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
3.5.1 Read protection (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
3.5.2 Proprietary code readout protection (PCROP) . . . . . . . . . . . . . . . . . . 146
3.5.3 Write protection (WRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
3.6 FLASH interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
3.7 FLASH registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
3.7.1 Flash access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . 150
3.7.2 Flash Power-down key register (FLASH_PDKEYR) . . . . . . . . . . . . . . 151
3.7.3 Flash key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
3.7.4 Flash option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . 152
3.7.5 Flash status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
3.7.6 Flash control register (FLASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
3.7.7 Flash ECC register (FLASH_ECCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 157
3.7.8 Flash option register (FLASH_OPTR) . . . . . . . . . . . . . . . . . . . . . . . . . 159
3.7.9 Flash PCROP1 Start address register (FLASH_PCROP1SR) . . . . . . 161
3.7.10 Flash PCROP1 End address register (FLASH_PCROP1ER) . . . . . . . 162
3.7.11 Flash WRP1 area A address register (FLASH_WRP1AR) . . . . . . . . . 162
3.7.12 Flash WRP2 area A address register (FLASH_WRP2AR) . . . . . . . . . 163
3.7.13 Flash PCROP2 Start address register (FLASH_PCROP2SR) . . . . . . 164
3.7.14 Flash PCROP2 End address register (FLASH_PCROP2ER) . . . . . . . 164
3.7.15 Flash WRP1 area B address register (FLASH_WRP1BR) . . . . . . . . . 165
3.7.16 Flash WRP2 area B address register (FLASH_WRP2BR) . . . . . . . . . 165

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3.7.17 Flash configuration register (FLASH_CFGR) . . . . . . . . . . . . . . . . . . . 166

3.7.18 FLASH register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

4 Firewall (FW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
4.2 Firewall main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
4.3 Firewall functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
4.3.1 Firewall AMBA bus snoop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
4.3.2 Functional requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
4.3.3 Firewall segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
4.3.4 Segment accesses and properties . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
4.3.5 Firewall initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
4.3.6 Firewall states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
4.4 Firewall registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
4.4.1 Code segment start address (FW_CSSA) . . . . . . . . . . . . . . . . . . . . . . 176
4.4.2 Code segment length (FW_CSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
4.4.3 Non-volatile data segment start address (FW_NVDSSA) . . . . . . . . . . 177
4.4.4 Non-volatile data segment length (FW_NVDSL) . . . . . . . . . . . . . . . . . 177
4.4.5 Volatile data segment start address (FW_VDSSA) . . . . . . . . . . . . . . . 178
4.4.6 Volatile data segment length (FW_VDSL) . . . . . . . . . . . . . . . . . . . . . . 178
4.4.7 Configuration register (FW_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
4.4.8 Firewall register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

5 Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

5.1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
5.1.1 Independent analog peripherals supply . . . . . . . . . . . . . . . . . . . . . . . . 184
5.1.2 Independent I/O supply rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
5.1.3 Independent USB transceivers supply . . . . . . . . . . . . . . . . . . . . . . . . . 185
5.1.4 Independent DSI supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
5.1.5 Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
5.1.6 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
5.1.7 VDD12 domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
5.1.8 Dynamic voltage scaling management . . . . . . . . . . . . . . . . . . . . . . . . 189
5.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
5.2.1 Power-on reset (POR) / power-down reset (PDR) / brown-out reset
(BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
5.2.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . 193

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5.2.3 Peripheral Voltage Monitoring (PVM) . . . . . . . . . . . . . . . . . . . . . . . . . 194

5.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
5.3.1 Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
5.3.2 Low-power run mode (LP run) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
5.3.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
5.3.4 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
5.3.5 Low-power sleep mode (LP sleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
5.3.6 Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
5.3.7 Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
5.3.8 Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
5.3.9 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
5.3.10 Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
5.3.11 Auto-wakeup from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . 216
5.4 PWR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
5.4.1 Power control register 1 (PWR_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . 217
5.4.2 Power control register 2 (PWR_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . 218
5.4.3 Power control register 3 (PWR_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . 219
5.4.4 Power control register 4 (PWR_CR4) . . . . . . . . . . . . . . . . . . . . . . . . . 221
5.4.5 Power status register 1 (PWR_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 222
5.4.6 Power status register 2 (PWR_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 223
5.4.7 Power status clear register (PWR_SCR) . . . . . . . . . . . . . . . . . . . . . . . 224
5.4.8 Power Port A pull-up control register (PWR_PUCRA) . . . . . . . . . . . . . 225
5.4.9 Power Port A pull-down control register (PWR_PDCRA) . . . . . . . . . . 226
5.4.10 Power Port B pull-up control register (PWR_PUCRB) . . . . . . . . . . . . . 226
5.4.11 Power Port B pull-down control register (PWR_PDCRB) . . . . . . . . . . 227
5.4.12 Power Port C pull-up control register (PWR_PUCRC) . . . . . . . . . . . . 227
5.4.13 Power Port C pull-down control register (PWR_PDCRC) . . . . . . . . . . 228
5.4.14 Power Port D pull-up control register (PWR_PUCRD) . . . . . . . . . . . . 228
5.4.15 Power Port D pull-down control register (PWR_PDCRD) . . . . . . . . . . 229
5.4.16 Power Port E pull-up control register (PWR_PUCRE) . . . . . . . . . . . . . 229
5.4.17 Power Port E pull-down control register (PWR_PDCRE) . . . . . . . . . . 230
5.4.18 Power Port F pull-up control register (PWR_PUCRF) . . . . . . . . . . . . . 230
5.4.19 Power Port F pull-down control register (PWR_PDCRF) . . . . . . . . . . 231
5.4.20 Power Port G pull-up control register (PWR_PUCRG) . . . . . . . . . . . . 231
5.4.21 Power Port G pull-down control register (PWR_PDCRG) . . . . . . . . . . 232
5.4.22 Power Port H pull-up control register (PWR_PUCRH) . . . . . . . . . . . . 232
5.4.23 Power Port H pull-down control register (PWR_PDCRH) . . . . . . . . . . 233

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5.4.24 Power Port I pull-up control register (PWR_PUCRI) . . . . . . . . . . . . . . 233

5.4.25 Power Port I pull-down control register (PWR_PDCRI) . . . . . . . . . . . . 234
5.4.26 PWR control register (PWR_CR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
5.4.27 PWR register map and reset value table . . . . . . . . . . . . . . . . . . . . . . . 236

6 Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

6.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
6.1.1 Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
6.1.2 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
6.1.3 Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
6.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
6.2.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
6.2.2 HSI16 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
6.2.3 MSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
6.2.4 HSI48 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
6.2.5 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
6.2.6 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
6.2.7 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
6.2.8 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
6.2.9 Clock source frequency versus voltage scaling . . . . . . . . . . . . . . . . . . 251
6.2.10 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
6.2.11 Clock security system on LSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
6.2.12 ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
6.2.13 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
6.2.14 Timer clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
6.2.15 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
6.2.16 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
6.2.17 Internal/external clock measurement with TIM15/TIM16/TIM17 . . . . . 254
6.2.18 Peripheral clock enable register
(RCC_AHBxENR, RCC_APBxENRy) . . . . . . . . . . . . . . . . . . . . . . . . . 257
6.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
6.4 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
6.4.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
6.4.2 Internal clock sources calibration register (RCC_ICSCR) . . . . . . . . . . 261
6.4.3 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 261
6.4.4 PLL configuration register (RCC_PLLCFGR) . . . . . . . . . . . . . . . . . . . 264
6.4.5 PLLSAI1 configuration register (RCC_PLLSAI1CFGR) . . . . . . . . . . . 266

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6.4.6 PLLSAI2 configuration register (RCC_PLLSAI2CFGR) . . . . . . . . . . . 270

6.4.7 Clock interrupt enable register (RCC_CIER) . . . . . . . . . . . . . . . . . . . . 272
6.4.8 Clock interrupt flag register (RCC_CIFR) . . . . . . . . . . . . . . . . . . . . . . 274
6.4.9 Clock interrupt clear register (RCC_CICR) . . . . . . . . . . . . . . . . . . . . . 275
6.4.10 AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . . . . . . . . . . . 277
6.4.11 AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . . . . . . . . . . . 278
6.4.12 AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . . . . . . . . . . . 280
6.4.13 APB1 peripheral reset register 1 (RCC_APB1RSTR1) . . . . . . . . . . . . 281
6.4.14 APB1 peripheral reset register 2 (RCC_APB1RSTR2) . . . . . . . . . . . . 283
6.4.15 APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 284
6.4.16 AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . . . . . . 286
6.4.17 AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . . . . . . 287
6.4.18 AHB3 peripheral clock enable register(RCC_AHB3ENR) . . . . . . . . . . 289
6.4.19 APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . . . . . 290
6.4.20 APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . . . . . 292
6.4.21 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 294
6.4.22 AHB1 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB1SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
6.4.23 AHB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
6.4.24 AHB3 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB3SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
6.4.25 APB1 peripheral clocks enable in Sleep and Stop modes register 1
(RCC_APB1SMENR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
6.4.26 APB1 peripheral clocks enable in Sleep and Stop modes register 2
(RCC_APB1SMENR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
6.4.27 APB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_APB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
6.4.28 Peripherals independent clock configuration register (RCC_CCIPR) . 305
6.4.29 Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . 308
6.4.30 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
6.4.31 Clock recovery RC register (RCC_CRRCR) . . . . . . . . . . . . . . . . . . . . 312
6.4.32 Peripherals independent clock configuration register (RCC_CCIPR2) 313
6.4.33 OCTOSPI delay configuration register (RCC_DLYCFGR) . . . . . . . . . 315
6.4.34 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

7 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
7.2 CRS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

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7.3 CRS implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

7.4 CRS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
7.4.1 CRS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
7.4.2 Synchronization input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
7.4.3 Frequency error measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
7.4.4 Frequency error evaluation and automatic trimming . . . . . . . . . . . . . . 324
7.4.5 CRS initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
7.5 CRS low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
7.6 CRS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
7.7 CRS registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
7.7.1 CRS control register (CRS_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
7.7.2 CRS configuration register (CRS_CFGR) . . . . . . . . . . . . . . . . . . . . . . 327
7.7.3 CRS interrupt and status register (CRS_ISR) . . . . . . . . . . . . . . . . . . . 328
7.7.4 CRS interrupt flag clear register (CRS_ICR) . . . . . . . . . . . . . . . . . . . . 330
7.7.5 CRS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

8 General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
8.2 GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
8.3 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
8.3.1 General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
8.3.2 I/O pin alternate function multiplexer and mapping . . . . . . . . . . . . . . . 335
8.3.3 I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
8.3.4 I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
8.3.5 I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
8.3.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
8.3.7 I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
8.3.8 External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
8.3.9 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
8.3.10 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
8.3.11 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
8.3.12 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
8.3.13 Using the HSE or LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . . 340
8.3.14 Using the GPIO pins in the RTC supply domain . . . . . . . . . . . . . . . . . 340
8.3.15 Using PH3 as GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
8.4 GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

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8.4.1 GPIO port mode register (GPIOx_MODER)

(x =A to I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
8.4.2 GPIO port output type register (GPIOx_OTYPER)
(x = A to I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
8.4.3 GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
8.4.5 GPIO port input data register (GPIOx_IDR)
(x = A to I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
8.4.6 GPIO port output data register (GPIOx_ODR)
(x = A to I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
8.4.7 GPIO port bit set/reset register (GPIOx_BSRR)
(x = A to I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
8.4.8 GPIO port configuration lock register (GPIOx_LCKR)
(x = A to I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
8.4.9 GPIO alternate function low register (GPIOx_AFRL)
(x = A to I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
8.4.10 GPIO alternate function high register (GPIOx_AFRH)
(x = A to I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
8.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A to I) . . . . . . . . . . . . . 348
8.4.12 GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

9 System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 351

9.1 SYSCFG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
9.2 SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
9.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . . . . . . . 351
9.2.2 SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . . . . . . . . . 352
9.2.3 SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
9.2.4 SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
9.2.5 SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
9.2.6 SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
9.2.7 SYSCFG SRAM2 control and status register (SYSCFG_SCSR) . . . . 360
9.2.8 SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . . . . . . . . . 361
9.2.9 SYSCFG SRAM2 write protection register (SYSCFG_SWPR) . . . . . . 362
9.2.10 SYSCFG SRAM2 key register (SYSCFG_SKR) . . . . . . . . . . . . . . . . . 362
9.2.11 SYSCFG SRAM2 write protection register 2 (SYSCFG_SWPR2) . . . 363

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9.2.12 SYSCFG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

10 Peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
10.2 Connection summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
10.3 Interconnection details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
10.3.1 From timer (TIM1/TIM2/TIM3/TIM4/TIM5/TIM8/TIM15/TIM16/TIM17)
to timer (TIM1/TIM2/TIM3/TIM4/TIM5/TIM8/TIM15) . . . . . . . . . . . . . . 367
10.3.2 From timer (TIM1/TIM2/TIM3/TIM4/TIM6/TIM8/TIM15) and EXTI
to ADC (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
10.3.3 From ADC to timer (TIM1/TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
10.3.4 From timer (TIM2/TIM4/TIM5/TIM6/TIM7/TIM8) and EXTI to DAC
(DAC1/DAC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
10.3.5 From timer (TIM1/TIM3/TIM4/TIM6/TIM7/TIM8/TIM16/LPTIM1/LPTIM2)
and EXTI to DFSDM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
10.3.6 From DFSDM1 to timer (TIM1/TIM8/TIM15/TIM16/TIM17) . . . . . . . . . 370
10.3.7 From HSE, LSE, LSI, MSI, MCO, RTC to timer
(TIM2/TIM15/TIM16/TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
10.3.8 From RTC, COMP1, COMP2 to low-power timer (LPTIM1/LPTIM2) . . 371
10.3.9 From timer (TIM1/TIM2/TIM3/TIM8/TIM15) to comparators
(COMP1/COMP2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
10.3.10 From ADC (ADC1) to ADC (ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
10.3.11 From USB to timer (TIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
10.3.12 From internal analog source to ADC and OPAMP
(OPAMP1/OPAM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
10.3.13 From comparators (COMP1/COMP2) to timers
(TIM1/TIM2/TIM3/TIM8/TIM15/TIM16/TIM17) . . . . . . . . . . . . . . . . . . . 373
10.3.14 From system errors to timers (TIM1/TIM8/TIM15/TIM16/TIM17) . . . . 373
10.3.15 From timers (TIM16/TIM17) to IRTIM . . . . . . . . . . . . . . . . . . . . . . . . . 374
10.3.16 From ADC (ADC1/ADC2) to DFSDM . . . . . . . . . . . . . . . . . . . . . . . . . . 374

11 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 375

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
11.2 DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
11.3 DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
11.3.1 DMA1 and DMA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
11.3.2 DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
11.4 DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
11.4.1 DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376

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11.4.2 DMA pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

11.4.3 DMA transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
11.4.4 DMA arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
11.4.5 DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
11.4.6 DMA data width, alignment and endianness . . . . . . . . . . . . . . . . . . . . 384
11.4.7 DMA error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
11.5 DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
11.6 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
11.6.1 DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 386
11.6.2 DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 389
11.6.3 DMA channel x configuration register (DMA_CCRx) . . . . . . . . . . . . . . 390
11.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx) . 393
11.6.5 DMA channel x peripheral address register (DMA_CPARx) . . . . . . . . 393
11.6.6 DMA channel x memory address register (DMA_CMARx) . . . . . . . . . 394
11.6.7 DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

12 DMA request multiplexer (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . 397

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
12.2 DMAMUX main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
12.3 DMAMUX implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
12.3.1 DMAMUX instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
12.3.2 DMAMUX mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
12.4 DMAMUX functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
12.4.1 DMAMUX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
12.4.2 DMAMUX signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
12.4.3 DMAMUX channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
12.4.4 DMAMUX request line multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
12.4.5 DMAMUX request generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
12.5 DMAMUX interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
12.6 DMAMUX registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
12.6.1 DMAMUX request line multiplexer channel x configuration register
(DMAMUX_CxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
12.6.2 DMAMUX request line multiplexer interrupt channel status register
(DMAMUX_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
12.6.3 DMAMUX request line multiplexer interrupt clear flag register
(DMAMUX_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

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12.6.4 DMAMUX request generator channel x configuration register

(DMAMUX_RGxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
12.6.5 DMAMUX request generator interrupt status register
(DMAMUX_RGSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
12.6.6 DMAMUX request generator interrupt clear flag register
(DMAMUX_RGCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
12.6.7 DMAMUX register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

13 Chrom-ART Accelerator controller (DMA2D) . . . . . . . . . . . . . . . . . . . 416

13.1 DMA2D introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
13.2 DMA2D main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
13.3 DMA2D functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
13.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
13.3.2 DMA2D control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
13.3.3 DMA2D foreground and background FIFOs . . . . . . . . . . . . . . . . . . . . 418
13.3.4 DMA2D foreground and background pixel format converter (PFC) . . . 419
13.3.5 DMA2D foreground and background CLUT interface . . . . . . . . . . . . . 421
13.3.6 DMA2D blender . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
13.3.7 DMA2D output PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
13.3.8 DMA2D output FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
13.3.9 DMA2D output FIFO byte reordering . . . . . . . . . . . . . . . . . . . . . . . . . . 424
13.3.10 DMA2D AHB master port timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
13.3.11 DMA2D transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
13.3.12 DMA2D configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
13.3.13 DMA2D transfer control (start, suspend, abort and completion) . . . . . 430
13.3.14 Watermark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
13.3.15 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
13.3.16 AHB dead time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
13.4 DMA2D interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
13.5 DMA2D registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
13.5.1 DMA2D control register (DMA2D_CR) . . . . . . . . . . . . . . . . . . . . . . . . 432
13.5.2 DMA2D interrupt status register (DMA2D_ISR) . . . . . . . . . . . . . . . . . 434
13.5.3 DMA2D interrupt flag clear register (DMA2D_IFCR) . . . . . . . . . . . . . . 435
13.5.4 DMA2D foreground memory address register (DMA2D_FGMAR) . . . 435
13.5.5 DMA2D foreground offset register (DMA2D_FGOR) . . . . . . . . . . . . . . 436
13.5.6 DMA2D background memory address register (DMA2D_BGMAR) . . 436
13.5.7 DMA2D background offset register (DMA2D_BGOR) . . . . . . . . . . . . . 437

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13.5.8 DMA2D foreground PFC control register (DMA2D_FGPFCCR) . . . . . 438

13.5.9 DMA2D foreground color register (DMA2D_FGCOLR) . . . . . . . . . . . . 440
13.5.10 DMA2D background PFC control register (DMA2D_BGPFCCR) . . . . 441
13.5.11 DMA2D background color register (DMA2D_BGCOLR) . . . . . . . . . . . 443
13.5.12 DMA2D foreground CLUT memory address register
(DMA2D_FGCMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
13.5.13 DMA2D background CLUT memory address register
(DMA2D_BGCMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
13.5.14 DMA2D output PFC control register (DMA2D_OPFCCR) . . . . . . . . . . 444
13.5.15 DMA2D output color register (DMA2D_OCOLR) . . . . . . . . . . . . . . . . . 445
13.5.16 DMA2D output memory address register (DMA2D_OMAR) . . . . . . . . 447
13.5.17 DMA2D output offset register (DMA2D_OOR) . . . . . . . . . . . . . . . . . . 447
13.5.18 DMA2D number of line register (DMA2D_NLR) . . . . . . . . . . . . . . . . . 448
13.5.19 DMA2D line watermark register (DMA2D_LWR) . . . . . . . . . . . . . . . . . 448
13.5.20 DMA2D AHB master timer configuration register (DMA2D_AMTCR) . 449
13.5.21 DMA2D foreground CLUT (DMA2D_FGCLUT[y]) . . . . . . . . . . . . . . . . 449
13.5.22 DMA2D background CLUT (DMA2D_BGCLUT[y]) . . . . . . . . . . . . . . . 450
13.5.23 DMA2D register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451

14 Chrom-GRC™ (GFXMMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
14.2 Chrom-GRC™ main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
14.3 Chrom-GRC™ functional and architectural description . . . . . . . . . . . . . 454
14.3.1 Virtual memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
14.3.2 MMU architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
14.4 Graphic MMU interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
14.5 Graphic MMU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
14.5.1 Graphic MMU configuration register (GFXMMU_CR) . . . . . . . . . . . . . 461
14.5.2 Graphic MMU status register (GFXMMU_SR) . . . . . . . . . . . . . . . . . . . 462
14.5.3 Graphic MMU flag clear register (GFXMMU_FCR) . . . . . . . . . . . . . . . 462
14.5.4 Graphic MMU default value register (GFXMMU_DVR) . . . . . . . . . . . . 463
14.5.5 Graphic MMU buffer 0 configuration register (GFXMMU_B0CR) . . . . 463
14.5.6 Graphic MMU buffer 1 configuration register (GFXMMU_B1CR) . . . . 464
14.5.7 Graphic MMU buffer 2 configuration register (GFXMMU_B2CR) . . . . 464
14.5.8 Graphic MMU buffer 3 configuration register (GFXMMU_B3CR) . . . . 465
14.5.9 Graphic MMU LUT entry x low (GFXMMU_LUTxL) . . . . . . . . . . . . . . . 465
14.5.10 Graphic MMU LUT entry x high (GFXMMU_LUTxH) . . . . . . . . . . . . . . 465

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14.5.11 Graphic MMU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467

15 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . 468

15.1 NVIC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
15.2 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
15.3 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469

16 Extended interrupts and events controller (EXTI) . . . . . . . . . . . . . . . 477

16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
16.2 EXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
16.3 EXTI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
16.3.1 EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
16.3.2 Wakeup event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
16.3.3 Peripherals asynchronous Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 479
16.3.4 Hardware interrupt selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
16.3.5 Hardware event selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
16.3.6 Software interrupt/event selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
16.4 EXTI interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
16.5 EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
16.5.1 Interrupt mask register 1 (EXTI_IMR1) . . . . . . . . . . . . . . . . . . . . . . . . 482
16.5.2 Event mask register 1 (EXTI_EMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 482
16.5.3 Rising trigger selection register 1 (EXTI_RTSR1) . . . . . . . . . . . . . . . . 482
16.5.4 Falling trigger selection register 1 (EXTI_FTSR1) . . . . . . . . . . . . . . . . 483
16.5.5 Software interrupt event register 1 (EXTI_SWIER1) . . . . . . . . . . . . . . 484
16.5.6 Pending register 1 (EXTI_PR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
16.5.7 Interrupt mask register 2 (EXTI_IMR2) . . . . . . . . . . . . . . . . . . . . . . . . 485
16.5.8 Event mask register 2 (EXTI_EMR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 486
16.5.9 Rising trigger selection register 2 (EXTI_RTSR2) . . . . . . . . . . . . . . . . 486
16.5.10 Falling trigger selection register 2 (EXTI_FTSR2) . . . . . . . . . . . . . . . . 487
16.5.11 Software interrupt event register 2 (EXTI_SWIER2) . . . . . . . . . . . . . . 487
16.5.12 Pending register 2 (EXTI_PR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
16.5.13 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

17 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . 490

17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
17.2 CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490

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17.3 CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

17.3.1 CRC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
17.3.2 CRC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
17.3.3 CRC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
17.4 CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
17.4.1 CRC data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
17.4.2 CRC independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . 493
17.4.3 CRC control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
17.4.4 CRC initial value (CRC_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
17.4.5 CRC polynomial (CRC_POL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
17.4.6 CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

18 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . 496

18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
18.2 FMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
18.3 FMC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
18.4 FMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
18.5 AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
18.5.1 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 498
18.6 External device address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
18.6.1 NOR/PSRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
18.6.2 NAND Flash memory address mapping . . . . . . . . . . . . . . . . . . . . . . . 501
18.7 NOR Flash/PSRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
18.7.1 External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
18.7.2 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 505
18.7.3 General timing rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
18.7.4 NOR Flash/PSRAM controller asynchronous transactions . . . . . . . . . 507
18.7.5 Synchronous transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
18.7.6 NOR/PSRAM controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
18.8 NAND Flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
18.8.1 External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
18.8.2 NAND Flash supported memories and transactions . . . . . . . . . . . . . . 543
18.8.3 Timing diagrams for NAND Flash memory . . . . . . . . . . . . . . . . . . . . . 543
18.8.4 NAND Flash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
18.8.5 NAND Flash prewait functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545

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18.8.6 Computation of the error correction code (ECC)

in NAND Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
18.8.7 NAND Flash controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
18.8.8 FMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553

19 Octo-SPI interface (OCTOSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555

19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
19.2 OCTOSPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
19.3 OCTOSPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
19.4 OCTOSPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
19.4.1 OCTOSPI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
19.4.2 OCTOSPI interface to memory modes . . . . . . . . . . . . . . . . . . . . . . . . 558
19.4.3 OCTOSPI Regular-command mode . . . . . . . . . . . . . . . . . . . . . . . . . . 558
19.4.4 OCTOSPI Regular-command mode signal interface . . . . . . . . . . . . . . 562
19.4.5 HyperBus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
19.4.6 Common functionality between the Regular-command and
HyperBus modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
19.4.7 OCTOSPI operating modes introduction . . . . . . . . . . . . . . . . . . . . . . . 570
19.4.8 OCTOSPI Indirect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
19.4.9 OCTOSPI Status-flag polling mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
19.4.10 OCTOSPI Memory-mapped mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
19.4.11 OCTOSPI configuration introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 574
19.4.12 OCTOSPI system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
19.4.13 OCTOSPI device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
19.4.14 OCTOSPI Regular-command mode configuration . . . . . . . . . . . . . . . . 575
19.4.15 OCTOSPI HyperBus mode configuration . . . . . . . . . . . . . . . . . . . . . . 578
19.4.16 OCTOSPI error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
19.4.17 OCTOSPI busy bit and abort functionality . . . . . . . . . . . . . . . . . . . . . . 579
19.4.18 OCTOSPI reconfiguration or deactivation . . . . . . . . . . . . . . . . . . . . . . 580
19.4.19 nCS behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
19.5 OCTOSPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
19.6 OCTOSPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
19.6.1 OCTOSPI control register (OCTOSPI_CR) . . . . . . . . . . . . . . . . . . . . . 582
19.6.2 OCTOSPI device configuration register 1 (OCTOSPI_DCR1) . . . . . . 585
19.6.3 OCTOSPI device configuration register 2 (OCTOSPI_DCR2) . . . . . . 586
19.6.4 OCTOSPI device configuration register 3 (OCTOSPI_DCR3) . . . . . . 587
19.6.5 OCTOSPI device configuration register 4 (OCTOSPI_DCR4) . . . . . . 588

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19.6.6 OCTOSPI status register (OCTOSPI_SR) . . . . . . . . . . . . . . . . . . . . . . 588

19.6.7 OCTOSPI flag clear register (OCTOSPI_FCR) . . . . . . . . . . . . . . . . . . 589
19.6.8 OCTOSPI data length register (OCTOSPI_DLR) . . . . . . . . . . . . . . . . 590
19.6.9 OCTOSPI address register (OCTOSPI_AR) . . . . . . . . . . . . . . . . . . . . 590
19.6.10 OCTOSPI data register (OCTOSPI_DR) . . . . . . . . . . . . . . . . . . . . . . . 591
19.6.11 OCTOSPI polling status mask register (OCTOSPI _PSMKR) . . . . . . . 591
19.6.12 OCTOSPI polling status match register (OCTOSPI_PSMAR) . . . . . . . 592
19.6.13 OCTOSPI polling interval register (OCTOSPI_PIR) . . . . . . . . . . . . . . 592
19.6.14 OCTOSPI communication configuration register (OCTOSPI_CCR) . . 592
19.6.15 OCTOSPI timing configuration register (OCTOSPI_TCR) . . . . . . . . . . 595
19.6.16 OCTOSPI instruction register (OCTOSPI_IR) . . . . . . . . . . . . . . . . . . . 595
19.6.17 OCTOSPI alternate bytes register (OCTOSPI_ABR) . . . . . . . . . . . . . 596
19.6.18 OCTOSPI low-power timeout register (OCTOSPI_LPTR) . . . . . . . . . . 596
19.6.19 OCTOSPI write communication configuration register
(OCTOSPI_WCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
19.6.20 OCTOSPI write timing configuration register (OCTOSPI_WTCR) . . . . 599
19.6.21 OCTOSPI write instruction register (OCTOSPI_WIR) . . . . . . . . . . . . . 600
19.6.22 OCTOSPI write alternate bytes register (OCTOSPI_WABR) . . . . . . . 600
19.6.23 OCTOSPI HyperBus latency configuration register
(OCTOSPI_HLCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
19.6.24 OCTOSPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601

20 OCTOSPI I/O manager (OCTOSPIM) . . . . . . . . . . . . . . . . . . . . . . . . . . 604

20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
20.2 OCTOSPIM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
20.3 OCTOSPIM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
20.4 OCTOSPIM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
20.4.1 OCTOSPIM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
20.4.2 OCTOSPIM matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
20.4.3 OCTOSPIM multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
20.5 OCTOSPI I/O manager registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
20.5.1 OCTOSPI I/O manager control register (OCTOSPIM_CR) . . . . . . . . . 608
20.5.2 OCTOSPI I/O manager Port n configuration register
(OCTOSPIM_PnCR) (n=1 to 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
20.5.3 OCTOSPIM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611

21 Analog-to-digital converters (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 612

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21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612

21.2 ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
21.3 ADC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
21.4 ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
21.4.1 ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
21.4.2 ADC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
21.4.3 ADC clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
21.4.4 ADC1/2 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
21.4.5 Slave AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
21.4.6 ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator
(ADVREGEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
21.4.7 Single-ended and differential input channels . . . . . . . . . . . . . . . . . . . . 622
21.4.8 Calibration (ADCAL, ADCALDIF, ADC_CALFACT) . . . . . . . . . . . . . . . 622
21.4.9 ADC on-off control (ADEN, ADDIS, ADRDY) . . . . . . . . . . . . . . . . . . . . 625
21.4.10 Constraints when writing the ADC control bits . . . . . . . . . . . . . . . . . . . 626
21.4.11 Channel selection (SQRx, JSQRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
21.4.12 Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . . 628
21.4.13 Single conversion mode (CONT=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
21.4.14 Continuous conversion mode (CONT=1) . . . . . . . . . . . . . . . . . . . . . . . 629
21.4.15 Starting conversions (ADSTART, JADSTART) . . . . . . . . . . . . . . . . . . . 630
21.4.16 ADC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
21.4.17 Stopping an ongoing conversion (ADSTP, JADSTP) . . . . . . . . . . . . . . 631
21.4.18 Conversion on external trigger and trigger polarity
(EXTSEL, EXTEN,JEXTSEL, JEXTEN) . . . . . . . . . . . . . . . . . . . . . . . 633
21.4.19 Injected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
21.4.20 Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . . . . . . . . . 637
21.4.21 Queue of context for injected conversions . . . . . . . . . . . . . . . . . . . . . . 638
21.4.22 Programmable resolution (RES) - fast conversion mode . . . . . . . . . . 646
21.4.23 End of conversion, end of sampling phase (EOC, JEOC, EOSMP) . . 647
21.4.24 End of conversion sequence (EOS, JEOS) . . . . . . . . . . . . . . . . . . . . . 647
21.4.25 Timing diagrams example (single/continuous modes,
hardware/software triggers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
21.4.26 Data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
21.4.27 Managing conversions using the DFSDM . . . . . . . . . . . . . . . . . . . . . . 655
21.4.28 Dynamic low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
21.4.29 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL,
AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) . . . . . 661
21.4.30 Oversampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665

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21.4.31 Dual ADC modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671

21.4.32 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
21.4.33 VBAT supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
21.4.34 Monitoring the internal voltage reference . . . . . . . . . . . . . . . . . . . . . . 687
21.5 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
21.6 ADC registers (for each ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
21.6.1 ADC interrupt and status register (ADC_ISR) . . . . . . . . . . . . . . . . . . . 690
21.6.2 ADC interrupt enable register (ADC_IER) . . . . . . . . . . . . . . . . . . . . . . 692
21.6.3 ADC control register (ADC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
21.6.4 ADC configuration register (ADC_CFGR) . . . . . . . . . . . . . . . . . . . . . . 697
21.6.5 ADC configuration register 2 (ADC_CFGR2) . . . . . . . . . . . . . . . . . . . 701
21.6.6 ADC sample time register 1 (ADC_SMPR1) . . . . . . . . . . . . . . . . . . . . 703
21.6.7 ADC sample time register 2 (ADC_SMPR2) . . . . . . . . . . . . . . . . . . . . 704
21.6.8 ADC watchdog threshold register 1 (ADC_TR1) . . . . . . . . . . . . . . . . . 705
21.6.9 ADC watchdog threshold register 2 (ADC_TR2) . . . . . . . . . . . . . . . . . 706
21.6.10 ADC watchdog threshold register 3 (ADC_TR3) . . . . . . . . . . . . . . . . . 706
21.6.11 ADC regular sequence register 1 (ADC_SQR1) . . . . . . . . . . . . . . . . . 707
21.6.12 ADC regular sequence register 2 (ADC_SQR2) . . . . . . . . . . . . . . . . . 708
21.6.13 ADC regular sequence register 3 (ADC_SQR3) . . . . . . . . . . . . . . . . . 709
21.6.14 ADC regular sequence register 4 (ADC_SQR4) . . . . . . . . . . . . . . . . . 710
21.6.15 ADC regular data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . 711
21.6.16 ADC injected sequence register (ADC_JSQR) . . . . . . . . . . . . . . . . . . 711
21.6.17 ADC offset y register (ADC_OFRy) . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
21.6.18 ADC injected channel y data register (ADC_JDRy) . . . . . . . . . . . . . . . 714
21.6.19 ADC Analog Watchdog 2 Configuration Register (ADC_AWD2CR) . . 714
21.6.20 ADC Analog Watchdog 3 Configuration Register (ADC_AWD3CR) . . 715
21.6.21 ADC Differential mode Selection Register (ADC_DIFSEL) . . . . . . . . . 715
21.6.22 ADC Calibration Factors (ADC_CALFACT) . . . . . . . . . . . . . . . . . . . . . 716
21.7 ADC common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
21.7.1 ADC common status register (ADC_CSR) . . . . . . . . . . . . . . . . . . . . . 716
21.7.2 ADC common control register (ADC_CCR) . . . . . . . . . . . . . . . . . . . . . 718
21.7.3 ADC common regular data register for dual mode (ADC_CDR) . . . . . 721
21.8 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721

22 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725

22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725

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22.2 DAC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725

22.3 DAC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
22.4 DAC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
22.4.1 DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
22.4.2 DAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
22.4.3 DAC data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
22.4.4 DAC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
22.4.5 DAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
22.4.6 DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
22.4.7 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732
22.4.8 DAC noise generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732
22.4.9 DAC triangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
22.4.10 DAC channel modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
22.4.11 DAC channel buffer calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
22.4.12 Dual DAC channel conversion modes (if dual channels are
available) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
22.5 DAC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
22.6 DAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
22.7 DAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
22.7.1 DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
22.7.2 DAC software trigger register (DAC_SWTRGR) . . . . . . . . . . . . . . . . . 748
22.7.3 DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
22.7.4 DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
22.7.5 DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
22.7.6 DAC channel2 12-bit right aligned data holding register
(DAC_DHR12R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
22.7.7 DAC channel2 12-bit left aligned data holding register
(DAC_DHR12L2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
22.7.8 DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
22.7.9 Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
22.7.10 Dual DAC 12-bit left aligned data holding register
(DAC_DHR12LD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
22.7.11 Dual DAC 8-bit right aligned data holding register
(DAC_DHR8RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753

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22.7.12 DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 753

22.7.13 DAC channel2 data output register (DAC_DOR2) . . . . . . . . . . . . . . . . 754
22.7.14 DAC status register (DAC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
22.7.15 DAC calibration control register (DAC_CCR) . . . . . . . . . . . . . . . . . . . 756
22.7.16 DAC mode control register (DAC_MCR) . . . . . . . . . . . . . . . . . . . . . . . 756
22.7.17 DAC channel1 sample and hold sample time register
(DAC_SHSR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
22.7.18 DAC channel2 sample and hold sample time register
(DAC_SHSR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
22.7.19 DAC sample and hold time register (DAC_SHHR) . . . . . . . . . . . . . . . 759
22.7.20 DAC sample and hold refresh time register (DAC_SHRR) . . . . . . . . . 759
22.7.21 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761

23 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . 763

23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763
23.2 VREFBUF functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763
23.3 VREFBUF registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764
23.3.1 VREFBUF control and status register (VREFBUF_CSR) . . . . . . . . . . 764
23.3.2 VREFBUF calibration control register (VREFBUF_CCR) . . . . . . . . . . 765
23.3.3 VREFBUF register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765

24 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766

24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
24.2 DCMI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
24.3 DCMI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
24.3.1 DCMI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
24.3.2 DCMI pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
24.3.3 DCMI clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
24.3.4 DCMI DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768
24.3.5 DCMI physical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768
24.3.6 DCMI synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
24.3.7 DCMI capture modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772
24.3.8 DCMI crop feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773
24.3.9 DCMI JPEG format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
24.3.10 DCMI FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
24.3.11 DCMI data format description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
24.4 DCMI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777

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24.5 DCMI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778

24.5.1 DCMI control register (DCMI_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
24.5.2 DCMI status register (DCMI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
24.5.3 DCMI raw interrupt status register (DCMI_RIS) . . . . . . . . . . . . . . . . . 781
24.5.4 DCMI interrupt enable register (DCMI_IER) . . . . . . . . . . . . . . . . . . . . 782
24.5.5 DCMI masked interrupt status register (DCMI_MIS) . . . . . . . . . . . . . . 783
24.5.6 DCMI interrupt clear register (DCMI_ICR) . . . . . . . . . . . . . . . . . . . . . . 784
24.5.7 DCMI embedded synchronization code register (DCMI_ESCR) . . . . . 784
24.5.8 DCMI embedded synchronization unmask register (DCMI_ESUR) . . 786
24.5.9 DCMI crop window start (DCMI_CWSTRT) . . . . . . . . . . . . . . . . . . . . . 786
24.5.10 DCMI crop window size (DCMI_CWSIZE) . . . . . . . . . . . . . . . . . . . . . . 787
24.5.11 DCMI data register (DCMI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
24.5.12 DCMI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789

25 Parallel synchronous slave interface (PSSI) applied

to STM32L4P5xx and STM32LQ5xx only . . . . . . . . . . . . . . . . . . . . . . 790
25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790
25.2 PSSI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790
25.3 PSSI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790
25.3.1 PSSI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
25.3.2 PSSI pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
25.3.3 PSSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
25.3.4 PSSI data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
25.3.5 PSSI optional control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794
25.4 PSSI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
25.5 PSSI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
25.5.1 PSSI control register (PSSI_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
25.5.2 PSSI status register (PSSI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
25.5.3 PSSI raw interrupt status register (PSSI_RIS) . . . . . . . . . . . . . . . . . . 800
25.5.4 PSSI interrupt enable register (PSSI_IER) . . . . . . . . . . . . . . . . . . . . . 801
25.5.5 PSSI masked interrupt status register (PSSI_MIS) . . . . . . . . . . . . . . . 801
25.5.6 PSSI interrupt clear register (PSSI_ICR) . . . . . . . . . . . . . . . . . . . . . . . 802
25.5.7 PSSI data register (PSSI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
25.5.8 PSSI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804

26 Comparator (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805

26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805

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26.2 COMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805

26.3 COMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806
26.3.1 COMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806
26.3.2 COMP pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806
26.3.3 COMP reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
26.3.4 Comparator LOCK mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
26.3.5 Window comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
26.3.6 Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
26.3.7 Comparator output blanking function . . . . . . . . . . . . . . . . . . . . . . . . . . 809
26.3.8 COMP power and speed modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
26.4 COMP low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
26.5 COMP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
26.6 COMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .811
26.6.1 Comparator 1 control and status register (COMP1_CSR) . . . . . . . . . . 811
26.6.2 Comparator 2 control and status register (COMP2_CSR) . . . . . . . . . . 813
26.6.3 COMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816

27 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817

27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
27.2 OPAMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
27.3 OPAMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
27.3.1 OPAMP reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
27.3.2 Initial configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
27.3.3 Signal routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
27.3.4 OPAMP modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
27.3.5 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
27.4 OPAMP low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
27.5 OPAMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
27.5.1 OPAMP1 control/status register (OPAMP1_CSR) . . . . . . . . . . . . . . . . 825
27.5.2 OPAMP1 offset trimming register in normal mode (OPAMP1_OTR) . . 826
27.5.3 OPAMP1 offset trimming register in low-power mode
(OPAMP1_LPOTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
27.5.4 OPAMP2 control/status register (OPAMP2_CRS) . . . . . . . . . . . . . . . . 827
27.5.5 OPAMP2 offset trimming register in normal mode (OPAMP2_OTR) . . 828
27.5.6 OPAMP2 offset trimming register in low-power mode
(OPAMP2_LPOTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
27.5.7 OPAMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829

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28 Digital filter for sigma delta modulators (DFSDM) . . . . . . . . . . . . . . . 830

28.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830
28.2 DFSDM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
28.3 DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
28.4 DFSDM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
28.4.1 DFSDM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
28.4.2 DFSDM pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
28.4.3 DFSDM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
28.4.4 Serial channel transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
28.4.5 Configuring the input serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . 846
28.4.6 Parallel data inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
28.4.7 Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
28.4.8 Digital filter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849
28.4.9 Integrator unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850
28.4.10 Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
28.4.11 Short-circuit detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853
28.4.12 Extreme detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854
28.4.13 Data unit block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854
28.4.14 Signed data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
28.4.15 Launching conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856
28.4.16 Continuous and fast continuous modes . . . . . . . . . . . . . . . . . . . . . . . . 856
28.4.17 Request precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857
28.4.18 Power optimization in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858
28.5 DFSDM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858
28.6 DFSDM DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
28.7 DFSDM channel y registers (y=0..7) . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
28.7.1 DFSDM channel y configuration register (DFSDM_CHyCFGR1) . . . . 860
28.7.2 DFSDM channel y configuration register (DFSDM_CHyCFGR2) . . . . 862
28.7.3 DFSDM channel y analog watchdog and short-circuit detector register
(DFSDM_CHyAWSCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863
28.7.4 DFSDM channel y watchdog filter data register
(DFSDM_CHyWDATR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864
28.7.5 DFSDM channel y data input register (DFSDM_CHyDATINR) . . . . . . 864
28.7.6 DFSDM channel y delay register (DFSDM_CHyDLYR) . . . . . . . . . . . . 865
28.8 DFSDM filter x module registers (x=0..3) . . . . . . . . . . . . . . . . . . . . . . . . 866
28.8.1 DFSDM filter x control register 1 (DFSDM_FLTxCR1) . . . . . . . . . . . . 866
28.8.2 DFSDM filter x control register 2 (DFSDM_FLTxCR2) . . . . . . . . . . . . 869

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28.8.3 DFSDM filter x interrupt and status register (DFSDM_FLTxISR) . . . . . 870

28.8.4 DFSDM filter x interrupt flag clear register (DFSDM_FLTxICR) . . . . . 872
28.8.5 DFSDM filter x injected channel group selection register
(DFSDM_FLTxJCHGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873
28.8.6 DFSDM filter x control register (DFSDM_FLTxFCR) . . . . . . . . . . . . . . 873
28.8.7 DFSDM filter x data register for injected group
(DFSDM_FLTxJDATAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
28.8.8 DFSDM filter x data register for the regular channel
(DFSDM_FLTxRDATAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
28.8.9 DFSDM filter x analog watchdog high threshold register
(DFSDM_FLTxAWHTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
28.8.10 DFSDM filter x analog watchdog low threshold register
(DFSDM_FLTxAWLTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
28.8.11 DFSDM filter x analog watchdog status register
(DFSDM_FLTxAWSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
28.8.12 DFSDM filter x analog watchdog clear flag register
(DFSDM_FLTxAWCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878
28.8.13 DFSDM filter x extremes detector maximum register
(DFSDM_FLTxEXMAX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878
28.8.14 DFSDM filter x extremes detector minimum register
(DFSDM_FLTxEXMIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
28.8.15 DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR) . . 879
28.8.16 DFSDM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880

29 LCD-TFT display controller (LTDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 890

29.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
29.2 LTDC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
29.3 LTDC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
29.4 LTDC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
29.4.1 LTDC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
29.4.2 LTDC pins and external signal interface . . . . . . . . . . . . . . . . . . . . . . . 891
29.4.3 LTDC reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
29.5 LTDC programmable parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
29.5.1 LTDC global configuration parameters . . . . . . . . . . . . . . . . . . . . . . . . 893
29.5.2 Layer programmable parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896
29.6 LTDC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901
29.7 LTDC programming procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902
29.8 LTDC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903
29.8.1 LTDC synchronization size configuration register (LTDC_SSCR) . . . . 903

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29.8.2 LTDC back porch configuration register (LTDC_BPCR) . . . . . . . . . . . 903

29.8.3 LTDC active width configuration register (LTDC_AWCR) . . . . . . . . . . 904
29.8.4 LTDC total width configuration register (LTDC_TWCR) . . . . . . . . . . . . 905
29.8.5 LTDC global control register (LTDC_GCR) . . . . . . . . . . . . . . . . . . . . . 905
29.8.6 LTDC shadow reload configuration register (LTDC_SRCR) . . . . . . . . 907
29.8.7 LTDC background color configuration register (LTDC_BCCR) . . . . . . 907
29.8.8 LTDC interrupt enable register (LTDC_IER) . . . . . . . . . . . . . . . . . . . . 908
29.8.9 LTDC interrupt status register (LTDC_ISR) . . . . . . . . . . . . . . . . . . . . . 909
29.8.10 LTDC Interrupt Clear Register (LTDC_ICR) . . . . . . . . . . . . . . . . . . . . . 909
29.8.11 LTDC line interrupt position configuration register (LTDC_LIPCR) . . . 910
29.8.12 LTDC current position status register (LTDC_CPSR) . . . . . . . . . . . . . 910
29.8.13 LTDC current display status register (LTDC_CDSR) . . . . . . . . . . . . . . 911
29.8.14 LTDC layer x control register (LTDC_LxCR) . . . . . . . . . . . . . . . . . . . . 911
29.8.15 LTDC layer x window horizontal position configuration register
(LTDC_LxWHPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912
29.8.16 LTDC layer x window vertical position configuration register
(LTDC_LxWVPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913
29.8.17 LTDC layer x color keying configuration register
(LTDC_LxCKCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914
29.8.18 LTDC layer x pixel format configuration register
(LTDC_LxPFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914
29.8.19 LTDC layer x constant alpha configuration register
(LTDC_LxCACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
29.8.20 LTDC layer x default color configuration register
(LTDC_LxDCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916
29.8.21 LTDC layer x blending factors configuration register
(LTDC_LxBFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917
29.8.22 LTDC layer x color frame buffer address register
(LTDC_LxCFBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918
29.8.23 LTDC layer x color frame buffer length register
(LTDC_LxCFBLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918
29.8.24 LTDC layer x color frame buffer line number register
(LTDC_LxCFBLNR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919
29.8.25 LTDC layer x CLUT write register (LTDC_LxCLUTWR) . . . . . . . . . . . 920
29.8.26 LTDC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921

30 DSI Host (DSIHOST) applied to

STM32L4R9xx and STM32L4S9xx only . . . . . . . . . . . . . . . . . . . . . . . . 924
30.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924
30.2 Standard and references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924

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30.3 DSI Host main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925

30.4 DSI Host functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
30.4.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
30.4.2 Supported resolutions and frame rates . . . . . . . . . . . . . . . . . . . . . . . . 926
30.4.3 System level architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
30.5 Functional description: Video mode on LTDC interface . . . . . . . . . . . . . 929
30.5.1 Video transmission mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930
30.5.2 Updating the LTDC interface configuration in video mode . . . . . . . . . . 932
30.6 Functional description: adapted command mode on LTDC interface . . . 934
30.7 Functional description: APB slave generic interface . . . . . . . . . . . . . . . 938
30.7.1 Packet transmission using the generic interface . . . . . . . . . . . . . . . . . 939
30.8 Functional description: Timeout counters . . . . . . . . . . . . . . . . . . . . . . . . 942
30.8.1 Contention error detection timeout counters . . . . . . . . . . . . . . . . . . . . 942
30.8.2 Peripheral response timeout counters . . . . . . . . . . . . . . . . . . . . . . . . . 943
30.9 Functional description: transmission of commands . . . . . . . . . . . . . . . . 948
30.9.1 Transmission of commands in Video mode . . . . . . . . . . . . . . . . . . . . . 948
30.9.2 Transmission of commands in Low-power mode . . . . . . . . . . . . . . . . . 950
30.9.3 Transmission of commands in High-speed . . . . . . . . . . . . . . . . . . . . . 954
30.9.4 Read command transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
30.9.5 Clock lane in Low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
30.10 Functional description: virtual channels . . . . . . . . . . . . . . . . . . . . . . . . . 957
30.11 Functional description: video mode pattern generator . . . . . . . . . . . . . . 958
30.11.1 Color bar pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
30.11.2 Color coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959
30.11.3 BER testing pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960
30.11.4 Video mode pattern generator resolution . . . . . . . . . . . . . . . . . . . . . . 961
30.12 Functional description: D-PHY management . . . . . . . . . . . . . . . . . . . . . 962
30.12.1 D-PHY configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
30.12.2 Special D-PHY operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964
30.12.3 Special Low-power D-PHY functions . . . . . . . . . . . . . . . . . . . . . . . . . . 964
30.12.4 DSI PLL control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965
30.12.5 Regulator control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966
30.13 Functional description: interrupts and errors . . . . . . . . . . . . . . . . . . . . . 967
30.13.1 DSI wrapper interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
30.13.2 DSI host interrupts and errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
30.14 Programing procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974

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30.14.1 Programing procedure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974

30.14.2 Configuring the D-PHY parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 974
30.14.3 Configuring the DSI host timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
30.14.4 Configuring flow control and DBI interface . . . . . . . . . . . . . . . . . . . . . 976
30.14.5 Configuring the DSI host LTDC interface . . . . . . . . . . . . . . . . . . . . . . . 976
30.14.6 Configuring the video mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977
30.14.7 Configuring the adapted command mode . . . . . . . . . . . . . . . . . . . . . . 980
30.14.8 Configuring the video mode pattern generator . . . . . . . . . . . . . . . . . . 981
30.14.9 Managing ULPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
30.15 DSI Host registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
30.15.1 DSI Host Version Register (DSI_VR) . . . . . . . . . . . . . . . . . . . . . . . . . . 985
30.15.2 DSI Host Control Register (DSI_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 985
30.15.3 DSI HOST Clock Control Register (DSI_CCR) . . . . . . . . . . . . . . . . . . 986
30.15.4 DSI Host LTDC VCID Register (DSI_LVCIDR) . . . . . . . . . . . . . . . . . . 986
30.15.5 DSI Host LTDC Color Coding Register (DSI_LCOLCR) . . . . . . . . . . . 987
30.15.6 DSI Host LTDC Polarity Configuration Register (DSI_LPCR) . . . . . . . 987
30.15.7 DSI Host Low-Power mode Configuration Register (DSI_LPMCR) . . . 988
30.15.8 DSI Host Protocol Configuration Register (DSI_PCR) . . . . . . . . . . . . 988
30.15.9 DSI Host Generic VCID Register (DSI_GVCIDR) . . . . . . . . . . . . . . . . 989
30.15.10 DSI Host mode Configuration Register (DSI_MCR) . . . . . . . . . . . . . . 990
30.15.11 DSI Host video mode Configuration Register (DSI_VMCR) . . . . . . . . 990
30.15.12 DSI Host video Packet Configuration Register (DSI_VPCR) . . . . . . . . 992
30.15.13 DSI Host video Chunks Configuration Register (DSI_VCCR) . . . . . . . 992
30.15.14 DSI Host Video Null Packet Configuration Register (DSI_VNPCR) . . 993
30.15.15 DSI Host Video HSA Configuration Register (DSI_VHSACR) . . . . . . . 993
30.15.16 DSI Host Video HBP Configuration Register (DSI_VHBPCR) . . . . . . . 994
30.15.17 DSI Host Video Line Configuration Register (DSI_VLCR) . . . . . . . . . . 994
30.15.18 DSI Host Video VSA Configuration Register (DSI_VVSACR) . . . . . . . 994
30.15.19 DSI Host Video VBP Configuration Register (DSI_VVBPCR) . . . . . . . 995
30.15.20 DSI Host Video VFP Configuration Register (DSI_VVFPCR) . . . . . . . 995
30.15.21 DSI Host Video VA Configuration Register (DSI_VVACR) . . . . . . . . . . 996
30.15.22 DSI Host LTDC Command Configuration Register (DSI_LCCR) . . . . . 996
30.15.23 DSI Host Command mode Configuration Register (DSI_CMCR) . . . . 997
30.15.24 DSI Host Generic Header Configuration Register (DSI_GHCR) . . . . . 999
30.15.25 DSI Host Generic Payload Data Register (DSI_GPDR) . . . . . . . . . . . 999
30.15.26 DSI Host Generic Packet Status Register (DSI_GPSR) . . . . . . . . . . 1000
30.15.27 DSI Host Timeout Counter Configuration Register 0 (DSI_TCCR0) . 1001

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30.15.28 DSI Host Timeout Counter Configuration Register 1 (DSI_TCCR1) . 1001

30.15.29 DSI Host Timeout Counter Configuration Register 2 (DSI_TCCR2) . 1002
30.15.30 DSI Host Timeout Counter Configuration Register 3 (DSI_TCCR3) . 1002
30.15.31 DSI Host Timeout Counter Configuration Register 4 (DSI_TCCR4) . 1003
30.15.32 DSI Host Timeout Counter Configuration Register 5 (DSI_TCCR5) . 1004
30.15.33 DSI Host Clock Lane Configuration Register (DSI_CLCR) . . . . . . . . 1004
30.15.34 DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR) . . 1005
30.15.35 DSI Host Data Lane Timer Configuration Register (DSI_DLTCR) . . . 1005
30.15.36 DSI Host PHY Control Register (DSI_PCTLR) . . . . . . . . . . . . . . . . . 1006
30.15.37 DSI Host PHY Configuration Register (DSI_PCONFR) . . . . . . . . . . . 1006
30.15.38 DSI Host PHY ULPS Control Register (DSI_PUCR) . . . . . . . . . . . . . 1007
30.15.39 DSI Host PHY TX Triggers Configuration Register (DSI_PTTCR) . . 1008
30.15.40 DSI Host PHY Status Register (DSI_PSR) . . . . . . . . . . . . . . . . . . . . 1008
30.15.41 DSI Host Interrupt & Status Register 0 (DSI_ISR0) . . . . . . . . . . . . . . 1009
30.15.42 DSI Host Interrupt & Status Register 1 (DSI_ISR1) . . . . . . . . . . . . . . 1010
30.15.43 DSI Host Interrupt Enable Register 0 (DSI_IER0) . . . . . . . . . . . . . . . 1011
30.15.44 DSI Host Interrupt Enable Register 1 (DSI_IER1) . . . . . . . . . . . . . . . 1014
30.15.45 DSI Host Force Interrupt Register 0 (DSI_FIR0) . . . . . . . . . . . . . . . . 1015
30.15.46 DSI Host Force Interrupt Register 1 (DSI_FIR1) . . . . . . . . . . . . . . . . 1017
30.15.47 DSI Host Video Shadow Control Register (DSI_VSCR) . . . . . . . . . . 1018
30.15.48 DSI Host LTDC Current VCID Register (DSI_LCVCIDR) . . . . . . . . . 1018
30.15.49 DSI Host LTDC Current Color Coding Register (DSI_LCCCR) . . . . . 1019
30.15.50 DSI Host Low-Power mode Current Configuration Register
(DSI_LPMCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
30.15.51 DSI Host Video mode Current Configuration Register
(DSI_VMCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020
30.15.52 DSI Host Video Packet Current Configuration Register
(DSI_VPCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021
30.15.53 DSI Host Video Chunks Current Configuration Register
(DSI_VCCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022
30.15.54 DSI Host Video Null Packet Current Configuration Register
(DSI_VNPCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022
30.15.55 DSI Host Video HSA Current Configuration Register
(DSI_VHSACCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023
30.15.56 DSI Host Video HBP Current Configuration Register
(DSI_VHBPCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023
30.15.57 DSI Host Video Line Current Configuration Register (DSI_VLCCR) . 1024
30.15.58 DSI Host Video VSA Current Configuration Register
(DSI_VVSACCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024

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30.15.59 DSI Host Video VBP Current Configuration Register

(DSI_VVBPCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025
30.15.60 DSI Host Video VFP Current Configuration Register
(DSI_VVFPCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025
30.15.61 DSI Host Video VA Current Configuration Register
(DSI_VVACCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026
30.16 DSI Wrapper Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
30.16.1 DSI Wrapper Configuration Register (DSI_WCFGR) . . . . . . . . . . . . 1027
30.16.2 DSI Wrapper Control Register (DSI_WCR) . . . . . . . . . . . . . . . . . . . . 1028
30.16.3 DSI Wrapper Interrupt Enable Register (DSI_WIER) . . . . . . . . . . . . 1029
30.16.4 DSI Wrapper Interrupt & Status Register (DSI_WISR) . . . . . . . . . . . 1030
30.16.5 DSI Wrapper Interrupt Flag Clear Register (DSI_WIFCR) . . . . . . . . . 1031
30.16.6 DSI Wrapper PHY Configuration Register 0 (DSI_WPCR0) . . . . . . . 1032
30.16.7 DSI Wrapper PHY Configuration Register 1 (DSI_WPCR1) . . . . . . . 1034
30.16.8 DSI Wrapper PHY Configuration Register 2 (DSI_WPCR2) . . . . . . . 1036
30.16.9 DSI Wrapper PHY Configuration Register 3 (DSI_WPCR4) . . . . . . . 1037
30.16.10 DSI Wrapper PHY Configuration Register 4 (DSI_WPCR4) . . . . . . . 1038
30.16.11 DSI Wrapper Regulator and PLL Control Register (DSI_WRPCR) . . 1038
30.17 DSI Host register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040

31 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045

31.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045
31.2 TSC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045
31.3 TSC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046
31.3.1 TSC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046
31.3.2 Surface charge transfer acquisition overview . . . . . . . . . . . . . . . . . . 1046
31.3.3 Reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
31.3.4 Charge transfer acquisition sequence . . . . . . . . . . . . . . . . . . . . . . . . 1049
31.3.5 Spread spectrum feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
31.3.6 Max count error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
31.3.7 Sampling capacitor I/O and channel I/O mode selection . . . . . . . . . . 1051
31.3.8 Acquisition mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
31.3.9 I/O hysteresis and analog switch control . . . . . . . . . . . . . . . . . . . . . . 1052
31.4 TSC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053
31.5 TSC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053
31.6 TSC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054
31.6.1 TSC control register (TSC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054

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31.6.2 TSC interrupt enable register (TSC_IER) . . . . . . . . . . . . . . . . . . . . . 1056

31.6.3 TSC interrupt clear register (TSC_ICR) . . . . . . . . . . . . . . . . . . . . . . . 1057
31.6.4 TSC interrupt status register (TSC_ISR) . . . . . . . . . . . . . . . . . . . . . . 1058
31.6.5 TSC I/O hysteresis control register (TSC_IOHCR) . . . . . . . . . . . . . . 1058
31.6.6 TSC I/O analog switch control register (TSC_IOASCR) . . . . . . . . . . 1059
31.6.7 TSC I/O sampling control register (TSC_IOSCR) . . . . . . . . . . . . . . . 1059
31.6.8 TSC I/O channel control register (TSC_IOCCR) . . . . . . . . . . . . . . . . 1060
31.6.9 TSC I/O group control status register (TSC_IOGCSR) . . . . . . . . . . . 1060
31.6.10 TSC I/O group x counter register (TSC_IOGxCR) . . . . . . . . . . . . . . . 1061
31.6.11 TSC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062

32 True random number generator (RNG) applied to

STM32L4Rxxx and STM32L4Sxxx only . . . . . . . . . . . . . . . . . . . . . . . 1064
32.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
32.2 RNG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
32.3 RNG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
32.3.1 RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
32.3.2 RNG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
32.3.3 Random number generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066
32.3.4 RNG initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068
32.3.5 RNG operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069
32.3.6 RNG clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070
32.3.7 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070
32.3.8 WWRNG low-power usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071
32.4 RNG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072
32.5 RNG processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072
32.6 RNG entropy source validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073
32.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073
32.6.2 Validation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073
32.6.3 Data collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073
32.7 RNG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074
32.7.1 RNG control register (RNG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074
32.7.2 RNG status register (RNG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075
32.7.3 RNG data register (RNG_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076
32.7.4 RNG health test control register (RNG_HTCR) . . . . . . . . . . . . . . . . . 1076
32.7.5 RNG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077

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33 True random number generator (RNG) applied to

STM32L4P5xx and STM32L4Q5xx only . . . . . . . . . . . . . . . . . . . . . . . 1078
33.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078
33.2 RNG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078
33.3 RNG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079
33.3.1 RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079
33.3.2 RNG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079
33.3.3 Random number generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080
33.3.4 RNG initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082
33.3.5 RNG operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084
33.3.6 RNG clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
33.3.7 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
33.3.8 RNG low-power usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086
33.4 RNG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086
33.5 RNG processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087
33.6 RNG entropy source validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
33.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
33.6.2 Validation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
33.6.3 Data collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
33.7 RNG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089
33.7.1 RNG control register (RNG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089
33.7.2 RNG status register (RNG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091
33.7.3 RNG data register (RNG_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092
33.7.4 RNG health test control register (RNG_HTCR) . . . . . . . . . . . . . . . . . 1092
33.7.5 RNG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093

34 AES hardware accelerator (AES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094

34.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094
34.2 AES main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094
34.3 AES implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
34.4 AES functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
34.4.1 AES block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
34.4.2 AES internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
34.4.3 AES cryptographic core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096
34.4.4 AES procedure to perform a cipher operation . . . . . . . . . . . . . . . . . . 1101
34.4.5 AES decryption round key preparation . . . . . . . . . . . . . . . . . . . . . . . 1104

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34.4.6 AES ciphertext stealing and data padding . . . . . . . . . . . . . . . . . . . . . 1105

34.4.7 AES task suspend and resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105
34.4.8 AES basic chaining modes (ECB, CBC) . . . . . . . . . . . . . . . . . . . . . . 1106
34.4.9 AES counter (CTR) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111
34.4.10 AES Galois/counter mode (GCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113
34.4.11 AES Galois message authentication code (GMAC) . . . . . . . . . . . . . 1118
34.4.12 AES counter with CBC-MAC (CCM) . . . . . . . . . . . . . . . . . . . . . . . . . 1120
34.4.13 AES data registers and data swapping . . . . . . . . . . . . . . . . . . . . . . . 1126
34.4.14 AES key registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128
34.4.15 AES initialization vector registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128
34.4.16 AES DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128
34.4.17 AES error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130
34.5 AES interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1130
34.6 AES processing latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1131
34.7 AES registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1132
34.7.1 AES control register (AES_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132
34.7.2 AES status register (AES_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134
34.7.3 AES data input register (AES_DINR) . . . . . . . . . . . . . . . . . . . . . . . . 1136
34.7.4 AES data output register (AES_DOUTR) . . . . . . . . . . . . . . . . . . . . . 1136
34.7.5 AES key register 0 (AES_KEYR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137
34.7.6 AES key register 1 (AES_KEYR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138
34.7.7 AES key register 2 (AES_KEYR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138
34.7.8 AES key register 3 (AES_KEYR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138
34.7.9 AES initialization vector register 0 (AES_IVR0) . . . . . . . . . . . . . . . . . 1139
34.7.10 AES initialization vector register 1 (AES_IVR1) . . . . . . . . . . . . . . . . . 1139
34.7.11 AES initialization vector register 2 (AES_IVR2) . . . . . . . . . . . . . . . . . 1139
34.7.12 AES initialization vector register 3 (AES_IVR3) . . . . . . . . . . . . . . . . . 1140
34.7.13 AES key register 4 (AES_KEYR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140
34.7.14 AES key register 5 (AES_KEYR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140
34.7.15 AES key register 6 (AES_KEYR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1141
34.7.16 AES key register 7 (AES_KEYR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1141
34.7.17 AES suspend registers (AES_SUSPxR) . . . . . . . . . . . . . . . . . . . . . . 1141
34.7.18 AES register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1142

35 Hash processor (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1144

35.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1144
35.2 HASH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1144

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35.3 HASH implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1145

35.4 HASH functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1145
35.4.1 HASH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1145
35.4.2 HASH internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146
35.4.3 About secure hash algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146
35.4.4 Message data feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146
35.4.5 Message digest computing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148
35.4.6 Message padding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1149
35.4.7 HMAC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1151
35.4.8 HASH suspend/resume operations . . . . . . . . . . . . . . . . . . . . . . . . . . 1153
35.4.9 HASH DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1155
35.4.10 HASH error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1155
35.5 HASH interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1155
35.6 HASH processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1156
35.7 HASH registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1157
35.7.1 HASH control register (HASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1157
35.7.2 HASH data input register (HASH_DIN) . . . . . . . . . . . . . . . . . . . . . . . 1160
35.7.3 HASH start register (HASH_STR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1161
35.7.4 HASH digest registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1162
35.7.5 HASH interrupt enable register (HASH_IMR) . . . . . . . . . . . . . . . . . . 1163
35.7.6 HASH status register (HASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164
35.7.7 HASH context swap registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164
35.7.8 HASH register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166

36 Public key accelerator (PKA) applied to

STM32L4P5xx and STM32L4Q5xx only . . . . . . . . . . . . . . . . . . . . . . . 1167
36.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1167
36.2 PKA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1167
36.3 PKA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1167
36.3.1 PKA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167
36.3.2 PKA internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1168
36.3.3 PKA reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1168
36.3.4 PKA public key acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1168
36.3.5 Typical applications for PKA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1170
36.3.6 PKA procedure to perform an operation . . . . . . . . . . . . . . . . . . . . . . 1172
36.3.7 PKA error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173

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36.4 PKA operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1173

36.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173
36.4.2 Montgomery parameter computation . . . . . . . . . . . . . . . . . . . . . . . . . 1174
36.4.3 Modular addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175
36.4.4 Modular subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175
36.4.5 Modular and Montgomery multiplication . . . . . . . . . . . . . . . . . . . . . . 1175
36.4.6 Modular exponentiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1176
36.4.7 Modular inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177
36.4.8 Modular reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178
36.4.9 Arithmetic addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178
36.4.10 Arithmetic subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178
36.4.11 Arithmetic multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179
36.4.12 Arithmetic comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179
36.4.13 RSA CRT exponentiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179
36.4.14 Point on elliptic curve Fp check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1180
36.4.15 ECC Fp scalar multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1181
36.4.16 ECDSA sign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1182
36.4.17 ECDSA verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1184
36.5 Example of configurations and processing times . . . . . . . . . . . . . . . . . .1185
36.5.1 Configuration of curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1185
36.5.2 Computation times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191
36.6 PKA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1192
36.7 PKA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1193
36.7.1 PKA control register (PKA_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193
36.7.2 PKA status register (PKA_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194
36.7.3 PKA clear flag register (PKA_CLRFR) . . . . . . . . . . . . . . . . . . . . . . . . 1195
36.7.4 PKA RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195
36.7.5 PKA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 1196

37 Advanced-control timers (TIM1/TIM8) . . . . . . . . . . . . . . . . . . . . . . . . 1197

37.1 TIM1/TIM8 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1197
37.2 TIM1/TIM8 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1197
37.3 TIM1/TIM8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1199
37.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199
37.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201
37.3.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212

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37.3.4 External trigger input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1214

37.3.5 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215
37.3.6 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219
37.3.7 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1221
37.3.8 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1222
37.3.9 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223
37.3.10 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224
37.3.11 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225
37.3.12 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1228
37.3.13 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1229
37.3.14 Combined 3-phase PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1230
37.3.15 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . 1231
37.3.16 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233
37.3.17 Bidirectional break inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239
37.3.18 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . 1240
37.3.19 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242
37.3.20 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1243
37.3.21 Retriggerable one pulse mode (OPM) . . . . . . . . . . . . . . . . . . . . . . . . 1244
37.3.22 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245
37.3.23 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1247
37.3.24 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1248
37.3.25 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1248
37.3.26 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1251
37.3.27 ADC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255
37.3.28 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255
37.3.29 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256
37.4 TIM1/TIM8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257
37.4.1 TIMx control register 1 (TIMx_CR1)(x = 1, 8) . . . . . . . . . . . . . . . . . . 1257
37.4.2 TIMx control register 2 (TIMx_CR2)(x = 1, 8) . . . . . . . . . . . . . . . . . . 1258
37.4.3 TIMx slave mode control register (TIMx_SMCR)(x = 1, 8) . . . . . . . . 1261
37.4.4 TIMx DMA/interrupt enable register (TIMx_DIER)(x = 1, 8) . . . . . . . . 1263
37.4.5 TIMx status register (TIMx_SR)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . 1265
37.4.6 TIMx event generation register (TIMx_EGR)(x = 1, 8) . . . . . . . . . . . . 1267
37.4.7 TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1268
37.4.8 TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269

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37.4.9 TIMx capture/compare mode register 2 [alternate]

(TIMx_CCMR2)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1272
37.4.10 TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273
37.4.11 TIMx capture/compare enable register
(TIMx_CCER)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275
37.4.12 TIMx counter (TIMx_CNT)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . 1278
37.4.13 TIMx prescaler (TIMx_PSC)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . 1278
37.4.14 TIMx auto-reload register (TIMx_ARR)(x = 1, 8) . . . . . . . . . . . . . . . . 1278
37.4.15 TIMx repetition counter register (TIMx_RCR)(x = 1, 8) . . . . . . . . . . . 1279
37.4.16 TIMx capture/compare register 1 (TIMx_CCR1)(x = 1, 8) . . . . . . . . . 1279
37.4.17 TIMx capture/compare register 2 (TIMx_CCR2)(x = 1, 8) . . . . . . . . . 1280
37.4.18 TIMx capture/compare register 3 (TIMx_CCR3)(x = 1, 8) . . . . . . . . . 1280
37.4.19 TIMx capture/compare register 4 (TIMx_CCR4)(x = 1, 8) . . . . . . . . . 1281
37.4.20 TIMx break and dead-time register
(TIMx_BDTR)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1281
37.4.21 TIMx DMA control register (TIMx_DCR)(x = 1, 8) . . . . . . . . . . . . . . . 1285
37.4.22 TIMx DMA address for full transfer
(TIMx_DMAR)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286
37.4.23 TIM1 option register 1 (TIM1_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 1287
37.4.24 TIM8 option register 1 (TIM8_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 1287
37.4.25 TIMx capture/compare mode register 3
(TIMx_CCMR3)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1288
37.4.26 TIMx capture/compare register 5 (TIMx_CCR5)(x = 1, 8) . . . . . . . . . 1289
37.4.27 TIMx capture/compare register 6 (TIMx_CCR6)(x = 1, 8) . . . . . . . . . 1290
37.4.28 TIM1 option register 2 (TIM1_OR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 1290
37.4.29 TIM1 option register 3 (TIM1_OR3) . . . . . . . . . . . . . . . . . . . . . . . . . . 1292
37.4.30 TIM8 option register 2 (TIM8_OR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 1294
37.4.31 TIM8 option register 3 (TIM8_OR3) . . . . . . . . . . . . . . . . . . . . . . . . . . 1295
37.4.32 TIM1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1298
37.4.33 TIM8 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1300

38 General-purpose timers (TIM2/TIM3/TIM4/TIM5) . . . . . . . . . . . . . . . . 1303

38.1 TIM2/TIM3/TIM4/TIM5 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303
38.2 TIM2/TIM3/TIM4/TIM5 main features . . . . . . . . . . . . . . . . . . . . . . . . . . 1303
38.3 TIM2/TIM3/TIM4/TIM5 functional description . . . . . . . . . . . . . . . . . . . . 1305
38.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305
38.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1307
38.3.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1317

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38.3.4 Capture/Compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1321

38.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1323
38.3.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1324
38.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1325
38.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1326
38.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1327
38.3.10 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1330
38.3.11 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1331
38.3.12 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . 1332
38.3.13 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1334
38.3.14 Retriggerable one pulse mode (OPM) . . . . . . . . . . . . . . . . . . . . . . . . 1335
38.3.15 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1336
38.3.16 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1338
38.3.17 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1338
38.3.18 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . 1339
38.3.19 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1342
38.3.20 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1346
38.3.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1347
38.4 TIM2/TIM3/TIM4/TIM5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1348
38.4.1 TIMx control register 1 (TIMx_CR1)(x = 2 to 5) . . . . . . . . . . . . . . . . . 1348
38.4.2 TIMx control register 2 (TIMx_CR2)(x = 2 to 5) . . . . . . . . . . . . . . . . . 1349
38.4.3 TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5) . . . . . . . 1351
38.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 5) . . . . . . 1354
38.4.5 TIMx status register (TIMx_SR)(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . 1355
38.4.6 TIMx event generation register (TIMx_EGR)(x = 2 to 5) . . . . . . . . . . 1356
38.4.7 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1357
38.4.8 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1359
38.4.9 TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)
(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1361
38.4.10 TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)
(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1362
38.4.11 TIMx capture/compare enable register
(TIMx_CCER)(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1363
38.4.12 TIMx counter [alternate] (TIMx_CNT)(x = 2 to 5) . . . . . . . . . . . . . . . . 1364
38.4.13 TIMx counter [alternate] (TIMx_CNT)(x = 2 to 5) . . . . . . . . . . . . . . . . 1365
38.4.14 TIMx prescaler (TIMx_PSC)(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . 1365

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38.4.15 TIMx auto-reload register (TIMx_ARR)(x = 2 to 5) . . . . . . . . . . . . . . 1366

38.4.16 TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 5) . . . . . . . 1366
38.4.17 TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 5) . . . . . . . 1367
38.4.18 TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 5) . . . . . . . 1367
38.4.19 TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 5) . . . . . . . 1368
38.4.20 TIMx DMA control register (TIMx_DCR)(x = 2 to 5) . . . . . . . . . . . . . . 1369
38.4.21 TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 5) . . . . . . 1369
38.4.22 TIM2 option register 1 (TIM2_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 1369
38.4.23 TIM3 option register 1 (TIM3_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 1370
38.4.24 TIM2 option register 2 (TIM2_OR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 1370
38.4.25 TIM3 option register 2 (TIM3_OR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 1371
38.4.26 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1372

39 General-purpose timers (TIM15/TIM16/TIM17) . . . . . . . . . . . . . . . . . 1375

39.1 TIM15/TIM16/TIM17 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1375
39.2 TIM15 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1375
39.3 TIM16/TIM17 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1376
39.4 TIM15/TIM16/TIM17 functional description . . . . . . . . . . . . . . . . . . . . . 1379
39.4.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1379
39.4.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1381
39.4.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1385
39.4.4 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386
39.4.5 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388
39.4.6 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1390
39.4.7 PWM input mode (only for TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1391
39.4.8 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1392
39.4.9 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1393
39.4.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1394
39.4.11 Combined PWM mode (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . . . 1395
39.4.12 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . 1396
39.4.13 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1398
39.4.14 Bidirectional break inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1403
39.4.15 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1405
39.4.16 Retriggerable one pulse mode (OPM) (TIM15 only) . . . . . . . . . . . . . 1407
39.4.17 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407
39.4.18 Timer input XOR function (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . 1409
39.4.19 External trigger synchronization (TIM15 only) . . . . . . . . . . . . . . . . . . 1410

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39.4.20 Slave mode – combined reset + trigger mode . . . . . . . . . . . . . . . . . . 1412

39.4.21 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1412
39.4.22 Timer synchronization (TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1414
39.4.23 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1414
39.5 TIM15 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1415
39.5.1 TIM15 control register 1 (TIM15_CR1) . . . . . . . . . . . . . . . . . . . . . . . 1415
39.5.2 TIM15 control register 2 (TIM15_CR2) . . . . . . . . . . . . . . . . . . . . . . . 1416
39.5.3 TIM15 slave mode control register (TIM15_SMCR) . . . . . . . . . . . . . 1418
39.5.4 TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . . . . . . . . . 1419
39.5.5 TIM15 status register (TIM15_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1420
39.5.6 TIM15 event generation register (TIM15_EGR) . . . . . . . . . . . . . . . . 1422
39.5.7 TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1423
39.5.8 TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424
39.5.9 TIM15 capture/compare enable register (TIM15_CCER) . . . . . . . . . 1427
39.5.10 TIM15 counter (TIM15_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1430
39.5.11 TIM15 prescaler (TIM15_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1430
39.5.12 TIM15 auto-reload register (TIM15_ARR) . . . . . . . . . . . . . . . . . . . . . 1430
39.5.13 TIM15 repetition counter register (TIM15_RCR) . . . . . . . . . . . . . . . . 1431
39.5.14 TIM15 capture/compare register 1 (TIM15_CCR1) . . . . . . . . . . . . . . 1431
39.5.15 TIM15 capture/compare register 2 (TIM15_CCR2) . . . . . . . . . . . . . . 1432
39.5.16 TIM15 break and dead-time register (TIM15_BDTR) . . . . . . . . . . . . 1432
39.5.17 TIM15 DMA control register (TIM15_DCR) . . . . . . . . . . . . . . . . . . . . 1435
39.5.18 TIM15 DMA address for full transfer (TIM15_DMAR) . . . . . . . . . . . . 1435
39.5.19 TIM15 option register 1 (TIM15_OR1) . . . . . . . . . . . . . . . . . . . . . . . . 1436
39.5.20 TIM15 option register 2 (TIM15_OR2) . . . . . . . . . . . . . . . . . . . . . . . . 1436
39.5.21 TIM15 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1438
39.6 TIM16/TIM17 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1441
39.6.1 TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . . . . . . . . . . . . 1441
39.6.2 TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . . . . . . . . . . . . 1442
39.6.3 TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . 1443
39.6.4 TIMx status register (TIMx_SR)(x = 16 to 17) . . . . . . . . . . . . . . . . . . 1444
39.6.5 TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . . . . . 1445
39.6.6 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1446
39.6.7 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447

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39.6.8 TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . 1449

39.6.9 TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . 1451
39.6.10 TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . 1452
39.6.11 TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) . . . . . . . . . . . . 1452
39.6.12 TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . . . . . 1453
39.6.13 TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . . 1453
39.6.14 TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . 1454
39.6.15 TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . . . . . . . . . 1456
39.6.16 TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) . . . . 1457
39.6.17 TIM16 option register 1 (TIM16_OR1) . . . . . . . . . . . . . . . . . . . . . . . . 1457
39.6.18 TIM16 option register 2 (TIM16_OR2) . . . . . . . . . . . . . . . . . . . . . . . . 1458
39.6.19 TIM17 option register 1 (TIM17_OR1) . . . . . . . . . . . . . . . . . . . . . . . . 1459
39.6.20 TIM17 option register 2 (TIM17_OR2) . . . . . . . . . . . . . . . . . . . . . . . . 1460
39.6.21 TIM16/TIM17 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1462

40 Basic timers (TIM6/TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1464

40.1 TIM6/TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1464
40.2 TIM6/TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1464
40.3 TIM6/TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1465
40.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1465
40.3.2 Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1467
40.3.3 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1470
40.3.4 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1470
40.3.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1471
40.4 TIM6/TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1471
40.4.1 TIMx control register 1 (TIMx_CR1)(x = 6 to 7) . . . . . . . . . . . . . . . . . 1471
40.4.2 TIMx control register 2 (TIMx_CR2)(x = 6 to 7) . . . . . . . . . . . . . . . . . 1473
40.4.3 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) . . . . . . 1473
40.4.4 TIMx status register (TIMx_SR)(x = 6 to 7) . . . . . . . . . . . . . . . . . . . . 1474
40.4.5 TIMx event generation register (TIMx_EGR)(x = 6 to 7) . . . . . . . . . . 1474
40.4.6 TIMx counter (TIMx_CNT)(x = 6 to 7) . . . . . . . . . . . . . . . . . . . . . . . . 1474
40.4.7 TIMx prescaler (TIMx_PSC)(x = 6 to 7) . . . . . . . . . . . . . . . . . . . . . . . 1475
40.4.8 TIMx auto-reload register (TIMx_ARR)(x = 6 to 7) . . . . . . . . . . . . . . 1475
40.4.9 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1476

41 Low-power timer (LPTIM) applied to

STM32L4Rxxx and STM32L4Sxxx only . . . . . . . . . . . . . . . . . . . . . . . 1477

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41.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477

41.2 LPTIM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477
41.3 LPTIM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478
41.4 LPTIM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478
41.4.1 LPTIM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478
41.4.2 LPTIM pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479
41.4.3 LPTIM trigger mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479
41.4.4 LPTIM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1480
41.4.5 Glitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1480
41.4.6 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1481
41.4.7 Trigger multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482
41.4.8 Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482
41.4.9 Timeout function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1484
41.4.10 Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1484
41.4.11 Register update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1485
41.4.12 Counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1486
41.4.13 Timer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1486
41.4.14 Timer counter reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1487
41.4.15 Encoder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1487
41.4.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489
41.5 LPTIM low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489
41.6 LPTIM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490
41.7 LPTIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490
41.7.1 LPTIM interrupt and status register (LPTIM_ISR) . . . . . . . . . . . . . . . 1491
41.7.2 LPTIM interrupt clear register (LPTIM_ICR) . . . . . . . . . . . . . . . . . . . 1492
41.7.3 LPTIM interrupt enable register (LPTIM_IER) . . . . . . . . . . . . . . . . . . 1492
41.7.4 LPTIM configuration register (LPTIM_CFGR) . . . . . . . . . . . . . . . . . . 1493
41.7.5 LPTIM control register (LPTIM_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 1496
41.7.6 LPTIM compare register (LPTIM_CMP) . . . . . . . . . . . . . . . . . . . . . . 1498
41.7.7 LPTIM autoreload register (LPTIM_ARR) . . . . . . . . . . . . . . . . . . . . . 1498
41.7.8 LPTIM counter register (LPTIM_CNT) . . . . . . . . . . . . . . . . . . . . . . . . 1499
41.7.9 LPTIM1 option register (LPTIM1_OR) . . . . . . . . . . . . . . . . . . . . . . . . 1499
41.7.10 LPTIM2 option register (LPTIM2_OR) . . . . . . . . . . . . . . . . . . . . . . . . 1500
41.7.11 LPTIM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1501

42 Low-power timer (LPTIM) applied to

STM32L4P5xx and STM32L4Q5xx only . . . . . . . . . . . . . . . . . . . . . . . 1503

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42.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1503

42.2 LPTIM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1503
42.3 LPTIM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504
42.4 LPTIM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504
42.4.1 LPTIM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504
42.4.2 LPTIM pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505
42.4.3 LPTIM trigger mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505
42.4.4 LPTIM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1506
42.4.5 Glitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1506
42.4.6 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507
42.4.7 Trigger multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1508
42.4.8 Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1508
42.4.9 Timeout function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1510
42.4.10 Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1510
42.4.11 Register update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1511
42.4.12 Counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1512
42.4.13 Timer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1513
42.4.14 Timer counter reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1513
42.4.15 Encoder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1514
42.4.16 Repetition Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1515
42.4.17 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1516
42.5 LPTIM low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1517
42.6 LPTIM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1517
42.7 LPTIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1518
42.7.1 LPTIM interrupt and status register (LPTIM_ISR) . . . . . . . . . . . . . . . 1518
42.7.2 LPTIM interrupt clear register (LPTIM_ICR) . . . . . . . . . . . . . . . . . . . 1519
42.7.3 LPTIM interrupt enable register (LPTIM_IER) . . . . . . . . . . . . . . . . . . 1520
42.7.4 LPTIM configuration register (LPTIM_CFGR) . . . . . . . . . . . . . . . . . . 1521
42.7.5 LPTIM control register (LPTIM_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 1524
42.7.6 LPTIM compare register (LPTIM_CMP) . . . . . . . . . . . . . . . . . . . . . . 1525
42.7.7 LPTIM autoreload register (LPTIM_ARR) . . . . . . . . . . . . . . . . . . . . . 1525
42.7.8 LPTIM counter register (LPTIM_CNT) . . . . . . . . . . . . . . . . . . . . . . . . 1526
42.7.9 LPTIM1 option register (LPTIM1_OR) . . . . . . . . . . . . . . . . . . . . . . . . 1526
42.7.10 LPTIM2 option register (LPTIM2_OR) . . . . . . . . . . . . . . . . . . . . . . . . 1527
42.7.11 LPTIM repetition register (LPTIM_RCR) . . . . . . . . . . . . . . . . . . . . . . 1527
42.7.12 LPTIM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1528

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43 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1530

44 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1531

44.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1531
44.2 IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1531
44.3 IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1531
44.3.1 IWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1531
44.3.2 Window option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1532
44.3.3 Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1533
44.3.4 Low-power freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1533
44.3.5 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1533
44.3.6 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1533
44.4 IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1534
44.4.1 IWDG key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1534
44.4.2 IWDG prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . 1535
44.4.3 IWDG reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1536
44.4.4 IWDG status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1537
44.4.5 IWDG window register (IWDG_WINR) . . . . . . . . . . . . . . . . . . . . . . . 1538
44.4.6 IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1539

45 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . 1540

45.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1540
45.2 WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1540
45.3 WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1540
45.3.1 WWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1541
45.3.2 Enabling the watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1541
45.3.3 Controlling the down-counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1541
45.3.4 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . 1541
45.3.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1542
45.4 WWDG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1543
45.5 WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1543
45.5.1 WWDG control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . 1543
45.5.2 WWDG configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . 1544
45.5.3 WWDG status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . 1544
45.5.4 WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1544

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46 Real-time clock (RTC) applied to

STM32L4Rxxx and STM32L4Sxxx only . . . . . . . . . . . . . . . . . . . . . . . 1546
46.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1546
46.2 RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1547
46.3 RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1548
46.3.1 RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1548
46.3.2 GPIOs controlled by the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1549
46.3.3 Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1551
46.3.4 Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1552
46.3.5 Programmable alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1552
46.3.6 Periodic auto-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1552
46.3.7 RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 1553
46.3.8 Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1555
46.3.9 Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1556
46.3.10 RTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1556
46.3.11 RTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1557
46.3.12 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1557
46.3.13 Time-stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1559
46.3.14 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1560
46.3.15 Calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1562
46.3.16 Alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1563
46.4 RTC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1563
46.5 RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564
46.6 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1565
46.6.1 RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1565
46.6.2 RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566
46.6.3 RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1567
46.6.4 RTC initialization and status register (RTC_ISR) . . . . . . . . . . . . . . . . 1570
46.6.5 RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . 1573
46.6.6 RTC wakeup timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . . 1574
46.6.7 RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . 1575
46.6.8 RTC alarm B register (RTC_ALRMBR) . . . . . . . . . . . . . . . . . . . . . . . 1576
46.6.9 RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . 1577
46.6.10 RTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . 1577
46.6.11 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . 1578
46.6.12 RTC timestamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . 1579

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46.6.13 RTC timestamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . 1580

46.6.14 RTC time-stamp sub second register (RTC_TSSSR) . . . . . . . . . . . . 1581
46.6.15 RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . 1582
46.6.16 RTC tamper configuration register (RTC_TAMPCR) . . . . . . . . . . . . . 1583
46.6.17 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . 1586
46.6.18 RTC alarm B sub second register (RTC_ALRMBSSR) . . . . . . . . . . . 1587
46.6.19 RTC option register (RTC_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1588
46.6.20 RTC backup registers (RTC_BKPxR) . . . . . . . . . . . . . . . . . . . . . . . . 1588
46.6.21 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1589

47 Real-time clock (RTC) applied to

STM32L4P5xx and STM32L4Q5xx only . . . . . . . . . . . . . . . . . . . . . . . 1591
47.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1591
47.2 RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1591
47.3 RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1592
47.3.1 RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1592
47.3.2 RTC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1593
47.3.3 GPIOs controlled by the RTC and TAMP . . . . . . . . . . . . . . . . . . . . . . 1594
47.3.4 Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1596
47.3.5 Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1597
47.3.6 Calendar ultra-low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1598
47.3.7 Programmable alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1598
47.3.8 Periodic auto-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1598
47.3.9 RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 1599
47.3.10 Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1602
47.3.11 Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603
47.3.12 RTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603
47.3.13 RTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603
47.3.14 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1604
47.3.15 Timestamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1606
47.3.16 Calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1607
47.3.17 Tamper and alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1608
47.4 RTC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1608
47.5 RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1609
47.6 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1609
47.6.1 RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610
47.6.2 RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1611

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47.6.3 RTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . 1612

47.6.4 RTC initialization control and status register (RTC_ICSR) . . . . . . . . 1612
47.6.5 RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . 1614
47.6.6 RTC wakeup timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . . 1615
47.6.7 RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1615
47.6.8 RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . 1619
47.6.9 RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . 1619
47.6.10 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . 1620
47.6.11 RTC timestamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . 1621
47.6.12 RTC timestamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . 1622
47.6.13 RTC timestamp sub second register (RTC_TSSSR) . . . . . . . . . . . . . 1622
47.6.14 RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . 1623
47.6.15 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . 1624
47.6.16 RTC alarm B register (RTC_ALRMBR) . . . . . . . . . . . . . . . . . . . . . . . 1625
47.6.17 RTC alarm B sub second register (RTC_ALRMBSSR) . . . . . . . . . . . 1626
47.6.18 RTC status register (RTC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1627
47.6.19 RTC masked interrupt status register (RTC_MISR) . . . . . . . . . . . . . 1628
47.6.20 RTC status clear register (RTC_SCR) . . . . . . . . . . . . . . . . . . . . . . . . 1629
47.6.21 RTC alarm A binary mode register (RTC_ALRABINR) . . . . . . . . . . . 1630
47.6.22 RTC alarm B binary mode register (RTC_ALRBBINR) . . . . . . . . . . . 1630
47.6.23 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1631

48 Tamper and backup registers (TAMP) applied to

STM32L4P5xx and STM32L4Q5xx only . . . . . . . . . . . . . . . . . . . . . . . 1633
48.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633
48.2 TAMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633
48.3 TAMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634
48.3.1 TAMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634
48.3.2 TAMP pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634
48.3.3 TAMP register write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1635
48.3.4 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1635
48.4 TAMP low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1638
48.5 TAMP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1638
48.6 TAMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1638
48.6.1 TAMP control register 1 (TAMP_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 1639
48.6.2 TAMP control register 2 (TAMP_CR2) . . . . . . . . . . . . . . . . . . . . . . . . 1640
48.6.3 TAMP filter control register (TAMP_FLTCR) . . . . . . . . . . . . . . . . . . . 1641

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48.6.4 TAMP interrupt enable register (TAMP_IER) . . . . . . . . . . . . . . . . . . . 1642

48.6.5 TAMP status register (TAMP_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1643
48.6.6 TAMP masked interrupt status register (TAMP_MISR) . . . . . . . . . . . 1644
48.6.7 TAMP status clear register (TAMP_SCR) . . . . . . . . . . . . . . . . . . . . . 1645
48.6.8 TAMP backup x register (TAMP_BKPxR) . . . . . . . . . . . . . . . . . . . . . 1645
48.6.9 TAMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1647

49 Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . 1648

49.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1648
49.2 I2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1648
49.3 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1649
49.4 I2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1649
49.4.1 I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1650
49.4.2 I2C pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651
49.4.3 I2C clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651
49.4.4 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1652
49.4.5 I2C initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1652
49.4.6 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1657
49.4.7 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1658
49.4.8 I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1660
49.4.9 I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1669
49.4.10 I2C_TIMINGR register configuration examples . . . . . . . . . . . . . . . . . 1681
49.4.11 SMBus specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1682
49.4.12 SMBus initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1685
49.4.13 SMBus: I2C_TIMEOUTR register configuration examples . . . . . . . . 1687
49.4.14 SMBus slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1688
49.4.15 Wakeup from Stop mode on address match . . . . . . . . . . . . . . . . . . . 1696
49.4.16 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1696
49.4.17 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1698
49.4.18 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1699
49.5 I2C low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1699
49.6 I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1700
49.7 I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1701
49.7.1 I2C control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1701
49.7.2 I2C control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704
49.7.3 I2C own address 1 register (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . 1707

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49.7.4 I2C own address 2 register (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . 1708

49.7.5 I2C timing register (I2C_TIMINGR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1709
49.7.6 I2C timeout register (I2C_TIMEOUTR) . . . . . . . . . . . . . . . . . . . . . . . 1710
49.7.7 I2C interrupt and status register (I2C_ISR) . . . . . . . . . . . . . . . . . . . . 1711
49.7.8 I2C interrupt clear register (I2C_ICR) . . . . . . . . . . . . . . . . . . . . . . . . 1713
49.7.9 I2C PEC register (I2C_PECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714
49.7.10 I2C receive data register (I2C_RXDR) . . . . . . . . . . . . . . . . . . . . . . . 1715
49.7.11 I2C transmit data register (I2C_TXDR) . . . . . . . . . . . . . . . . . . . . . . . 1715
49.7.12 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1716

50 Universal synchronous/asynchronous receiver

transmitter (USART/UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1718
50.1 USART introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1718
50.2 USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1719
50.3 USART extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1720
50.4 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1720
50.5 USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1721
50.5.1 USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1721
50.5.2 USART signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1722
50.5.3 USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1723
50.5.4 USART FIFOs and thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1725
50.5.5 USART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1725
50.5.6 USART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1729
50.5.7 USART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1736
50.5.8 Tolerance of the USART receiver to clock deviation . . . . . . . . . . . . . 1737
50.5.9 USART Auto baud rate detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1739
50.5.10 USART multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . 1741
50.5.11 USART Modbus communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1743
50.5.12 USART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1744
50.5.13 USART LIN (local interconnection network) mode . . . . . . . . . . . . . . 1745
50.5.14 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1747
50.5.15 USART single-wire Half-duplex communication . . . . . . . . . . . . . . . . 1751
50.5.16 USART receiver timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1751
50.5.17 USART Smartcard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1752
50.5.18 USART IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1756
50.5.19 Continuous communication using USART and DMA . . . . . . . . . . . . . 1759
50.5.20 RS232 Hardware flow control and RS485 Driver Enable . . . . . . . . . 1761

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50.5.21 USART low-power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1764

50.6 USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1767
50.7 USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1770
50.7.1 USART control register 1 [alternate] (USART_CR1) . . . . . . . . . . . . . 1770
50.7.2 USART control register 1 [alternate] (USART_CR1) . . . . . . . . . . . . . 1774
50.7.3 USART control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . 1777
50.7.4 USART control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . 1781
50.7.5 USART baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . 1786
50.7.6 USART guard time and prescaler register (USART_GTPR) . . . . . . . 1786
50.7.7 USART receiver timeout register (USART_RTOR) . . . . . . . . . . . . . . 1787
50.7.8 USART request register (USART_RQR) . . . . . . . . . . . . . . . . . . . . . . 1788
50.7.9 USART interrupt and status register [alternate] (USART_ISR) . . . . . 1789
50.7.10 USART interrupt and status register [alternate] (USART_ISR) . . . . . 1795
50.7.11 USART interrupt flag clear register (USART_ICR) . . . . . . . . . . . . . . 1800
50.7.12 USART receive data register (USART_RDR) . . . . . . . . . . . . . . . . . . 1802
50.7.13 USART transmit data register (USART_TDR) . . . . . . . . . . . . . . . . . . 1802
50.7.14 USART prescaler register (USART_PRESC) . . . . . . . . . . . . . . . . . . 1803
50.7.15 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1804

51 Low-power universal asynchronous receiver

transmitter (LPUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1806
51.1 LPUART introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1806
51.2 LPUART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1807
51.3 LPUART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1807
51.4 LPUART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1809
51.4.1 LPUART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1809
51.4.2 LPUART signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1810
51.4.3 LPUART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1810
51.4.4 LPUART FIFOs and thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1811
51.4.5 LPUART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1812
51.4.6 LPUART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1815
51.4.7 LPUART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1819
51.4.8 Tolerance of the LPUART receiver to clock deviation . . . . . . . . . . . . 1820
51.4.9 LPUART multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . 1821
51.4.10 LPUART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1823
51.4.11 LPUART single-wire Half-duplex communication . . . . . . . . . . . . . . . 1824
51.4.12 Continuous communication using DMA and LPUART . . . . . . . . . . . . 1824

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51.4.13 RS232 Hardware flow control and RS485 Driver Enable . . . . . . . . . 1827
51.4.14 LPUART low-power management . . . . . . . . . . . . . . . . . . . . . . . . . . . 1829
51.5 LPUART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1832
51.6 LPUART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1834
51.6.1 LPUART control register 1 [alternate] (LPUART_CR1) . . . . . . . . . . . 1834
51.6.2 LPUART control register 1 [alternate] (LPUART_CR1) . . . . . . . . . . . 1837
51.6.3 LPUART control register 2 (LPUART_CR2) . . . . . . . . . . . . . . . . . . . 1840
51.6.4 LPUART control register 3 (LPUART_CR3) . . . . . . . . . . . . . . . . . . . 1842
51.6.5 LPUART baud rate register (LPUART_BRR) . . . . . . . . . . . . . . . . . . 1845
51.6.6 LPUART request register (LPUART_RQR) . . . . . . . . . . . . . . . . . . . . 1846
51.6.7 LPUART interrupt and status register [alternate] (LPUART_ISR) . . . 1846
51.6.8 LPUART interrupt and status register [alternate] (LPUART_ISR) . . . 1851
51.6.9 LPUART interrupt flag clear register (LPUART_ICR) . . . . . . . . . . . . 1854
51.6.10 LPUART receive data register (LPUART_RDR) . . . . . . . . . . . . . . . . 1855
51.6.11 LPUART transmit data register (LPUART_TDR) . . . . . . . . . . . . . . . . 1855
51.6.12 LPUART prescaler register (LPUART_PRESC) . . . . . . . . . . . . . . . . 1856
51.6.13 LPUART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1857

52 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1859

52.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1859
52.2 SPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1859
52.3 SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1859
52.4 SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1860
52.4.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1860
52.4.2 Communications between one master and one slave . . . . . . . . . . . . 1861
52.4.3 Standard multi-slave communication . . . . . . . . . . . . . . . . . . . . . . . . . 1864
52.4.4 Multi-master communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1864
52.4.5 Slave select (NSS) pin management . . . . . . . . . . . . . . . . . . . . . . . . . 1865
52.4.6 Communication formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1866
52.4.7 Configuration of SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1868
52.4.8 Procedure for enabling SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1869
52.4.9 Data transmission and reception procedures . . . . . . . . . . . . . . . . . . 1869
52.4.10 SPI status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1879
52.4.11 SPI error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1880
52.4.12 NSS pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1881
52.4.13 TI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1881

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52.4.14 CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1882

52.5 SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1884
52.6 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1885
52.6.1 SPI control register 1 (SPIx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1885
52.6.2 SPI control register 2 (SPIx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1887
52.6.3 SPI status register (SPIx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1889
52.6.4 SPI data register (SPIx_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1890
52.6.5 SPI CRC polynomial register (SPIx_CRCPR) . . . . . . . . . . . . . . . . . . 1891
52.6.6 SPI Rx CRC register (SPIx_RXCRCR) . . . . . . . . . . . . . . . . . . . . . . . 1891
52.6.7 SPI Tx CRC register (SPIx_TXCRCR) . . . . . . . . . . . . . . . . . . . . . . . 1891
52.6.8 SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1893

53 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1894

53.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1894
53.2 SAI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1895
53.3 SAI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1895
53.4 SAI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1896
53.4.1 SAI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1896
53.4.2 SAI pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1897
53.4.3 Main SAI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1898
53.4.4 SAI synchronization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1899
53.4.5 Audio data size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1900
53.4.6 Frame synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1900
53.4.7 Slot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1903
53.4.8 SAI clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1905
53.4.9 Internal FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1907
53.4.10 PDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1909
53.4.11 AC’97 link controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1917
53.4.12 SPDIF output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1919
53.4.13 Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1922
53.4.14 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1926
53.4.15 Disabling the SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1929
53.4.16 SAI DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1929
53.5 SAI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1930
53.6 SAI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1932
53.6.1 SAI global configuration register (SAI_GCR) . . . . . . . . . . . . . . . . . . . 1932

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53.6.2 SAI configuration register 1 (SAI_ACR1) . . . . . . . . . . . . . . . . . . . . . . 1932

53.6.3 SAI configuration register 1 (SAI_BCR1) . . . . . . . . . . . . . . . . . . . . . . 1935
53.6.4 SAI configuration register 2 (SAI_ACR2) . . . . . . . . . . . . . . . . . . . . . . 1938
53.6.5 SAI configuration register 2 (SAI_BCR2) . . . . . . . . . . . . . . . . . . . . . . 1940
53.6.6 SAI frame configuration register (SAI_AFRCR) . . . . . . . . . . . . . . . . . 1942
53.6.7 SAI frame configuration register (SAI_BFRCR) . . . . . . . . . . . . . . . . . 1943
53.6.8 SAI slot register (SAI_ASLOTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1944
53.6.9 SAI slot register (SAI_BSLOTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1945
53.6.10 SAI interrupt mask register (SAI_AIM) . . . . . . . . . . . . . . . . . . . . . . . . 1946
53.6.11 SAI interrupt mask register (SAI_BIM) . . . . . . . . . . . . . . . . . . . . . . . . 1948
53.6.12 SAI status register (SAI_ASR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1949
53.6.13 SAI status register (SAI_BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1951
53.6.14 SAI clear flag register (SAI_ACLRFR) . . . . . . . . . . . . . . . . . . . . . . . . 1953
53.6.15 SAI clear flag register (SAI_BCLRFR) . . . . . . . . . . . . . . . . . . . . . . . . 1954
53.6.16 SAI data register (SAI_ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1955
53.6.17 SAI data register (SAI_BDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1956
53.6.18 SAI PDM control register (SAI_PDMCR) . . . . . . . . . . . . . . . . . . . . . . 1956
53.6.19 SAI PDM delay register (SAI_PDMDLY) . . . . . . . . . . . . . . . . . . . . . . 1957
53.6.20 SAI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1960

54 Secure digital input/output MultiMediaCard interface (SDMMC) . . 1962

54.1 SDMMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1962
54.2 SDMMC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1962
54.3 SDMMC bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1963
54.4 SDMMC operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1965
54.5 SDMMC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1965
54.5.1 SDMMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1966
54.5.2 SDMMC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1966
54.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1967
54.5.4 SDMMC adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1968
54.5.5 SDMMC AHB slave interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1989
54.5.6 SDMMC AHB master interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1990
54.5.7 AHB and SDMMC_CK clock relation . . . . . . . . . . . . . . . . . . . . . . . . . 1992
54.5.8 Hardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1992
54.6 Card functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1992
54.6.1 SD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1992

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54.6.2 CMD12 send timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2001

54.6.3 Sleep (CMD5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2004
54.6.4 Interrupt mode (Wait-IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2005
54.6.5 Boot operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2006
54.6.6 Response R1b handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2009
54.6.7 Reset and card cycle power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2010
54.7 Ultra-high-speed phase I (UHS-I) voltage switch . . . . . . . . . . . . . . . . . .2011
54.8 SDMMC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2015
54.9 SDMMC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2017
54.9.1 SDMMC power control register (SDMMC_POWER) . . . . . . . . . . . . . 2017
54.9.2 SDMMC clock control register (SDMMC_CLKCR) . . . . . . . . . . . . . . 2018
54.9.3 SDMMC argument register (SDMMC_ARGR) . . . . . . . . . . . . . . . . . . 2020
54.9.4 SDMMC command register (SDMMC_CMDR) . . . . . . . . . . . . . . . . . 2020
54.9.5 SDMMC command response register (SDMMC_RESPCMDR) . . . . 2022
54.9.6 SDMMC response x register (SDMMC_RESPxR) . . . . . . . . . . . . . . 2023
54.9.7 SDMMC data timer register (SDMMC_DTIMER) . . . . . . . . . . . . . . . 2023
54.9.8 SDMMC data length register (SDMMC_DLENR) . . . . . . . . . . . . . . . 2024
54.9.9 SDMMC data control register (SDMMC_DCTRL) . . . . . . . . . . . . . . . 2025
54.9.10 SDMMC data counter register (SDMMC_DCNTR) . . . . . . . . . . . . . . 2026
54.9.11 SDMMC status register (SDMMC_STAR) . . . . . . . . . . . . . . . . . . . . . 2027
54.9.12 SDMMC interrupt clear register (SDMMC_ICR) . . . . . . . . . . . . . . . . 2030
54.9.13 SDMMC mask register (SDMMC_MASKR) . . . . . . . . . . . . . . . . . . . . 2032
54.9.14 SDMMC acknowledgment timer register (SDMMC_ACKTIMER) . . . 2035
54.9.15 SDMMC data FIFO registers x (SDMMC_FIFORx) . . . . . . . . . . . . . . 2035
54.9.16 SDMMC DMA control register (SDMMC_IDMACTRLR) . . . . . . . . . . 2036
54.9.17 SDMMC IDMA buffer size register (SDMMC_IDMABSIZER) . . . . . . 2037
54.9.18 SDMMC IDMA buffer 0 base address register
(SDMMC_IDMABASE0R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2037
54.9.19 SDMMC IDMA buffer 1 base address register
(SDMMC_IDMABASE1R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2038
54.9.20 SDMMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2039

55 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2042

55.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2042
55.2 bxCAN main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2042
55.3 bxCAN general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2043
55.3.1 CAN 2.0B active core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2043

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55.3.2 Control, status and configuration registers . . . . . . . . . . . . . . . . . . . . 2043

55.3.3 Tx mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2043
55.3.4 Acceptance filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2044
55.4 bxCAN operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2045
55.4.1 Initialization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2045
55.4.2 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2045
55.4.3 Sleep mode (low-power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2046
55.5 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2047
55.5.1 Silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2047
55.5.2 Loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2047
55.5.3 Loop back combined with silent mode . . . . . . . . . . . . . . . . . . . . . . . . 2048
55.6 Behavior in debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2048
55.7 bxCAN functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2048
55.7.1 Transmission handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2048
55.7.2 Time triggered communication mode . . . . . . . . . . . . . . . . . . . . . . . . . 2050
55.7.3 Reception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2050
55.7.4 Identifier filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2052
55.7.5 Message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2056
55.7.6 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2058
55.7.7 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2058
55.8 bxCAN interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2061
55.9 CAN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2062
55.9.1 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2062
55.9.2 CAN control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2062
55.9.3 CAN mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2072
55.9.4 CAN filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2079
55.9.5 bxCAN register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2083

56 USB on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . . . . . . . . . . 2087

56.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2087
56.2 OTG_FS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2088
56.2.1 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2088
56.2.2 Host-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2089
56.2.3 Peripheral-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2089
56.3 OTG_FS implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2090
56.4 OTG_FS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2091

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56.4.1 OTG_FS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2091

56.4.2 OTG_FS pin and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2091
56.4.3 OTG_FS core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2092
56.4.4 Full-speed OTG PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2092
56.5 OTG_FS dual role device (DRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2093
56.5.1 ID line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2093
56.5.2 HNP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2094
56.5.3 SRP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2094
56.6 OTG_FS as a USB peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2094
56.6.1 SRP-capable peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2095
56.6.2 Peripheral states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2095
56.6.3 Peripheral endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2096
56.7 OTG_FS as a USB host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2098
56.7.1 SRP-capable host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2099
56.7.2 USB host states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2099
56.7.3 Host channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2101
56.7.4 Host scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2102
56.8 OTG_FS SOF trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2103
56.8.1 Host SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2103
56.8.2 Peripheral SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2103
56.9 OTG_FS low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2104
56.10 OTG_FS Dynamic update of the OTG_HFIR register . . . . . . . . . . . . . 2105
56.11 OTG_FS data FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2105
56.11.1 Peripheral FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2106
56.11.2 Host FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2107
56.11.3 FIFO RAM allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2108
56.12 OTG_FS system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2110
56.13 OTG_FS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2110
56.14 OTG_FS control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . .2112
56.14.1 CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2112
56.15 OTG_FS registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2117
56.15.1 OTG control and status register (OTG_GOTGCTL) . . . . . . . . . . . . . 2117
56.15.2 OTG interrupt register (OTG_GOTGINT) . . . . . . . . . . . . . . . . . . . . . 2120
56.15.3 OTG AHB configuration register (OTG_GAHBCFG) . . . . . . . . . . . . . 2121
56.15.4 OTG USB configuration register (OTG_GUSBCFG) . . . . . . . . . . . . . 2122
56.15.5 OTG reset register (OTG_GRSTCTL) . . . . . . . . . . . . . . . . . . . . . . . . 2124

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56.15.6 OTG core interrupt register (OTG_GINTSTS) . . . . . . . . . . . . . . . . . . 2126

56.15.7 OTG interrupt mask register (OTG_GINTMSK) . . . . . . . . . . . . . . . . . 2130
56.15.8 OTG receive status debug read register (OTG_GRXSTSR) . . . . . . . 2133
56.15.9 OTG receive status debug read [alternate] (OTG_GRXSTSR) . . . . . 2134
56.15.10 OTG status read and pop registers (OTG_GRXSTSP) . . . . . . . . . . . 2135
56.15.11 OTG status read and pop registers [alternate] (OTG_GRXSTSP) . . 2136
56.15.12 OTG receive FIFO size register (OTG_GRXFSIZ) . . . . . . . . . . . . . . 2137
56.15.13 OTG host non-periodic transmit FIFO size register
(OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size
(OTG_DIEPTXF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2137
56.15.14 OTG non-periodic transmit FIFO/queue status register
(OTG_HNPTXSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2138
56.15.15 OTG general core configuration register (OTG_GCCFG) . . . . . . . . . 2139
56.15.16 OTG core ID register (OTG_CID) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2141
56.15.17 OTG core LPM configuration register (OTG_GLPMCFG) . . . . . . . . . 2141
56.15.18 OTG power down register (OTG_GPWRDN) . . . . . . . . . . . . . . . . . . 2145
56.15.19 OTG ADP timer, control and status register
(OTG_GADPCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2145
56.15.20 OTG host periodic transmit FIFO size register
(OTG_HPTXFSIZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2147
56.15.21 OTG device IN endpoint transmit FIFO x size register
(OTG_DIEPTXFx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2148
56.15.22 Host-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2148
56.15.23 OTG host configuration register (OTG_HCFG) . . . . . . . . . . . . . . . . . 2148
56.15.24 OTG host frame interval register (OTG_HFIR) . . . . . . . . . . . . . . . . . 2149
56.15.25 OTG host frame number/frame time remaining register
(OTG_HFNUM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2150
56.15.26 OTG_Host periodic transmit FIFO/queue status register
(OTG_HPTXSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2151
56.15.27 OTG host all channels interrupt register (OTG_HAINT) . . . . . . . . . . 2152
56.15.28 OTG host all channels interrupt mask register
(OTG_HAINTMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2152
56.15.29 OTG host port control and status register (OTG_HPRT) . . . . . . . . . . 2153
56.15.30 OTG host channel x characteristics register (OTG_HCCHARx) . . . . 2155
56.15.31 OTG host channel x interrupt register (OTG_HCINTx) . . . . . . . . . . . 2156
56.15.32 OTG host channel x interrupt mask register (OTG_HCINTMSKx) . . 2157
56.15.33 OTG host channel x transfer size register (OTG_HCTSIZx) . . . . . . . 2158
56.15.34 Device-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2159
56.15.35 OTG device configuration register (OTG_DCFG) . . . . . . . . . . . . . . . 2159
56.15.36 OTG device control register (OTG_DCTL) . . . . . . . . . . . . . . . . . . . . 2161

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56.15.37 OTG device status register (OTG_DSTS) . . . . . . . . . . . . . . . . . . . . . 2163

56.15.38 OTG device IN endpoint common interrupt mask register
(OTG_DIEPMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2164
56.15.39 OTG device OUT endpoint common interrupt mask register
(OTG_DOEPMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2165
56.15.40 OTG device all endpoints interrupt register (OTG_DAINT) . . . . . . . . 2166
56.15.41 OTG all endpoints interrupt mask register
(OTG_DAINTMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2167
56.15.42 OTG device VBUS discharge time register
(OTG_DVBUSDIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2167
56.15.43 OTG device VBUS pulsing time register
(OTG_DVBUSPULSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2168
56.15.44 OTG device IN endpoint FIFO empty interrupt mask register
(OTG_DIEPEMPMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2168
56.15.45 OTG device control IN endpoint 0 control register
(OTG_DIEPCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2169
56.15.46 OTG device IN endpoint x control register (OTG_DIEPCTLx) . . . . . 2170
56.15.47 OTG device IN endpoint x interrupt register (OTG_DIEPINTx) . . . . . 2173
56.15.48 OTG device IN endpoint 0 transfer size register
(OTG_DIEPTSIZ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2174
56.15.49 OTG device IN endpoint transmit FIFO status register
(OTG_DTXFSTSx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2175
56.15.50 OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) . 2176
56.15.51 OTG device control OUT endpoint 0 control register
(OTG_DOEPCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2177
56.15.52 OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) . . 2178
56.15.53 OTG device OUT endpoint 0 transfer size register
(OTG_DOEPTSIZ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2180
56.15.54 OTG device OUT endpoint x control register
(OTG_DOEPCTLx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2181
56.15.55 OTG device OUT endpoint x transfer size register
(OTG_DOEPTSIZx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2183
56.15.56 OTG power and clock gating control register (OTG_PCGCCTL) . . . 2184
56.15.57 OTG_FS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2185
56.16 OTG_FS programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2194
56.16.1 Core initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2194
56.16.2 Host initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2194
56.16.3 Device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2195
56.16.4 Host programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2196
56.16.5 Device programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2217
56.16.6 Worst case response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2238

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56.16.7 OTG programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2240

57 Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2246

57.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2246
57.2 Reference Arm® documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2247
57.3 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . 2247
57.3.1 Mechanism to select the JTAG-DP or the SW-DP . . . . . . . . . . . . . . . 2248
57.4 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2248
57.4.1 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2249
57.4.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2249
57.4.3 Internal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . 2250
57.4.4 Using serial wire and releasing the unused debug pins as GPIOs . . 2251
57.5 JTAG TAP connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2251
57.6 ID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2252
57.6.1 MCU device ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2253
57.6.2 Boundary scan TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2253
57.6.3 Cortex®-M4 TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2253
57.6.4 Cortex®-M4 JEDEC-106 ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2254
57.7 JTAG debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2254
57.8 SW debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2256
57.8.1 SW protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2256
57.8.2 SW protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2256
57.8.3 SW DP state machine (reset, idle states, ID code) . . . . . . . . . . . . . . 2257
57.8.4 DP and AP read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2257
57.8.5 SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2258
57.8.6 SW-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2259
57.9 AHB-AP (AHB access port) - valid for both JTAG-DP
and SW-DP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2259
57.10 Core debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2260
57.11 Capability of the debugger host to connect under system reset . . . . . 2260
57.12 FPB (Flash patch breakpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2261
57.13 DWT (data watchpoint trigger) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2261
57.14 ITM (instrumentation trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . 2261
57.14.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2261
57.14.2 Time stamp packets, synchronization and overflow packets . . . . . . . 2262
57.15 ETM (Embedded trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2263

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57.15.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2263

57.15.2 Signal protocol, packet types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2264
57.15.3 Main ETM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2264
57.15.4 Configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2264
57.16 MCU debug component (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . . . . 2265
57.16.1 Debug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . 2265
57.16.2 Debug support for timers, RTC, watchdog, bxCAN and I2C . . . . . . . 2265
57.16.3 Debug MCU configuration register (DBGMCU_CR) . . . . . . . . . . . . . 2265
57.16.4 Debug MCU APB1 freeze register1(DBGMCU_APB1FZR1) . . . . . . 2267
57.16.5 Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2) . . . . . 2269
57.16.6 Debug MCU APB2 freeze register (DBGMCU_APB2FZR) . . . . . . . . 2269
57.17 TPIU (trace port interface unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2271
57.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2271
57.17.2 TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2271
57.17.3 TPIU formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2273
57.17.4 TPIU frame synchronization packets . . . . . . . . . . . . . . . . . . . . . . . . . 2274
57.17.5 Transmission of the synchronization frame packet . . . . . . . . . . . . . . 2274
57.17.6 Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2274
57.17.7 Asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2275
57.17.8 TRACECLKIN connection inside STM32L4+ Series . . . . . . . . . . . . . 2275
57.17.9 TPIU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2276
57.17.10 Example of configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2277
57.17.11 DBGMCU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2278

58 Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2279

58.1 Unique device ID register (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2279
58.2 Flash size data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2280
58.3 Package data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2281

59 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2282

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List of tables

Table 1. STM32L4Rxxx and STM32L4Sxxx memory map and peripheral register boundary
addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 2. STM32L4P5xx and STM32L4Q5xx memory map and peripheral register boundary
addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 3. SRAM2 organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 4. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 5. Memory mapping versus boot mode/physical remap . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 6. Flash module - 2 Mbytes dual-bank organization
(64 bits read width) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 7. Flash module - 2 Mbytes single-bank organization
(128 bits read width) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 8. Flash module - 1 Mbyte dual-bank organization
(64 bits read width) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 9. Flash module - 1 Mbyte single-bank organization
(128 bits read width) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 10. Flash module - 512 Kbytes dual-bank organization
(64 bits read width) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 11. Flash module - 512 Kbytes single-bank organization
(128 bits read width) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 12. Number of wait states according to CPU clock (HCLK) frequency . . . . . . . . . . . . . . . . . . 122
Table 13. Option byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 14. Option byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 15. Flash memory read protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 16. Access status versus protection level and execution modes . . . . . . . . . . . . . . . . . . . . . . 145
Table 17. PCROP protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 18. WRP protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 19. Flash interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 20. Flash interface - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 21. Segment accesses according to the Firewall state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 22. Segment granularity and area ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 23. Firewall register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 24. Range 1 boost mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 25. PVM features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 26. Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 27. Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 28. Low-power run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 29. Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 30. Low-power sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 31. Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 32. Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 33. Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 34. Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 35. Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 36. PWR register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Table 37. Clock source frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Table 38. RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Table 39. CRS features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Table 40. Effect of low-power modes on CRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

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Table 41. Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

Table 42. CRS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Table 43. Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Table 44. GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Table 45. BOOSTEN and ANASWVDD set/reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Table 46. SYSCFG register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Table 47. STM32L4+ Series peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Table 48. DMA1 and DMA2 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Table 49. DMA internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Table 50. Programmable data width and endian behavior (when PINC = MINC = 1) . . . . . . . . . . . 384
Table 51. DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
Table 52. DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Table 53. DMAMUX instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
Table 54. DMAMUX: assignment of multiplexer inputs to resources
(STM32L4Rxxx and STM32L4Sxxx devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Table 55. DMAMUX: assignment of multiplexer inputs to resources
(STM32L4P5xx and STM32L4Q5xx devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Table 56. DMAMUX: assignment of trigger inputs to resources
(STM32L4Rxxx and STM32L4Sxxx devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Table 57. DMAMUX: assignment of trigger inputs to resources
(STM32L4P5xx and STM32L4Q5xx devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Table 58. DMAMUX: assignment of synchronization inputs to resources
(STM32L4Rxxx and STM32L4Sxxx devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Table 59. DMAMUX: assignment of synchronization inputs to resources
(STM32L4P5xx and STM32L4Q5xx devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Table 60. DMAMUX signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Table 61. DMAMUX interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
Table 62. DMAMUX register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Table 63. Supported color mode in input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Table 64. Data order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
Table 65. Alpha mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
Table 66. Supported CLUT color mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Table 67. CLUT data order in system memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Table 68. Supported color mode in output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Table 69. Data order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Table 70. Standard data order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
Table 71. Output FIFO byte reordering steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Table 72. DMA2D interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
Table 73. DMA2D register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
Table 74. Graphic MMU interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
Table 75. Graphic MMU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
Table 76. STM32L4Rxxx and STM32L4Sxxx vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
Table 77. STM32L4P5xx and STM32Q5xx vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
Table 78. EXTI lines connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
Table 79. Extended interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . 489
Table 80. CRC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
Table 81. CRC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
Table 82. FMC implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
Table 83. NOR/PSRAM bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
Table 84. NOR/PSRAM External memory address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
Table 85. NAND memory mapping and timing registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
Table 86. NAND bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501

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Table 87. Programmable NOR/PSRAM access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

Table 88. Non-multiplexed I/O NOR Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
Table 89. 16-bit multiplexed I/O NOR Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
Table 90. Non-multiplexed I/Os PSRAM/SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
Table 91. 16-Bit multiplexed I/O PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
Table 92. NOR Flash/PSRAM: example of supported memories
and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
Table 93. FMC_BCRx bitfields (mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Table 94. FMC_BTRx bitfields (mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
Table 95. FMC_BCRx bitfields (mode A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
Table 96. FMC_BTRx bitfields (mode A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
Table 97. FMC_BWTRx bitfields (mode A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
Table 98. FMC_BCRx bitfields (mode 2/B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
Table 99. FMC_BTRx bitfields (mode 2/B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
Table 100. FMC_BWTRx bitfields (mode 2/B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
Table 101. FMC_BCRx bitfields (mode C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
Table 102. FMC_BTRx bitfields (mode C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
Table 103. FMC_BWTRx bitfields (mode C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
Table 104. FMC_BCRx bitfields (mode D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
Table 105. FMC_BTRx bitfields (mode D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
Table 106. FMC_BWTRx bitfields (mode D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
Table 107. FMC_BCRx bitfields (Muxed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
Table 108. FMC_BTRx bitfields (Muxed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
Table 109. FMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . . . . . . . . . . . . . . . . . . . 528
Table 110. FMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . . . . . . . . . . . . . . . . . . . 529
Table 111. FMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . . . . . . . . . . . . . . . . . . . 530
Table 112. FMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . . . . . . . . . . . . . . . . . . . 531
Table 113. Programmable NAND Flash access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
Table 114. 8-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
Table 115. 16-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
Table 116. Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
Table 117. ECC result relevant bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
Table 118. FMC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
Table 119. OCTOSPI implementation on STM32L4+ Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
Table 120. Command/address phase description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
Table 121. OCTOSPI interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
Table 122. OCTOSPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
Table 123. OCTOSPI implementation on STM32L4+ Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
Table 124. OCTOSPIM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
Table 125. Main ADC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
Table 126. ADC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
Table 127. ADC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
Table 128. Configuring the trigger polarity for regular external triggers . . . . . . . . . . . . . . . . . . . . . . . 633
Table 129. Configuring the trigger polarity for injected external triggers . . . . . . . . . . . . . . . . . . . . . . 633
Table 130. ADC1 - External triggers for regular channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
Table 131. ADC1 - External trigger for injected channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
Table 132. TSAR timings depending on resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
Table 133. Offset computation versus data resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
Table 134. Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
Table 135. Analog watchdog 1 comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
Table 136. Analog watchdog 2 and 3 comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
Table 137. Maximum output results versus N and M (gray cells indicate truncation). . . . . . . . . . . . . 666

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Table 138. Oversampler operating modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670

Table 139. ADC interrupts per each ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
Table 140. DELAY bits versus ADC resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
Table 141. ADC global register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
Table 142. ADC register map and reset values for each ADC (offset=0x000
for master ADC, 0x100 for slave ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
Table 143. ADC register map and reset values (master and slave ADC
common registers) offset = 0x300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
Table 144. DAC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
Table 145. DAC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
Table 146. DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
Table 147. Sample and refresh timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
Table 148. Channel output modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
Table 149. Effect of low-power modes on DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
Table 150. DAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
Table 151. DAC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
Table 152. VREF buffer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763
Table 153. VREFBUF register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
Table 154. DCMI input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
Table 155. Positioning of captured data bytes in 32-bit words (8-bit width) . . . . . . . . . . . . . . . . . . . . 769
Table 156. Positioning of captured data bytes in 32-bit words (10-bit width) . . . . . . . . . . . . . . . . . . . 769
Table 157. Positioning of captured data bytes in 32-bit words (12-bit width) . . . . . . . . . . . . . . . . . . . 769
Table 158. Positioning of captured data bytes in 32-bit words (14-bit width) . . . . . . . . . . . . . . . . . . . 770
Table 159. Data storage in monochrome progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . 775
Table 160. Data storage in RGB progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
Table 161. Data storage in YCbCr progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
Table 162. Data storage in YCbCr progressive video format - Y extraction mode . . . . . . . . . . . . . . . 777
Table 163. DCMI interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
Table 164. DCMI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
Table 165. PSSI input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
Table 166. PSSI internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
Table 167. Positioning of captured data bytes in 32-bit words (8-bit width) . . . . . . . . . . . . . . . . . . . . 793
Table 168. Positioning of captured data bytes in 32-bit words (16-bit width) . . . . . . . . . . . . . . . . . . . 794
Table 169. PSSI interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
Table 170. PSSI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
Table 171. COMP1 input plus assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806
Table 172. COMP1 input minus assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806
Table 173. COMP2 input plus assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
Table 174. COMP2 input minus assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
Table 175. Comparator behavior in the low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
Table 176. Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
Table 177. COMP register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
Table 178. Operational amplifier possible connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
Table 179. Operating modes and calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
Table 180. Effect of low-power modes on the OPAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
Table 181. OPAMP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
Table 182. STM32L4Rxxx and STM32L4Sxxx DFSDM1 implementation . . . . . . . . . . . . . . . . . . . . . 832
Table 183. STM32L4P5xx and STM32L4Q5xx DFSDM1 implementation . . . . . . . . . . . . . . . . . . . . . 832
Table 184. DFSDM external pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
Table 185. DFSDM internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
Table 186. DFSDM triggers connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
Table 187. DFSDM break connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835

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Table 188. Filter maximum output resolution (peak data values from filter output)
for some FOSR values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850
Table 189. Integrator maximum output resolution (peak data values from integrator
output) for some IOSR values and FOSR = 256 and Sinc3 filter type (largest data) . . . . 851
Table 190. DFSDM interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859
Table 191. DFSDM register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
Table 192. LTDC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
Table 193. LTDC pins and signal interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
Table 194. Clock domain for each register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
Table 195. Pixel data mapping versus color format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897
Table 196. LTDC interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901
Table 197. LTDC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921
Table 198. Location of color components in the LTDC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
Table 199. Multiplicity of the payload size in pixels for each data type . . . . . . . . . . . . . . . . . . . . . . . 930
Table 200. Contention detection timeout counters configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
Table 201. List of events of different categories of the PRESP_TO counter . . . . . . . . . . . . . . . . . . . 943
Table 202. PRESP_TO counter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946
Table 203. Frame requirement configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
Table 204. RGB components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960
Table 205. Slew-rate and delay tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
Table 206. Custom lane configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
Table 207. Custom timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
Table 208. DSI wrapper interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
Table 209. Error causes and recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
Table 210. DSIHOST register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040
Table 211. Acquisition sequence summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
Table 212. Spread spectrum deviation versus AHB clock frequency . . . . . . . . . . . . . . . . . . . . . . . . 1050
Table 213. I/O state depending on its mode and IODEF bit value . . . . . . . . . . . . . . . . . . . . . . . . . . 1051
Table 214. Effect of low-power modes on TSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053
Table 215. Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053
Table 216. TSC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
Table 217. RNG internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
Table 218. RNG interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072
Table 219. RNG configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073
Table 220. RNG register map and reset map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077
Table 221. RNG internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079
Table 222. RNG interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087
Table 223. RNG configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
Table 224. RNG register map and reset map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093
Table 225. AES internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
Table 226. CTR mode initialization vector definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112
Table 227. GCM last block definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1114
Table 228. GCM mode IVI bitfield initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115
Table 229. Initialization of AES_IVRx registers in CCM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1123
Table 230. Key endianness in AES_KEYRx registers (128- or 256-bit key length) . . . . . . . . . . . . . 1128
Table 231. AES interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131
Table 232. Processing latency for ECB, CBC and CTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131
Table 233. Processing latency for GCM and CCM (in clock cycles). . . . . . . . . . . . . . . . . . . . . . . . . 1131
Table 234. AES register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1142
Table 235. HASH internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146
Table 236. Hash processor outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1149
Table 237. HASH interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1156

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Table 238. Processing time (in clock cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1156

Table 239. HASH1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166
Table 240. Internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1168
Table 241. PKA integer arithmetic functions list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169
Table 242. PKA prime field (Fp) elliptic curve functions list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169
Table 243. Montgomery parameter computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1174
Table 244. Modular addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175
Table 245. Modular subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175
Table 246. Montgomery multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1176
Table 247. Modular exponentiation (normal mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177
Table 248. Modular exponentiation (fast mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177
Table 249. Modular inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177
Table 250. Modular reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178
Table 251. Arithmetic addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178
Table 252. Arithmetic subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178
Table 253. Arithmetic multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179
Table 254. Arithmetic comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179
Table 255. CRT exponentiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1180
Table 256. Point on elliptic curve Fp check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1181
Table 257. ECC Fp scalar multiplication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1181
Table 258. ECC Fp scalar multiplication (Fast Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1182
Table 259. ECDSA sign - Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183
Table 260. ECDSA sign - Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183
Table 261. Extended ECDSA sign (extra outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1184
Table 262. ECDSA verification (inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1184
Table 263. ECDSA verification (outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1184
Table 264. ECC curves parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1185
Table 265. Modular exponentiation computation times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191
Table 266. ECC scalar multiplication computation times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191
Table 267. ECDSA signature average computation times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191
Table 268. ECDSA verification average computation times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192
Table 269. Montgomery parameters average computation times. . . . . . . . . . . . . . . . . . . . . . . . . . . 1192
Table 270. PKA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192
Table 271. PKA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1196
Table 272. Behavior of timer outputs versus BRK/BRK2 inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1238
Table 273. Break protection disarming conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1240
Table 274. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246
Table 275. TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263
Table 276. Output control bits for complementary OCx and OCxN channels with break feature . . . 1277
Table 277. TIM1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1298
Table 278. TIM8 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1300
Table 279. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1337
Table 280. TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353
Table 281. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1364
Table 282. TIM2/TIM3/TIM4/TIM5 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 1372
Table 283. Break protection disarming conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1403
Table 284. TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1419
Table 285. Output control bits for complementary OCx and OCxN channels with break feature
(TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1429
Table 286. TIM15 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1438
Table 287. Output control bits for complementary OCx and OCxN channels with break feature
(TIM16/17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1451

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Table 288. TIM16/TIM17 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1462

Table 289. TIMx register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1476
Table 290. STM32L4Rxxx and STM32L4Sxxx LPTIM features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478
Table 291. LPTIM input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479
Table 292. LPTIM internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479
Table 293. LPTIM1 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479
Table 294. LPTIM2 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1480
Table 295. Prescaler division ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1481
Table 296. Encoder counting scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1488
Table 297. Effect of low-power modes on the LPTIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489
Table 298. Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490
Table 299. LPTIM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1501
Table 300. STM32L4Pxxx and STM32L4Qxxx LPTIM features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504
Table 301. LPTIM input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505
Table 302. LPTIM internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505
Table 303. LPTIM1 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505
Table 304. LPTIM2 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1506
Table 305. Prescaler division ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507
Table 306. Encoder counting scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1514
Table 307. Effect of low-power modes on the LPTIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1517
Table 308. Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1517
Table 309. LPTIM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1528
Table 310. IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1539
Table 311. WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1545
Table 312. RTC pin PC13 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1549
Table 313. RTC_OUT mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1550
Table 314. RTC functions over modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1551
Table 315. Effect of low-power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1563
Table 316. Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564
Table 317. RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1589
Table 318. RTC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1593
Table 319. RTC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1593
Table 320. RTC interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1593
Table 321. PC13 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1594
Table 322. RTC_OUT mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1596
Table 323. Effect of low-power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1608
Table 324. RTC pins functionality over modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1609
Table 325. Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1609
Table 326. RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1631
Table 327. TAMP input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634
Table 328. TAMP internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1635
Table 329. TAMP interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1635
Table 330. Effect of low-power modes on TAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1638
Table 331. Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1638
Table 332. TAMP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1647
Table 333. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1649
Table 334. I2C input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651
Table 335. I2C internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651
Table 336. Comparison of analog vs. digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1653
Table 337. I2C-SMBus specification data setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . . . . 1656
Table 338. I2C configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1660
Table 339. I2C-SMBus specification clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1671

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Table 340. Examples of timing settings for fI2CCLK = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1681

Table 341. Examples of timings settings for fI2CCLK = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . 1681
Table 342. Examples of timings settings for fI2CCLK = 48 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . 1682
Table 343. SMBus timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1684
Table 344. SMBus with PEC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1686
Table 345. Examples of TIMEOUTA settings for various I2CCLK frequencies
(max tTIMEOUT = 25 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1687
Table 346. Examples of TIMEOUTB settings for various I2CCLK frequencies . . . . . . . . . . . . . . . . 1687
Table 347. Examples of TIMEOUTA settings for various I2CCLK frequencies
(max tIDLE = 50 µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1688
Table 348. Effect of low-power modes on the I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1699
Table 349. I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1700
Table 350. I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1716
Table 351. USART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1720
Table 352. Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1735
Table 353. Tolerance of the USART receiver when BRR [3:0] = 0000. . . . . . . . . . . . . . . . . . . . . . . 1738
Table 354. Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . . . . . . . . . 1739
Table 355. USART frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1744
Table 356. USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1767
Table 357. USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1804
Table 358. USART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1808
Table 359. Error calculation for programmed baud rates at lpuart_ker_ck_pres= 32,768 KHz . . . . 1819
Table 360. Error calculation for programmed baud rates at fCK = 100 MHz . . . . . . . . . . . . . . . . . . 1820
Table 361. Tolerance of the LPUART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1821
Table 363. LPUART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1832
Table 364. LPUART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1857
Table 365. STM32L4Rxxx/STM32L4Sxxx and STM32L4P5xx/STM32L4Q5xx SPI implementation 1860
Table 366. STM32L4Rxxx/STM32L4Sxxx and STM32L4P5xx/STM32L4Q5xx SPI implementation 1860
Table 367. SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1884
Table 368. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1893
Table 369. STM32L4S/STM32L4R SAI interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1895
Table 370. SAI internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1897
Table 371. SAI input/output pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1897
Table 372. External synchronization selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1900
Table 373. Clock generator programming examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1907
Table 374. TDM settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1914
Table 375. Allowed TDM frame configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1916
Table 376. SOPD pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1920
Table 377. Parity bit calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1920
Table 378. Audio sampling frequency versus symbol rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1921
Table 379. SAI interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1930
Table 380. SAI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1960
Table 381. STM32L4Rxxx and STM32L4Sxxx SDMMC features . . . . . . . . . . . . . . . . . . . . . . . . . . 1962
Table 382. STM32L4P5xx and STM32L4Q5xx SDMMC features . . . . . . . . . . . . . . . . . . . . . . . . . . 1962
Table 383. SDMMC operation modes SD & SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1965
Table 384. SDMMC operation modes e•MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1965
Table 385. SDMMC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1966
Table 386. SDMMC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1966
Table 387. SDMMC Command and data phase selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1968
Table 388. Command token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1973
Table 389. Short response with CRC token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1974
Table 390. Short response without CRC token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1974

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Table 391. Long response with CRC token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1974

Table 392. Specific Commands overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1975
Table 393. Command path status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1976
Table 394. Command path error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1976
Table 395. Data token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1984
Table 396. Data path status flags and clear bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1984
Table 397. Data path error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1986
Table 398. Data FIFO access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1987
Table 399. Transmit FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1988
Table 400. Receive FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1989
Table 401. AHB and SDMMC_CK clock frequency relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1992
Table 402. SDIO special operation control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1993
Table 403. 4-bit mode Start, interrupt, and CRC-status Signaling detection . . . . . . . . . . . . . . . . . . 1997
Table 404. CMD12 use cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2001
Table 405. SDMMC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2015
Table 406. Response type and SDMMC_RESPxR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2023
Table 407. SDMMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2039
Table 408. Transmit mailbox mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2057
Table 409. Receive mailbox mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2057
Table 410. bxCAN register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2083
Table 411. OTG_FS speeds supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2087
Table 412. OTG_FS implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2090
Table 413. OTG_FS input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2091
Table 414. OTG_FS input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2092
Table 415. Compatibility of STM32 low power modes with the OTG . . . . . . . . . . . . . . . . . . . . . . . . 2104
Table 416. Core global control and status registers (CSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2112
Table 417. Host-mode control and status registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2113
Table 418. Device-mode control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2114
Table 419. Data FIFO (DFIFO) access register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2116
Table 420. Power and clock gating control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 2116
Table 421. TRDT values (FS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2123
Table 422. Minimum duration for soft disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2162
Table 423. OTG_FS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2185
Table 424. SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2249
Table 425. Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2249
Table 426. JTAG debug port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2254
Table 427. 32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . . 2255
Table 428. Packet request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2256
Table 429. ACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2257
Table 430. DATA transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2257
Table 431. SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2258
Table 432. Cortex®-M4 AHB-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2259
Table 433. Core debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2260
Table 434. Main ITM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2262
Table 435. Main ETM registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2264
Table 436. Asynchronous TRACE pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2271
Table 437. Synchronous TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2272
Table 438. Flexible TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2272
Table 439. Important TPIU registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2276
Table 440. DBGMCU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2278
Table 441. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2282

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List of figures RM0432

List of figures

Figure 1. System architecture for STM32L4Rxxx and STM32L4Sxxx . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 2. System architecture for STM32L4P5xx and STM32L4Q5xx . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 3. Memory map for STM32L4Rxxx and STM32L4Sxxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 4. Memory map for STM32L4P5xx and STM32L4Q5xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 5. Sequential 16-bit instructions execution (64-bit read data width) . . . . . . . . . . . . . . . . . . . 124
Figure 6. Changing the Read protection (RDP) level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 7. STM32L4+ Series firewall connection schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 8. Firewall functional states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 9. STM32L4P5xx/Q5xx, STM32L4S5xx/R5xx and STM32L4S7xx/L4R7xx
power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 10. STM32L4S9xx/L4R9xx power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 11. Internal main regulator overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 12. Brown-out reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 13. PVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 14. Low-power modes possible transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 15. Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Figure 16. Clock tree for STM32L4Rxxx and STM32L4Sxxx devices . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 17. DSI clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Figure 18. Clock tree for STM32L4P5xx and STM32L4Q5xx devices. . . . . . . . . . . . . . . . . . . . . . . . 245
Figure 19. HSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Figure 20. Frequency measurement with TIM15 in capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Figure 21. Frequency measurement with TIM16 in capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Figure 22. Frequency measurement with TIM17 in capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Figure 23. CRS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Figure 24. CRS counter behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Figure 25. Basic structure of an I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Figure 26. Basic structure of a 5-Volt tolerant I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Figure 27. Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Figure 28. Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Figure 29. Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Figure 30. High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Figure 31. DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
Figure 32. DMAMUX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Figure 33. Synchronization mode of the DMAMUX request line multiplexer channel . . . . . . . . . . . . 407
Figure 34. Event generation of the DMA request line multiplexer channel . . . . . . . . . . . . . . . . . . . . 407
Figure 35. DMA2D block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Figure 36. Intel 8080 16-bit mode (RGB565) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
Figure 37. Intel 8080 18/24-bit mode (RGB888) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Figure 38. Chrom-GRC™ block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
Figure 39. Virtual buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Figure 40. Virtual buffer and physical buffer memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
Figure 41. MMU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
Figure 42. Block validation/comparator implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
Figure 43. Configurable interrupt/event block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
Figure 44. External interrupt/event GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
Figure 45. CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
Figure 46. FMC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
Figure 47. FMC memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

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Figure 48. Mode 1 read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

Figure 49. Mode 1 write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Figure 50. Mode A read access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
Figure 51. Mode A write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
Figure 52. Mode 2 and mode B read access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
Figure 53. Mode 2 write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Figure 54. Mode B write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Figure 55. Mode C read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
Figure 56. Mode C write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
Figure 57. Mode D read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
Figure 58. Mode D write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
Figure 59. Muxed read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
Figure 60. Muxed write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
Figure 61. Asynchronous wait during a read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
Figure 62. Asynchronous wait during a write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
Figure 63. Wait configuration waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
Figure 64. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . . . . . . . . 528
Figure 65. Synchronous multiplexed write mode waveforms - PSRAM (CRAM). . . . . . . . . . . . . . . . 530
Figure 66. NAND Flash controller waveforms for common memory access . . . . . . . . . . . . . . . . . . . 544
Figure 67. Access to non ‘CE don’t care’ NAND-Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
Figure 68. OCTOSPI block diagram for octal communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
Figure 69. OCTOSPI block diagram in Quad mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
Figure 70. OCTOSPI block diagram when dual-Flash is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
Figure 71. SDR read command in Octal mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
Figure 72. DTR read in Octal mode with DQS (Macronix mode) example . . . . . . . . . . . . . . . . . . . . 562
Figure 73. SDR write command in Octo-SPI mode example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
Figure 74. DTR write in Octal mode (Macronix mode) example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
Figure 75. Example of HyperBus read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
Figure 76. HyperBus read operation with initial latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
Figure 77. HyperBus write operation with initial latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
Figure 78. HyperBus read operation with additional latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
Figure 79. HyperBus write operation with additional latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
Figure 80. HyperBus write operation with no latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
Figure 81. HyperBus read operation page crossing with latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
Figure 82. nCS when CKMODE=0 (T = CLK period). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
Figure 83. CS when CKMODE=1 in SDR mode (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . . . 580
Figure 84. nCS when CKMODE=1 in DDTR mode (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . 581
Figure 85. nCS when CKMODE=1 with an abort (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . . . 581
Figure 86. OCTOSPIM block diagram for SMT32L4P5xx and STM32L4Q5xx . . . . . . . . . . . . . . . . . 605
Figure 87. OCTOSPIM block diagram for SMT32L4Rxxx and STM32L4Sxxx . . . . . . . . . . . . . . . . . 605
Figure 88. ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
Figure 89. ADC clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
Figure 90. ADC1 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
Figure 91. ADC2 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
Figure 92. ADC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
Figure 93. Updating the ADC calibration factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
Figure 94. Mixing single-ended and differential channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
Figure 95. Enabling / disabling the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
Figure 96. Analog to digital conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
Figure 97. Stopping ongoing regular conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
Figure 98. Stopping ongoing regular and injected conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
Figure 99. Triggers sharing between ADC master and ADC slave . . . . . . . . . . . . . . . . . . . . . . . . . . 634

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Figure 100. Injected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637

Figure 101. Example of JSQR queue of context (sequence change) . . . . . . . . . . . . . . . . . . . . . . . . . 640
Figure 102. Example of JSQR queue of context (trigger change) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
Figure 103. Example of JSQR queue of context with overflow before conversion . . . . . . . . . . . . . . . 641
Figure 104. Example of JSQR queue of context with overflow during conversion . . . . . . . . . . . . . . . 641
Figure 105. Example of JSQR queue of context with empty queue (case JQM=0). . . . . . . . . . . . . . . 642
Figure 106. Example of JSQR queue of context with empty queue (case JQM=1). . . . . . . . . . . . . . . 643
Figure 107. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion. . . . . . . . . . . . . . . . . . . . . . . 643
Figure 108. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion and a new
trigger occurs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
Figure 109. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs outside an ongoing conversion . . . . . . . . . . . . . . . . . . . . . . 644
Figure 110. Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) . . . . . . . . . . . . . . . . . . 645
Figure 111. Flushing JSQR queue of context by setting ADDIS=1 (JQM=0). . . . . . . . . . . . . . . . . . . . 645
Figure 112. Flushing JSQR queue of context by setting ADDIS=1 (JQM=1). . . . . . . . . . . . . . . . . . . . 646
Figure 113. Single conversions of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
Figure 114. Continuous conversion of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . 648
Figure 115. Single conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
Figure 116. Continuous conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . 649
Figure 117. Right alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
Figure 118. Right alignment (offset enabled, signed value). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
Figure 119. Left alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
Figure 120. Left alignment (offset enabled, signed value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
Figure 121. Example of overrun (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
Figure 122. AUTODLY=1, regular conversion in continuous mode, software trigger . . . . . . . . . . . . . 657
Figure 123. AUTODLY=1, regular HW conversions interrupted by injected conversions
(DISCEN=0; JDISCEN=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
Figure 124. AUTODLY=1, regular HW conversions interrupted by injected conversions . . . . . . . . . . . . .
(DISCEN=1, JDISCEN=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
Figure 125. AUTODLY=1, regular continuous conversions interrupted by injected conversions . . . . 660
Figure 126. AUTODLY=1 in auto- injected mode (JAUTO=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
Figure 127. Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
Figure 128. ADCy_AWDx_OUT signal generation (on all regular channels). . . . . . . . . . . . . . . . . . . . 663
Figure 129. ADCy_AWDx_OUT signal generation (AWDx flag not cleared by software) . . . . . . . . . . 664
Figure 130. ADCy_AWDx_OUT signal generation (on a single regular channel) . . . . . . . . . . . . . . . . 664
Figure 131. ADCy_AWDx_OUT signal generation (on all injected channels) . . . . . . . . . . . . . . . . . . . 664
Figure 132. 20-bit to 16-bit result truncation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
Figure 133. Numerical example with 5-bit shift and rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
Figure 134. Triggered regular oversampling mode (TROVS bit = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 667
Figure 135. Regular oversampling modes (4x ratio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
Figure 136. Regular and injected oversampling modes used simultaneously . . . . . . . . . . . . . . . . . . . 669
Figure 137. Triggered regular oversampling with injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
Figure 138. Oversampling in auto-injected mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
Figure 139. Dual ADC block diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
Figure 140. Injected simultaneous mode on 4 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . . 673
Figure 141. Regular simultaneous mode on 16 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . 675
Figure 142. Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode. . . . . . 676
Figure 143. Interleaved mode on 1 channel in single conversion mode: dual ADC mode. . . . . . . . . . 677
Figure 144. Interleaved conversion with injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
Figure 145. Alternate trigger: injected group of each ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678

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Figure 146. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode . . . . . . . . . . . . 679
Figure 147. Alternate + regular simultaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
Figure 148. Case of trigger occurring during injected conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
Figure 149. Interleaved single channel CH0 with injected sequence CH11, CH12 . . . . . . . . . . . . . . . 681
Figure 150. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 1: Master interrupted first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
Figure 151. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 2: Slave interrupted first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
Figure 152. DMA Requests in regular simultaneous mode when MDMA=0b00 . . . . . . . . . . . . . . . . . 682
Figure 153. DMA requests in regular simultaneous mode when MDMA=0b10 . . . . . . . . . . . . . . . . . . 683
Figure 154. DMA requests in interleaved mode when MDMA=0b10 . . . . . . . . . . . . . . . . . . . . . . . . . . 683
Figure 155. Temperature sensor channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
Figure 156. VBAT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
Figure 157. VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
Figure 158. Dual-channel DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
Figure 159. Data registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
Figure 160. Data registers in dual DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
Figure 161. Timing diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . . 730
Figure 162. DAC LFSR register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
Figure 163. DAC conversion (SW trigger enabled) with LFSR wave generation . . . . . . . . . . . . . . . . 733
Figure 164. DAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
Figure 165. DAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 734
Figure 166. DAC Sample and hold mode phase diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
Figure 167. DCMI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
Figure 168. Top-level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
Figure 169. DCMI signal waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768
Figure 170. Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
Figure 171. Frame capture waveforms in snapshot mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772
Figure 172. Frame capture waveforms in continuous grab mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773
Figure 173. Coordinates and size of the window after cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773
Figure 174. Data capture waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
Figure 175. Pixel raster scan order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
Figure 176. PSSI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
Figure 177. Top-level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
Figure 178. Data enable in receive mode waveform diagram (CKPOL=0) . . . . . . . . . . . . . . . . . . . . . 795
Figure 179. Data enable waveform diagram in transmit mode (CKPOL=0). . . . . . . . . . . . . . . . . . . . . 795
Figure 180. Ready in receive mode waveform diagram (CKPOL=0). . . . . . . . . . . . . . . . . . . . . . . . . . 796
Figure 181. Bidirectional PSSI_DE/PSSI_RDY waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
Figure 182. Bidirectional PSSI_DE/PSSI_RDY connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . 797
Figure 183. Comparator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806
Figure 184. Window mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
Figure 185. Comparator hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
Figure 186. Comparator output blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
Figure 187. Standalone mode: external gain setting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
Figure 188. Follower configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820
Figure 189. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used . . . . . . . . . . . . 821
Figure 190. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input used for
filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
Figure 191. Single DFSDM block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
Figure 192. Input channel pins redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837
Figure 193. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
Figure 194. Clock absence timing diagram for SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841

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Figure 195. Clock absence timing diagram for Manchester coding . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
Figure 196. First conversion for Manchester coding (Manchester synchronization) . . . . . . . . . . . . . . 844
Figure 197. DFSDM_CHyDATINR registers operation modes and assignment . . . . . . . . . . . . . . . . . 848
Figure 198. Example: Sinc3 filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850
Figure 199. LTDC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
Figure 200. LCD-TFT synchronous timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
Figure 201. Layer window programmable parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897
Figure 202. Blending two layers with background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
Figure 203. Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901
Figure 204. DSI Host block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
Figure 205. DSI Host architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
Figure 206. Flow to update the LTDC interface configuration using shadow registers . . . . . . . . . . . . 932
Figure 207. Immediate update procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933
Figure 208. Configuration update during the trasmission of a frame . . . . . . . . . . . . . . . . . . . . . . . . . . 933
Figure 209. Adapted command mode usage flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
Figure 210. 24 bpp APB pixel to byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
Figure 211. 18 bpp APB pixel to byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
Figure 212. 16 bpp APB pixel to byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
Figure 213. 12 bpp APB pixel to byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
Figure 214. 8 bpp APB pixel to byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
Figure 215. Timing of PRESP_TO after a bus turn-around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
Figure 216. Timing of PRESP_TO after a Read Request (HS or LP) . . . . . . . . . . . . . . . . . . . . . . . . . 945
Figure 217. Timing of PRESP_TO after a Write Request (HS or LP) . . . . . . . . . . . . . . . . . . . . . . . . . 946
Figure 218. Effect of Prep mode at 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947
Figure 219. Command transmission periods within the image area . . . . . . . . . . . . . . . . . . . . . . . . . . 948
Figure 220. Transmission of commands on the last line of a frame. . . . . . . . . . . . . . . . . . . . . . . . . . . 949
Figure 221. LPSIZE for Non-Burst with sync pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
Figure 222. LPSIZE for Burst or Non-Burst with sync events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
Figure 223. VLPSIZE for Non-Burst with sync pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952
Figure 224. VLPSIZE for Non-Burst with sync events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952
Figure 225. VLPSIZE for Burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952
Figure 226. Location of LPSIZE and VLPSIZE in the image area . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
Figure 227. Clock lane and data lanes in HS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956
Figure 228. Clock lane in HS and data lanes in LP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956
Figure 229. Clock lane and data lanes in LP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956
Figure 230. Command transmission by the generic interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
Figure 231. Vertical color bar mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959
Figure 232. Horizontal color bar mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959
Figure 233. RGB888 BER testing pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960
Figure 234. Vertical pattern (103x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961
Figure 235. Horizontal pattern (103x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961
Figure 236. PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965
Figure 237. Error sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
Figure 238. Video packet transmission configuration flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 979
Figure 239. Programming sequence to send a test pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
Figure 240. Frame configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
Figure 241. TSC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046
Figure 242. Surface charge transfer analog I/O group structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047
Figure 243. Sampling capacitor voltage variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
Figure 244. Charge transfer acquisition sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049
Figure 245. Spread spectrum variation principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
Figure 246. RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065

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Figure 247. Entropy source model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066

Figure 248. RNG initialization overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069
Figure 249. RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079
Figure 250. NIST SP800-90B entropy source model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080
Figure 251. RNG initialization overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083
Figure 252. AES block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
Figure 253. ECB encryption and decryption principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097
Figure 254. CBC encryption and decryption principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098
Figure 255. CTR encryption and decryption principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099
Figure 256. GCM encryption and authentication principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100
Figure 257. GMAC authentication principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100
Figure 258. CCM encryption and authentication principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1101
Figure 259. Encryption key derivation for ECB/CBC decryption (Mode 2). . . . . . . . . . . . . . . . . . . . . 1104
Figure 260. Example of suspend mode management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105
Figure 261. ECB encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1106
Figure 262. ECB decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1106
Figure 263. CBC encryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107
Figure 264. CBC decryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107
Figure 265. ECB/CBC encryption (Mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1108
Figure 266. ECB/CBC decryption (Mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1109
Figure 267. Message construction in CTR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111
Figure 268. CTR encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112
Figure 269. CTR decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112
Figure 270. Message construction in GCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1114
Figure 271. GCM authenticated encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115
Figure 272. Message construction in GMAC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119
Figure 273. GMAC authentication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119
Figure 274. Message construction in CCM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120
Figure 275. CCM mode authenticated encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
Figure 276. 128-bit block construction with respect to data swap . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127
Figure 277. DMA transfer of a 128-bit data block during input phase . . . . . . . . . . . . . . . . . . . . . . . . 1129
Figure 278. DMA transfer of a 128-bit data block during output phase . . . . . . . . . . . . . . . . . . . . . . . 1129
Figure 279. HASH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1145
Figure 280. Message data swapping feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147
Figure 281. HASH suspend/resume mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1153
Figure 282. PKA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1168
Figure 283. Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1198
Figure 284. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1200
Figure 285. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1200
Figure 286. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1202
Figure 287. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1202
Figure 288. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203
Figure 289. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203
Figure 290. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . 1204
Figure 291. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . 1204
Figure 292. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1206
Figure 293. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1206
Figure 294. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1207
Figure 295. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1207
Figure 296. Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . 1208
Figure 297. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . 1209
Figure 298. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1210

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Figure 299. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . 1210
Figure 300. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1211
Figure 301. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . 1211
Figure 302. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . 1212
Figure 303. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . 1213
Figure 304. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1214
Figure 305. TIM1 ETR input circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1214
Figure 306. TIM8 ETR input circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1214
Figure 307. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 1215
Figure 308. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1216
Figure 309. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217
Figure 310. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217
Figure 311. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218
Figure 312. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 1219
Figure 313. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1220
Figure 314. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . . . . . . . . 1220
Figure 315. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . 1221
Figure 316. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . . . . . . . . . . . . . 1221
Figure 317. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223
Figure 318. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225
Figure 319. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1226
Figure 320. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227
Figure 321. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . 1229
Figure 322. Combined PWM mode on channel 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1230
Figure 323. 3-phase combined PWM signals with multiple trigger pulses per period . . . . . . . . . . . . 1231
Figure 324. Complementary output with dead-time insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232
Figure 325. Dead-time waveforms with delay greater than the negative pulse . . . . . . . . . . . . . . . . . 1232
Figure 326. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . 1233
Figure 327. Break and Break2 circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235
Figure 328. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . . . . . . . 1237
Figure 329. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . . . . . . . . . . . 1238
Figure 330. PWM output state following BRK assertion (OSSI=0) . . . . . . . . . . . . . . . . . . . . . . . . . . 1239
Figure 331. Output redirection (BRK2 request not represented) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1240
Figure 332. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1241
Figure 333. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242
Figure 334. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1243
Figure 335. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245
Figure 336. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . 1246
Figure 337. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . 1247
Figure 338. Measuring time interval between edges on 3 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1248
Figure 339. Example of Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1250
Figure 340. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1251
Figure 341. Control circuit in Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1252
Figure 342. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253
Figure 343. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . 1254
Figure 344. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1304
Figure 345. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1306
Figure 346. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1306
Figure 347. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1307
Figure 348. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1308
Figure 349. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1308
Figure 350. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1309

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Figure 351. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . 1309
Figure 352. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . 1310
Figure 353. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1311
Figure 354. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1311
Figure 355. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1312
Figure 356. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1312
Figure 357. Counter timing diagram, Update event when repetition counter
is not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1313
Figure 358. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . 1314
Figure 359. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1315
Figure 360. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . 1315
Figure 361. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1316
Figure 362. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . 1316
Figure 363. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . 1317
Figure 364. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 1318
Figure 365. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1318
Figure 366. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1319
Figure 367. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1320
Figure 368. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1321
Figure 369. Capture/Compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . 1322
Figure 370. Capture/Compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1322
Figure 371. Output stage of Capture/Compare channel (channel 1) . . . . . . . . . . . . . . . . . . . . . . . . . 1323
Figure 372. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1325
Figure 373. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1327
Figure 374. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1328
Figure 375. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1329
Figure 376. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . 1330
Figure 377. Combined PWM mode on channels 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1332
Figure 378. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1333
Figure 379. Example of one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1334
Figure 380. Retriggerable one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1336
Figure 381. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . 1337
Figure 382. Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . 1338
Figure 383. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1339
Figure 384. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1340
Figure 385. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1341
Figure 386. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . 1342
Figure 387. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1342
Figure 388. Gating TIM2 with OC1REF of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1343
Figure 389. Gating TIM2 with Enable of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1344
Figure 390. Triggering TIM2 with update of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1345
Figure 391. Triggering TIM2 with Enable of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1345
Figure 392. Triggering TIM3 and TIM2 with TIM3 TI1 input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1346
Figure 393. TIM15 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1377
Figure 394. TIM16/TIM17 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1378
Figure 395. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1380
Figure 396. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1380
Figure 397. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1382
Figure 398. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1382
Figure 399. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1383
Figure 400. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1383
Figure 401. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not

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preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1384
Figure 402. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1384
Figure 403. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . 1386
Figure 404. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 1387
Figure 405. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1387
Figure 406. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388
Figure 407. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 1389
Figure 408. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1389
Figure 409. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . 1390
Figure 410. Output stage of capture/compare channel (channel 2 for TIM15) . . . . . . . . . . . . . . . . . 1390
Figure 411. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1392
Figure 412. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1394
Figure 413. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1395
Figure 414. Combined PWM mode on channel 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1396
Figure 415. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1397
Figure 416. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . 1397
Figure 417. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . 1398
Figure 418. Break circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1400
Figure 419. Output behavior in response to a break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1402
Figure 420. Output redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1404
Figure 421. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1406
Figure 422. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407
Figure 423. Measuring time interval between edges on 2 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1409
Figure 424. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1410
Figure 425. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1411
Figure 426. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1412
Figure 427. Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1464
Figure 428. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1466
Figure 429. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1466
Figure 430. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1467
Figure 431. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1468
Figure 432. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1468
Figure 433. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1469
Figure 434. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1469
Figure 435. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1470
Figure 436. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 1471
Figure 437. Low-power timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478
Figure 438. Glitch filter timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1481
Figure 439. LPTIM output waveform, single counting mode configuration . . . . . . . . . . . . . . . . . . . . 1483
Figure 440. LPTIM output waveform, Single counting mode configuration
and Set-once mode activated (WAVE bit is set) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1483
Figure 441. LPTIM output waveform, Continuous counting mode configuration . . . . . . . . . . . . . . . . 1484
Figure 442. Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1485
Figure 443. Encoder mode counting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489
Figure 444. Low-power timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504
Figure 445. Glitch filter timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507
Figure 446. LPTIM output waveform, single counting mode configuration
when repetition register content is different than zero (with PRELOAD = 1) . . . . . . . . . 1509
Figure 447. LPTIM output waveform, Single counting mode configuration

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and Set-once mode activated (WAVE bit is set) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1509

Figure 448. LPTIM output waveform, Continuous counting mode configuration . . . . . . . . . . . . . . . . 1510
Figure 449. Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1511
Figure 450. Encoder mode counting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1515
Figure 451. Continuous counting mode when repetition register LPTIM_RCR
different from zero (with PRELOAD = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1516
Figure 452. IRTIM internal hardware connections with TIM16 and TIM17 . . . . . . . . . . . . . . . . . . 1530
Figure 453. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1531
Figure 454. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1541
Figure 455. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1542
Figure 456. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1548
Figure 457. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1592
Figure 458. TAMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634
Figure 459. I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1650
Figure 460. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1652
Figure 461. Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654
Figure 462. I2C initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1657
Figure 463. Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1658
Figure 464. Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1659
Figure 465. Slave initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1662
Figure 466. Transfer sequence flowchart for I2C slave transmitter,
NOSTRETCH= 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1664
Figure 467. Transfer sequence flowchart for I2C slave transmitter,
NOSTRETCH= 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1665
Figure 468. Transfer bus diagrams for I2C slave transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666
Figure 469. Transfer sequence flowchart for slave receiver with NOSTRETCH=0 . . . . . . . . . . . . . 1667
Figure 470. Transfer sequence flowchart for slave receiver with NOSTRETCH=1 . . . . . . . . . . . . . 1668
Figure 471. Transfer bus diagrams for I2C slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1668
Figure 472. Master clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1670
Figure 473. Master initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672
Figure 474. 10-bit address read access with HEAD10R=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672
Figure 475. 10-bit address read access with HEAD10R=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673
Figure 476. Transfer sequence flowchart for I2C master transmitter for N≤255 bytes . . . . . . . . . . . 1674
Figure 477. Transfer sequence flowchart for I2C master transmitter for N>255 bytes . . . . . . . . . . . 1675
Figure 478. Transfer bus diagrams for I2C master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1676
Figure 479. Transfer sequence flowchart for I2C master receiver for N≤255 bytes . . . . . . . . . . . . . 1678
Figure 480. Transfer sequence flowchart for I2C master receiver for N >255 bytes . . . . . . . . . . . . . 1679
Figure 481. Transfer bus diagrams for I2C master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1680
Figure 482. Timeout intervals for tLOW:SEXT, tLOW:MEXT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1685
Figure 483. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC. . . . . . . . . . . 1689
Figure 484. Transfer bus diagrams for SMBus slave transmitter (SBC=1) . . . . . . . . . . . . . . . . . . . . 1689
Figure 485. Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC . . . . . . . . . . . . 1691
Figure 486. Bus transfer diagrams for SMBus slave receiver (SBC=1). . . . . . . . . . . . . . . . . . . . . . . 1692
Figure 487. Bus transfer diagrams for SMBus master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 1693
Figure 488. Bus transfer diagrams for SMBus master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1695
Figure 489. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1721
Figure 490. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1724
Figure 491. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1726
Figure 492. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1729
Figure 493. Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1730
Figure 494. usart_ker_ck clock divider block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1733
Figure 495. Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1734

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Figure 496. Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1735

Figure 497. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1742
Figure 498. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1743
Figure 499. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . 1746
Figure 500. Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . 1747
Figure 501. USART example of synchronous master transmission. . . . . . . . . . . . . . . . . . . . . . . . . . 1748
Figure 502. USART data clock timing diagram in synchronous master mode
(M bits =00). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1748
Figure 503. USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1749
Figure 504. USART data clock timing diagram in synchronous slave mode
(M bits =00). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1750
Figure 505. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1752
Figure 506. Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1754
Figure 507. IrDA SIR ENDEC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1758
Figure 508. IrDA data modulation (3/16) - Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1758
Figure 509. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1760
Figure 510. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1761
Figure 511. Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1761
Figure 512. RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1762
Figure 513. RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1763
Figure 514. Wakeup event verified (wakeup event = address match, FIFO disabled) . . . . . . . . . . . 1766
Figure 515. Wakeup event not verified (wakeup event = address match,
FIFO disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1766
Figure 516. LPUART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1809
Figure 517. LPUART word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1811
Figure 518. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1813
Figure 519. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1815
Figure 520. lpuart_ker_ck clock divider block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1818
Figure 521. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1822
Figure 522. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1823
Figure 523. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1825
Figure 524. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1826
Figure 525. Hardware flow control between 2 LPUARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1827
Figure 526. RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1827
Figure 527. RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1828
Figure 528. Wakeup event verified (wakeup event = address match,
FIFO disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1831
Figure 529. Wakeup event not verified (wakeup event = address match,
FIFO disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1831
Figure 530. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1861
Figure 531. Full-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1862
Figure 532. Half-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1862
Figure 533. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1863
Figure 534. Master and three independent slaves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1864
Figure 535. Multi-master application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1865
Figure 536. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1866
Figure 537. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1867
Figure 538. Data alignment when data length is not equal to 8-bit or 16-bit . . . . . . . . . . . . . . . . . . . 1868
Figure 539. Packing data in FIFO for transmission and reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 1872
Figure 540. Master full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1875

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Figure 541. Slave full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1876

Figure 542. Master full-duplex communication with CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1877
Figure 543. Master full-duplex communication in packed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1878
Figure 544. NSSP pulse generation in Motorola SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . 1881
Figure 545. TI mode transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1882
Figure 546. SAI functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1896
Figure 547. Audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1900
Figure 548. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . . . . . . . 1902
Figure 549. FS role is start of frame (FSDEF = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1903
Figure 550. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . . . . . . . . . . . . . . . . . . . . . 1904
Figure 551. First bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1904
Figure 552. Audio block clock generator overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1905
Figure 553. PDM typical connection and timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1909
Figure 554. Detailed PDM interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1910
Figure 555. Start-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1911
Figure 556. SAI_ADR format in TDM, 32-bit slot width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1912
Figure 557. SAI_ADR format in TDM, 16-bit slot width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1913
Figure 558. SAI_ADR format in TDM, 8-bit slot width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1914
Figure 559. AC’97 audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1917
Figure 560. Example of typical AC’97 configuration on devices featuring at least
2 embedded SAIs (three external AC’97 decoders) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1918
Figure 561. SPDIF format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1919
Figure 562. SAI_xDR register ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1920
Figure 563. Data companding hardware in an audio block in the SAI . . . . . . . . . . . . . . . . . . . . . . . . 1924
Figure 564. Tristate strategy on SD output line on an inactive slot . . . . . . . . . . . . . . . . . . . . . . . . . . 1925
Figure 565. Tristate on output data line in a protocol like I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1926
Figure 566. Overrun detection error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1927
Figure 567. FIFO underrun event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1927
Figure 568. SDMMC “no response” and “no data” operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1963
Figure 569. SDMMC (multiple) block read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1963
Figure 570. SDMMC (multiple) block write operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1964
Figure 571. SDMMC (sequential) stream read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1964
Figure 572. SDMMC (sequential) stream write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1964
Figure 573. SDMMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1966
Figure 574. SDMMC Command and data phase relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1967
Figure 575. Control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1969
Figure 576. Command/Response path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1970
Figure 577. Command path state machine (CPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1971
Figure 578. Data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1977
Figure 579. DDR mode data packet clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1978
Figure 580. DDR mode CRC status / boot acknowledgment clocking. . . . . . . . . . . . . . . . . . . . . . . . 1978
Figure 581. Data path state machine (DPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1979
Figure 582. CLKMUX unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1989
Figure 583. Asynchronous interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1994
Figure 584. Synchronous interrupt period data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1994
Figure 585. Synchronous interrupt period data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1995
Figure 586. Asynchronous interrupt period data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1996
Figure 587. Asynchronous interrupt period data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1996
Figure 588. Clock stop with SDMMC_CK for DS, HS, SDR12, SDR25. . . . . . . . . . . . . . . . . . . . . . . 1999
Figure 589. Clock stop with SDMMC_CK for DDR50, SDR50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1999
Figure 590. ReadWait with SDMMC_CK < 50 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000
Figure 591. ReadWait with SDMMC_CK > 50 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2001

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Figure 592. CMD12 stream timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2003

Figure 593. CMD5 Sleep Awake procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2005
Figure 594. Normal boot mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2007
Figure 595. Alternative boot mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2008
Figure 596. Command response R1b busy signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2009
Figure 597. SDMMC state control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2010
Figure 598. Card cycle power / power up diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2011
Figure 599. CMD11 signal voltage switch sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2012
Figure 600. Voltage switch transceiver typical application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2014
Figure 601. CAN network topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2043
Figure 602. Dual-CAN block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2044
Figure 603. bxCAN operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2046
Figure 604. bxCAN in silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2047
Figure 605. bxCAN in loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2047
Figure 606. bxCAN in combined mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2048
Figure 607. Transmit mailbox states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2050
Figure 608. Receive FIFO states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2051
Figure 609. Filter bank scale configuration - register organization . . . . . . . . . . . . . . . . . . . . . . . . . . 2054
Figure 610. Example of filter numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2055
Figure 611. Filtering mechanism - example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2056
Figure 612. CAN error state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2057
Figure 613. Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2059
Figure 614. CAN frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2060
Figure 615. Event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2061
Figure 616. CAN mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2073
Figure 617. OTG_FS full-speed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2091
Figure 618. OTG_FS A-B device connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2093
Figure 619. USB_FS peripheral-only connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2095
Figure 620. USB_FS host-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2099
Figure 621. SOF connectivity (SOF trigger output to TIM and ITR1 connection) . . . . . . . . . . . . . . . 2103
Figure 622. Updating OTG_HFIR dynamically (RLDCTRL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2105
Figure 623. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . 2106
Figure 624. Host-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . . . 2107
Figure 625. Interrupt hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2111
Figure 626. Transmit FIFO write task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2197
Figure 627. Receive FIFO read task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2198
Figure 628. Normal bulk/control OUT/SETUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2199
Figure 629. Bulk/control IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2203
Figure 630. Normal interrupt OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2206
Figure 631. Normal interrupt IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2211
Figure 632. Isochronous OUT transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2213
Figure 633. Isochronous IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2216
Figure 634. Receive FIFO packet read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2220
Figure 635. Processing a SETUP packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2222
Figure 636. Bulk OUT transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2229
Figure 637. TRDT max timing case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2239
Figure 638. A-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2240
Figure 639. B-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2241
Figure 640. A-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2242
Figure 641. B-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2244
Figure 642. Block diagram of STM32 MCU and Cortex®-M4-level debug support . . . . . . . . . . . . . . 2246
Figure 643. SWJ debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2248

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Figure 644. JTAG TAP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2252

Figure 645. TPIU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2271

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1 Documentation conventions

1.1 General information

The STM32L4+ Series devices have an Arm®(a) Cortex®-M4 core.

1.2 List of abbreviations for registers

The following abbreviations(b) are used in register descriptions:

read/write (rw) Software can read and write to this bit.

read-only (r) Software can only read this bit.
write-only (w) Software can only write to this bit. Reading this bit returns the reset value.
read/clear write0 (rc_w0) Software can read as well as clear this bit by writing 0. Writing 1 has no
effect on the bit value.
read/clear write1 (rc_w1) Software can read as well as clear this bit by writing 1. Writing 0 has no
effect on the bit value.
read/clear write (rc_w) Software can read as well as clear this bit by writing to the register. The
value written to this bit is not important.
read/clear by read (rc_r) Software can read this bit. Reading this bit automatically clears it to 0.
Writing this bit has no effect on the bit value.
read/set by read (rs_r) Software can read this bit. Reading this bit automatically sets it to 1.
Writing this bit has no effect on the bit value.
read/set (rs) Software can read as well as set this bit. Writing 0 has no effect on the bit
value.
read/write once (rwo) Software can only write once to this bit and can also read it at any time.
Only a reset can return the bit to its reset value.
toggle (t) The software can toggle this bit by writing 1. Writing 0 has no effect.
read-only write trigger (rt_w1) Software can read this bit. Writing 1 triggers an event but has no effect on
the bit value.
Reserved (Res.) Reserved bit, must be kept at reset value.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
b. This is an exhaustive list of all abbreviations applicable to STM microcontrollers, some of them may not be
used in the current document.

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1.3 Glossary
This section gives a brief definition of acronyms and abbreviations used in this document:
• Word: data of 32-bit length.
• Half-word: data of 16-bit length.
• Byte: data of 8-bit length.
• IAP (in-application programming): IAP is the ability to re-program the Flash memory
of a microcontroller while the user program is running.
• ICP (in-circuit programming): ICP is the ability to program the Flash memory of a
microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the
device is mounted on the user application board.
• Option bytes: product configuration bits stored in the Flash memory.
• OBL: option byte loader.
• AHB: advanced high-performance bus.
• APB: advanced peripheral bus.

1.4 Availability of peripherals

For availability of peripherals and their number across all sales types, refer to the particular
device datasheet.

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2 System and memory overview

2.1 System architecture

The main system consists of 32-bit multilayer AHB bus matrix that interconnects:
• Up to nine masters:
– Cortex®-M4 with FPU core I-bus
– Cortex®-M4 with FPU core D-bus
– Cortex®-M4 with FPU core S-bus
– DMA1
– DMA2
– DMA2D (Chrom-Art Accelerator™) memory bus
– LCD-TFT controller DMA-bus
– SDMMC1 bus
– SDMMC2 bus
(only for STM32L4P5xx and STM32L4Q5xx devices)
– GFXMMU (Chrom-GRC™) bus
(only for STM32L4Sxxx and STM32L4R5xxx devices)
• Up to eleven slaves:
– Internal Flash memory on the I-Code bus
– Internal Flash memory on D-Code bus
– Internal SRAM1
(192 Kbytes for STM32L4Rxxx and STM32Sxxx devices and
128 Kbytes for STM32L4P5xx and STM32Q5xx devices)
– Internal SRAM2 (64 Kbytes)
– Internal SRAM3
(384 Kbytes for STM32L4Rxxx and STM32L4Sxxx devices and
128 Kbytes for STM32L4P5xx and STM32L4Q5xx devices)
– GFXMMU (Chrom-GRC™)
(only for STM32L4Rxxx and STM32L4Sxxx devices)
– AHB1 peripherals including AHB to APB bridges and APB peripherals (connected
to APB1 and APB2)
– AHB2 peripherals
– Flexible memory controller (FMC)
– OCTOSPI1
– OCTOSPI2
The bus matrix provides access from a master to a slave, enabling concurrent access and
efficient operation even when several high-speed peripherals work simultaneously. This
architecture is shown in Figure 1:

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Figure 1. System architecture for STM32L4Rxxx and STM32L4Sxxx

Cortex®-M4
DMA1 DMA2 DMA2D LCD-TFT SDMMC1 GFXMMU
with FPU
D-bus

S-bus
I-bus

ICode

ACCEL
FLASH
DCode 2 MB

SRAM1

SRAM2

SRAM3

GFXMMU

AHB1
peripherals

AHB2
peripherals

FSMC

OCTOSPI1

OCTOSPI2
BusMatrix-S
MSv38490V1

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Figure 2. System architecture for STM32L4P5xx and STM32L4Q5xx

Cortex®-M4
DMA1 DMA2 DMA2D LCD-TFT SDMMC1 SDMMC2
with FPU
D-bus

S-bus
I-bus

ICode

ACCEL
FLASH
DCode 2 MB

SRAM1

SRAM2

SRAM3

AHB1
peripherals

AHB2
peripherals

FSMC

OCTOSPI1

OCTOSPI2

BusMatrix-S
MSv61196V1

2.1.1 I-bus
This bus connects the instruction bus of the Cortex®-M4 core to the BusMatrix. This bus is
used by the core to fetch instructions. The target of this bus is a memory containing code
(either internal Flash memory, internal SRAM or external memories through the FMC or
OCTOSPIs).

2.1.2 D-bus
This bus connects the data bus of the Cortex®-M4 core to the BusMatrix. This bus is used
by the core for literal load and debug access. The target of this bus is a memory containing
code (either internal Flash memory, internal SRAM or external memories through the FMC
or OCTOSPIs).

2.1.3 S-bus
This bus connects the system bus of the Cortex®-M4 core to the BusMatrix. This bus is
used by the core to access data located in a peripheral or SRAM area. The targets of this
bus are the internal SRAM, the AHB1 peripherals including the APB1 and APB2

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peripherals, the AHB2 peripherals and the external memories through the OCTOSPI or the
FMC.
The SRAM2 is also accessible on this bus to allow continuous mapping with SRAM1 and
SRAM3.

2.1.4 DMA-bus
This bus connects the AHB master interface of the DMA to the BusMatrix.The targets of this
bus are the SRAM1,SRAM2 and SRAM3, the AHB1 peripherals including the APB1 and
APB2 peripherals, the AHB2 peripherals and the external memories through the OCTOSPI
or the FMC.

2.1.5 DMA2D-bus
This bus connects the AHB master interface of the DMA2D to the BusMatrix. The targets of
this bus are the SRAM1, SRAM2 and SRAM3 and external memories through the OCTOSPI
or the FMC.

2.1.6 LCD-TFT controller DMA bus

This bus connects the LCD controller DMA master interface to the BusMatrix. The targets of
this bus are data memories: internal SRAMs (SRAM1, SRAM2, SRAM3), internal Flash
memory or external memories through FMC or OCTOSPI.

2.1.7 SDMMC1 controller DMA bus

This bus connects the SDMMC1 DMA master interface to the BusMatrix. This bus is used
only by the SDMMC1 DMA to load/store data from/to memory. The targets of this bus are
data memories: internal SRAMs (SRAM1, SRAM2, SRAM3), internal Flash memory or
external memories through FMC or OCTOSPI.

2.1.8 SDMMC2 controller DMA bus (only for STM32L4P5xx and

STM32L4Q5xx devices)
This bus connects the SDMMC2 DMA master interface to the BusMatrix. This bus is used
only by the SDMMC2 DMA to load/store data from/to memory. The targets of this bus are
data memories: internal SRAMs (SRAM1, SRAM2, SRAM3), internal Flash memory or
external memories through FMC or OCTOSPI.

2.1.9 GFXMMU-bus (only for STM32L4Rxxx and STM32L4Sxxx devices)

This bus connects the GFXMMU (Chrom-GRC™) AHB master interface to the BusMatrix.
The targets of this bus are data memories: internal SRAMs (SRAM1, SRAM2, SRAM3),
internal Flash memory or external memories through FMC or OCTOSPI.

2.1.10 BusMatrix
The BusMatrix manages the access arbitration between masters. The arbitration uses a
Round Robin algorithm.

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For STM32L4Rxxx and STM32L4Sxxx devices, the BusMatrix is composed of

• up to nine masters:
– CPU AHB system bus, D-Code bus, I-Code bus, DMA1, DMA2, DMA2D,
SDMMC1, LCD-TFT and GFXMMU
• up to eleven slaves:
– FLASH, SRAM1, SRAM2, SRAM3, AHB1 (including APB1 and APB2), AHB2,
GFXMMU, OCTOSTPI1, OCTOSPI2 and FMC
For STM32L4P5xx and STM32Q5xx devices, the BusMatrix is composed of:
• nine masters:
– CPU AHB system bus, D-Code bus, I-Code bus, DMA1, DMA2, DMA2D,
SDMMC1, SDMMC2 and LCD-TFT
• ten slaves:
– FLASH, SRAM1, SRAM2, SRAM3, AHB1 (including APB1 and APB2), AHB2,
OCTOSTPI1, OCTOSPI2 and FMC.

AHB/APB bridges
The two AHB/APB bridges provide full synchronous connections between the AHB and the
two APB buses, allowing flexible selection of the peripheral frequency.
Refer to Section 2.2.2: Memory map and register boundary addresses on page 92 for the
address mapping of the peripherals connected to this bridge.
After each device reset, all peripheral clocks are disabled (except for the SRAM1/2 and
Flash memory interface). Before using a peripheral you have to enable its clock in the
RCC_AHBxENR and the RCC_APBxENR registers.
Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into
a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

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2.2 Memory organization

2.2.1 Introduction
Program memory, data memory, registers and I/O ports are organized within the same linear
4-Gbyte address space.
The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word
is considered the word’s least significant byte and the highest numbered byte the most
significant.
The addressable memory space is divided into eight main blocks, of 512 Mbytes each.

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2.2.2 Memory map and register boundary addresses

Figure 3. Memory map for STM32L4Rxxx and STM32L4Sxxx

0xFFFF FFFF 0xBFFF FFFF

Cortex™-M4 Reserved
0xA000 1800
with FPU
7 Internal
OCTOSPI registers
Peripherals 0xA000 1000
FMC registers
0xE000 0000 0xA000 0000

0x5FFF FFFF
Reserved
6 Reserved 0x5006 0C00
AHB2
0x4800 0000
0xC000 0000 Reserved
0x4002 4400
FMC and AHB1
5 OCTOSPI 0x4002 0000
registers Reserved
0x4001 6400
0xA000 0000 APB2
0x4001 0000
OctoSPI bank1 Reserved
0x4000 9800
4 0x9000 0000
APB1
FMC bank3 0x4000 0000

0x8000 0000 0x1FFF FFFF

Reserved
OCTOSPI bank2 0x1FFF F810
Option bytes
3 0x7000 0000 0x1FFF F800
Reserved
FMC bank1
0x1FFF F000
0x6000 0000 System memory
0x1FFF 8000
Reserved
0x1FFF 7810
Options bytes
2 Peripherals 0x1FFF 7800
Reserved
0x1FFF 7400
OTP area
0x4000 0000
GFXMMU 0x1FFF 7000
Virtual buffer System memory
0x3000 0000
0x2FFF FFFF 0x1FFF 0000
Reserved Reserved
1 0x200A 0000
SRAM3
0x2004 0000
SRAM2 0x1001 0000
0x2003 0000 SRAM2
SRAM1 0x1000 0000
0x2000 0000 Reserved
0 0x0820 0000
Flash memory
CODE 0x0800 0000
Reserved
0x0020 0000 Flash, system memory
0x0000 0000
or SRAM, depending on
0x0000 0000 BOOT configuration
Reserved
MSv44746V3

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Figure 4. Memory map for STM32L4P5xx and STM32L4Q5xx

0xFFFF FFFF 0xBFFF FFFF

Cortex™-M4 Reserved
0xA000 1800
with FPU
7 Internal
OCTOSPI registers
Peripherals 0xA000 1000
FMC registers
0xE000 0000 0xA000 0000

0x5FFF FFFF
Reserved
6 Reserved 0x5006 2C00
AHB2
0x4800 0000
0xC000 0000 Reserved
0x4002 BC00
FMC and AHB1
5 OCTOSPI 0x4002 0000
registers Reserved
0x4001 7400
0xA000 0000 APB2
0x4001 0000
OCTOSPI bank1 Reserved
0x4000 9800
4 0x9000 0000
APB1
FMC bank3 0x4000 0000

0x8000 0000 0x1FFF FFFF

Reserved
OCTOSPI bank2 0x1FFF F810
Option bytes
3 0x7000 0000 0x1FFF F800
Reserved
FMC bank1
0x1FFF F000
0x6000 0000 System memory
0x1FFF 8000
Reserved
0x1FFF 7810
Options bytes
2 Peripherals
0x1FFF 7800
Reserved
0x1FFF 7400
OTP area
0x4000 0000
0x1FFF 7000
System memory
Reserved 0x1FFF 0000
Reserved
1 0x2005 0000
SRAM3
0x2003 0000
SRAM2 0x1001 0000
0x2002 0000 SRAM2
SRAM1 0x1000 0000
0x2000 0000 Reserved
0 0x0810 0000
Flash memory
CODE 0x0800 0000
Reserved
0x0010 0000 Flash, system memory
0x0000 0000
or SRAM, depending on
0x0000 0000 BOOT configuration
Reserved
MSv61134V1

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All the memory map areas that are not allocated to on-chip memories and peripherals are
considered “Reserved” (highlighted in gray). For the detailed mapping of available memory
and register areas, refer to the following table.
The following table gives the boundary addresses of the peripherals available in the
devices.
Table 1. STM32L4Rxxx and STM32L4Sxxx memory map and peripheral register boundary
addresses
Size
Bus Boundary address Peripheral Peripheral register map
(bytes)

0xA000 1800 - 0xDFFF FFFF 1 KB Reserved -

OCTOSPI2 Section 19.6.24: OCTOSPI register
0xA000 1400 - 0xA000 17FF 1 KB
registers map
- OCTOSPI1 Section 19.6.24: OCTOSPI register
0xA000 1000 - 0xA000 13FF 1 KB
registers map
0xA000 0400 - 0xA000 0FFF 1 KB Reserved -
0xA000 0000 - 0xA000 03FF 1 KB FSMC registers Section 18.8.8: FMC register map

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Table 1. STM32L4Rxxx and STM32L4Sxxx memory map and peripheral register boundary
addresses (continued)
Size
Bus Boundary address Peripheral Peripheral register map
(bytes)

0x5006 2000 - 0x5FFF FFFF ~260 MB Reserved -

0x5006 2400 - 0x5006 27FF Section 54.9.20: SDMMC register
1 KB SDMMC1
map
0x5006 2000 - 0x5006 23FF 1 KB Reserved -
0x5006 1C00 - 0x5006 1FFF Section 20.5.3: OCTOSPIM register
1 KB OCTOSPIM
map
0x5006 0C00 - 0x5006 1BFF 4 KB Reserved -
0x5006 0800 - 0x5006 0BFF 1 KB RNG Section 32.7.5: RNG register map
0x5006 0400 - 0x5006 07FF 1 KB HASH Section 35.7.8: HASH register map
0x5006 0000 - 0x5006 03FF 1 KB AES Section 34.7.18: AES register map
0x5005 0800 - 0x5005 FFFF 61 KB Reserved -
0x5005 0400 - 0x5005 07FF 1 KB Reserved -
0x5005 0000 - 0x5005 03FF 1 KB DCMI Section 24.5.12: DCMI register map
0x5004 0400 - 0x5004 FFFF 62 KB Reserved -
AHB2
0x5004 0000 - 0x5004 03FF Section 21.8: ADC register map on
1 KB ADC
page 721
0x5000 0000 - 0x5003 FFFF Section 56.15.57: OTG_FS register
16 KB OTG_FS
map
0x4800 2400 - 0x4FFF FFFF ~127 MB Reserved -
0x4800 2000 - 0x4800 23FF 1 KB GPIOI Section 8.4.12: GPIO register map
0x4800 1C00 - 0x4800 1FFF 1 KB GPIOH Section 8.4.12: GPIO register map
0x4800 1800 - 0x4800 1BFF 1 KB GPIOG Section 8.4.12: GPIO register map
0x4800 1400 - 0x4800 17FF 1 KB GPIOF Section 8.4.12: GPIO register map
0x4800 1000 - 0x4800 13FF 1 KB GPIOE Section 8.4.12: GPIO register map
0x4800 0C00 - 0x4800 0FFF 1 KB GPIOD Section 8.4.12: GPIO register map
0x4800 0800 - 0x4800 0BFF 1 KB GPIOC Section 8.4.12: GPIO register map
0x4800 0400 - 0x4800 07FF 1 KB GPIOB Section 8.4.12: GPIO register map
0x4800 0000 - 0x4800 03FF 1 KB GPIOA Section 8.4.12: GPIO register map

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Table 1. STM32L4Rxxx and STM32L4Sxxx memory map and peripheral register boundary
addresses (continued)
Size
Bus Boundary address Peripheral Peripheral register map
(bytes)

0x4002 F000 - 0x47FF FFFF ~127 MB Reserved -

0x4002 C000 - 0x4002 EFFF 1KB GFXMMU Section 14.5.11: Graphic MMU
register map
0x4002 BC00 - 0x4002 BBFF 1 KB Reserved -
0x4002 B000 - 0x4002 BBFF Section 13.5.23: DMA2D register
3 KB DMA2D
map
0x4002 4400 - 0x4002 AFFF 26 KB Reserved -
0x4002 4000 - 0x4002 43FF 1 KB TSC Section 31.6.11: TSC register map
0x4002 3400 - 0x4002 3FFF 1 KB Reserved -
0x4002 3000 - 0x4002 33FF 1 KB CRC Section 17.4.6: CRC register map
AHB1 0x4002 2400 - 0x4002 2FFF 3 KB Reserved -
0x4002 2000 - 0x4002 23FF FLASH
1 KB Section 3.7.18: FLASH register map
registers
0x4002 1400 - 0x4002 1FFF 3 KB Reserved -
0x4002 1000 - 0x4002 13FF 1 KB RCC Section 6.4.34: RCC register map
0x4002 0800 - 0x4002 0FFF 2 KB Reserved -
0x4002 0400 - 0x4002 07FF 1 KB DMA2 Section 11.6.7: DMA register map
0x4002 0800 - 0x4002 0BFF Section 12.6.7: DMAMUX register
1 KB DMAMUX1
map
0x4002 0C00 - 0x4002 0FFF 1 KB Reserved -
0x4002 0000 - 0x4002 03FF 1 KB DMA1 Section 11.6.7: DMA register map

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Table 1. STM32L4Rxxx and STM32L4Sxxx memory map and peripheral register boundary
addresses (continued)
Size
Bus Boundary address Peripheral Peripheral register map
(bytes)

0x4001 7400 - 0x4001 FFFF 33 KB Reserved -

0x4001 6C00 - 0x4001 73FF 1 KB DSIHOST Section 30.17: DSI Host register map
0x4001 6800 - 0x4001 6BFF 1 KB LCD-TFT Section 29.8.26: LTDC register map
0x4001 6000 - 0x4001 67FF Section 28.8.16: DFSDM register
2 KB DFSDM1
map
0x4001 5C00 - 0x4001 5FFF 1 KB Reserved -
0x4001 5800 - 0x4001 5BFF 1 KB SAI2 Section 53.6.20: SAI register map
0x4001 5400 - 0x4001 57FF 1 KB SAI1 Section 53.6.20: SAI register map
0x4001 4C00 - 0x4001 53FF 2 KB Reserved -
0x4001 4800 - 0x4001 4BFF Section 39.6.21: TIM16/TIM17
1 KB TIM17
register map
0x4001 4400 - 0x4001 47FF Section 39.6.21: TIM16/TIM17
1 KB TIM16
register map
0x4001 4000 - 0x4001 43FF 1 KB TIM15 Section 39.5.21: TIM15 register map
APB2
0x4001 3C00 - 0x4001 3FFF 1 KB Reserved -
0x4001 3800 - 0x4001 3BFF 1 KB USART1 Section 50.7.15: USART register map
0x4001 3400 - 0x4001 37FF 1 KB TIM8 Section 37.4.33: TIM8 register map
0x4001 3000 - 0x4001 33FF 1 KB SPI1 Section 52.6.8: SPI register map
0x4001 2C00 - 0x4001 2FFF 1 KB TIM1 Section 37.4.32: TIM1 register map
0x4001 2000 - 0x4001 2BFF 3 KB Reserved -
0x4001 1C00 - 0x4001 1FFF 1 KB FIREWALL Section 4.4.8: Firewall register map
0x4001 0800- 0x4001 1BFF 5 KB Reserved -
0x4001 0400 - 0x4001 07FF 1 KB EXTI Section 16.5.13: EXTI register map
0x4001 0200 - 0x4001 03FF 1 KB COMP Section 26.6.3: COMP register map
0x4001 0030 - 0x4001 01FF Section 23.3.3: VREFBUF register
1 KB VREFBUF
map
0x4001 0000 - 0x4001 002F Section 9.2.12: SYSCFG register
1 KB SYSCFG
map

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Table 1. STM32L4Rxxx and STM32L4Sxxx memory map and peripheral register boundary
addresses (continued)
Size
Bus Boundary address Peripheral Peripheral register map
(bytes)

0x4000 9800 - 0x4000 FFFF 26 KB Reserved -

0x4000 9400 - 0x4000 97FF 1 KB LPTIM2 Section 41.7.11: LPTIM register map
0x4000 8C00 - 0x4000 93FF 3 KB Reserved -
0x4000 8400 - 0x4000 87FF 1 KB I2C4 Section 49.7.12: I2C register map
Section 51.6.13: LPUART register
0x4000 8000 - 0x4000 83FF 1 KB LPUART1
map
0x4000 7C00 - 0x4000 7FFF 1 KB LPTIM1 Section 41.7.11: LPTIM register map
0x4000 7800 - 0x4000 7BFF 1 KB OPAMP Section 27.5.7: OPAMP register map
0x4000 7400 - 0x4000 77FF 1 KB DAC1 Section 22.7.21: DAC register map
APB1 Section 5.4.27: PWR register map
0x4000 7000 - 0x4000 73FF 1 KB PWR
and reset value table
0x4000 6800 - 0x4000 6FFF 2 KB Reserved -
0x4000 6400 - 0x4000 67FF 1 KB CAN1 Section 55.9.5: bxCAN register map
0x4000 6000 - 0x4000 63FF 1 KB CRS Section 7.7.5: CRS register map
0x4000 5C00- 0x4000 5FFF 1 KB I2C3 Section 49.7.12: I2C register map
0x4000 5800 - 0x4000 5BFF 1 KB I2C2 Section 49.7.12: I2C register map
0x4000 5400 - 0x4000 57FF 1 KB I2C1 Section 49.7.12: I2C register map
0x4000 5000 - 0x4000 53FF 1 KB UART5 Section 50.7.15: USART register map
0x4000 4C00 - 0x4000 4FFF 1 KB UART4 Section 50.7.15: USART register map

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Table 1. STM32L4Rxxx and STM32L4Sxxx memory map and peripheral register boundary
addresses (continued)
Size
Bus Boundary address Peripheral Peripheral register map
(bytes)

0x4000 4800 - 0x4000 4BFF 1 KB USART3 Section 50.7.15: USART register map
0x4000 4400 - 0x4000 47FF 1 KB USART2 Section 50.7.15: USART register map
0x4000 4000 - 0x4000 43FF 1 KB Reserved -
0x4000 3C00 - 0x4000 3FFF 1 KB SPI3 Section 52.6.8: SPI register map
0x4000 3800 - 0x4000 3BFF 1 KB SPI2 Section 52.6.8: SPI register map
0x4000 3400 - 0x4000 37FF 1 KB Reserved -
0x4000 3000 - 0x4000 33FF 1 KB IWDG Section 44.4.6: IWDG register map
0x4000 2C00 - 0x4000 2FFF 1 KB WWDG Section 45.5.4: WWDG register map
APB1
0x4000 2800 - 0x4000 2BFF 1 KB RTC Section 46.6.21: RTC register map
0x4000 1800 - 0x4000 23FF 4 KB Reserved -
0x4000 1400 - 0x4000 17FF 1 KB TIM7 Section 40.4.9: TIMx register map
0x4000 1000 - 0x4000 13FF 1 KB TIM6 Section 40.4.9: TIMx register map
0x4000 0C00- 0x4000 0FFF 1 KB TIM5 Section 38.4.26: TIMx register map
0x4000 0800 - 0x4000 0BFF 1 KB TIM4 Section 38.4.26: TIMx register map
0x4000 0400 - 0x4000 07FF 1 KB TIM3 Section 38.4.26: TIMx register map
0x4000 0000 - 0x4000 03FF 1 KB TIM2 Section 38.4.26: TIMx register map

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Table 2. STM32L4P5xx and STM32L4Q5xx memory map and peripheral register boundary
addresses
Size
Bus Boundary address Peripheral Peripheral register map
(bytes)

0xA000 1800 - 0xDFFF FFFF 1 KB Reserved -

OCTOSPI2 Section 19.6.24: OCTOSPI register
0xA000 1400 - 0xA000 17FF 1 KB
registers map
- OCTOSPI1 Section 19.6.24: OCTOSPI register
0xA000 1000 - 0xA000 13FF 1 KB
registers map
0xA000 0400 - 0xA000 0FFF 1 KB Reserved -
0xA000 0000 - 0xA000 03FF 1 KB FSMC registers Section 18.8.8: FMC register map

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Table 2. STM32L4P5xx and STM32L4Q5xx memory map and peripheral register boundary
addresses (continued)
Size
Bus Boundary address Peripheral Peripheral register map
(bytes)

0x5006 2C00 - 0x5FFF FFFF ~260 MB Reserved -

0x5006 2400 - 0x5006 27FF Section 54.9.20: SDMMC register
1 KB SDMMC1
map
0x5006 2800 - 0x5006 2BFF Section 54.9.20: SDMMC register
1 KB SDMMC2
map
0x5006 2000 - 0x5006 23FF 1 KB Reserved -
0x5006 1C00 - 0x5006 1FFF Section 20.5.3: OCTOSPIM register
1 KB OCTOSPIM
map
0x5006 0C00 - 0x5006 1BFF 4 KB Reserved -
0x5006 0800 - 0x5006 0BFF 1 KB RNG Section 32.7.5: RNG register map
0x5006 0400 - 0x5006 07FF 1 KB HASH Section 35.7.8: HASH register map
0x5006 0000 - 0x5006 03FF 1 KB AES Section 34.7.18: AES register map
0x5005 E000 - 0x5005 FFFF Section 36.7.5: PKA register map
8 KB PKA + RAM
and reset values
0x5005 0800 - 0x5005 DFFF 54 KB Reserved -
0x5005 0400 - 0x5005 07FF 1 KB PSSI Section 25.5.8: PSSI register map
AHB2 0x5005 0000 - 0x5005 03FF 1 KB DCMI Section 24.5.12: DCMI register map
0x5004 0400 - 0x5004 FFFF 62 KB Reserved -
0x5004 0000 - 0x5004 03FF Section 21.8: ADC register map on
1 KB ADC1 + ADC2
page 721
0x5000 0000 - 0x5003 FFFF Section 56.15.57: OTG_FS register
16 KB OTG_FS
map
0x4800 2400 - 0x4FFF FFFF ~127 MB Reserved -
0x4800 2000 - 0x4800 23FF 1 KB GPIOI Section 8.4.12: GPIO register map
0x4800 1C00 - 0x4800 1FFF 1 KB GPIOH Section 8.4.12: GPIO register map
0x4800 1800 - 0x4800 1BFF 1 KB GPIOG Section 8.4.12: GPIO register map
0x4800 1400 - 0x4800 17FF 1 KB GPIOF Section 8.4.12: GPIO register map
0x4800 1000 - 0x4800 13FF 1 KB GPIOE Section 8.4.12: GPIO register map
0x4800 0C00 - 0x4800 0FFF 1 KB GPIOD Section 8.4.12: GPIO register map
0x4800 0800 - 0x4800 0BFF 1 KB GPIOC Section 8.4.12: GPIO register map
0x4800 0400 - 0x4800 07FF 1 KB GPIOB Section 8.4.12: GPIO register map
0x4800 0000 - 0x4800 03FF 1 KB GPIOA Section 8.4.12: GPIO register map

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Table 2. STM32L4P5xx and STM32L4Q5xx memory map and peripheral register boundary
addresses (continued)
Size
Bus Boundary address Peripheral Peripheral register map
(bytes)

0x4002 BC00 - 0x47FF FFFF ~127 MB Reserved -

0x4002 B000 - 0x4002 BBFF Section 13.5.23: DMA2D register
3 KB DMA2D
map
0x4002 4400 - 0x4002 AFFF 26 KB Reserved -
0x4002 4000 - 0x4002 43FF 1 KB TSC Section 31.6.11: TSC register map
0x4002 3400 - 0x4002 3FFF 1 KB Reserved -
0x4002 3000 - 0x4002 33FF 1 KB CRC Section 17.4.6: CRC register map
0x4002 2400 - 0x4002 2FFF 3 KB Reserved -
0x4002 2000 - 0x4002 23FF FLASH
AHB1 1 KB Section 3.7.18: FLASH register map
registers
0x4002 1400 - 0x4002 1FFF 3 KB Reserved -
0x4002 1000 - 0x4002 13FF 1 KB RCC Section 6.4.34: RCC register map
0x4002 0800 - 0x4002 0FFF 2 KB Reserved -
0x4002 0400 - 0x4002 07FF 1 KB DMA2 Section 11.6.7: DMA register map
0x4002 0000 - 0x4002 03FF 1 KB DMA1 Section 11.6.7: DMA register map
0x4002 0800 - 0x4002 0BFF Section 12.6.7: DMAMUX register
1 KB DMAMUX1
map
0x4002 0C00 - 0x4002 0FFF 1 KB Reserved -

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Table 2. STM32L4P5xx and STM32L4Q5xx memory map and peripheral register boundary
addresses (continued)
Size
Bus Boundary address Peripheral Peripheral register map
(bytes)

0x4001 7400 - 0x4001 FFFF 33 KB Reserved -

0x4001 6C00 - 0x4001 73FF 1 KB Reserved -
0x4001 6800 - 0x4001 6BFF 1 KB LCD-TFT Section 29.8.26: LTDC register map
0x4001 6000 - 0x4001 67FF Section 28.8.16: DFSDM register
2 KB DFSDM1
map
0x4001 5C00 - 0x4001 5FFF 1 KB Reserved -
0x4001 5800 - 0x4001 5BFF 1 KB SAI2 Section 53.6.20: SAI register map
0x4001 5400 - 0x4001 57FF 1 KB SAI1 Section 53.6.20: SAI register map
0x4001 4C00 - 0x4001 53FF 2 KB Reserved -
0x4001 4800 - 0x4001 4BFF Section 39.6.21: TIM16/TIM17
1 KB TIM17
register map
0x4001 4400 - 0x4001 47FF Section 39.6.21: TIM16/TIM17
1 KB TIM16
register map
0x4001 4000 - 0x4001 43FF 1 KB TIM15 Section 39.5.21: TIM15 register map
APB2 0x4001 3C00 - 0x4001 3FFF 1 KB Reserved -
0x4001 3800 - 0x4001 3BFF Section 50.7.15: USART register
1 KB USART1
map
0x4001 3400 - 0x4001 37FF 1 KB TIM8 Section 37.4.33: TIM8 register map
0x4001 3000 - 0x4001 33FF 1 KB SPI1 Section 52.6.8: SPI register map
0x4001 2C00 - 0x4001 2FFF 1 KB TIM1 Section 37.4.32: TIM1 register map
0x4001 2000 - 0x4001 2BFF 3 KB Reserved -
0x4001 1C00 - 0x4001 1FFF 1 KB FIREWALL Section 4.4.8: Firewall register map
0x4001 0800- 0x4001 1BFF 5 KB Reserved -
0x4001 0400 - 0x4001 07FF 1 KB EXTI Section 16.5.13: EXTI register map
0x4001 0200 - 0x4001 03FF 1 KB COMP Section 26.6.3: COMP register map
0x4001 0030 - 0x4001 01FF Section 23.3.3: VREFBUF register
1 KB VREFBUF
map
0x4001 0000 - 0x4001 002F Section 9.2.12: SYSCFG register
1 KB SYSCFG
map

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Table 2. STM32L4P5xx and STM32L4Q5xx memory map and peripheral register boundary
addresses (continued)
Size
Bus Boundary address Peripheral Peripheral register map
(bytes)

0x4000 9800 - 0x4000 FFFF 26 KB Reserved -

0x4000 9400 - 0x4000 97FF 1 KB LPTIM2 Section 41.7.11: LPTIM register map
0x4000 8C00 - 0x4000 93FF 3 KB Reserved -
0x4000 8400 - 0x4000 87FF 1 KB I2C4 Section 49.7.12: I2C register map
Section 51.6.13: LPUART register
0x4000 8000 - 0x4000 83FF 1 KB LPUART1
map
0x4000 7C00 - 0x4000 7FFF 1 KB LPTIM1 Section 41.7.11: LPTIM register map
0x4000 7800 - 0x4000 7BFF 1 KB OPAMP Section 27.5.7: OPAMP register map
0x4000 7400 - 0x4000 77FF 1 KB DAC1 Section 22.7.21: DAC register map
Section 5.4.27: PWR register map
0x4000 7000 - 0x4000 73FF 1 KB PWR
APB1 and reset value table
0x4000 6800 - 0x4000 6FFF 2 KB Reserved -
0x4000 6400 - 0x4000 67FF 1 KB CAN1 Section 55.9.5: bxCAN register map
0x4000 6000 - 0x4000 63FF 1 KB CRS Section 7.7.5: CRS register map
0x4000 5C00- 0x4000 5FFF 1 KB I2C3 Section 49.7.12: I2C register map
0x4000 5800 - 0x4000 5BFF 1 KB I2C2 Section 49.7.12: I2C register map
0x4000 5400 - 0x4000 57FF 1 KB I2C1 Section 49.7.12: I2C register map
Section 50.7.15: USART register
0x4000 5000 - 0x4000 53FF 1 KB UART5
map
Section 50.7.15: USART register
0x4000 4C00 - 0x4000 4FFF 1 KB UART4
map

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Table 2. STM32L4P5xx and STM32L4Q5xx memory map and peripheral register boundary
addresses (continued)
Size
Bus Boundary address Peripheral Peripheral register map
(bytes)

Section 50.7.15: USART register

0x4000 4800 - 0x4000 4BFF 1 KB USART3
map
Section 50.7.15: USART register
0x4000 4400 - 0x4000 47FF 1 KB USART2
map
0x4000 4000 - 0x4000 43FF 1 KB Reserved -
0x4000 3C00 - 0x4000 3FFF 1 KB SPI3 Section 52.6.8: SPI register map
0x4000 3800 - 0x4000 3BFF 1 KB SPI2 Section 52.6.8: SPI register map
TAMPER and
0x4000 3400 - 0x4000 37FF 1 KB Section 48.6.9: TAMP register map
BKP registers
0x4000 3000 - 0x4000 33FF 1 KB IWDG Section 44.4.6: IWDG register map
APB1
0x4000 2C00 - 0x4000 2FFF 1 KB WWDG Section 45.5.4: WWDG register map
0x4000 2800 - 0x4000 2BFF 1 KB RTC Section 47.6.23: RTC register map
0x4000 1800 - 0x4000 23FF 4 KB Reserved -
0x4000 1400 - 0x4000 17FF 1 KB TIM7 Section 40.4.9: TIMx register map
0x4000 1000 - 0x4000 13FF 1 KB TIM6 Section 40.4.9: TIMx register map
0x4000 0C00- 0x4000 0FFF 1 KB TIM5 Section 38.4.26: TIMx register map
0x4000 0800 - 0x4000 0BFF 1 KB TIM4 Section 38.4.26: TIMx register map
0x4000 0400 - 0x4000 07FF 1 KB TIM3 Section 38.4.26: TIMx register map
0x4000 0000 - 0x4000 03FF 1 KB TIM2 Section 38.4.26: TIMx register map

2.3 Bit banding

The Cortex®-M4 with FPU memory map includes two bit-band regions. These regions map
each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a
word in the alias region has the same effect as a read-modify-write operation on the
targeted bit in the bit-band region.
In the STM32L4+ Series devices both the peripheral registers and the SRAM1 are mapped
to a bit-band region, so that single bit-band write and read operations are allowed. The
operations are only available for Cortex®-M4 with FPU accesses, and not from other bus
masters (such as DMA).

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A mapping formula shows how to reference each word in the alias region to a corresponding
bit in the bit-band region. The mapping formula is:
bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4)
where:
– bit_word_addr is the address of the word in the alias memory region that maps to
the targeted bit
– bit_band_base is the starting address of the alias region
– byte_offset is the number of the byte in the bit-band region that contains the
targeted bit
– bit_number is the bit position (0-7) of the targeted bit

Example
The following example shows how to map bit 2 of the byte located at SRAM1 address
0x20000300 to the alias region:
0x22006008 = 0x22000000 + (0x300*32) + (2*4)
Writing to address 0x22006008 has the same effect as a read-modify-write operation on bit
2 of the byte at SRAM1 address 0x20000300.
Reading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM1
address 0x20000300 (0x01: bit set; 0x00: bit reset).
For more information on bit-banding, refer to the Cortex®-M4 programming manual (see
Related documents on page 1).

2.4 Embedded SRAM

The STM32L4Rxxx and STM32L4Sxxx devices feature up to 640 Kbytes SRAM:
• 192 Kbytes SRAM1
• 64 Kbytes SRAM2
• 384 Kbytes SRAM3
The STM32L4P5xx and STM32L4Q5xx devices feature up to 320 Kbytes SRAM:
• 128 Kbytes SRAM1
• 64 Kbytes SRAM2
• 128 Kbytes SRAM3
These SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits). These
memories can be addressed at maximum system clock frequency without wait state and
thus by both CPU and DMA.
The CPU can access the SRAM1 through the system bus or through the ICode/DCode
buses when boot from SRAM1 is selected or when physical remap is selected
(Section 9.2.1: SYSCFG memory remap register (SYSCFG_MEMRMP) in the SYSCFG
controller). To get the maximum performance on SRAM1 execution, physical remap should
be selected (boot or software selection).
Execution can be performed from SRAM2 with maximum performance without any remap
thanks to access through ICode bus.
The SRAM2 is aliased at address 0x2003 0000 for STM32L4Rxxx and STM32L4Sxxx
devices and at address 0x2002 0000 for STM32L4P5xx and STM32L4Q5xx devices,

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offering a continuous address space with the SRAM1 and SRAM3.

2.4.1 SRAM2 parity check

The user can enable the SRAM2 parity check using the option bit SRAM2_PE in the user
option byte (refer to Section 3.4.1: Option bytes description).
The data bus width is 36 bits because 4 bits are available for parity check (1 bit per byte) in
order to increase memory robustness, as required for instance by Class B or SIL norms.
The parity bits are computed and stored when writing into the SRAM2. Then, they are
automatically checked when reading. If one bit fails, an NMI is generated. The same error
can also be linked to the BRK_IN Break input of TIM1/TIM8/TIM15/TIM16/TIM17, with the
SPL control bit in the SYSCFG configuration register 2 (SYSCFG_CFGR2). The SRAM2
Parity Error flag (SPF) is available in the SYSCFG configuration register 2
(SYSCFG_CFGR2).
Note: When enabling the RAM parity check, it is advised to initialize by software the whole RAM
memory at the beginning of the code, to avoid getting parity errors when reading non-
initialized locations.

2.4.2 SRAM2 Write protection

The SRAM2 can be write protected with a page granularity of 1 Kbyte.

Table 3. SRAM2 organization

Page number Start address End address

Page 0 0x1000 0000 0x1000 03FF

Page 1 0x1000 0400 0x1000 07FF
Page 2 0x1000 0800 0x1000 0BFF
Page 3 0x1000 0C00 0x1000 0FFF
Page 4 0x1000 1000 0x1000 13FF
Page 5 0x1000 1400 0x1000 17FF
Page 6 0x1000 1800 0x1000 1BFF
Page 7 0x1000 1C00 0x1000 1FFF
Page 8 0x1000 2000 0x1000 23FF
Page 9 0x1000 2400 0x1000 27FF
Page 10 0x1000 2800 0x1000 2BFF
Page 11 0x1000 2C00 0x1000 2FFF
Page 12 0x1000 3000 0x1000 33FF
Page 13 0x1000 3400 0x1000 37FF
Page 14 0x1000 3800 0x1000 3BFF
Page 15 0x1000 3C00 0x1000 3FFF
Page 16 0x1000 4000 0x1000 43FF
Page 17 0x1000 4400 0x1000 47FF

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Table 3. SRAM2 organization (continued)

Page number Start address End address

Page 18 0x1000 4800 0x1000 4BFF

Page 19 0x1000 4C00 0x1000 4FFF
Page 20 0x1000 5000 0x1000 53FF
Page 21 0x1000 5400 0x1000 57FF
Page 22 0x1000 5800 0x1000 5BFF
Page 23 0x1000 5C00 0x1000 5FFF
Page 24 0x1000 6000 0x1000 63FF
Page 25 0x1000 6400 0x1000 67FF
Page 26 0x1000 6800 0x1000 6BFF
Page 27 0x1000 6C00 0x1000 6FFF
Page 28 0x1000 7000 0x1000 73FF
Page 29 0x1000 7400 0x1000 77FF
Page 30 0x1000 7800 0x1000 7BFF
Page 31 0x1000 7C00 0x1000 7FFF
Page 32 0x1000 8000 0x1000 83FF
Page 33 0x1000 8400 0x1000 87FF
Page 34 0x1000 8800 0x1000 8BFF
Page 35 0x1000 8C00 0x1000 8FFF
Page 36 0x1000 9000 0x1000 93FF
Page 37 0x1000 9400 0x1000 97FF
Page 38 0x1000 9800 0x1000 9BFF
Page 39 0x1000 9C00 0x1000 9FFF
Page 40 0x1000 A000 0x1000 A3FF
Page 41 0x1000 A400 0x1000 A7FF
Page 42 0x1000 A800 0x1000 ABFF
Page 43 0x1000 AC00 0x1000 AFFF
Page 44 0x1000 B000 0x1000 B3FF
Page 45 0x1000 B400 0x1000 B7FF
Page 46 0x1000 B800 0x1000 BBFF
Page 47 0x1000 BC00 0x1000 BFFF
Page 48 0x1000 C000 0x1000 C3FF
Page 49 0x1000 C400 0x1000 C7FF
Page 50 0x1000 C800 0x1000 CBFF
Page 51 0x1000 CC00 0x1000 CFFF
Page 52 0x1000 D000 0x1000 D3FF

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Table 3. SRAM2 organization (continued)

Page number Start address End address

Page 53 0x1000 D400 0x1000 D7FF

Page 54 0x1000 D800 0x1000 DBFF
Page 55 0x1000 DC00 0x1000 DFFF
Page 56 0x1000 E000 0x1000 E3FF
Page 57 0x1000 E400 0x1000 E7FF
Page 58 0x1000 E800 0x1000 EBFF
Page 59 0x1000 EC00 0x1000 EFFF
Page 60 0x1000 F000 0x1000 F3FF
Page 61 0x1000 F400 0x1000 F7FF
Page 62 0x1000 F800 0x1000 FBFF
Page 63 0x1000 FC00 0x1000 FFFF

The write protection can be enabled in SYSCFG SRAM2 write protection register
(SYSCFG_SWPR) in the SYSCFG block. This is a register with write ‘1’ once mechanism,
which means by writing ‘1’ on a bit it will setup the write protection for that page of SRAM
and it can be removed/cleared by a system reset only.

2.4.3 SRAM2 Read protection

The SRAM2 is protected with the Read protection (RDP). Refer to Section 3.5.1: Read
protection (RDP) for more details.

2.4.4 SRAM2 Erase

The SRAM2 can be erased with a system reset using the option bit SRAM2_RST in the user
option byte (refer to Section 3.4.1: Option bytes description).
The SRAM2 erase can also be requested by software by setting the bit SRAM2ER in the
SYSCFG SRAM2 control and status register (SYSCFG_SCSR).

2.5 Flash memory overview

The Flash memory is composed of two distinct physical areas:
• The main Flash memory block. It contains the application program and user data if
necessary.
• The information block. It is composed of three parts:
– Option bytes for hardware and memory protection user configuration.
– System memory that contains the ST proprietary code.
– OTP (one-time programmable) area
The Flash interface implements instruction access and data access based on the AHB
protocol. It also implements the logic necessary to carry out the Flash memory operations

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(program/erase) controlled through the Flash registers Refer to Section 3: Embedded Flash
memory (FLASH) for more details.

2.6 Boot configuration

2.6.1 Boot configuration

Three different boot modes can be selected through the BOOT0 pin or the nBOOT0 bit into
the FLASH_OPTR register (if the nSWBOOT0 bit is cleared into the FLASH_OPTR
register), and nBOOT1 bit in FLASH_OPTR register, as shown in the following table.

Table 4. Boot modes

nBOOT1 nBOOT0 BOOT0 nSWBOOT0 Main Flash Boot Memory Space
FLASH_OPTR[23] FLASH_OPTR[27] pin PH3 FLASH_OPTR[26] empty(1) Alias

Main Flash memory is

X X 0 1 0
selected as boot area
System memory is
X X 0 1 1
selected as boot area
Main Flash memory is
X 1 X 0 X
selected as boot area
Embedded SRAM1 is
0 X 1 1 X
selected as boot area
Embedded SRAM1 is
0 0 X 0 X
selected as boot area
System memory is
1 X 1 1 X
selected as boot area
System memory is
1 0 X 0 X
selected as boot area
1. A Flash empty check mechanism is implemented to force the boot from system Flash if the first Flash memory location is
not programmed (0xFFFF FFFF) and if the boot selection was configured to boot from the main Flash.

The values on both BOOT0 pin (coming from the pin or the option bit) and nBOOT1 bit are
latched upon reset release. It is up to the user to set nBOOT1 and BOOT0 to select the
required boot mode.
The BOOT0 pin or user option bit (depending on the nSWBOOT0 bit value in the
FLASH_OPTR register), and nBOOT1 bit are also re-sampled when exiting from Standby
mode. Consequently, they must be kept in the required Boot mode configuration in Standby
mode. After this startup delay has elapsed, the CPU fetches the top-of-stack value from
address 0x0000 0000, then starts code execution from the boot memory at 0x0000 0004.
Depending on the selected boot mode, main Flash memory, system memory or SRAM1 is
accessible as follows:
• Boot from main Flash memory: the main Flash memory is aliased in the boot memory
space (0x0000 0000), but still accessible from its original memory space

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(0x0800 0000). In other words, the Flash memory contents can be accessed starting
from address 0x0000 0000 or 0x0800 0000.
• Boot from system memory: the system memory is aliased in the boot memory space
(0x0000 0000), but still accessible from its original memory space (0x1FFF 0000).
• Boot from the embedded SRAM1: the SRAM1 is aliased in the boot memory space
(0x0000 0000), but it is still accessible from its original memory space (0x2000 0000).
PH3/BOOT0 GPIO is configured in:
• Input mode during the complete reset phase if the option bit nSWBOOT0 is set into the
FLASH_OPTR register and then switches automatically in analog mode after reset is
released (BOOT0 pin).
• Input mode from the reset phase to the completion of the option byte loading if the bit
nSWBOOT0 is cleared into the FLASH_OPTR register (BOOT0 value coming from the
option bit). It switches then automatically to the analog mode even if the reset phase is
not complete.
Note: When the device boots from SRAM, in the application initialization code, you have to
relocate the vector table in SRAM using the NVIC exception table and the offset register.
When booting from the main Flash memory, the application software can either boot from
bank 1 or from bank 2. By default, boot from bank 1 is selected.
To select boot from Flash memory bank 2, set the BFB2 bit in the user option bytes. When
this bit is set and the boot pins are in the boot from main Flash memory configuration, the
device boots from system memory, and the boot loader jumps to execute the user
application programmed in Flash memory bank 2. For further details, please refer to
AN2606.

Physical remap
Once the boot pins mode is selected, the application software can modify the memory
accessible in the code area (in this way the code can be executed through the ICode bus in
place of the System bus). This modification is performed by programming the SYSCFG
memory remap register (SYSCFG_MEMRMP) in the SYSCFG controller.
The following memories can thus be remapped:
• Main Flash memory
• System memory
• Embedded SRAM1 (192 Kbytes for STM32L4Rxxx and STM32L4Sxxx devices and
128 Kbytes for STM32L4P5xx and STM32L4Q5xx devices)
• FSMC bank 1 (NOR/PSRAM 1 and 2)
• OctoSPI (OCTOSPI1 or OSCTOSPI2) memory

Table 5. Memory mapping versus boot mode/physical remap(1)

Boot/remap in Boot/remap in Boot/remap in
Remap in Remap in
Addresses main Flash embedded system
FSMC OCTOSPI
memory SRAM 1 memory

0x2000 0000 - 0x2002 FFFF SRAM1 SRAM1 SRAM1 SRAM1 SRAM1

System System System System System
0x1FFF 7000 - 0x1FFF FFFF memory/OTP/ memory/OTP/ memory/OTP/ memory/OTP/ memory/OTP/
Options bytes Options bytes Options bytes Options bytes Options bytes

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Table 5. Memory mapping versus boot mode/physical remap(1) (continued)

Boot/remap in Boot/remap in Boot/remap in
Remap in Remap in
Addresses main Flash embedded system
FSMC OCTOSPI
memory SRAM 1 memory

0x1000 8000 - 0x1FFE FFFF Reserved Reserved Reserved Reserved Reserved

0x1000 0000 - 0x1000 FFFF SRAM2 SRAM2 SRAM2 SRAM2 SRAM2
0x0820 0000 - 0x0FFF FFFF Reserved Reserved Reserved Reserved Reserved
0x0800 0000 - 0x081F FFFF Flash memory Flash memory Flash memory Flash memory Flash memory
FSMC bank 1
OCTOSPI
NOR/
bank
0x0400 0000 - 0x07FF FFFF Reserved Reserved Reserved PSRAM 2
(128 Mbytes)
(128 Mbytes)
Aliased
Aliased
FSMC bank 1
OCTOSPI
NOR/
bank
0x0010 0000 - 0x03FF FFFF Reserved Reserved Reserved PSRAM 1
(128 Mbytes)
(128 Mbytes)
Aliased
Aliased
FSMC bank 1
System OCTOSPI
Flash SRAM1 NOR/
0x0000 0000 - 0x001F FFFF memory bank
(2) (3) (2 Mbytes)(4) (192 Kbytes) (5)
PSRAM 1
(28 Kbytes) (128 Mbytes)
Aliased Aliased (128 Mbytes)
Aliased Aliased)
Aliased)
1. Reserved areas highlighted in gray.
2. When the FSMC is remapped at address 0x0000 0000, only the first two regions of bank 1 memory controller (bank 1
NOR/PSRAM 1 and NOR/PSRAM 2) can be remapped. When the OCTOSPI is remapped at address 0x0000 0000, only
128 Mbytes are remapped. In remap mode, the CPU can access the external memory via ICode bus instead of system bus,
which boosts up the performance.
3. Even when aliased in the boot memory space, the related memory is still accessible at its original memory space.
4. 2 Mbytes for STM32L4Rxxx and STM32L4Sxxx devices and 1 Mbyte for STM32L4P5xx and STM32L4Q5xx devices.
5. 192 Kbytes for STM32L4Rxxx and STM32L4Sxxx devices and 128 Kbytes for STM32L4P5xx and STM32L4Q5xx devices.

Embedded boot loader

The embedded boot loader is located in the system memory, programmed by ST during
production. Refer to AN2606 STM32 microcontroller system memory boot mode.

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3 Embedded Flash memory (FLASH)

3.1 Introduction
The Flash memory interface manages CPU AHB ICode and DCode accesses to the Flash
memory. It implements the erase and program Flash memory operations and the read and
write protection mechanisms.
The Flash memory interface accelerates code execution with a system of instruction
prefetch and cache lines.

3.2 FLASH main features

• Up to 2 Mbytes of Flash memory with dual-bank architecture supporting read-while-
write capability (RWW).
• Flash memory read operations with two data width modes supported:
– Single-bank mode DBANK=0: read access of 128 bits
– Dual-bank mode DBANK=1: read access of 64 bits
• Page erase, bank erase and mass erase (both banks)
Flash memory interface features:
• Flash memory read operations
• Flash memory program/erase operations
• Read protection activated by option (RDP)
• 4 Write protection areas (2 per bank when DBANK=1 and 4 for full memory when
DBANK=0)
• 2 proprietary code read protection areas (1 per bank when DBANK=1, 2 for all memory
when DBANK=0)
• Flash empty check
• Prefetch on ICODE
• Instruction Cache: 32 cache lines of 4 x 64 or 2 x 128 bits on ICode (1 Kbyte RAM)
• Data Cache: 8 cache lines of 4 x 64 bits or 2 x 128 on DCode (256 bytes RAM)
• Error Code Correction ECC: 8 bits per 64-bit double-word
– DBANK=1: 8 + 64 = 72 bits, 2 bits detection, 1 bit correction
– DBANK=0: (8+64) + (8+64) = 144 bits, 2 bits detection, 1 bit correction
• Option byte loader
• Low-power mode

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3.3 FLASH functional description

3.3.1 Flash memory organization

The Flash memory has the following main features:
• Capacity up to 2 Mbytes, in Single-bank mode (read width of 128 bits) or in Dual-bank
mode (read width of 64-bits)
• Supports dual boot mode thanks to the BFB2 option bit (only in Dual-bank mode)
• Dual-bank mode when DBANK bit is set:
– 2 Mbytes organized in 2 banks for main memory
– Page size of 4 Kbytes
– 72 bits wide data read (64 bits plus 8 ECC bits)
– Bank and Mass erase
• Single-bank mode when DBANK is reset:
– 2 Mbytes organized in one single-bank for main memory
– Page size of 8 Kbytes
– 144 bits wide data read (128 bits plus 2x8 ECC bits)
– Mass erase
The Flash memory is organized as follows:
For STM32L4Rxxx and STM32L4Sxxx devices:
• A main memory block organized depending on the dual-bank configuration bit:
– When dual-bank is enabled (DBANK bit set), the Flash is divided in 2 banks of
1 Mbyte, and each bank is organized as follows:
The main memory block containing 256 pages of 4 Kbytes
Each page is composed of 8 rows of 512 bytes
– When dual-bank is disabled (DBANK bit reset), the main memory block is
organized as one single-bank of 2 Mbytes as follows:
The main memory block containing 256 pages of 8 Kbytes
Each page is composed of 8 rows of 1024 bytes
• Dual-bank organization on 1 Mbyte devices
The dual-bank feature on 1 Mbyte devices is enabled by setting the DB1M option bit.
The dual-bank memory organization is different from the single-bank: the single-bank
memory contains 128 pages of 8 Kbytes whereas the dual-bank memory each bank
contains 128 pages of 4 Kbytes.
For erase operation, the right page numbering and address must be considered
according to the DB1M option bit.
– When the DB1M bit is reset, the erase operation must be performed on the
Bank 1.
– When the DB1M bit is set, to perform an erase operation on Bank 2, the page
number must be programmed (page number from 0 to 127) on Bank 2.
For STM32L4P5xx and STM32L4Q5xx devices
• A main memory block organized depending on the dual-bank configuration bit:
– When dual-bank is enabled (DBANK bit set), the Flash is divided in 2 banks of
512 Kbytes, and each bank is organized as follows:

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The main memory block containing 128 pages of 4 Kbytes

Each page is composed of 8 rows of 512 bytes
– When dual-bank is disabled (DBANK bit reset), the main memory block is
organized as one single-bank of 1 Mbyte as follows:
The main memory block containing 128 pages of 8 Kbytes
Each page is composed of 8 rows of 1024 bytes
• Dual-bank organization on 512 Kbytes devices
The dual-bank feature on 512 Kbytes devices is enabled by setting the DB1M option
bit. The dual-bank memory organization is different from the single-bank: the single-
bank memory contains 128 pages of 8 Kbytes whereas the dual-bank memory each
bank contains 64 pages of 4 Kbytes.
Refer to Table 8: Flash module - 1 Mbyte dual-bank organization (64 bits read width) and
Table 9: Flash module - 1 Mbyte single-bank organization (128 bits read width) for details
on 1 Mbyte single-bank and 1 Mbyte dual-bank organizations.
Refer to Table 10: Flash module - 512 Kbytes dual-bank organization (64 bits read width)
and Table 11: Flash module - 512 Kbytes single-bank organization (128 bits read width) for
details on 512 Kbytes single-bank and 512 Kbytes dual-bank organizations.
For all STM32L4+ Series:
• An Information block containing:
– System memory from which the device boots in System memory boot mode. The
area is reserved for use by STMicroelectronics and contains the bootloader that is
used to reprogram the Flash memory through one of the following interfaces:
USART1, USART2, USART3, USB (DFU), I2C1, I2C2, I2C3, SPI1, SPI2, SPI3. It
is programmed by STMicroelectronics when the device is manufactured, and
protected against spurious write/erase operations. For further details, please refer
to the AN2606 available from www.st.com.
– 1 Kbyte (128 double word) OTP (one-time programmable) bytes for user data. The
OTP area is available in Bank 1 only. The OTP data cannot be erased and can be
written only once. If only one bit is at 0, the entire double word cannot be written
anymore, even with the value 0x0000 0000 0000 0000.
– Option bytes for user configuration.
The memory organization is based on a main area and an information block as shown in the
tables below.

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Table 6. Flash module - 2 Mbytes dual-bank organization

(64 bits read width)
Flash area Flash memory address Size (bytes) Name

0x0800 0000 - 0x0800 0FFF 4K Page 0

0x0800 1000 - 0x0800 1FFF 4K Page 1
0x0800 2000 - 0x0800 2FFF 4K Page 2
0x0800 3000 - 0x0800 3FFF 4K Page 3
Bank 1
- - -
- - -
- - -
- - -
0x080F F000 - 0x080F FFFF 4K Page 255
Main memory
0x0810 0000 - 0x0810 0FFF 4K Page 0
0x0810 1000 - 0x0810 1FFF 4K Page 1
0x0810 2000 - 0x0810 2FFF 4K Page 2
0x0810 3000 - 0x0810 3FFF 4K Page 3
Bank 2
- - -
- - -
- - -
- - -
0x081F F000 - 0x081F FFFF 4K Page 255
Bank 1 0x1FFF 0000 - 0x1FFF 6FFF 28 K
System memory
Bank 2 0x1FFF 8000 - 0x1FFF EFFF 28 K
Information
Bank 1 0x1FFF 7000 - 0x1FFF 73FF 1K OTP area
block
Bank 1 0x1FF0 0000 - 0x1FF0 000F 16
Option bytes
Bank 2 0x1FF0 1000 - 0x1FF0 100F 16

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Table 7. Flash module - 2 Mbytes single-bank organization

(128 bits read width)
Flash area Flash memory address Size (bytes) Name

0x0800 0000 - 0x0800 1FFF 8K Page 0

0x0800 2000 - 0x0800 3FFF 8K Page 1
0x0800 4000 - 0x0800 5FFF 8K Page 2
- - -
Main memory - - -
- - -
- - -
0x0801 C000 0x0801 DFFF 8K Page 244
0x081F E000 - 0x081F FFFF 8K Page 255
Bank 1 0x1FFF 0000 - 0x1FFF 6FFF 28 K
System memory
Bank 2 0x1FFF 8000 - 0x1FFF EFFF 28 K
Information
Bank 1 0x1FFF 7000 - 0x1FFF 73FF 1K OTP area
block
Bank 1 0x1FF0 0000 - 0x1FF0 000F 16
Option bytes
Bank 2 0x1FF0 1000 - 0x1FF0 100F 16

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Table 8. Flash module - 1 Mbyte dual-bank organization

(64 bits read width)
Flash area Flash memory address Size (bytes) Name

0x0800 0000 - 0x0800 0FFF 4K Page 0

0x0800 1000 - 0x0800 1FFF 4K Page 1
0x0800 2000 - 0x0800 2FFF 4K Page 2
0x0800 3000 - 0x0800 3FFF 4K Page 3
Bank 1
512 Kbytes - - -
- - -
- - -
- - -

Main memory 0x0807 F000 - 0x0807 FFFF 4K Page 127

1 Mbyte 0x0808 0000 - 0x0808 0FFF 4K Page 0
0x0808 1000 - 0x0808 1FFF 4K Page 1
0x0808 2000 - 0x0808 2FFF 4K Page 2
0x0808 3000 - 0x0808 3FFF 4K Page 3
Bank 2
512 Kbytes - - -
- - -
- - -
- - -
0x080F F000 - 0x080F FFFF 4K Page 127
Bank 1 0x1FFF 0000 - 0x1FFF 6FFF 28 K
System memory
Bank 2 0x1FFF 8000 - 0x1FFF EFFF 28 K
Information
Bank 1 0x1FFF 7000 - 0x1FFF 73FF 1K OTP area
block
Bank 1 0x1FF0 0000 - 0x1FF0 000F 16
Option bytes
Bank 2 0x1FF0 1000 - 0x1FF0 100F 16

Table 9. Flash module - 1 Mbyte single-bank organization

(128 bits read width)
Flash area Flash memory address Size (bytes) Name

0x0800 0000 - 0x0800 1FFF 8K Page 0

0x0800 2000 - 0x0800 3FFF 8K Page 1
0x0800 4000 - 0x0800 5FFF 8K Page 2

Main memory - - -
- - -
- - -
- - -
0x080F E000 - 0x080F FFFF 8K Page 127

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Table 9. Flash module - 1 Mbyte single-bank organization

(128 bits read width) (continued)
Flash area Flash memory address Size (bytes) Name

Bank 1 0x1FFF 0000 - 0x1FFF 6FFF 28 K

System memory
Bank 2 0x1FFF 8000 - 0x1FFF EFFF 28 K
Information
Bank 1 0x1FFF 7000 - 0x1FFF 73FF 1K OTP area
block
Bank 1 0x1FF0 0000 - 0x1FF0 000F 16
Option bytes
Bank 2 0x1FF0 1000 - 0x1FF0 100F 16

Table 10. Flash module - 512 Kbytes dual-bank organization

(64 bits read width)
Flash area Flash memory address Size (bytes) Name

0x0800 0000 - 0x0800 0FFF 4K Page 0

0x0800 1000 - 0x0800 1FFF 4K Page 1
0x0800 2000 - 0x0800 2FFF 4K Page 2

Bank 1 0x0800 3000 - 0x0800 3FFF 4K Page 3

256 Kbytes - - -
- - -
- - -
- - -

Main memory 0x0803 F000 - 0x0803 FFFF 4K Page 63

512 Kbytes 0x0804 0000 - 0x0804 0FFF 4K Page 0
0x0804 1000 - 0x0804 1FFF 4K Page 1
0x0804 2000 - 0x0804 2FFF 4K Page 2

Bank 2 0x0804 3000 - 0x0804 3FFF 4K Page 3

256 Kbytes - - -
- - -
- - -
- - -
0x0807 F000 - 0x0807 FFFF 4K Page 63
Bank 1 0x1FFF 0000 - 0x1FFF 6FFF 28 K
System memory
Bank 2 0x1FFF 8000 - 0x1FFF EFFF 28 K
Information
Bank 1 0x1FFF 7000 - 0x1FFF 73FF 1K OTP area
block
Bank 1 0x1FF0 0000 - 0x1FF0 000F 16
Option bytes
Bank 2 0x1FF0 1000 - 0x1FF0 100F 16

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Table 11. Flash module - 512 Kbytes single-bank organization

(128 bits read width)
Flash area Flash memory address Size (bytes) Name

0x0800 0000 - 0x0800 1FFF 8K Page 0

0x0800 2000 - 0x0800 3FFF 8K Page 1
0x0800 4000 - 0x0800 5FFF 8K Page 2
Main
Bank 1 - - -
memory
512 Kbytes - - -
512 Kbytes
- - -
- - -
0x0807 E000 - 0x0807 FFFF 8K Page 127
Bank 1 0x1FFF 0000 - 0x1FFF 6FFF 28 K
System memory
Bank 2 0x1FFF 8000 - 0x1FFF EFFF 28 K
Information
Bank 1 0x1FFF 7000 - 0x1FFF 73FF 1K OTP area
block
Bank 1 0x1FF0 0000 - 0x1FF0 000F 16
Option bytes
Bank 2 0x1FF0 1000 - 0x1FF0 100F 16

3.3.2 Error code correction (ECC)

Dual-bank mode (DBANK=1, 64-bits data width)
Data in Flash memory are 72-bits words: 8 bits are added per double word (64 bits). The
ECC mechanism supports:
• One error detection and correction
• Two errors detection
When one error is detected and corrected, the flag ECCC (ECC correction) is set in Flash
ECC register (FLASH_ECCR). If ECCCIE is set, an interrupt is generated.
When two errors are detected, a flag ECCD (ECC detection) is set in FLASH_ECCR
register. In this case, a NMI is generated.
When an ECC error is detected, the address of the failing double word and its associated
bank are saved in ADDR_ECC[20:0] and BK_ECC in the FLASH_ECCR register.
ADDR_ECC[2:0] are always cleared.
When ECCC or ECCD is set, ADDR_ECC and BK_ECC are not updated if a new ECC error
occurs. FLASH_ECCR is updated only when ECC flags are cleared.
Note: For a virgin data: 0xFF FFFF FFFF FFFF FFFF, one error is detected and corrected but two
errors detection is not supported.
When an ECC error is reported, a new read at the failing address may not generate an ECC
error if the data is still present in the current buffer, even if ECCC and ECCD are cleared.

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Single-bank mode (DBANK=0, 128-bits data width)

Data in Flash memory are 144-bits words: 8 bits are added per each double word. The ECC
mechanism supports:
• One error detection and correction
• Two errors detection per 64 double words
The user must first check the SYSF_ECC bit, and if it is set, the user must refer to the
DBANK=1 programming model (because system Flash is always on 2 banks). If the bit is
not set, the user must refer to the following programing model:
Each double word (bits 63:0 and bits 127:64) has ECC.
When one error is detected in 64 LSB bits (bits 63:0) and corrected, a flag ECCC (ECC
correction) is set in the FLASH_ECCR register.
When one error is detected in 64 MSB bits (bits 127:64) and corrected, a flag ECCC2
(ECC2 correction) is set in the FLASH_ECCR register.
If the ECCCIE is set, an interrupt is generated. The user has to read ECCC and ECCC2 to
see which part of the 128-bits data has been corrected (either 63:0, 127:64 or both).
When two errors are detected in 64 LSB bits, a flag ECCD (ECC detection) is set in the
FLASH_ECCR register.
When two errors are detected in 64 MSB bits (bits 127:64), a flag ECCD2 (ECC2 detection)
is set in the FLASH_ECCR register.
In this case, a NMI is generated. The user has to read ECCD and ECCD2 to see which part
of the 128-bits data has error detection (either 63:0, 127:64 or both).
When an ECC error is detected, the address of the failing the 2 times double word is saved
into ADDR_ECC[20:0] in FLASH_ECCR. ADDR_ECC[20:0] contains an address of a 2
times double word.
The ADDR_ECC[3:0] are always cleared. BK_ECC is not used in this mode.
When ECCC/ECCC2 or ECCD/ECCD2 is/are set, if a new ECC error occurs, the
ADDR_ECC is not updated. The FLASH_ECCR is updated only if the ECC flags
(ECCC/ECCC2/ECCD/ECCD2) are cleared.
Note: For a virgin data: 0xFF FFFF FFFF FFFF FFFF, one error is detected and corrected but two
errors detection is not supported.
When an ECC error is reported, a new read at the failing address may not generate an ECC
error if the data is still present in the current buffer, even if ECCC and ECCD are cleared.

3.3.3 Read access latency

To correctly read data from Flash memory, the number of wait states (LATENCY) must be
correctly programmed in the Flash access control register (FLASH_ACR) according to the
frequency of the CPU clock (HCLK) and the internal voltage range of the device VCORE.
Refer to Section 5.1.8: Dynamic voltage scaling management. Table 12 shows the
correspondence between wait states and CPU clock frequency.

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Table 12. Number of wait states according to CPU clock (HCLK) frequency
HCLK (MHz)
Wait states (WS)
(Latency)
VCORE Range 1 VCORE Range 2

0 WS (1 CPU cycles) ≤20 ≤8

1 WS (2 CPU cycles) ≤40 ≤16
2 WS (3 CPU cycles) ≤60 ≤26
3 WS (4 CPU cycles) ≤80 -
4 WS (5 CPU cycles) ≤100 -
5 WS (6 CPU cycles) ≤120 -

After reset, the CPU clock frequency is 4 MHz and 0 wait state (WS) is configured in the
FLASH_ACR register.
When changing the CPU frequency, the following software sequences must be applied in
order to tune the number of wait states needed to access the Flash memory:

Increasing the CPU frequency:

1. Program the new number of wait states to the LATENCY bits in the Flash access
control register (FLASH_ACR).
2. Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register.
3. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register.
4. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR.
5. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are
taken into account by reading the clock source status (SWS bits) or/and the AHB
prescaler value (HPRE bits), respectively, in the RCC_CFGR register.

Decreasing the CPU frequency:

1. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register.
2. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR.
3. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are
taken into account by reading the clock source status (SWS bits) or/and the AHB
prescaler value (HPRE bits), respectively, in the RCC_CFGR register.
4. Program the new number of wait states to the LATENCY bits in Flash access control
register (FLASH_ACR).
5. Check that the new number of wait states is used to access the Flash memory by
reading the FLASH_ACR register.

3.3.4 Adaptive real-time memory accelerator (ART Accelerator

The proprietary Adaptive real-time (ART) memory accelerator is optimized for STM32
industry-standard Arm® Cortex®-M4 with FPU processors. It balances the inherent
performance advantage of the Arm® Cortex®-M4 with FPU over Flash memory
technologies, which normally requires the processor to wait for the Flash memory at higher
operating frequencies.

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To release the processor full performance, the accelerator implements an instruction

prefetch queue and branch cache which increases program execution speed from the 64-
bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the
ART accelerator is equivalent to 0 wait state program execution from Flash memory at a
CPU frequency up to 120 MHz.

Instruction prefetch
The Cortex®-M4 fetches the instruction over the ICode bus and the literal pool
(constant/data) over the DCode bus. The prefetch block aims at increasing the efficiency of
ICode bus accesses.
In case of Single-bank mode (DBANK option bit is reset), each Flash memory read
operation provides 128 bits from either four instructions of 32 bits or eight instructions of
16 bits depending on the launched program. This 128-bits current instruction line is saved in
a current buffer, and in case of sequential code, at least four CPU cycles are needed to
execute the previous read instruction line.
When in Dual-bank mode (DBANK option bit is set), each Flash memory read operation
provides 64 bits from either two instructions of 32 bits or four instructions of 16 bits
depending on the launched program. This 64-bits current instruction line is saved in a
current buffer, and in case of sequential code, at least two CPU cycles are needed to
execute the previous read instruction line.
Prefetch on the ICode bus can be used to read the next sequential instruction line from the
Flash memory while the current instruction line is being requested by the CPU.
Prefetch is enabled by setting the PRFTEN bit in the Flash access control register
(FLASH_ACR). This feature is useful if at least one wait state is needed to access the Flash
memory.
Figure 5 shows the execution of sequential 16-bit instructions with and without prefetch
when 3 WS are needed to access the Flash memory.

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Figure 5. Sequential 16-bit instructions execution (64-bit read data width)

@ F D E
WAIT
1 1 1 1 WITHOUT PREFETCH
@ F D E
2 2 2 2
@ F D E
3 3 3 3
@ F D E
4 4 4 4
@ F D E
WAIT
5 5 5 5
@ F D E
6 6 6 6
@ F D
7 7 7
@ F
8 8

ins 1 ins 2 ins 3 ins 4 ins 5 ins 6 ins 7 ins 8

fetch fetch fetch fetch fetch fetch fetch fetch

Read ins 1, 2, 3, 4 Gives ins 1, 2, 3, 4 Read ins 5, 6, 7, 8 Gives ins 5, 6, 7, 8

@ F D E
WAIT
1 1 1 1 WITH PREFETCH
@ F D E
2 2 2 2
@ F D E
3 3 3 3
@ F D E
4 4 4 4
@ F D E
5 5 5 5
@ F D E
6 6 6 6
@ F D
7 7 7 Cortex-M4 pipeline
@ F
8 8 @ F D E
6 6 6 6
ins 1 ins 2 ins 3 ins 4 ins 5 ins 6 ins 7 ins 8
AHB protocol
fetch fetch fetch fetch fetch fetch fetch fetch
@: address requested
F: Fetch stage
Read ins 1, 2, 3, 4 Gives ins 1, 2, 3, 4 Gives ins 5, 6, 7, 8 D: Decode stage
E: Execute stage
Read ins 5, 6, 7, 8 Read ins 9, 10, ...

MS33467V1

When the code is not sequential (branch), the instruction may not be present in the currently
used instruction line or in the prefetched instruction line. In this case (miss), the penalty in
terms of number of cycles is at least equal to the number of wait states.

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If a loop is present in the current buffer, no new Flash access is performed.

Instruction cache memory (I-Cache)

To limit the time lost due to jumps, it is possible to retain 32 lines of 4 x 64 bits in Dual-bank
mode or 32 lines of 2 x 128 bits in Single-bank mode in an instruction cache memory.This
feature can be enabled by setting the instruction cache enable (ICEN) bit in the Flash
access control register (FLASH_ACR). Each time a miss occurs (requested data not
present in the currently used instruction line, in the prefetched instruction line or in the
instruction cache memory), the line read is copied into the instruction cache memory. If
some data contained in the instruction cache memory are requested by the CPU, they are
provided without inserting any delay. Once all the instruction cache memory lines have been
filled, the LRU (least recently used) policy is used to determine the line to replace in the
instruction memory cache. This feature is particularly useful in case of code containing
loops.
The Instruction cache memory is enable after system reset.

Data cache memory (D-Cache)

Literal pools are fetched from Flash memory through the DCode bus during the execution
stage of the CPU pipeline. Each DCode bus read access fetches 64 or 128 bits which are
saved in a current buffer. The CPU pipeline is consequently stalled until the requested literal
pool is provided. To limit the time lost due to literal pools, accesses through the AHB
databus DCode have priority over accesses through the AHB instruction bus ICode.
If some literal pools are frequently used, the data cache memory can be enabled by setting
the data cache enable (DCEN) bit in the Flash access control register (FLASH_ACR). This
feature works like the instruction cache memory, but the retained data size is limited to 8
rows of 4x64 bits in Dual-bank mode and to 8 rows of 2x128 bits in Single-bank mode.
The Data cache memory is enable after system reset.
Note: The D-Cache is active only when data is requested by the CPU (not by DMA1 and DMA2).
Data in option bytes block are not cacheable.

3.3.5 Flash program and erase operations

The STM32L4+ Series embedded Flash memory can be programmed using in-circuit
programming or in-application programming.
The in-circuit programming (ICP) method is used to update the entire contents of the
Flash memory, using the JTAG, SWD protocol or the bootloader to load the user application
into the microcontroller. ICP offers quick and efficient design iterations and eliminates
unnecessary package handling or socketing of devices.
In contrast to the ICP method, in-application programming (IAP) can use any
communication interface supported by the microcontroller (I/Os, USB, CAN, UART, I2C, SPI,
etc.) to download programming data into memory. IAP allows the user to re-program the
Flash memory while the application is running. Nevertheless, part of the application has to
have been previously programmed in the Flash memory using ICP.
Note: The contents of the Flash memory are not guaranteed if a device reset occurs during a
Flash memory operation.
An on-going Flash memory operation will not block the CPU as long as the CPU does not
access the same Flash memory bank. Code or data fetches are possible on one bank while

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a write/erase operation is performed to the other bank (refer to Section 3.3.8: Read-while-
write (RWW) available only in Dual-bank mode (DBANK=1)). The Flash erase and
programming is only possible in the voltage scaling range 1. The VOS[1:0] bits in the
PWR_CR1 must be programmed to 01b.
On the contrary, during a program/erase operation to the Flash memory, any attempt to read
the same Flash memory bank will stall the bus. The read operation will proceed correctly
once the program/erase operation has completed.

Unlocking the Flash memory

After reset, write is not allowed in the Flash control register (FLASH_CR) to protect the
Flash memory against possible unwanted operations due, for example, to electric
disturbances. The following sequence is used to unlock this register:
1. Write KEY1 = 0x45670123 in the Flash key register (FLASH_KEYR)
2. Write KEY2 = 0xCDEF89AB in the FLASH_KEYR register.
Any wrong sequence will lock up the FLASH_CR register until the next system reset. In the
case of a wrong key sequence, a bus error is detected and a Hard Fault interrupt is
generated.
The FLASH_CR register can be locked again by software by setting the LOCK bit in the
FLASH_CR register.
Note: The FLASH_CR register cannot be written when the BSY bit in the Flash status register
(FLASH_SR) is set. Any attempt to write to it with the BSY bit set will cause the AHB bus to
stall until the BSY bit is cleared.

3.3.6 Flash main memory erase sequences

The Flash memory erase operation can be performed at page level, bank level or on the
whole Flash memory (Mass Erase). Mass Erase does not affect the Information block
(system Flash, OTP and option bytes).

Page erase
To erase a page, follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the BSY bit in the Flash
status register (FLASH_SR).
2. Check and clear all error programming flags due to a previous programming. If not,
PGSERR is set.
3. In Dual-bank mode (DBANK option bit is set), set the PER bit and select the page to
erase (PNB) with the associated bank (BKER) in the Flash control register
(FLASH_CR). In Single-bank mode (DBANK option bit is reset), set the PER bit and
select the page to erase (PNB). The BKER bit in the Flash control register
(FLASH_CR) must be kept cleared.
4. Set the STRT bit in the FLASH_CR register.
5. Wait for the BSY bit to be cleared in the FLASH_SR register.
Note: The internal oscillator HSI16 (16 MHz) is enabled automatically when STRT bit is set, and
disabled automatically when STRT bit is cleared, except if the HSI16 is previously enabled
with HSION in RCC_CR register.
If the page erase is part of write-protected area (by WRP or PCROP), WRPERR is set and
the page erase request is aborted.

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Bank 1, Bank 2 Mass erase (available only in Dual-bank mode when

DBANK=1)
To perform a bank Mass Erase, follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register.
2. Check and clear all error programming flags due to a previous programming. If not,
PGSERR is set.
3. Set the MER1 bit or MER2 (depending on the bank) in the Flash control register
(FLASH_CR). Both banks can be selected in the same operation, in that case it
corresponds to a mass erase.
4. Set the STRT bit in the FLACH_CR register.
5. Wait for the BSY bit to be cleared in the Flash status register (FLASH_SR).

Mass erase
To perform a Mass erase, follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register.
2. Check and clear all error programming flags due to a previous programming. If not,
PGSERR is set.
3. Set the MER1 bit and MER2 in the Flash control register (FLASH_CR).
4. Set the STRT bit in the FLACH_CR register.
5. Wait for the BSY bit to be cleared in the Flash status register (FLASH_SR).
Note: The internal oscillator HSI16 (16 MHz) is enabled automatically when STRT bit is set, and
disabled automatically when STRT bit is cleared, except if the HSI16 is previously enabled
with HSION in RCC_CR register.
When DBANK=0, if only the MERA or the MERB bit is set, PGSERR is set and no erase
operation is performed.
If the bank to erase or if one of the banks to erase contains a write-protected area (by WRP
or PCROP), WRPERR is set and the mass erase request is aborted (for both banks if both
are selected).

3.3.7 Flash main memory programming sequences

The Flash memory is programmed 72 bits at a time (64 bits + 8 bits ECC).
Programming in a previously programmed address is not allowed except if the data to write
is full zero, and any attempt will set PROGERR flag in the Flash status register
(FLASH_SR).
It is only possible to program double word (2 x 32-bit data).
• Any attempt to write byte or half-word will set SIZERR flag in the FLASH_SR register.
• Any attempt to write a double word which is not aligned with a double word address will
set PGAERR flag in the FLASH_SR register.

Standard programming
The Flash memory programming sequence in standard mode is as follows:

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1. Check that no Flash main memory operation is ongoing by checking the BSY bit in the
Flash status register (FLASH_SR).
2. Check and clear all error programming flags due to a previous programming. If not,
PGSERR is set.
3. Set the PG bit in the Flash control register (FLASH_CR).
4. Perform the data write operation at the desired memory address, inside main memory
block or OTP area. Only double word can be programmed.
– Write a first word in an address aligned with double word
– Write the second word
5. Wait until the BSY bit is cleared in the FLASH_SR register.
6. Check that EOP flag is set in the FLASH_SR register (meaning that the programming
operation has succeed), and clear it by software.
7. Clear the PG bit in the FLASH_SR register if there no more programming request
anymore.
Note: When the Flash interface has received a good sequence (a double word), programming is
automatically launched and BSY bit is set. The internal oscillator HSI16 (16 MHz) is enabled
automatically when PG bit is set, and disabled automatically when PG bit is cleared, except
if the HSI16 is previously enabled with HSION in RCC_CR register.
If the user needs to program only one word, double word must be completed with the erase
value 0xFFFF FFFF to launch automatically the programming.
ECC is calculated from the double word to program.

Fast programming for a row (64 double words if DBANK=1) or for half row (64
double words if DBANK=0)
This mode allows to program a row (64 double words if DBANK=1) or half row (64 double
words if DBANK=0), and to reduce the page programming time by eliminating the need for
verifying the Flash locations before they are programmed and to avoid rising and falling time
of high voltage for each double word. During fast programming, the CPU clock frequency
(HCLK) must be at least 8 MHz.
Only the main memory can be programmed in fast programming mode.
The Flash main memory programming sequence in standard mode is as follows:
1. In Single-bank mode (DBANK=0), perform a mass erase. If not, PGSERR is set. The
Fast programing can be performed only if the code is executed from RAM or from

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bootloader. In Dual-bank mode (DBANK=1), perform a mass erase of the bank to

program. If not, PGSERR is set.
2. Check that no Flash main memory operation is ongoing by checking the BSY bit in the
Flash status register (FLASH_SR).
3. Check and clear all error programming flag due to a previous programming.
4. Set the FSTPG bit in Flash control register (FLASH_CR).
5. Write the 64 double words to program a row or half row. Only double words can be
programmed:
– Write a first word in an address aligned with double word
– Write the second word.
6. Wait until the BSY bit is cleared in the FLASH_SR register.
7. Check that EOP flag is set in the FLASH_SR register (meaning that the programming
operation has succeed), and clear it by software.
8. Clear the FSTPG bit in the FLASH_SR register if there no more programming request
anymore.
Note: If the Flash is attempted to be written in fast programming mode while a read operation is on
going in the same bank, the programming is aborted without any system notification (no
error flag is set).
When the Flash interface has received the first double word, programming is automatically
launched. The BSY bit is set when the high voltage is applied for the first double word, and it
is cleared when the last double word has been programmed or in case of error. The internal
oscillator HSI16 (16 MHz) is enabled automatically when FSTPG bit is set, and disabled
automatically when FSTPG bit is cleared, except if the HSI16 is previously enabled with
HSION in RCC_CR register.
The 64 double word must be written successively. The high voltage is kept on the Flash for
all the programming (around 2 x 25 us). Maximum time between two double words write
requests is the time programming. If a second double word arrives after this time
programming, fast programming is interrupted and MISSERR is set.
High voltage mustn’t exceed 8 ms for a full row between 2 erases. This is guaranteed by the
sequence of 64 double words successively written with a clock system greater or equal to
8MHz. An internal time-out counter counts 7ms when fast programming is set and stops the
programming when time-out is over. In this case the FASTERR bit is set.
If an error occurs, high voltage is stopped and next double word to programmed is not
programmed. Anyway, all previous double words have been properly programmed.

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Programming errors
Several kind of errors can be detected. In case of error, the Flash operation (programming
or erasing) is aborted.
• PROGERR: Programming error
In standard programming: PROGERR is set if the word to write is not previously erased
(except if the value to program is full zero).
• SIZERR: Size programming error
In standard programming or in fast programming: only double word can be
programmed and only 32-bit data can be written. SIZERR is set if a byte or an half-
word is written.
• PGAERR: Alignment programming error
PGAERR is set if one of the following conditions occurs:
– In standard programming: the first word to be programmed is not aligned with a
double word address, or the second word doesn’t belong to the same double word
address.
– In fast programming: the data to program does not belong to the same row than
the previous programmed double words, or the address to program is not greater
than the previous one.
• PGSERR: Programming sequence error
PGSERR is set if one of the following conditions occurs:
– In the standard programming sequence or the fast programming sequence: a data
is written when PG and FSTPG are cleared.
– In the standard programming sequence or the fast programming sequence:
MER1, MER2, and PER are not cleared when PG or FSTPG is set.
– In the fast programming sequence: the Mass erase is not performed before setting
FSTPG bit.
– In the mass erase sequence: PG, FSTPG, and PER are not cleared when MER1
or MER2 is set.
– In the page erase sequence: PG, FSTPG, MER1 and MER2 are not cleared when
PER is set.
– PGSERR is set also if PROGERR, SIZERR, PGAERR, WRPERR, MISSERR,
FASTERR or PGSERR is set due to a previous programming error.
– When DBANK=0, in the case that only either MER1 or MER2 is set, PGSERR is
set (bank mass erase is not allowed).
• WRPERR: Write protection error
WRPERR is set if one of the following conditions occurs:
– Attempt to program or erase in a write protected area (WRP) or in a PCROP area.
– Attempt to perform a bank erase when one page or more is protected by WRP or
PCROP.
– The debug features are connected or the boot is executed from SRAM or from
System Flash when the read protection (RDP) is set to Level 1.
– Attempt to modify the option bytes when the read protection (RDP) is set to
Level 2.
• MISSERR: Fast programming data miss error
In fast programming: all the data must be written successively. MISSERR is set if the

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previous data programmation is finished and the next data to program is not written yet.
• FASTERR: Fast programming error
In fast programming: FASTERR is set if one of the following conditions occurs:
– When FSTPG bit is set for more than 7ms which generates a time-out detection.
– When the fast programming has been interrupted by a MISSERR, PGAERR,
WRPERR or SIZERR.
If an error occurs during a program or erase operation, one of the following error flags is set
in the FLASH_SR register:
PROGERR, SIZERR, PGAERR, PGSERR, MISSERR (Program error flags),
WRPERR (Protection error flag)
In this case, if the error interrupt enable bit ERRIE is set in the Flash status register
(FLASH_SR), an interrupt is generated and the operation error flag OPERR is set in the
FLASH_SR register.
Note: If several successive errors are detected (for example, in case of DMA transfer to the Flash
memory), the error flags cannot be cleared until the end of the successive write requests.

Programming and caches

If a Flash memory write access concerns some data in the data cache, the Flash write
access modifies the data in the Flash memory and the data in the cache.
If an erase operation in Flash memory also concerns data in the data or instruction cache,
you have to make sure that these data are rewritten before they are accessed during code
execution. If this cannot be done safely, it is recommended to flush the caches by setting the
DCRST and ICRST bits in the Flash access control register (FLASH_ACR).
Note: The I/D cache should be flushed only when it is disabled (I/DCEN = 0).

3.3.8 Read-while-write (RWW) available only in Dual-bank mode

(DBANK=1)
The Dual-bank mode is available only when the DBANK option bit is reset, allowing read-
while-write operations. This feature allows to perform a read operation from one bank while
erase or program operation is performed to the other bank.
Note: Write-while-write operations are not allowed. As an example, It is not possible to perform an
erase operation on one bank while programming the other one.

Read from bank 1 while page erasing in bank 2 (or vice versa)
While executing a program code from bank 1, it is possible to perform a page erase
operation on bank 2 (and vice versa). Follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the BSY bit in the Flash
status register (FLASH_SR) (BSY is active when erase/program operation is on going
in bank 1 or bank 2).
2. Set PER bit, PSB to select the page and BKER to select the bank in the Flash control
register (FLASH_CR).
3. Set the STRT bit in the FLASH_CR register.
4. Wait for the BSY bit to be cleared (or use the EOP interrupt).

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Read from bank 1 while mass erasing bank 2 (or vice versa)
While executing a program code from bank 1, it is possible to perform a mass erase
operation on bank 2 (and vice versa). Follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the BSY bit in the Flash
status register (FLASH_SR) (BSY is active when erase/program operation is on going
in bank 1 or bank 2).
2. Set MER1 or MER2 to in the Flash control register (FLASH_CR).
3. Set the STRT bit in the FLASH_CR register.
4. Wait for the BSY bit to be cleared (or use the EOP interrupt).

Read from bank 1 while programming bank 2 (or vice versa)

While executing a program code from bank 1, it is possible to perform a program operation
on the bank 2. (and vice versa). Follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the BSY bit in the Flash
status register (FLASH_SR) (BSY is active when erase/program operation is on going
on bank 1 or bank 2).
2. Set the PG bit in the Flash control register (FLASH_CR).
3. Perform the data write operations at the desired address memory inside the main
memory block or OTP area.
4. Wait for the BSY bit to be cleared (or use the EOP interrupt).

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3.4 FLASH option bytes

3.4.1 Option bytes description

The option bytes are configured by the end user depending on the application requirements.
As a configuration example, the watchdog may be selected in hardware or software mode
(refer to Section 3.4.2: Option bytes programming).
A double word is split up as follows in the option bytes:

Table 13. Option byte format

63-24 23-16 15 -8 7-0 31-24 23-16 15 -8 7-0

Complemented Complemented Complemented Complemented Option Option Option Option

option byte 3 option byte 2 option byte 1 option byte 0 byte 3 byte 2 byte 1 byte 0

The organization of these bytes inside the information block is as shown in Table 14.
The option bytes can be read from the memory locations listed in Table 14 or from the
Option byte registers:
• Flash option register (FLASH_OPTR)
• Flash PCROP1 Start address register (FLASH_PCROP1SR)
• Flash PCROP1 End address register (FLASH_PCROP1ER)
• Flash WRP1 area A address register (FLASH_WRP1AR)
• Flash WRP1 area B address register (FLASH_WRP1BR)
• Flash PCROP2 Start address register (FLASH_PCROP2SR)
• Flash PCROP2 End address register (FLASH_PCROP2ER)
• Flash WRP2 area A address register (FLASH_WRP2AR)
• Flash WRP2 area B address register (FLASH_WRP2BR).
Table 14. Option byte organization
BANK Address [63:56] [55:48] [47:40] [39:32] [31:24] [23:16] [15:8] [7:0]

1FF00000 USER OPT RDP USER OPT RDP

Unused and Unused and
1FF00008 PCROP1_STRT[15:0] PCROP1_STRT[15]
PCROP1_STRT[16] PCROP1_STRT[16]
PCROP_RDP and PCROP_RDP and
1FF00010 Unused and PCROP1_END[15:0] Unused and PCROP1_END[15:0]
Bank 1
PCROP1_END[16] PCROP1_END[16]
WRP1A WRP1A WRP1A_ WRP1A
1FF00018 Unused Unused Unused Unused
_END _STRT END _STRT
WRP2A WRP2A WRP2A_ WRP2A
1FF00020 Unused Unused Unused Unused
_END _STRT END _STRT

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Table 14. Option byte organization (continued)

BANK Address [63:56] [55:48] [47:40] [39:32] [31:24] [23:16] [15:8] [7:0]

1FF01000 Unused
Unused and Unused and
1FF01008 PCROP2_STRT[15] PCROP2_STRT[15]
PCROP2_STRT[16] PCROP2_STRT[16]
Unused and Unused and
1FF01010 PCROP2_END[15] PCROP2_END[15]
Bank 2 PCROP2_END[16] PCROP2_END[16]
WRP1A WRP1B WRP1A WRP1B
1FF01018 Unused Unused Unused Unused
_END _STRT _END _STRT
WRP2A WRP2B WRP2A WRP2B
1FF01020 Unused Unused Unused Unused
_END _STRT _END _STRT

User and read protection option bytes

Flash memory address: 0x1FF0 0000
ST production value: 0xFFEF F8AA

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
n nSW SRAM2 SRAM2 n WWDG IWGD_ IWDG_ IWDG_
Res. Res. Res. Res. DBANK DB1M BFB2
BOOT0 BOOT0 _RST _PE BOOT1 _SW STDBY STOP SW
r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
nRST_ nRST_ nRST_
Res. Res. BOR_LEV[2:0] RDP[7:0]
SHDW STDBY STOP
r r r r r r r r r r r r r r

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 nBOOT0: nBOOT0 option bit
0: nBOOT0 = 0
1: nBOOT0 = 1
Bit 26 nSWBOOT0: Software BOOT0
0: BOOT0 taken from the option bit nBOOT0
1: BOOT0 taken from PH3/BOOT0 pin
Bit 25 SRAM2_RST: SRAM2 Erase when system reset
0: SRAM2 erased when a system reset occurs
1: SRAM2 is not erased when a system reset occurs
Bit 24 SRAM2_PE: SRAM2 parity check enable
0: SRAM2 parity check enable
1: SRAM2 parity check disable
Bit 23 nBOOT1: Boot configuration
Together with the BOOT0 pin, this bit selects boot mode from the Flash main
memory, SRAM1 or the System memory. Refer to Section 2.6: Boot
configuration.

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Bit 22 DBANK:
0: Single-bank mode with 128 bits data read width
1: Dual-bank mode with 64 bits data
This bit can be written only when PCROP1/2 is disabled.
Bit 21 DB1M:
For STM32L4Rxxx and STM32L4Sxxx devices:
Dual-bank on 1-Mbyte Flash memory devices
0: 1 Mbyte single Flash contiguous address in Bank1
1: 1 Mbyte dual-bank Flash with contiguous addresses
For STM32L4P5xx and STM32L4Q5xx devices:
Dual-bank on 512 Kbytes Flash memory devices
0: 512 Kbytes single Flash contiguous address in Bank1
1: 512 Kbytes Dual-bank Flash with contiguous addresses
Bit 20 BFB2: Dual-bank boot
0: Dual-bank boot disable
1: Dual-bank boot enable
Bit 19 WWDG_SW: Window watchdog selection
0: Hardware window watchdog
1: Software window watchdog
Bit 18 IWDG_STDBY: Independent watchdog counter freeze in Standby mode
0: Independent watchdog counter is frozen in Standby mode
1: Independent watchdog counter is running in Standby mode
Bit 17 IWDG_STOP: Independent watchdog counter freeze in Stop mode
0: Independent watchdog counter is frozen in Stop mode
1: Independent watchdog counter is running in Stop mode
Bit 16 IDWG_SW: Independent watchdog selection
0: Hardware independent watchdog
1: Software independent watchdog
Bit 15 Reserved, must be kept at reset value.
Bit 14 nRST_SHDW:
0: Reset generated when entering the Shutdown mode
1: No reset generated when entering the Shutdown mode
Bit 13 nRST_STDBY
0: Reset generated when entering the Standby mode
1: No reset generate when entering the Standby mode
Bit 12 nRST_STOP
0: Reset generated when entering the Stop mode
1: No reset generated when entering the Stop mode

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Bit 11 Reserved, must be kept at reset value.

Bits10:8 BOR_LEV: BOR reset Level
These bits contain the VDD supply level threshold that activates/releases the
reset.
000: BOR Level 0. Reset level threshold is around 1.7 V
001: BOR Level 1. Reset level threshold is around 2.0 V
010: BOR Level 2. Reset level threshold is around 2.2 V
011: BOR Level 3. Reset level threshold is around 2.5 V
100: BOR Level 4. Reset level threshold is around 2.8 V
Bits 7:0 RDP: Read protection level
0xAA: Level 0, read protection not active
0xCC: Level 2, chip read protection active
Others: Level 1, memories read protection active

PCROP1 Start address option bytes

Flash memory address: 0x1FF0 0008
ST production value: 0xFFFF FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCROP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1_STRT
[16:0]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP1_STRT[16:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:17 Reserved, must be kept at reset value.

Bits 16:0 PCROP1_STRT[16:0]: PCROP area start offset
DBANK=1
PCROP1_STRT contains the first double-word of the PCROP area for bank1.
DBANK=0
PCROP1_STRT contains the first 2xdouble-word of the PCROP area for all
memory.

PCROP1 End address option bytes

Flash memory address: 0x1FF0 0010
ST production value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCRO
PCROP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. P1_EN
_RDP
D
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP1_END[16:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bit 31 PCROP_RDP: PCROP area preserved when RDP level decreased

This bit is set only. It is reset after a full mass erase due to a change of RDP
from Level 1 to Level 0.
0: PCROP area is not erased when the RDP level is decreased from Level 1 to
Level 0.
1: PCROP area is erased when the RDP level is decreased from Level 1 to
Level 0 (full mass erase).
Bits 30:17 Reserved, must be kept at reset value.
Bits 16:0 PCROP1_END: Bank 1 PCROP area end offset
DBANK=1
PCROP1_END contains the last double-word of the bank 1 PCROP area.
DBANK=0
PCROP1_END contains the last 2x double-word PCROP area for all memory.

WRP Area A address option bytes

Flash memory address: 0x1FF0 0018
ST production value: 0x0000 00FF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. WRP1A_END[7:0]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. WRP1A_STRT[7:0]
rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 WRP1A_END[7:0]: WRP first area “A” end offset
DBANK=1
WRP1A_END contains the last page of WRP first area in bank1.
DBANK=0
WRP1A_END contains the last page of WRP first area for all memory.
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 WRP1A_STRT[7:0]: WRP first area “A” start offset
DBANK=1
WRP1A_STRT contains the first page of WRP first area for bank1.
DBANK=0
WRP1A_STRT contains the first page of WRP first area for all memory.

WRP1 Area B address option bytes

Flash memory address: 0x1FF0 0020
ST production value: 0x0000 00FF

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. WRP1B_END[7:0]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. WRP1B_STRT[7:0]
rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 WRP1B_END[7:0]: WRP second area “B” end offset
DBANK=1
WRP1B_END contains the last page of the WRP second area for bank1.
DBANK=0
WRP1B_END contains the last page of the WPR second area for all memory.
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 WRP1B_STRT[7:0]: WRP second area “B” start offset
DBANK=1
WRP1B_STRT contains the last page of the WRP second area for bank1.
DBANK=0
WRP1B_STRT contains the last page of the WPR second area for all memory.

PCROP2 Start address option bytes

Flash memory address: 0x1FF0 1008
ST production value: 0xFFFF FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCROP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 2_STRT
[16:0]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP2_STRT[16:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:17 Reserved, must be kept at reset value.

Bits 16:0 PCROP2_STRT[16:0]: PCROP area start offset
DBANK=1
PCROP2_STRT contains the first double-word of the PCROP area for bank 2.
DBANK=0
PCROP2_STRT contains the first double-word PCROP area for all memory.

PCROP2 End address option bytes

Flash memory address: 0x1FF0 1010
ST production value: 0x0000 0000

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCRO
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. P2_EN
D[16:0]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP2_END[16:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:17 Reserved, must be kept at reset value.

Bits 16:0 PCROP2_END[16:0]: PCROP area end offset
DBANK=1
PCROP2_END contains the last double-word of the PCROP area for bank2.
DBANK=0
PCROP2_END contains the last 2xdouble-word of the PCROP area for all the
memory.

WRP2 Area A address option bytes

Flash memory address: 0x1FF0 1018
ST production value: 0x0000 00FF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. WRP2A_END[23:16]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. WRP2A_STRT[7:0]
rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 WRP2A_END: WRP first area “A” end offset
DBANK=1
WRP2A_END contains the last page of the WRP first area for bank2.
DBANK=0
WRP2A_END contains the last page of the WRP third area for all memory.
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 WRP2A_STRT: WRP first area “A” start offset
DBANK=1
WRP2A_STRT contains the first page of the WRP first area for bank2.
DBANK=0
WRP2A_STRT contains the first page of the WRP third area for all memory.

WRP Area B address option bytes

Flash memory address: 0x1FF0 1020
ST production value: 0x0000 00FF

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. WRP2B_END[23:16]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. WRP2B_STRT[7:0]
rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 WRP2B_END: WRP second area “B” end offset
DBANK=1
WRP2B_END contains the last page of the WRP second area for bank2.
DBANK=0
WRP2B_END contains the last page of the WRP fourth area for all memory.
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 WRP2B_STRT: WRP second area “B” start offset
DBANK=1
WRP2B_STRT contains the first page of the WRP second area for bank2.
DBANK=0
WRP2B_STRT contains the first page of the WRP second area for all memory.

3.4.2 Option bytes programming

After reset, the options related bits in the Flash control register (FLASH_CR) are write-
protected. To run any operation on the option bytes page, the option lock bit OPTLOCK in
the Flash control register (FLASH_CR) must be cleared. The following sequence is used to
unlock this register:
1. Unlock the FLASH_CR with the LOCK clearing sequence (refer to Unlocking the Flash
memory).
2. Write OPTKEY1 = 0x08192A3B in the Flash option key register (FLASH_OPTKEYR).
3. Write OPTKEY2 = 0x4C5D6E7F in the FLASH_OPTKEYR register.
The user options can be protected against unwanted erase/program operations by setting
the OPTLOCK bit by software.
Note: If LOCK is set by software, OPTLOCK is automatically set too.

Modifying user options

The option bytes are programmed differently from a main memory user address. It is not
possible to modify independently user options of bank 1 or bank 2. The users Options of the
bank 1 are modified first.
To modify the user options value, follow the procedure below:
1. Check that no Flash memory operation is on going by checking the BSY bit in the Flash
status register (FLASH_SR).
2. Clear OPTLOCK option lock bit with the clearing sequence described above.
3. Write the desired options value in the options registers: Flash option register
(FLASH_OPTR), Flash PCROP1 Start address register (FLASH_PCROP1SR), Flash
PCROP1 End address register (FLASH_PCROP1ER), Flash WRP1 area A address
register (FLASH_WRP1AR), Flash WRP1 area B address register (FLASH_WRP1BR),

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Flash PCROP2 Start address register (FLASH_PCROP2SR), Flash PCROP2 End

address register (FLASH_PCROP2ER), Flash WRP2 area A address register
(FLASH_WRP2AR), Flash WRP2 area B address register (FLASH_WRP2BR).
4. Set the Options Start bit OPTSTRT in the Flash control register (FLASH_CR).
5. Wait for the BSY bit to be cleared.
Note: Any modification of the value of one option is automatically performed by erasing both user
option bytes pages first (bank 1 and bank 2) and then programming all the option bytes with
the values contained in the Flash option registers.

Option byte loading

After the BSY bit is cleared, all new options are updated into the Flash but they are not
applied to the system. They will have effect on the system when they are loaded. Option
bytes loading (OBL) is performed in two cases:
– when OBL_LAUNCH bit is set in the Flash control register (FLASH_CR).
– after a power reset (BOR reset or exit from Standby/Shutdown modes).
Option byte loader performs a read of the options block and stores the data into internal
option registers. These internal registers configure the system and cannot be read with by
software. Setting OBL_LAUNCH generates a reset so the option byte loading is performed
under system reset.
Each option bit has also its complement in the same double word. During option loading, a
verification of the option bit and its complement allows to check the loading has correctly
taken place.
During option byte loading, the options are read by double word with ECC. If the word and
its complement are matching, the option word/byte is copied into the option register.
If the comparison between the word and its complement fails, a status bit OPTVERR is set.
Mismatch values are forced into the option registers:
– For USR OPT option, the value of mismatch is all options at ‘1’, except for
BOR_LEV which is “000” (lowest threshold)
– For WRP option, the value of mismatch is the default value “No protection”
– For RDP option, the value of mismatch is the default value “Level 1”
– For PCROP, the value of mismatch is “all memory protected”
On system reset rising, internal option registers are copied into option registers which can
be read and written by software (FLASH_OPTR, FLASH_PCROP1/2SR,
FLASH_PCROP1/2ER, FLASH_WRP1/2AR, FLASH_WRP1/2BR). These registers are
also used to modify options. If these registers are not modified by user, they reflects the
options states of the system. See Section : Modifying user options for more details.

Activating Dual-bank mode (switching from DBANK=0 to DBANK=1)

When switching from one Flash mode to another (for example from single to dua- bank) it is
recommended to execute the code from the SRAM or use the bootloader. To avoid reading

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corrupted data from the Flash when the memory organization is changed, any access
(either CPU or DMAs) to Flash memory should be avoided before reprogramming.
• Disable Instruction/data caches and/or prefetch if they are enabled (reset PRFTEN and
ICEN/DCEN bits in the FLASH_ACR register).
• Flush instruction and data cache by setting the DCRST/ICRST bits in the FLASH_ACR
register.
• Set the DBANK option bit and clear all the WRP write protection (follow user option
modification and option bytes loader procedure).
– Once OBL is done with DBANK=0, perform a mass erase.
– Start a new programing of code in 64 bits mode with DBANK=0 memory mapping.
– Set the new WRP/PCROP with DBANK=0 scheme if needed.
– Set PRFTEN and ICEN/DCEN if needed.
The new software is ready to be run using the bank configuration.

De-activating Dual-bank mode (switching from DBANK=1 to DBANK=0)

When switching from one Flash mode to another (for example from single to dual-bank) it is
recommended to execute the code from the SRAM or use the bootloader. To avoid reading
corrupted data from the Flash when the memory organization is changed, any access
(either CPU or DMAs) to Flash memory should be avoided before reprogramming.
• Disable Instruction/data caches and/or prefetch if they are enabled (reset PRFTEN and
ICEN/DCEN bits in the FLASH_ACR register).
• Flush instruction and data cache by setting the DCRST/ICRST bits in the FLASH_ACR
register.
• Clear the DBANK option bit and all WRP write protection (follow user option
modification and option bytes loader procedure).
– Once OBL is done with DBANK=0, perform a mass erase.
– Start a new programing of code in 128 bits mode with DBANK=0 memory mapping
– Set the new WRP/PCROP with DBANK=0 scheme if needed. Set PRFTEN and
ICEN/DCEN if needed.
The new software is ready to be run using the bank configuration.

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3.5 FLASH memory protection

The Flash main memory can be protected against external accesses with the Read
protection (RDP). The pages of the Flash memory can also be protected against unwanted
write due to loss of program counter contexts. The write-protection (WRP) granularity is one
page (2 KByte). Apart of the Flash memory can also be protected against read and write
from third parties (PCROP). The PCROP granularity is double word (64-bit).

3.5.1 Read protection (RDP)

The read protection is activated by setting the RDP option byte and then, by applying a
system reset to reload the new RDP option byte. The read protection protects to the Flash
main memory, the option bytes, the backup registers (RTC_BKPxR in the RTC) and the
SRAM2.
Note: If the read protection is set while the debugger is still connected through JTAG/SWD, apply
a POR (power-on reset) instead of a system reset.
There are three levels of read protection from no protection (level 0) to maximum protection
or no debug (level 2).
The Flash memory is protected when the RDP option byte and its complement contain the
pair of values shown in Table 15.

Table 15. Flash memory read protection status

RDP byte value RDP complement value Read protection level

0xAA 0x55 Level 0

Any value (not necessarily
Any value except 0xAA or
complementary) except 0x55 and Level 1 (default)
0xCC
0x33
0xCC 0x33 Level 2

The System memory area is read accessible whatever the protection level. It is never
accessible for program/erase operation.

Level 0: no protection
Read, program and erase operations into the Flash main memory area are possible. The
option bytes, the SRAM2 and the backup registers are also accessible by all operations.

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Level 1: Read protection

This is the default protection level when RDP option byte is erased. It is defined as well
when RDP value is at any value different from 0xAA and 0xCC, or even if the complement is
not correct.
• User mode: Code executing in user mode (Boot Flash) can access Flash main
memory, option bytes, SRAM2 and backup registers with all operations.
• Debug, boot RAM and bootloader modes: In debug mode or when code is running
from boot RAM or bootloader, the Flash main memory, the backup registers
(RTC_BKPxR in the RTC) and the SRAM2 are totally inaccessible. In these modes, a
read or write access to the Flash generates a bus error and a Hard Fault interrupt.
Caution: In case the Level 1 is configured and no PCROP area is defined, it is mandatory to set
PCROP_RDP bit to 1 (full mass erase when the RDP level is decreased from Level 1 to
Level 0). In case the Level 1 is configured and a PCROP area is defined, if user code needs
to be protected by RDP but not by PCROP, it must not be placed in a page containing a
PCROP area.

Level 2: No debug
In this level, the protection level 1 is guaranteed. In addition, the Cortex®-M4 debug port, the
boot from RAM (boot RAM mode) and the boot from System memory (bootloader mode) are
no more available. In user execution mode (boot FLASH mode), all operations are allowed
on the Flash Main memory. On the contrary, only read operations can be performed on the
option bytes.
Option bytes cannot be programmed nor erased. Thus, the level 2 cannot be removed at all:
it is an irreversible operation. When attempting to modify the options bytes, the protection
error flag WRPERR is set in the Flash_SR register and an interrupt can be generated.
Note: The debug feature is also disabled under reset.
STMicroelectronics is not able to perform analysis on defective parts on which the level 2
protection has been set.

Changing the Read protection level

It is easy to move from level 0 to level 1 by changing the value of the RDP byte to any value
(except 0xCC). By programming the 0xCC value in the RDP byte, it is possible to go to level
2 either directly from level 0 or from level 1. Once in level 2, it is no more possible to modify
the Read protection level.
When the RDP is reprogrammed to the value 0xAA to move from Level 1 to Level 0, a mass
erase of the Flash main memory is performed if PCROP_RDP is set in the Flash PCROP1
End address register (FLASH_PCROP1ER). The backup registers (RTC_BKPxR in the
RTC) and the SRAM2 are also erased. The user options except PCROP protection are set
to their previous values copied from FLASH_OPTR, FLASH_WRPxyR (x=1, 2 and y =A or
B). PCROP is disable. The OTP area is not affected by mass erase and remains
unchanged.
If the bit PCROP_RDP is cleared in the FLASH_PCROP1ER, the full mass erase is
replaced by a partial mass erase that is successive page erases in the bank where PCROP
is active, except for the pages protected by PCROP. This is done in order to keep the
PCROP code. If PCROP is active for both banks, both banks are erased by page erases.
Only when both banks are erased, options are re-programmed with their previous values.
This is also true for FLASH_PCROPxSR and FLASH_PCROPxER registers (x=1,2).

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Note: Full Mass Erase or Partial Mass Erase is performed only when Level 1 is active and Level 0
requested. When the protection level is increased (0->1, 1->2, 0->2) there is no mass erase.
To validate the protection level change, the option bytes must be reloaded through the
OBL_LAUNCH bit in Flash control register.

Figure 6. Changing the Read protection (RDP) level

RDP ≠ 0xAA and RDP ≠ 0xCC
Others options modified

Level 1
RDP ≠ 0xAA
RDP ≠ 0xCC
default

Write options Including Write options including Write options including

RDP = 0xCC RDP ≠ 0xCC and RDP ≠ 0xAA RDP = 0xAA

Level 2 Level 0
RDP = 0xCC Write options including RDP = 0xAA
RDP = 0xCC

RDP = 0xAA
Options write (RDP level increase) includes: Other(s) option(s) modified
- Options page erase
- New options program
Options write (RDP level decrease) includes Options write (RDP level identical) includes
- Full Mass erase or Partial Mass erase to not - Options page erase
erase PCROP pages if PCROP_RDP is cleared - New options program
- Backup registers and SRAM2 erase
- Options page erase
- New options program MSv61195V1

Table 16. Access status versus protection level and execution modes
Debug/ BootFromRam/
User execution (BootFromFlash)
Area
Protection BootFromLoader(1)
level
Read Write Erase Read Write Erase

1 Yes Yes Yes No No No(3)

Flash main
memory
2 Yes Yes Yes N/A N/A N/A

1 Yes No No Yes No No
System
memory (2)
2 Yes No No N/A N/A N/A

1 Yes Yes(3) Yes Yes Yes(3) Yes

Option bytes
2 Yes No No N/A N/A N/A

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Table 16. Access status versus protection level and execution modes (continued)
Debug/ BootFromRam/
User execution (BootFromFlash)
Area
Protection BootFromLoader(1)
level
Read Write Erase Read Write Erase

1 Yes Yes(4) N/A No No N/A

OTP
2 Yes Yes(4) N/A N/A N/A N/A

1 Yes Yes N/A No No No(5)

Backup
registers
2 Yes Yes N/A N/A N/A N/A

1 Yes Yes N/A No No No(6)

SRAM2
2 Yes Yes N/A N/A N/A N/A

1. When the protection level 2 is active, the Debug port, the boot from RAM and the boot from system memory are disabled.
2. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode.
3. The Flash main memory is erased when the RDP option byte is programmed with all level protections disabled (0xAA).
4. OTP can only be written once.
5. The backup registers are erased when RDP changes from level 1 to level 0.
6. The SRAM2 is erased when RDP changes from level 1 to level 0.

3.5.2 Proprietary code readout protection (PCROP)

Apart of the Flash memory can be protected against read and write from third parties. The
protected area is execute-only: it can only be reached by the STM32 CPU, as an instruction
code, while all other accesses (DMA, debug and CPU data read, write and erase) are
strictly prohibited. Depending of the DBANK mode, it allows either to specify one PCROP
zone per bank in Dual-bank mode or to specify two PCROP zones for all memory. An
additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not
when the RDP protection is changed from Level 1 to Level 0 (refer to Changing the Read
protection level).
Each PCROP area is defined by a start page offset and an end page offset related to the
physical Flash bank base address. These offsets are defined in the PCROP address
registers Flash PCROP1 Start address register (FLASH_PCROP1SR), Flash PCROP1 End
address register (FLASH_PCROP1ER), Flash PCROP2 Start address register
(FLASH_PCROP2SR), Flash PCROP2 End address register (FLASH_PCROP2ER).
In Single-bank mode (DBANK=0):
• The PCROPx (x = 1,2) area is defined from the address: base address +
[PCROPx_STRT x 16] (included) to the address: base address +
[(PCROPx_END+1) x 16] (excluded). The minimum PCROP area size is two 2 x
double-words (256 bits).
In Dual-bank mode (DBANK=1)
• The PCROPx (x = 1,2) area is defined from the address: bank “x” base address +
[PCROPx_STRT x 0x8] (included) to the address: bank “x” base address +
[(PCROPx_END+1) x 0x8] (excluded). The minimum PCROP area size is two double-
words (128 bits).

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For example, to protect by PCROP from the address 0x0806 2F80 (included) to the address
0x0807 0004 (included):
• if boot in Flash is done in Bank 1, FLASH_PCROP1SR and FLASH_PCROP1ER
registers must be programmed with:
– PCROP1_STRT = 0xC5F0.
– PCROP1_END = 0xE000.
• If the two banks are swapped, the protection must apply to bank 2, and
FLASH_PCROP2SR and FLASH_PCROP2ER register must be programmed with:
– PCROP2_STRT = 0xC5F0.
– PCROP2_END = 0xE000.
Any read access performed through the D-bus to a PCROP protected area will trigger
RDERR flag error.
Any PCROP protected address is also write protected and any write access to one of these
addresses will trigger WRPERR.
Any PCROP area is also erase protected. Consequently, any erase to a page in this zone is
impossible (including the page containing the start address and the end address of this
zone). Moreover, a software mass erase cannot be performed if one zone is PCROP
protected.
For previous example, due to erase by page, all pages from page 0x62 to 0x70 are
protected in case of page erase. (All addresses from 0x0806 2000 to 0x080 70FFF cannot
be erased).
Deactivation of PCROP can only occurs when the RDP is changing from level 1 to level 0. If
the user options modification tries to clear PCROP or to decrease the PCROP area, the
options programming is launched but PCROP area stays unchanged. On the contrary, it is
possible to increase the PCROP area.
When option bit PCROP_RDP is cleared, when the RDP is changing from level 1 to level 0,
Full Mass Erase is replaced by Partial Mass Erase in order to keep the PCROP area (refer
to Changing the Read protection level). In this case, PCROP1/2_STRT and
PCROP1/2_END are also not erased.
Note: It is recommended to align PCROP area with page granularity when using PCROP_RDP, or
to leave free the rest of the page where PCROP zone starts or ends.

Table 17. PCROP protection(1)

PCROPx registers values
PCROP protection area
(x = 1,2)

PCROPx_offset_strt >
No PCROP area.
PCROPx_offset_end
The area between PCROPx_offset_strt and
PCROPx_offset_end is
PCROPx_offset_strt < protected.
PCROPx_offset_end It is possible to write:
– PCROPx_offset_strt with a lower value
– PCROPx_offset_end with a higher value.

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1. When DBANK=1, the minimum PCROP area size is 2xdouble words: PCROPx_offset_strt and
PCROPx_offset_end.
When DBANK=0, the minimum PCROP area size is 2x(2xdouble words): PCROPx_offset_strt and
PCROPx_offset_end.
When DBANK=1, it is the user’s responsibility to make sure no overlapping occurs on the PCROP zones.

3.5.3 Write protection (WRP)

The user area in Flash memory can be protected against unwanted write operations.
Depending on the DBANK option bit configuration, it allows either to specify:
• In Single-bank mode (DBANK=0): four write-protected (WRP) areas can be defined in
each bank, with page size (8 KByte) granularity.
• In Dual-bank mode (DBANK=1): two write-protected (WRP) areas can be defined in
each bank, with page (4 KByte) granularity.
Each area is defined by a start page offset and an end page offset related to the physical
Flash bank base address. These offsets are defined in the WRP address registers: Flash
WRP1 area A address register (FLASH_WRP1AR), Flash WRP1 area B address register
(FLASH_WRP1BR), Flash WRP2 area A address register (FLASH_WRP2AR), Flash
WRP2 area B address register (FLASH_WRP2BR).

Dual-bank mode (DBANK=1)

The bank “x” WRP “y” area (x=1,2 and y=A,B) is defined from the address: Bank “x” Base
address + [WRPxy_STRT x 0x1000] (included) to the address: Bank “x” Base address +
[(WRPxy_END+1) x 0x1000] (excluded).

Single-bank mode (DBANK=0)

The WRPx “y” area (x=1,2 and y=A,B) is defined from the address: Base address +
[WRPy_STRT x 0x2000] (included) to the address: Base address + [(WRPy_END+1) x
0x2000] (excluded).
For example, to protect by WRP from the address 0x0806 2800 (included) to the address
0x0807 07FF (included):
• If boot in Flash is done in Bank 1, FLASH_WRP1AR register must be programmed
with:
– WRP1A_STRT = 0x62.
– WRP1A_END = 0x70.
WRP1B_STRT and WRP1B_END in FLASH_WRP1BR can be used instead (area “B”
in Bank 1).
• If the two banks are swapped, the protection must apply to bank 2, and
FLASH_WRP2AR register must be programmed with:
– WRP2A_STRT = 0x62.
– WRP2A_END = 0x70.
– WRP2A_STRT = 0xC5.
– WRP2A_END = 0xE0.
WRP2B_STRT and WRP2B_END in FLASH_WRP2BR can be used instead (area “B
in Bank 2).

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When WRP is active, it cannot be erased or programmed. Consequently, a software mass

erase cannot be performed if one area is write-protected.
If an erase/program operation to a write-protected part of the Flash memory is attempted,
the write protection error flag (WRPERR) is set in the FLASH_SR register. This flag is also
set for any write access to:
– OTP area part of the Flash memory that can never be written like the ICP
– PCROP area.
Note: When the memory read protection level is selected (RDP level = 1), it is not possible to
program or erase Flash memory if the CPU debug features are connected (JTAG or single
wire) or boot code is being executed from RAM or System Flash, even if WRP is not
activated.
Note: To validate the WRP options, the option bytes must be reloaded through the OBL_LAUNCH
bit in Flash control register.
Note: When DBANK=0, it is the user’s responsibility to make sure that no overlapping occurs on
the WRP zone.

Table 18. WRP protection

WRP registers values
WRP protection area
(x=1/2 y= A/B)

WRPxy_STRT =
Page WRPxy is protected.
WRPxy_END
WRPxy_STRT >
No WRP area.
WRPxy_END
WRPxy_STRT < – The pages from WRPxy_STRT to WRPxy_END are
WRPxy_END protected.

3.6 FLASH interrupts

Table 19. Flash interrupt request
Event flag/interrupt Interrupt enable control
Interrupt event Event flag
clearing method bit

End of operation EOP(1) Write EOP=1 EOPIE

(2)
Operation error OPERR Write OPERR=1 ERRIE
Read error RDERR Write RDERR=1 RDERRIE
ECC correction ECCC Write ECCC=1 ECCCIE
1. EOP is set only if EOPIE is set.
2. OPERR is set only if ERRIE is set.

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3.7 FLASH registers

3.7.1 Flash access control register (FLASH_ACR)

Address offset: 0x00
Reset value: 0x0000 0600
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLEEP RUN_ PRFTE
Res. DCRST ICRST DCEN ICEN Res. Res. Res. Res. LATENCY [3:0
_PD PD N
rw rw rw rw rw rw rw rw rw rw rw

--

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 SLEEP_PD: Flash Power-down mode during Sleep or Low-power sleep mode
This bit determines whether the Flash memory is in Power-down mode or idle
mode when the device is in Sleep or Low-power sleep mode.
0: Flash in idle mode during Sleep and Low-power sleep modes
1: Flash in Power-down mode during Sleep and Low-power sleep modes
Caution: The Flash must not be put in power-down while a program or an erase
operation is on-going.
Bit 13 RUN_PD: Flash Power-down mode during Run or Low-power run mode
This bit is write-protected with FLASH_PDKEYR.
This bit determines whether the Flash memory is in Power-down mode or idle
mode when the device is in Run or Low-power run mode. The Flash memory can
be put in Power-down mode only when the code is executed from RAM. The
Flash must not be accessed when RUN_PD is set.
0: Flash in idle mode
1: Flash in Power-down mode
Caution: The Flash must not be put in power-down while a program or an erase
operation is on-going.
Bit 12 DCRST: Data cache reset
0: Data cache is not reset
1: Data cache is reset
This bit can be written only when the data cache is disabled.
Bit 11 ICRST: Instruction cache reset
0: Instruction cache is not reset
1: Instruction cache is reset
This bit can be written only when the instruction cache is disabled.
Bit 10 DCEN: Data cache enable
0: Data cache is disabled
1: Data cache is enabled

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Bit 9 ICEN: Instruction cache enable

0: Instruction cache is disabled
1: Instruction cache is enabled
Bit 8 PRFTEN: Prefetch enable
0: Prefetch disabled
1: Prefetch enabled
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 LATENCY[:0]: Latency
These bits represent the ratio of the SYSCLK (system clock) period to the Flash
access time.
0000: Zero wait state
0001: One wait state
0010: Two wait states
0011: Three wait states
0100: Four wait states
...1111: Fifteen wait states

3.7.2 Flash Power-down key register (FLASH_PDKEYR)

Address offset: 0x04
Reset value: 0x0000 0000
Access: no wait state, word access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PDKEYR[31:16]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PDKEYR[15:0]
w w w w w w w w w w w w w w w w

Bits 31:0 PDKEYR: Power-down in Run mode Flash key

The following values must be written consecutively to unlock the RUN_PD bit in
FLASH_ACR:
PDKEY1: 0x0415 2637
PDKEY2: 0xFAFB FCFD

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3.7.3 Flash key register (FLASH_KEYR)

Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait state, word access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEYR[31:16]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEYR[15:0]
w w w w w w w w w w w w w w w w

Bits 31:0 KEYR: Flash key

The following values must be written consecutively to unlock the FLACH_CR
register allowing Flash programming/erasing operations:
KEY1: 0x4567 0123
KEY2: 0xCDEF 89AB

3.7.4 Flash option key register (FLASH_OPTKEYR)

Address offset: 0x0C
Reset value: 0x0000 0000
Access: no wait state, word access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPTKEYR[31:16]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTKEYR[15:0]
w w w w w w w w w w w w w w w w

Bits 31:0 OPTKEYR: Option byte key

The following values must be written consecutively to unlock the FLACH_OPTR
register allowing option byte programming/erasing operations:
KEY1: 0x0819 2A3B
KEY2: 0x4C5D 6E7F

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3.7.5 Flash status register (FLASH_SR)

Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PEMPT
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BSY
Y
rc_w1 r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTV RD FAST MISS PGS SIZ PGA WRP PROG OP
Res. Res. Res. Res. Res. EOP
ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 PEMPTY: Program EMPTY
Set by hardware on power-on reset or after OBL_LAUNCH command execution
if the Flash is not programmed and the user intends to boot from the main Flash.
Cleared by hardware on power-on reset or after OBL_LAUNCH command
execution if the Flash is programmed and the user intends to boot from main
Flash. This bit can also be set and cleared by software.
1: The bit value is toggling
0: No effect
This bit can be set to clear the Program Empty bit if an OBL_LAUNCH is done by
software after Flash programming (boot in main Flash selected). It finally forces
the boot in the main Flash, without loosing the debugger connection.
Bit 16 BSY: Busy
This indicates that a Flash operation is in progress. This is set on the beginning
of a Flash operation and reset when the operation finishes or when an error
occurs.
Bit 15 OPTVERR: Option validity error
Set by hardware when the options read may not be the one configured by the
user. If option haven’t been properly loaded, OPTVERR is set again after each
system reset.
Cleared by writing 1.
Bit 14 RDERR: PCROP read error
Set by hardware when an address to be read through the D-bus belongs to a
read protected area of the Flash (PCROP protection). An interrupt is generated if
RDERRIE is set in FLASH_CR.
Cleared by writing 1.
Bits 13:10 Reserved, must be kept at reset value.
Bit 9 FASTERR: Fast programming error
Set by hardware when a fast programming sequence (activated by FSTPG) is
interrupted due to an error (alignment, size, write protection or data miss). The
corresponding status bit (PGAERR, SIZERR, WRPERR or MISSERR) is set at
the same time.
Cleared by writing 1.

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Bit 8 MISERR: Fast programming data miss error

In fast programming mode, 32 double words must be sent to Flash successively,
and the new data must be sent to the Flash logic control before the current data
is fully programmed. MISSERR is set by hardware when the new data is not
present in time.
Cleared by writing 1.
Bit 7 PGSERR: Programming sequence error
Set by hardware when a write access to the Flash memory is performed by the
code while PG or FSTPG have not been set previously. Set also by hardware
when PROGERR, SIZERR, PGAERR, WRPERR, MISSERR or FASTERR is set
due to a previous programming error.
Set also when trying to perform bank erase when DBANK=0.
Cleared by writing 1.
Bit 6 SIZERR: Size error
Set by hardware when the size of the access is a byte or half-word during a
program or a fast program sequence. Only double word programming is allowed
(consequently: word access).
Cleared by writing 1.
Bit 5 PGAERR: Programming alignment error
Set by hardware when the data to program cannot be contained in the same 64-
bit Flash memory row in case of standard programming, or if there is a change of
page during fast programming.
Cleared by writing 1.
Bit 4 WRPERR: Write protection error
Set by hardware when an address to be erased/programmed belongs to a write-
protected part (by WRP, PCROP or RDP level 1) of the Flash memory.
Cleared by writing 1.
Bit 3 PROGERR: Programming error
Set by hardware when a double-word address to be programmed contains a
value different from '0xFFFF FFFF' before programming, except if the data to
write is '0x0000 0000'.
Cleared by writing 1.
Bit 2 Reserved, must be kept at reset value.
Bit 1 OPERR: Operation error
Set by hardware when a Flash memory operation (program / erase) completes
unsuccessfully.
This bit is set only if error interrupts are enabled (ERRIE = 1).
Cleared by writing ‘1’.
Bit 0 EOP: End of operation
Set by hardware when one or more Flash memory operation (programming /
erase) has been completed successfully.
This bit is set only if the end of operation interrupts are enabled (EOPIE = 1).
Cleared by writing 1.

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3.7.6 Flash control register (FLASH_CR)

Address offset: 0x14
Reset value: 0xC000 0000
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPT OBL_ RD ERR EOP OPT
LOCK Res. Res. Res. Res. Res. Res. Res. FSTPG STRT
LOCK LAUNCH ERRIE IE IE STRT
rs rs rc_w1 rw rw rw rw rs rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MER2 Res. Res. Res. BKER PNB[7:0] MER1 PER PG
rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 LOCK: FLASH_CR Lock

This bit is set only. When set, the FLASH_CR register is locked. It is cleared by
hardware after detecting the unlock sequence.
In case of an unsuccessful unlock operation, this bit remains set until the next
system reset.
Bit 30 OPTLOCK: Options Lock
This bit is set only. When set, all bits concerning user option in FLASH_CR
register and so option page are locked. This bit is cleared by hardware after
detecting the unlock sequence. The LOCK bit must be cleared before doing the
unlock sequence for OPTLOCK bit.
In case of an unsuccessful unlock operation, this bit remains set until the next
reset.
Bits 29:28 Reserved, must be kept at reset value.
Bit 27 OBL_LAUNCH: Force the option byte loading
When set to 1, this bit forces the option byte reloading. This bit is cleared only
when the option byte loading is complete. It cannot be written if OPTLOCK is set.
0: Option byte loading complete
1: Option byte loading requested
Bit 26 RDERRIE: PCROP read error interrupt enable
This bit enables the interrupt generation when the RDERR bit in the FLASH_SR
is set to 1.
0: PCROP read error interrupt disabled
1: PCROP read error interrupt enabled
Bit 25 ERRIE: Error interrupt enable
This bit enables the interrupt generation when the OPERR bit in the FLASH_SR
is set to 1.
0: OPERR error interrupt disabled
1: OPERR error interrupt enabled
Bit 24 EOPIE: End of operation interrupt enable
This bit enables the interrupt generation when the EOP bit in the FLASH_SR is
set to 1.
0: EOP Interrupt disabled
1: EOP Interrupt enabled

RM0432 Rev 6 155/2301

168
Embedded Flash memory (FLASH) RM0432

Bits 23:19 Reserved, must be kept at reset value

Bit 18 FSTPG: Fast programming
0: Fast programming disabled
1: Fast programming enabled
Bit 17 OPTSTRT: Options modification start
This bit triggers an options operation when set.
This bit is set only by software, and is cleared when the BSY bit is cleared in
FLASH_SR.
Bit 16 START: Start
This bit triggers an erase operation when set. If MER1, MER2 and PER bits are
reset and the STRT bit is set, an unpredictable behavior may occur without
generating any error flag. This condition should be forbidden.
This bit is set only by software, and is cleared when the BSY bit is cleared in
FLASH_SR.
Bit 15 MER2: Bank 2 Mass erase
This bit triggers the bank 2 mass erase (all bank 2 user pages) when set.
Bits 14:12 Reserved, must be kept at reset value.
Bit 11 BKER: Bank erase
DBANK=1
0: Bank 1 is selected for page erase
1: Bank 2 is selected for page erase
DBANK=0
Reserved, must be kept cleared
Bits 10:3 PNB[7:0]: Page number selection
These bits select the page to erase:
00000000:page 0
00000001:page 1
...
11111111:page 255

Bit 2 MER1: Bank 1 Mass erase

This bit triggers the bank 1 mass erase (all bank 1 user pages) when set.
Bit 1 PER: Page erase
0: page erase disabled
1: page erase enabled
Bit 0 PG: Programming
0: Flash programming disabled
1: Flash programming enabled

156/2301 RM0432 Rev 6

RM0432 Embedded Flash memory (FLASH)

3.7.7 Flash ECC register (FLASH_ECCR)

Address offset: 0x18
Reset value: 0x0000 0000
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCD ECCC SYSF_ BK
ECCD ECCC ECCD2 Res. Res. Res. Res. ADDR_ECC[20:16]
2 IE ECC _ECC
rc_w1 rc_w1 rc_w1 rc_w1 rw r r r r r r r

ADDR_ECC[15:0]
r r r r r r r r r r r r r r r r

Bit 31 ECCD: ECC detection

DBANK=0
Set by hardware when two ECC errors have been detected (only if
ECCC/ECCC2/ECCD/ ECCD2 are previously cleared). When this bit is set, a
NMI is generated.
Cleared by writing 1.
DBANK=1
Set by hardware when two ECC errors have been detected on 64-bits LSB (bits
63:0) (only if ECCC/ECCC2/ECCD/ ECCD2 are previously cleared). When this
bit is set, a NMI is generated.
Cleared by writing 1.
Bit 30 ECCC: ECC correction
Set by hardware when one ECC error has been detected and corrected (only if
ECCC/ECCC2/ECCD/ECCD2 are previously cleared). An interrupt is generated
if ECCIE is set.
Cleared by writing 1.
Bit 29 ECCD2: ECC2 detection
DBANK=0
Set by hardware when two ECC errors have been detected on 64-bits MSB
(bits127:64). This bit is set (only if ECCC/ECCC2/ECCD/ECCD2 are previously
cleared). When this bit is set, a NMI is generated.
Cleared by writing 1.
DBANK=1
Reserved, must be kept at reset value.
Bit 28 ECCC2: ECC correction
DBANK=0
Set by hardware when one ECC error has been detected and corrected on 64-
bits MSB (bits127:64). This bit is set (only if ECCC/ECCC2/ECCD/ECCD2 are
previously cleared). An interrupt is generated if ECCIE is set.
Cleared by writing 1.
DBANK=1
Reserved, must be kept at reset value.
Bits 27:25 Reserved, must be kept at reset value.

RM0432 Rev 6 157/2301

168
Embedded Flash memory (FLASH) RM0432

Bit 24 ECCIE: ECC correction interrupt enable

0: ECCC interrupt disabled
1: ECCC interrupt enabled.
DBANK=0
This bit enables the interrupt generation when the ECCC or ECCC2 bits in the
FLASH_ECCR register are set.
DBANK=1
This bit enables the interrupt generation when the ECCC bit in the FLASH_ECCR
register is set.
Bit 23 Reserved, must be kept at reset value.
Bit 22 SYSF_ECC: System Flash ECC fail
This bit indicates that the ECC error correction or double ECC error detection is
located in the System Flash.
Bit 21 BK_ECC: ECC fail bank
DBANK=1
This bit indicates which bank is concerned by the ECC error correction or by the
double ECC error detection.
0: bank 1
1: bank 2
DBANK=0
If SYSF_ECC is 1, it indicates which bank is concerned by the ECC error
If SYSF_ECC is 0, reserved, must be kept cleared.
Bit 19 BK_ECC: ECC fail bank
This bit indicates which bank is concerned by the ECC error correction or by the
double ECC error detection.
0: bank 1
1: bank 2
Bits 20:0 ADDR_ECC: ECC fail address
DBANK=0
This bit indicates which address in the Flash memory is concerned by the ECC
error correction or by the double ECC error detection.
DBANK=1
This bit indicates which address in the bank is concerned by the ECC error
correction or by the double ECC error detection.

158/2301 RM0432 Rev 6

RM0432 Embedded Flash memory (FLASH)

3.7.8 Flash option register (FLASH_OPTR)

Address offset: 0x20
Reset value: 0xFFEF F8AA. Register bits are loaded with values from Flash memory at
OBL.
Access: no wait state when no Flash memory operation is on going; word, half-word and
byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
n nSW SRAM2 SRAM2 nBOOT WWDG IWGD_ IWDG_ IWDG_
Res. Res. Res. Res. DBANK DB1M BFB2
BOOT0 BOOT0 _RST _PE 1 _SW STDBY StOP SW
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
nRST_ nRST_ nRST_
Res. Res. BOR_LEV[2:0] RDP[7:0]
SHDW STDBY STOP
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 nBOOT0: nBOOT0 option bit
0: nBOOT0 = 0
1: nBOOT0 = 1
Bit 26 nSWBOOT0: Software BOOT0
0: BOOT0 taken from the option bit nBOOT0
1: BOOT0 taken from PH3/BOOT0 pin
Bit 25 SRAM2_RST: SRAM2 Erase when system reset
0: SRAM2 erased when a system reset occurs
1: SRAM2 is not erased when a system reset occurs
Bit 24 SRAM2_PE: SRAM2 parity check enable
0: SRAM2 parity check enable
1: SRAM2 parity check disable
Bit 23 nBOOT1: Boot configuration
Together with the BOOT0 pin, this bit selects boot mode from the Flash main
memory, SRAM1 or the System memory. Refer to Section 2.6: Boot
configuration.
Bit 22 DBANK:
0: Single-bank mode with 128 bits data read width
1: Dual-bank mode with 64 bits data
This bit can only be written when PCROPA/B is disabled.

RM0432 Rev 6 159/2301

168
Embedded Flash memory (FLASH) RM0432

Bit 21 DB1M:
For STM32L4Rxxx and STM32L4Sxxx devices:
Dual-bank on 1 Mbyte Flash memory devices
0: 1 Mbyte single Flash contiguous address in Bank 1
1: 1 Mbyte dual-bank Flash with contiguous addresses
When DB1M is set, a hard fault is generated when the requested address goes
over 1 Mbyte.
For STM32L4P5xx and STM32L4Q5xx devices:
Dual-bank on 512 Kbytes Flash memory devices
0: 512 Kbytes single Flash contiguous address in bank1
1: 512 Kbytes dual-bank Flash with contiguous addresses
When DB1M is set, a hard fault is generated when the requested address goes
over 512 Kbytes.
Bit 20 BFB2: Dual-bank boot
0: Dual-bank boot disable
1: Dual-bank boot enable
Bit 19 WWDG_SW: Window watchdog selection
0: Hardware window watchdog
1: Software window watchdog
Bit 18 IWDG_STDBY: Independent watchdog counter freeze in Standby mode
0: Independent watchdog counter is frozen in Standby mode
1: Independent watchdog counter is running in Standby mode
Bit 17 IWDG_STOP: Independent watchdog counter freeze in Stop mode
0: Independent watchdog counter is frozen in Stop mode
1: Independent watchdog counter is running in Stop mode
Bit 16 IDWG_SW: Independent watchdog selection
0: Hardware independent watchdog
1: Software independent watchdog
Bit 15 Reserved, must be kept cleared
Bit 14 nRST_SHDW
0: Reset generated when entering the Shutdown mode
1: No reset generated when entering the Shutdown mode
Bit 13 nRST_STDBY
0: Reset generated when entering the Standby mode
1: No reset generate when entering the Standby mode
Bit 12 nRST_STOP
0: Reset generated when entering the Stop mode
1: No reset generated when entering the Stop mode

160/2301 RM0432 Rev 6

RM0432 Embedded Flash memory (FLASH)

Bit 11 Reserved, must be kept cleared

Bits10:8 BOR_LEV: BOR reset Level
These bits contain the VDD supply level threshold that activates/releases the
reset.
000: BOR Level 0. Reset level threshold is around 1.7 V
001: BOR Level 1. Reset level threshold is around 2.0 V
010: BOR Level 2. Reset level threshold is around 2.2 V
011: BOR Level 3. Reset level threshold is around 2.5 V
100: BOR Level 4. Reset level threshold is around 2.8 V
Bits 7:0 RDP: Read protection level
0xAA: Level 0, read protection not active
0xCC: Level 2, chip read protection active
Others: Level 1, memories read protection active
Note: Take care about PCROP_RDP configuration in Level 1. Refer to Section :
Level 1: Read protection for more details.

3.7.9 Flash PCROP1 Start address register (FLASH_PCROP1SR)

Address offset: 0x24
Reset value: 0xFFFF FFFF. Register bits are loaded with values from Flash memory at
OBL.
Access: no wait state when no Flash memory operation is on going; word access.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCROP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1_STRT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP1_STRT[16:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:17 Reserved, must be kept

Bits 16:0 PCROP1_STRT: PCROP area start offset
DBANK=1
PCROP1_STRT contains the first double-word of the PCROP area for bank1.
DBANK=0
PCROP1_STRT contains the first 2xdouble-word of the PCROP area for all
memory.

RM0432 Rev 6 161/2301

168
Embedded Flash memory (FLASH) RM0432

3.7.10 Flash PCROP1 End address register (FLASH_PCROP1ER)

Address offset: 0x28
Reset value: 0xXFFX XXXX. Register bits are loaded with values from Flash memory at
OBL.
Access: no wait state when no Flash memory operation is on going; word, half-word access.
PCROP_RDP bit can be accessed with byte access.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCRO
PCROP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. P1_EN
_RDP
D
rs rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP1_END[16:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 PCROP_RDP: PCROP area preserved when RDP level decreased

This bit is set only. It is reset after a full mass erase due to a change of RDP
from Level 1 to Level 0.
0: PCROP area is not erased when the RDP level is decreased from Level 1 to
Level 0.
1: PCROP area is erased when the RDP level is decreased from Level 1 to
Level 0 (full mass erase).
Bits 30:17 Reserved, must be kept cleared
Bits 16:0 PCROP1_END: Bank 1 PCROP area end offset
DBANK=1
PCROP1_END contains the last double-word of the bank 1 PCROP area.
DBANK=0
PCROP1_END contains the last 2x double-word PCROP area for all memory.

3.7.11 Flash WRP1 area A address register (FLASH_WRP1AR)

Address offset: 0x2C
Reset value: 0xFFXX FFXX. Register bits are loaded with values from Flash memory at
OBL.
Access: no wait state when no Flash memory operation is on going; word, half-word and
byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. WRP1A_END[7:0]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. WRP1A_STRT[7:0]
rw rw rw rw rw rw rw rw

162/2301 RM0432 Rev 6

RM0432 Embedded Flash memory (FLASH)

Bits 31:24 Reserved, must be kept cleared

Bits 23:16 WRP1A_END: WRP first area “A” end offset
DBANK=1
WRP1A_END contains the last page of WRP first area in bank1.
DBANK=0
WRP1A_END contains the last page of WRP first area for all memory.
Bits 15:8 Reserved, must be kept cleared
Bits 7:0 WRP1A_STRT: WRP first area “A” start offset
DBANK=1
WRP1A_STRT contains the first page of WRP first area for bank1.
DBANK=0
WRP1A_STRT contains the first page of WRP first area for all memory.

3.7.12 Flash WRP2 area A address register (FLASH_WRP2AR)

Address offset: 0x30
Reset value: 0xFFXX FFXX
Access: no wait state when no Flash memory operation is on going; word, half-word and
byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. WRP2A_END[7:0]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. WRP2A_STRT[7:0]
rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept cleared

Bits 23:16 WRP2A_END: WRP first area “A” end offset
DBANK=1
WRP2A_END contains the last page of the WRP first area for bank2.
DBANK=0
WRP2A_END contains the last page of the WRP third area for all memory.
Bits 15:8 Reserved, must be kept cleared
Bits 7:0 WRP2A_STRT: WRP first area “A” start offset
DBANK=1
WRP2A_STRT contains the first page of the WRP first area for bank2.
DBANK=0
WRP2A_STRT contains the first page of the WRP third area for all memory.

RM0432 Rev 6 163/2301

168
Embedded Flash memory (FLASH) RM0432

3.7.13 Flash PCROP2 Start address register (FLASH_PCROP2SR)

Address offset: 0x44
Reset value: 0xFFFF FFFF
Access: no wait state when no Flash memory operation is on going; word access.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCRO
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. P2_ST
RT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP2_STRT[16:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:17 Reserved, must be kept cleared

Bits 16:0 PCROP2_STRT: PCROP area start offset
DBANK=1
PCROP2_STRT contains the first double-word of the PCROP area for bank 2.
DBANK=0
PCROP2_STRT contains the first double-word PCROP area for all memory.

3.7.14 Flash PCROP2 End address register (FLASH_PCROP2ER)

Address offset: 0x48
Reset value: 0xXFFX XXXX
Access: no wait state when no Flash memory operation is on going; word access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCRO
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. P2_EN
D
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP2_END[16:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:17 Reserved, must be kept cleared

Bits 23:16 PCROP2_END: PCROP area end offset
DBANK=1
PCROP2_END contains the last double-word of the PCROP area for bank2.
DBANK=0
PCROP2_END contains the last 2xdouble-word of the PCROP area for all the
memory.

164/2301 RM0432 Rev 6

RM0432 Embedded Flash memory (FLASH)

3.7.15 Flash WRP1 area B address register (FLASH_WRP1BR)

Address offset: 0x4C
Reset value: 0xFFXX FFXX. Register bits are loaded with values from Flash memory at
OBL.
Access: no wait state when no Flash memory operation is on going; word, half-word and
byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. WRP1B_END[7:0]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. WRP1B_STRT[7:0]
rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept cleared

Bits 23:16 WRP1B_END: WRP second area “B” end offset
DBANK=1
WRP1B_END contains the last page of the WRP second area for bank1.
DBANK=0
WRP1B_END contains the last page of the WPR second area for all memory.
Bits 15:8 Reserved, must be kept cleared
Bits 7:0 WRP1B_STRT: WRP second area “B” start offset
DBANK=1
WRP1B_STRT contains the last page of the WRP second area for bank1.
DBANK=0
WRP1B_STRT contains the last page of the WPR second area for all memory.

3.7.16 Flash WRP2 area B address register (FLASH_WRP2BR)

Address offset: 0x50
Reset value: 0xFFXX FFXX
Access: no wait state when no Flash memory operation is on going; word, half-word and
byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. WRP2B_END[7:0]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. WRP2B_STRT[7:0]
rw rw rw rw rw rw rw rw

RM0432 Rev 6 165/2301

168
Embedded Flash memory (FLASH) RM0432

Bits 31:24 Reserved, must be kept cleared

Bits 23:16 WRP2B_END: WRP second area “B” end offset
DBANK=1
WRP2B_END contains the last page of the WRP second area for bank2.
DBANK=0
WRP2B_END contains the last page of the WRP fourth area for all memory.
Bits 15:8 Reserved, must be kept cleared
Bits 23:16 WRP2B_STRT: WRP second area “B” start offset
DBANK=1
WRP2B_STRT contains the first page of the WRP second area for bank2.
DBANK=0
WRP2B_STRT contains the first page of the WRP second area for all memory.

3.7.17 Flash configuration register (FLASH_CFGR)

Address offset: 0x130
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LVEN
rw

Bits 31:1 Reserved, must be kept cleared

Bit 0 LVEN: Low voltage enable
This bit is set and cleared by software. This bit must be used only in case of
external SMPS.
0: Flash low voltage disable
1: Flash low voltage enabled. Before setting this bit, it is recommended to:
- Switch the voltage scaling to range 2
- Ensure that the minimum VDD12 is 1.08 V
- When the external SMPS is ON, the LVEN bit can be set.

166/2301 RM0432 Rev 6

RM0432 Embedded Flash memory (FLASH)

3.7.18 FLASH register map

Table 20. Flash interface - register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
SLEEP_PD
RUN_PD

PRFTEN
DCRST
ICRST
DCEN
ICEN
LATENCY
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
FLASH_ACR
0x00 [3:0]

Reset value 0 0 0 0 1 1 0 0 0 0 0

FLASH_
PDKEYR[31:0]
PDKEYR
0x04
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLASH_KEYR KEYR[31:0]
0x08
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLASH_OPT
OPTKEYR[31:0]
KEYR
0x0C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PROGERR
OPTVERR

FASTERR

WRPERR
PGSERR

PGAERR
PEMPTY

MISERR

SIZERR
RDERR

OPERR
EOP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.

Res.
FLASH_SR BSY
0x10

Reset value X 0 0 0 0 0 0 0 0 0 0 0 0
OBL_LAUNCH
OPTLOCK

OPTSTRT
RDERRIE

FSTPG
ERRIE
EOPIE

MER2

MER1
LOCK

BKER
STRT
Res.
Res.

Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.

PER
PG
FLASH_CR PNB[7:0]
0x14

Reset value 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SYSF_ECC
BK_ECC
ECCCIE
ECCD2
ECCC2
ECCD
ECCC

Res.
Res.
Res.

Res.

FLASH_ECCR ADDR_ECC[20:0]
0x18

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
nRST_SHDW
SRAM2_RST

IWDG_STOP
IWDG_STBY

nRST_STOP
nRST_STDB
WWDG_SW
nSWBOOT0

SRAM2_PE

IWDG_SW
.nBOOT0

nBOOT1
DBANK
DB1M
BFB2

BOR_
Res.
Res.
Res.
Res.

Res.

Res.

FLASH_OPTR RDP[7:0]
LEV[2:0]
0x20

Reset value X X X X X X X X X X X X X X X X X X X X X X X X X X

FLASH_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

PCROP1_STRT[16:0]
PCROP1SR
0x24
Reset value 1 X X X X X X X X X X X X X X X X
PCROP_RDP.

FLASH_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

PCROP1_END[16:0]
PCROP1ER
0x28

Reset value x 0 X X X X X X X X X X X X X X X X

FLASH_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

WRP1A_END[7:0] WRP1A_STRT[7:0]
WRP1AR
0x2C
Reset value X X X X X X X X X X X X X X X X

RM0432 Rev 6 167/2301

168
Embedded Flash memory (FLASH) RM0432

Table 20. Flash interface - register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
FLASH_

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WRP2A_END[7:0] WRP2A_STRT[7:0]
WRP2AR
0x30
Reset value X X X X X X X X X X X X X X X X

FLASH_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PCROP2_STRT[16:0]
PCROP2SR
0x44
Reset value 1 X X X X X X X X X X X X X X X X

FLASH_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PCROP2_END[16:0]
PCROP2ER
0x48
Reset value 0 X X X X X X X X X X X X X X X X

FLASH_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WRP1B_END[7:0] WRP1B_STRT[7:0]
WRP1BR
0x4C
Reset value X X X X X X X X X X X X X X X X

FLASH_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WRP2B_END[7:0] WRP2B_STRT[7:0]
WRP2BR
0x50
Reset value X X X X X X X X X X X X X X X X

LVEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FLASH_CFGR
0x130
Reset value 0

Refer to Section 2.2 on page 91 for the register boundary addresses.

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RM0432 Firewall (FW)

4 Firewall (FW)

4.1 Introduction
The Firewall is made to protect a specific part of code or data into the Non-Volatile Memory,
and/or to protect the Volatile data into the SRAM1 from the rest of the code executed
outside the protected area.

4.2 Firewall main features

• The code to protect by the Firewall (Code Segment) may be located in:
– The Flash memory map
– The SRAM1 memory, if declared as an executable protected area during the
Firewall configuration step.
• The data to protect can be located either
– in the Flash memory (non-volatile data segment)
– in the SRAM1 memory (volatile data segment)
The software can access these protected areas once the Firewall is opened. The Firewall
can be opened or closed using a mechanism based on “call gate” (Refer to Opening the
Firewall).
The start address of each segment and its respective length must be configured before
enabling the Firewall (Refer to Section 4.3.5: Firewall initialization).
Each illegal access into these protected segments (if the Firewall is enabled) generates a
reset which immediately kills the detected intrusion.
Any DMA access to protected segments is forbidden whatever the Firewall state (opened or
closed). It is considered as an illegal access and generates a reset.

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4.3 Firewall functional description

4.3.1 Firewall AMBA bus snoop

The Firewall peripheral is snooping the AMBA buses on which the memories (volatile and
non-volatile) are connected. A global architecture view is illustrated in Figure 7.

Figure 7. STM32L4+ Series firewall connection schematics

I
N
AHB Slave T
AHB Master 1 E
CORTEX M4 R FLASH
F
A
B C
U E
S

AHB Master 2 M FIREWALL

DMA A
T
R
I
X
SRAM 1
AHB Slave

MsV43402V1

4.3.2 Functional requirements

There are several requirements to guaranty the highest security level by the application
code/data which needs to be protected by the Firewall and to avoid unwanted Firewall alarm
(reset generation).

Debug consideration
In debug mode, if the Firewall is opened, the accesses by the debugger to the protected
segments are not blocked. For this reason, the Read out level 2 protection must be active in
conjunction with the Firewall implementation.
If the debug is needed, it is possible to proceed in the following way:
• A dummy code having the same API as the protected code may be developed during
the development phase of the final user code. This dummy code may send back
coherent answers (in terms of function and potentially timing if needed), as the
protected code should do in production phase.
• In the development phase, the protected code can be given to the customer-end under
NDA agreement and its software can be developed in level 0 protection. The customer-

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RM0432 Firewall (FW)

end code needs to embed an IAP located in a write protected segment in order to allow
future code updates when the production parts will be Level 2 ROP.

Write protection
In order to offer a maximum security level, the following points need to be respected:
• It is mandatory to keep a write protection on the part of the code enabling the Firewall.
This activation code should be located outside the segments protected by the Firewall.
• The write protection is also mandatory on the code segment protected by the Firewall.
• The page including the reset vector must be write-protected.

Interrupts management
The code protected by the Firewall must not be interruptible. It is up to the user code to
disable any interrupt source before executing the code protected by the Firewall. If this
constraint is not respected, if an interrupt comes while the protected code is executed
(Firewall opened), the Firewall will be closed as soon as the interrupt subroutine is
executed. When the code returns back to the protected code area, a Firewall alarm will raise
since the “call gate” sequence will not be applied and a reset will be generated.
Concerning the interrupt vectors and the first user page in the Flash memory:
• If the first user page (including the reset vector) is protected by the Firewall, the NVIC
vector should be reprogrammed outside the protected segment.
• If the first user page is not protected by the Firewall, the interrupt vectors may be kept
at this location.
There is no interrupt generated by the Firewall.

4.3.3 Firewall segments

The Firewall has been designed to protect three different segment areas:

Code segment
This segment is located into the Flash memory. It should contain the code to execute which
requires the Firewall protection. The segment must be reached using the “call gate” entry
sequence to open the Firewall. A system reset is generated if the “call gate” entry sequence
is not respected (refer to Opening the Firewall) and if the Firewall is enabled using the
FWDIS bit in the system configuration register. The length of the segment and the segment
base address must be configured before enabling the Firewall (refer to Section 4.3.5:
Firewall initialization).

Non-volatile data segment

This segment contains non-volatile data used by the protected code which must be
protected by the Firewall. The access to this segment is defined into Section 4.3.4: Segment
accesses and properties. The Firewall must be opened before accessing the data in this
area. The Non-Volatile data segment should be located into the Flash memory. The
segment length and the base address of the segment must be configured before enabling
the Firewall (refer to Section 4.3.5: Firewall initialization).

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Volatile data segment

Volatile data used by the protected code located into the code segment must be defined into
the SRAM1 memory. The access to this segment is defined into the Section 4.3.4: Segment
accesses and properties. Depending on the Volatile data segment configuration, the
Firewall must be opened or not before accessing this segment area. The segment length
and the base address of the segment as well as the segment options must be configured
before enabling the Firewall (refer to Section 4.3.5: Firewall initialization).
The Volatile data segment can also be defined as executable (for the code execution) or
shared using two bit of the Firewall configuration register (bit VDS for the volatile data
sharing option and bit VDE for the volatile data execution capability). For more details, refer
to Table 21.

4.3.4 Segment accesses and properties

All DMA accesses to the protected segments are forbidden, whatever the Firewall state, and
generate a system reset.

Segment access depending on the Firewall state

Each of the three segments has specific properties which are presented in Table 21.

Table 21. Segment accesses according to the Firewall state

Firewall opened Firewall closed Firewall disabled
Segment
access allowed access allowed access allowed

No access allowed. All accesses are allowed

Any access to the segment (according to the Flash page
Code segment Read and execute
(except the “call gate” entry) protection properties in which
generates a system reset the code is located)

All accesses are allowed

Non-volatile data (according to the Flash page
Read and write No access allowed
segment protection properties in which
the code is located)
No access allowed if VDS = 0
and VDE = 0 into the Firewall
configuration register
Read and Write
Read/write/execute accesses
Volatile data Execute if VDE = 1 and
allowed if VDS = 1 (whatever All accesses are allowed
segment VDS = 0 into the Firewall
VDE bit value)
configuration register
Execute if VDE = 1 and VDS = 0
but with a “call gate” entry to
open the Firewall at first.

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The Volatile data segment is a bit different from the two others. The segment can be:
• Shared (VDS bit in the register)
It means that the area and the data located into this segment can be shared between
the protected code and the user code executed in a non-protected area. The access is
allowed whether the Firewall is opened or closed or disabled.
The VDS bit gets priority over the VDE bit, this last bit value being ignored in such a
case. It means that the Volatile data segment can execute parts of code located there
without any need to open the Firewall before executing the code.
• Execute
The VDE bit is considered as soon as the VDS bit = 0 in the FW_CR register. If the
VDS bit = 1, refer to the description above on the Volatile data segment sharing. If VDS
= 0 and VDE = 1, the Volatile data segment is executable. To avoid a system reset
generation from the Firewall, the “call gate” sequence should be applied on the Volatile
data segment to open the Firewall as an entry point for the code execution.

Segments properties
Each segment has a specific length register to define the segment size to be protected by
the Firewall: CSL register for the Code segment length register, NVDSL for the Non-volatile
data segment length register, and VDSL register for the Volatile data segment length
register. Granularity and area ranges for each of the segments are presented in Table 22.

Table 22. Segment granularity and area ranges

Segment Granularity Area range

Code segment 256 byte 2048 Kbytes - 256 bytes

Non-volatile data segment 256 byte 2048 Kbytes - 256 bytes
Volatile data segment 64 byte 192 Kbyte - 64 bytes

4.3.5 Firewall initialization

The initialization phase should take place at the beginning of the user code execution (refer
to the Write protection).
The initialization phase consists of setting up the addresses and the lengths of each
segment which needs to be protected by the Firewall. It must be done before enabling the
Firewall, because the enabling bit can be written once. Thus, when the Firewall is enabled, it
cannot be disabled anymore until the next system reset.
Once the Firewall is enabled, the accesses to the address and length segments are no
longer possible. All write attempts are discarded.
A segment defined with a length equal to 0 is not considered as protected by the Firewall.
As a consequence, there is no reset generation from the Firewall when an access to the
base address of this segment is performed.
After a reset, the Firewall is disabled by default (FWDIS bit in the SYSCFG register is set). It
has to be cleared to enable the Firewall feature.

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Below is the initialization procedure to follow:

1. Configure the RCC to enable the clock to the Firewall module
2. Configure the RCC to enable the clock of the system configuration registers
3. Set the base address and length of each segment (CSSA, CSL, NVDSSA, NVDSL,
VDSSA, VDSL registers)
4. Set the configuration register of the Firewall (FW_CR register)
5. Enable the Firewall clearing the FWDIS bit in the system configuration register.
The Firewall configuration register (FW_CR register) is the only one which can be managed
in a dynamic way even if the Firewall is enabled:
• when the Non-Volatile data segment is undefined (meaning the NVDSL register is
equal to 0), the accesses to this register are possible whatever the Firewall state
(opened or closed).
• when the Non-Volatile data segment is defined (meaning the NVDSL register is
different from 0), the accesses to this register are only possible when the Firewall is
opened.

4.3.6 Firewall states

The Firewall has three different states as shown in Figure 8:
• Disabled: The FWDIS bit is set by default after the reset. The Firewall is not active.
• Closed: The Firewall protects the accesses to the three segments (Code, Non-volatile
data, and Volatile data segments).
• Opened: The Firewall allows access to the protected segments as defined in
Section 4.3.4: Segment accesses and properties.

Figure 8. Firewall functional states

Firewall disable
(reset)

Illegal accesses to
the protected Enable the firewall Protected code jumps
segments (FWDIS = 0) to an unprotected
segment and FPA = 0

‘‘call gate’’ entry

Firewall Firewall
closed opened

Code protected jumps

to unprotected
segments

MS32390V4

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Opening the Firewall

As soon as the Firewall is enabled, it is closed. It means that most of the accesses to the
protected segments are forbidden (refer to Section 4.3.4: Segment accesses and
properties). In order to open the Firewall to interact with the protected segments, it is
mandatory to apply the “call gate” sequence described hereafter.
“call gate” sequence
The “call gate” is composed of 3 words located on the first three 32-bit addresses of the
base address of the code segment and of the Volatile data segment if it is declared as
not shared (VDS = 0) and executable (VDE = 1).
– 1st word: Dummy 32-bit words always closed in order to protect the “call gate”
opening from an access due to a prefetch buffer.
– 2nd and 3rd words: 2 specific 32-bit words called “call gate” and always opened.
To open the Firewall, the code currently executed must jump to the 2nd word of the “call
gate” and execute the code from this point. The 2nd word and 3rd word execution must not
be interrupted by any intermediate instruction fetch; otherwise, the Firewall is not
considered open and comes back to a close state. Then, executing the 3rd word after
receiving the intermediate instruction fetch would generate a system reset as a
consequence.
As soon as the Firewall is opened, the protected segments can be accessed as described in
Section 4.3.4: Segment accesses and properties.

Closing the Firewall

The Firewall is closed immediately after it is enabled (clearing the FWDIS bit in the system
configuration register).
To close the Firewall, the protected code must:
• Write the correct value in the Firewall Pre Arm Flag into the FW_CR register.
• Jump to any executable location outside the Firewall segments.
If the Firewall Pre Arm Flag is not set when the protected code jumps to a non protected
segment, a reset is generated. This control bit is an additional protection to avoid an
undesired attempt to close the Firewall with the private information not yet cleaned (see the
note below).
For security reasons, following the application for which the Firewall is used, it is advised to
clean all private information from CPU registers and hardware cells.

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4.4 Firewall registers

4.4.1 Code segment start address (FW_CSSA)

Address offset: 0x00
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. ADD[23:16]

rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADD[15:8] Res. Res. Res. Res. Res. Res. Res. Res.

rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:8 ADD[23:8]: code segment start address
The LSB bits of the start address (bit 7:0) are reserved and forced to 0 in order to allow a
256-byte granularity.
Note: These bits can be written only before enabling the Firewall. Refer to Section 4.3.5:
Firewall initialization.
Bits 7:0 Reserved, must be kept at the reset value.

4.4.2 Code segment length (FW_CSL)

Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LENG[21:16]

rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LENG15:8] Res. Res. Res. Res. Res. Res. Res. Res.

rw

Bits 31:22 Reserved, must be kept at the reset value.

Bits 21:8 LENG[21:8]: code segment length
LENG[21:8] selects the size of the code segment expressed in bytes but is a multiple of
256 bytes.
The segment area is defined from {ADD[23:8],0x00} to {ADD[23:8]+LENG[21:8], 0x00} - 0x01
Note: If LENG[21:8] = 0 after enabling the Firewall, this segment is not defined, thus not
protected by the Firewall.
These bits can only be written before enabling the Firewall. Refer to Section 4.3.5:
Firewall initialization.
Bits 7:0 Reserved, must be kept at the reset value.

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RM0432 Firewall (FW)

4.4.3 Non-volatile data segment start address (FW_NVDSSA)

Address offset: 0x08
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. ADD[23:16]

rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADD[15:8] Res. Res. Res. Res. Res. Res. Res. Res.

rw

Bits 31:24 Reserved, must be kept at the reset value.

Bits 23:8 ADD[23:8]: Non-volatile data segment start address
The LSB bits of the start address (bit 7:0) are reserved and forced to 0 in order to allow a
256-byte granularity.
Note: These bits can only be written before enabling the Firewall. Refer to Section 4.3.5:
Firewall initialization.
Bits 7:0 Reserved, must be kept at the reset value.

4.4.4 Non-volatile data segment length (FW_NVDSL)

Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LENG[21:16]

rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LENG[15:8] Res. Res. Res. Res. Res. Res. Res. Res.

rw

Bits 31:22 Reserved, must be kept at the reset value.

Bits 21:8 LENG[21:8]: Non-volatile data segment length
LENG[21:8] selects the size of the Non-volatile data segment expressed in bytes but is a
multiple of 256 bytes.
The segment area is defined from {ADD[23:8],0x00} to {ADD[23:8]+LENG[21:8], 0x00} - 0x01
Note: If LENG[21:8] = 0 after enabling the Firewall, this segment is not defined, thus not
protected by the Firewall.
These bits can only be written before enabling the Firewall. Refer to Section 4.3.5:
Firewall initialization.
Bits 7:0 Reserved, must be kept at the reset value.

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4.4.5 Volatile data segment start address (FW_VDSSA)

Address offset: 0x10

Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADD
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
[17:16]

rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADD[15:6] Res. Res. Res. Res. Res. Res.

rw

Bits 31:18 Reserved, must be kept at the reset value.

Bit 17 ADD[17]: Volatile data segment start address
Bits 16:6 ADD[16:6]: Volatile data segment start address
The LSB bits of the start address (bit 5:0) are reserved and forced to 0 in order to allow a
64-byte granularity.
Note: These bits can only be written before enabling the Firewall. Refer to Section 4.3.5:
Firewall initialization
Bits 5:0 Reserved, must be kept at the reset value.

4.4.6 Volatile data segment length (FW_VDSL)

Address offset: 0x14
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

LENG
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
[17:16]

rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LENG[15:6] Res. Res. Res. Res. Res. Res.

rw

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RM0432 Firewall (FW)

Bits 31:18 Reserved, must be kept at the reset value.

Bit 17 LENG[17]: volatile data segment length
Bits 16:6 LENG[16:6]: volatile data segment length
LENG[16:6] selects the size of the volatile data segment expressed in bytes but is a multiple
of 64 bytes.
The segment area is defined from {ADD[16:6],0x00} to {ADD[16:6]+LENG[16:6], 0x00} - 0x01
Note: If LENG[17:6] = 0 after enabling the Firewall, this segment is not defined, thus not
protected by the Firewall.
These bits can only be written before enabling the Firewall. Refer to Section 4.3.5:
Firewall initialization.
Bits 5:0 Reserved, must be kept at the reset value.

4.4.7 Configuration register (FW_CR)

Address offset: 0x20
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. VDE VDS FPA

rw rw rw

Bits 31:3 Reserved, must be kept at the reset value.

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Bit 2 VDE: Volatile data execution

0: Volatile data segment cannot be executed if VDS = 0
1: Volatile data segment is declared executable whatever VDS bit value
When VDS = 1, this bit has no meaning. The Volatile data segment can be executed whatever
the VDE bit value.
If VDS = 1, the code can be executed whatever the Firewall state (opened or closed)
If VDS = 0, the code can only be executed if the Firewall is opened or applying the “call gate”
entry sequence if the Firewall is closed.
Refer to Segment access depending on the Firewall state.
Bit 1 VDS: Volatile data shared
0: Volatile data segment is not shared and cannot be hit by a non protected executable code
when the Firewall is closed. If it is accessed in such a condition, a system reset will be
generated by the Firewall.
1: Volatile data segment is shared with non protected application code. It can be accessed
whatever the Firewall state (opened or closed).
Refer to Segment access depending on the Firewall state.
Bit 0 FPA: Firewall prearm
0: any code executed outside the protected segment when the Firewall is opened will
generate a system reset.
1: any code executed outside the protected segment will close the Firewall.
Refer to Closing the Firewall.

This register is protected in the same way as the Non-volatile data segment (refer to
Section 4.3.5: Firewall initialization).

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 0x8
0x4
0x0

0xC

0x20
0x18
0x14
0x10
4.4.8

0x1C
Offset
RM0432

FW_CR
FW_CSL

FW_VDSL
FW_CSSA
Register

Reset Value
Reset Value
Reset Value
Reset Value
Reset Value
Reset Value
Reset Value
Reset Value
Reset Value

FW_NVDSL

FW_VDSSA
FW_NVDSSA
Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Firewall register map

Res. Res. Res. Res. Res. Res. Res. Res. Res. 24

0
0

Res. Res. Res. Res. Res. Res. Res. 23

0
0

Res. Res. Res. Res. Res. Res. Res. 22

0
0
0
0

Res. Res. Res. Res. Res. 21

0
0
0
0

Res. Res. Res. Res. Res. 20

0
0
0
0

Res. Res. Res. Res. Res. 19

0
0
0
0

Res. Res. Res. Res. Res. 18

RM0432 Rev 6
0
0
0
0
0
0

Res. Res. Res. 17

0
0
0
0
0
0

Res. Res. Res. 16

ADD
ADD

0
0
0
0
0
0

Res. Res. Res. 15

0
0
0
0
0
0

Res. Res. Res.

LENG
LENG

14

0
0
0
0
0
0

Res. Res. Res. 13

0
0
0
0
0
0

Res. Res. Res. 12

ADD

0
0
0
0
0
0

Res. Res. Res.

LENG
11
Table 23. Firewall register map and reset values

0
0
0
0
0
0

Res. Res. Res. 0 10

0
0
0
0
0

Res. Res. Res. 9

The table below provides the Firewall register map and reset values.

Refer to Section 2.2 on page 91 for the register boundary addresses.

0
0
0
0
0
0

Res. Res. Res. 8

0
0

Res. Res. Res. Res. Res. Res. Res. 7

0
0

Res. Res. Res. Res. Res. Res. Res. 6

Res. Res. Res. Res. Res. Res. Res. Res. Res. 5
Res. Res. Res. Res. Res. Res. Res. Res. Res. 4
Res. Res. Res. Res. Res. Res. Res. Res. Res. 3

0
VDE Res. Res. Res. Res. Res. Res. Res. Res. 2

0
VDS Res. Res. Res. Res. Res. Res. Res. Res. 1
0
FPA Res. Res. Res. Res. Res. Res. Res. Res. 0
Firewall (FW)

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5 Power control (PWR)

5.1 Power supplies

The STM32L4+ Series devices require a 1.71 V to 3.6 V operating supply voltage (VDD).
Several peripherals are supplied through independent power domains: VDDA, VDDIO2,
VDDUSB, VDDDSI. Those supplies must not be provided without a valid operating supply on
the VDD pin.
• VDD = 1.71 V to 3.6 V
VDD is the external power supply for the I/Os, the internal regulator and the system
analog such as reset, power management and internal clocks. It is provided externally
through VDD pins.
• VDDA = 1.62 V (ADCs/COMPs) / 1.8 V (DACs/OPAMPs) / 2.4 V (VREFBUF) to 3.6 V
VDDA is the external analog power supply for A/D converters, D/A converters, voltage
reference buffer, operational amplifiers and comparators. The VDDA voltage level is
independent from the VDD voltage. VDDA should be preferably connected to VDD when
these peripherals are not used.
• VDD12 = 1.05 to 1.32 V
VDD12 is the external power supply bypassing the internal regulator when connected to
an external SMPS. It is provided externally through VDD12 pins and only available on
packages with the external SMPS supply option. VDD12 does not require any external
decoupling capacitance and cannot support any external load.
• VDDUSB = 3.0 V to 3.6 V
VDDUSB is the external independent power supply for USB transceivers. The VDDUSB
voltage level is independent from the VDD voltage. VDDUSB should be preferably
connected to VDD when the USB is not used.
The VDDUSB power supply may not be present as a dedicated pin, but to be internally
bonded to VDD. For such devices, VDD has to respect the VDDUSB supply range when
the USB is used.
• VDDIO2 = 1.08 V to 3.6 V
VDDIO2 is the external power supply for 14 I/Os (Port G[15:2]). The VDDIO2 voltage level
is independent from the VDD voltage and should preferably be connected to VDD when
PG[15:2] are not used.
• VDDDSI is an independent DSI power supply dedicated to the DSI regulator and the
MIPI DPHY. This supply must be connected to the global VDD.
• VCAPDSI pin is the output of the DSI regulator (1.2 V) which must be connected
externally to VDD12DSI.
• VDD12DSI pin is used to supply the MIPI D-PHY, and to supply the clock and data lanes
pins. An external capacitor of 2.2 uF must be connected on VDD12DSI pin.
• VBAT = 1.55 V to 3.6 V
VBAT is the power supply for RTC, external clock 32 kHz oscillator and backup registers
(through power switch) when VDD is not present. VBAT is internally bonded to VDD for
small packages without dedicated pin.
• VREF-, VREF+
VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the
internal voltage reference buffer when enabled.

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When VDDA < 2 V, VREF+ must be equal to VDDA.

When VDDA ≥ 2 V, VREF+ must be between 2 V and VDDA.
VREF+ can be grounded when ADC and DAC are not active.
The internal voltage reference buffer supports two output voltages, which are
configured with VRS bit in the VREFBUF_CSR register:
– VREF+ around 2.048 V. This requires VDDA equal to or higher than 2.4 V.
– VREF+ around 2.5 V. This requires VDDA equal to or higher than 2.8 V.
VREF- and VREF+ pins are not available on all packages. When not available on the
package, they are bonded to VSSA and VDDA, respectively.
When the VREF+ is double-bonded with VDDA in a package, the internal voltage
reference buffer is not available and must be kept disable (refer to related device
datasheet for packages pinout description).
VREF- must always be equal to VSSA.
An embedded linear voltage regulator is used to supply the internal digital power VCORE.
VCORE is the power supply for digital peripherals and memories.

Figure 9. STM32L4P5xx/Q5xx, STM32L4S5xx/R5xx and STM32L4S7xx/L4R7xx

power supply overview

VDDA domain
1 x A/D converter
VDDA 2 x comparators
2 x D/A converters
VSSA 2 x operational amplifiers
Voltage reference buffer

VDDUSB
USB transceivers
VSS
VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS PG[15:2]

VDD domain
VDDIO1 I/O ring

Reset block VCORE domain

Temp. sensor
3 x PLL, HSI, MSI Core
SRAM1
Standby circuitry SRAM2
VSS (Wakeup logic, SRAM3
IWDG) Digital
VDD VCORE peripherals
Voltage regulator

2 x VDD12
Flash memory
Low voltage detector

Backup domain
LSE crystal 32 K osc
VBAT
BKP registers
RCC BDCR register
RTC

MSv43404V2

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Figure 10. STM32L4S9xx/L4R9xx power supply overview

VDDA domain
1 x A/D converter
VDDA 2 x comparators
2 x D/A converters
VSSA 2 x operational amplifiers
Voltage reference buffer

VDDUSB
USB transceivers
VSS
VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS PG[15:2]

VDDDSI DSI
voltage regulator
VCAPDSI
VDD12DSI DSI PHY

VDD domain
VDDIO1 I/O ring

Reset block VCORE domain

Temp. sensor
3 x PLL, HSI, MSI Core
SRAM1
Standby circuitry SRAM2
VSS (Wakeup logic, SRAM3
IWDG) Digital
VDD VCORE peripherals
Voltage regulator

2 x VDD12 Flash memory

Low voltage detector

Backup domain
LSE crystal 32 K osc
VBAT
BKP registers
RCC BDCR register
RTC

MSv43405V2

5.1.1 Independent analog peripherals supply

To improve ADC and DAC conversion accuracy and to extend the supply flexibility, the
analog peripherals have an independent power supply which can be separately filtered and
shielded from noise on the PCB.
• The analog peripherals voltage supply input is available on a separate VDDA pin.
• An isolated supply ground connection is provided on VSSA pin.
The VDDA supply voltage can be different from VDD. The presence of VDDA must be checked
before enabling any of the analog peripherals supplied by VDDA (A/D converter, D/A
converter, comparators, operational amplifiers, voltage reference buffer).
The VDDA supply can be monitored by the Peripheral Voltage Monitoring, and compared
with two thresholds (1.65 V for PVM3 or 2.2 V for PVM4), refer to Section 5.2.3: Peripheral
Voltage Monitoring (PVM) for more details.
When a single supply is used, VDDA can be externally connected to VDD through the
external filtering circuit in order to ensure a noise-free VDDA reference voltage.

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ADC and DAC reference voltage

To ensure a better accuracy on low-voltage inputs and outputs, the user can connect to
VREF+ a separate reference voltage lower than VDDA. VREF+ is the highest voltage,
represented by the full scale value, for an analog input (ADC) or output (DAC) signal.
VREF+ can be provided either by an external reference of by an internal buffered voltage
reference (VREFBUF).
The internal voltage reference is enabled by setting the ENVR bit in the Section 23.3.1:
VREFBUF control and status register (VREFBUF_CSR). The voltage reference is set to
2.5 V when the VRS bit is set and to 2.048 V when the VRS bit is cleared. The internal
voltage reference can also provide the voltage to external components through VREF+ pin.
Refer to the device datasheet and to Section 23: Voltage reference buffer (VREFBUF) for
further information.

5.1.2 Independent I/O supply rail

Some I/Os from Port G (PG[15:2]) are supplied from a separate supply rail. The power
supply for this rail can range from 1.08 V to 3.6 V and is provided externally through the
VDDIO2 pin. The VDDIO2 voltage level is completely independent from VDD or VDDA. The
VDDIO2 pin is available only for some packages. Refer to the pinout diagrams or tables in the
related device datasheet(s) for I/O list(s).
After reset, the I/Os supplied by VDDIO2 are logically and electrically isolated and therefore
are not available. The isolation must be removed before using any I/O from PG[15:2], by
setting the IOSV bit in the PWR_CR2 register, once the VDDIO2 supply is present.
The VDDIO2 supply is monitored by the Peripheral Voltage Monitoring (PVM2) and compared
with the internal reference voltage (3/4 VREFINT, around 0.9V), refer to Section 5.2.3:
Peripheral Voltage Monitoring (PVM) for more details.

5.1.3 Independent USB transceivers supply

The USB transceivers are supplied from a separate VDDUSB power supply pin. VDDUSB
range is from 3.0 V to 3.6 V and is completely independent from VDD or VDDA.
After reset, the USB features supplied by VDDUSB are logically and electrically isolated and
therefore are not available. The isolation must be removed before using the USB OTG
peripheral, by setting the USV bit in the PWR_CR2 register, once the VDDUSB supply is
present.
The VDDUSB supply is monitored by the Peripheral Voltage Monitoring (PVM1) and
compared with the internal reference voltage (VREFINT, around 1.2 V), refer to Section 5.2.3:
Peripheral Voltage Monitoring (PVM) for more details.

5.1.4 Independent DSI supply

The DSI (Display Serial Interface) sub-system uses several power supply pins which are
independent from the other supply pins:
• VDDDSI is an independent DSI power supply dedicated for DSI Regulator and MIPI
D-PHY. This supply must be connected to global VDD.
• VCAPDSI pin is the output of DSI Regulator (1.2V) which must be connected externally
to VDD12DSI.
• VDD12DSI pin is used to supply the MIPI D-PHY, and to supply clock and data lanes

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pins. An external capacitor of 2.2 uF must be connected on VDD12DSI pin.

• VSSDSI pin is an isolated supply ground used for DSI sub-system.
If DSI functionality is not used at all, then:
• VDDDSI pin must be connected to global VDD.
• VCAPDSI pin must be connected externally to VDD12DSI but the external capacitor is
no more needed. If the VDD12DSI is not available on a package, the VCAPDSI to be
kept floating.
• VSSDSI pin must be grounded.
Note: VDDDSI and VDD12DSI pins are not available on all packages. When not available, they
are bonded to VDD and VCAPDSI, respectively.

5.1.5 Battery backup domain

To retain the content of the Backup registers and supply the RTC function when VDD is
turned off, the VBAT pin can be connected to an optional backup voltage supplied by a
battery or by another source.
The VBAT pin powers the RTC unit, the LSE oscillator and the PC13 to PC15 I/Os, allowing
the RTC to operate even when the main power supply is turned off. The switch to the VBAT
supply is controlled by the power-down reset embedded in the Reset block.

Warning: During tRSTTEMPO (temporization at VDD startup) or after a PDR

has been detected, the power switch between VBAT and VDD
remains connected to VBAT.
During the startup phase, if VDD is established in less than
tRSTTEMPO (refer to the datasheet for the value of tRSTTEMPO)
and VDD > VBAT + 0.6 V, a current may be injected into VBAT
through an internal diode connected between VDD and the
power switch (VBAT).
If the power supply/battery connected to the VBAT pin cannot
support this current injection, it is strongly recommended to
connect an external low-drop diode between this power
supply and the VBAT pin.

If no external battery is used in the application, it is recommended to connect VBAT

externally to VDD with a 100 nF external ceramic decoupling capacitor.
When the backup domain is supplied by VDD (analog switch connected to VDD), the
following pins are available:
• PC13, PC14 and PC15, which can be used as GPIO pins
• PC13, PC14 and PC15, which can be configured by RTC or LSE (refer to Section 46.3:
RTC functional description on page 1548)
• PA0/RTC_TAMP2 and PE6/RTC_TAMP3 when they are configured by the RTC as
tamper pins
Note: Due to the fact that the analog switch can transfer only a limited amount of current (3 mA),
the use of GPIO PC13 to PC15 in output mode is restricted: the speed has to be limited to
2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source
(e.g. to drive a LED).

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When the backup domain is supplied by VBAT (analog switch connected to VBAT because
VDD is not present), the following functions are available:
• PC13, PC14 and PC15 can be controlled only by RTC or LSE (refer to Section 46.3:
RTC functional description)
• PA0/RTC_TAMP2 and PE6/RTC_TAMP3 when they are configured by the RTC as
tamper pins

Backup domain access

After a system reset, the backup domain (RTC registers and backup registers) is protected
against possible unwanted write accesses. To enable access to the backup domain,
proceed as follows:
1. Enable the power interface clock by setting the PWREN bits in the Section 6.4.19:
APB1 peripheral clock enable register 1 (RCC_APB1ENR1)
2. Set the DBP bit in the Power control register 1 (PWR_CR1) to enable access to the
backup domain
3. Select the RTC clock source in the Backup domain control register (RCC_BDCR).
4. Enable the RTC clock by setting the RTCEN [15] bit in the Backup domain control
register (RCC_BDCR).

VBAT battery charging

When VDD is present, It is possible to charge the external battery on VBAT through an
internal resistance.
The VBAT charging is done either through a 5 kOhm resistor or through a 1.5 kOhm resistor
depending on the VBRS bit value in the PWR_CR4 register.
The battery charging is enabled by setting VBE bit in the PWR_CR4 register. It is
automatically disabled in VBAT mode.

5.1.6 Voltage regulator

Two embedded linear voltage regulators supply all the digital circuitries, except for the
Standby circuitry and the backup domain. The main regulator output voltage (VCORE) can be
programmed by software to two different power ranges (Range 1 and Range 2) in order to
optimize the consumption depending on the system’s maximum operating frequency (refer
to Section 6.2.9: Clock source frequency versus voltage scaling and to Section 3.3.3: Read
access latency.
The voltage regulators are always enabled after a reset. Depending on the application
modes, the VCORE supply is provided either by the main regulator (MR) or by the low-power
regulator (LPR).
• In Run, Sleep and Stop 0 modes, both regulators are enabled and the main regulator
(MR) supplies full power to the VCORE domain (core, memories and digital peripherals).
• In Low-power run and Low-power sleep modes, the main regulator is off and the low-
power regulator (LPR) supplies low-power to the VCORE domain, preserving the
contents of the registers, SRAM1, SRAM2 and SRAM3.
• In Stop 1 and Stop 2 modes, the main regulator is off and the low-power regulator
(LPR) supplies low-power to the VCORE domain, preserving the contents of the
registers, SRAM1, SRAM2 and SRAM3.
• In Standby mode, the SRAM2 content can be fully or partially (see note below)

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preserved (depending on RRS[1:0] bits in the PWR_CR3 register). The main regulator
(MR) is off and the low-power regulator (LPR) provides the supply only to SRAM2. The
core, digital peripherals (except Standby circuitry and backup domain) and SRAM1 are
powered off.
Note: For STM32L4Rxxx and STM32L4Sxxx devices it is only possible to preserve the full
SRAM2 content depending on RRS bit in the PWR_CR3 register. For STM32L4P5xx and
STM32L4Q5xx devices it is possible to preserve the full (64 Kbytes) or partial (4 Kbytes)
SRAM2 content depending on RRS[1:0] bits in the PWR_CR3 register.
• In Standby mode, both regulators are powered off. The contents of the registers,
SRAM1, SRAM2 and SRAM3 is lost except for the Standby circuitry and the backup
domain.
• In Shutdown mode, both regulators are powered off. When exiting from Shutdown
mode, a power-on reset is generated. Consequently, the contents of the registers,
SRAM1, SRAM2 and SRAM3 is lost, except for the backup domain.

5.1.7 VDD12 domain

VDD12 is intended to be connected with external SMPS (switched-mode power supply) to
generate the VCORE logic supply in Run, Sleep and Stop 0 modes only.
VDD12 pins correspond to the internal VCORE powering the digital part of Core, RAMs,
FLASH and peripherals. This significantly improves the power consumption with a gain from
50% or more depending of the SMPS performances.
The main benefit occurs in Run and Sleep modes whereas in Stop 0 mode, the gain is less
significant.
The figure below shows a schematic to understand how the internal regulator stops
supplying VCORE when an external voltage VDD12 is provided.
As VDD12 shares the same pin as output of the internal regulator, applying a slightly higher
voltage (typically +50 mV) on the VDD12 blocks, the PMOS and the regulator consumption
is negligible.

Figure 11. Internal main regulator overview

VDD

PMOS
Switch VCORE
VDD12

Vsmps
Voltage regulator
Ref

MSv44809V1

A switch, controlled by the chosen GPIO, is inserted between the SMPS output and VDD12.

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There are two possible states:

• Connected: Switch is closed so SMPS powers VDD12
• Disconnected: Switch is open and VDD12 is disconnected from SMPS output
Proper software management through GPIOs to enable/disable SMPS and to
connect/disconnect SMPS through the switch, is required to conform with the rules
described below. See also Section 5.1.8: Dynamic voltage scaling management.
It is mandatory to respect the following rules to avoid any damage or instability on either
digital parts or internal regulators:
• In Run, Sleep and Stop 0 modes, VDD12 can be connected and should respect
– VDD12 < 1.32 V
– VDD12 ≥ VCORE + 50 mV giving for main regulator
Range 1 boost mode, VCORE =1.28 V so VDD12 should be greater than 1.33 V,
but this cannot match previous rule VDD12 < 1.32 V, so it is not a functional use
case with an external SMPS.
Range 1 normal mode, VCORE = 1.2 V so VDD12 should be greater than 1.25 V.
Range 2, VCORE = 1.0 V so VDD12 should be greater than 1.05 V
– VDD12 ≥ 1.08 V in Range 2 when 80 MHz ≥ SYSCLK frequency ≥ 26 MHz
– VDD12 ≥ 1.14 V in Range 2 when SYSCLK frequency > 80 MHz
• In all other modes, such as LPRun, LPSleep, Stop 1, Stop 2, Standby and Shutdown
modes, VDD12 must be disconnected from SMPS output. This means that the pin must
be connected to an high impedance output:
– VDD12 connected to HiZ (voltage is provided by internal regulators)
• Transitions of VDD12 from connected to disconnected is only allowed when SYSCLK
frequency ≤ 26 MHz to avoid to big voltage drop on main regulator side.
Note: In case of asynchronous reset while having the VDD12 ≤ 1.25 V, VDD12 should switch to
HiZ in less than regulator switching time from Range 2 to Range 1 (~1 us).
Note: On STM32L4P5xx and STM32L4Q5xx devices, VDD12 Range 2 is extended down to
1.00 V for better efficiency, thus following formula applies when bit EXT_SMPS_ON in the
Power control register 4 (PWR_CR4) is set:
Range 2, VCORE = 0.95 V so VDD12 should be greater than 1.00 V
Note: For more details on VDD12 management, refer to AN4978 “Design recommendations for
STM32L4xxxx with external SMPS, for ultra-low-power applications with high performance”.

5.1.8 Dynamic voltage scaling management

The dynamic voltage scaling is a power management technique which consists in
increasing or decreasing the voltage used for the digital peripherals (VCORE), according to
the application performance and power consumption needs.
Dynamic voltage scaling to increase VCORE is known as overvolting. It allows to improve the
device performance.
Dynamic voltage scaling to decrease VCORE is known as undervolting. It is performed to
save power, particularly in laptop and other mobile devices where the energy comes from a
battery and is thus limited.
• Range 1: High-performance range.

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In Range1, the main regulator operates in two modes following the R1MODE bit in the
PWR_CR5 register:
• Main regulator Range 1 normal mode: provides a typical output voltage at 1.2 V. It is
used when the system clock frequency is up to 80 MHz. The Flash access time for read
access is minimum, write and erase operations are possible.
• Main regulator Range 1 boost mode: provides a typical output voltage at 1.28 V. It is
used when the system clock frequency is up to 120 MHz. The Flash access time for
read access is minimum, write and erase operations are possible. To optimize the
power consumption it is recommended to select the range1 boost mode when the
system clock frequency is greater than 80 MHz. See Table 24.

Table 24. Range 1 boost mode configuration

System frequency 26 MHz < SYSCLK ≤ 80 MHz 80 MHz < SYSCLK ≤ 120 MHz

R1MODE bit configuration 1 0

• Range 2: Low-power range.

The main regulator provides a typical output voltage at 1.0 V. The system clock frequency
can be up to 26 MHz.The Flash access time for a read access is increased as compared to
Range 1; write and erase operations are not possible.
Voltage scaling is selected through the VOS bit in the PWR_CR1 register.
The sequence to go from Range 1 (Normal/Boost) to Range 2 is:
1. In case of switching from Range 1 boost mode to Range 2, the system clock must
be divided by 2 using the AHB prescaler before switching to a lower system
frequency for at least 1us and then reconfigure the AHB prescaler.:
2. Reduce the system frequency to a value lower than 26 MHz
3. Adjust number of wait states according new frequency target in Range 2
(LATENCY bits in the FLASH_ACR).
4. Program the VOS bits to “10” in the PWR_CR1 register.
The sequence to go from Range 2 to Range 1 (normal/boost mode) is:

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1. Program the VOS bits to “01” in the PWR_CR1 register.

2. Wait until the VOSF flag is cleared in the PWR_SR2 register.
3. Adjust number of wait states according new frequency target in Range 1
(LATENCY bits in the FLASH_ACR).
4. Increase the system frequency by following below procedure:
– If the system frequency is 26 MHz < SYSCLK ≤ 80 MHz:
- Select the Range 1 normal mode by setting R1MODE bit in the PWR_CR5
register.
- Configure and switch to PLL for a new system frequency.
– If the system frequency is SYSCLK > 80 MHz:
- The system clock must be divided by 2 using the AHB prescaler before switching
to a higher system frequency.
- Select the Range 1 boost mode by clearing the R1MODE bit is in the PWR_CR5
register,
- Configure and switch to PLL for a new system frequency.
- Wait for at least 1us and then reconfigure the AHB prescaler to get the needed
HCLK clock frequency.
The sequence to switch from Range1 normal mode to Range1 boost mode is:
1. The system clock must be divided by 2 using the AHB prescaler before switching
to a higher system frequency.
2. Clear the R1MODE bit is in the PWR_CR5 register,
3. Adjust the number of wait states according to the new frequency target in range1
boost mode
4. Configure and switch to new system frequency.
5. Wait for at least 1 1us and then reconfigure the AHB prescaler to get the needed
HCLK clock frequency.
The sequence to switch from Range1 boost mode to Range1 normal mode is:
1. Set the R1MODE bit is in the PWR_CR5 register.
2. Adjust the number of wait states according new frequency target in Range1
default mode
3. Configure and switch to new system frequency.
When supplying VDD12 with an external SMPS, three states can be configured:
• SMPS Range 1: main regulator is in normal Range 1, VCORE is supplied by external
SMPS and higher than 1.25 V. SYSCLK frequency can be up to 120 MHz.
• SMPS Range 2 high: main regulator is in Range 2, VCORE is supplied by external
SMPS and higher than
– 1.08 V when SYSCLK frequency ≤ 80 MHz
– 1.14 V when SYSCLK frequency > 80MHz
• SMPS Range 2 low: main regulator is in Range 2, VCORE is supplied by external SMPS
and higher than 1.05 V. Max SYSCLK frequency is 26 MHz without Flash write/erase
operations.
In order to match the upper rules described in Section 5.1.7: VDD12 domain, the transition
sequences can only be one of the following:
• Range 1 to SMPS Range 1:

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1. Start SMPS converter (if not always enabled by HW).

2. Check that SMPS converter output is at the correct level, like 1.25 V ≤ VDD12 < 1.32 V.
3. Connect VDD12 to external SMPS converter through the switch.

• Range 2 to SMPS Range 2 low and high:

1. Start SMPS (if not always enabled by HW).
2. Check that SMPS output is at the correct level like1.05 V ≤ VDD12 < 1.32 V.
3. Connect VDD12 to external SMPS converter through the switch.
– If 1.08 V ≤ VDD12 (like SMPS Range 2 high), then the following steps can be
applied:
1. Set register FLASH_CFGR bit LVEN to 1.
2. Adjust the number of wait states in the FLASH_ACR (up to max frequency of Range 1
refer to Section 3.3.3: Read access latency).
3. Increase the system frequency up to the maximum allowed value for voltage Range 1
(like 80 MHz when 1.08V < VDD12 < 1.14 V or 120 MHz when VDD12 > 1.14 V).

• SMPS Range 1 to Range 1 or SMPS Range 2 low and high to Range 2:

1. If in Range 1, reduce the system frequency to a value lower or equal to 26 MHz.
2. Adjust number of wait states according new frequency target corresponding to voltage
range (LATENCY bits in the FLASH_ACR).
3. Set register FLASH_CFGR bit LVEN to 0.
4. Disconnect VDD12 by opening the switch.
5. Stop SMPS (if required and not kept always enabled).

5.2 Power supply supervisor

5.2.1 Power-on reset (POR) / power-down reset (PDR) / brown-out reset

(BOR)
The device has an integrated power-on reset (POR) / power-down reset (PDR), coupled
with a brown-out reset (BOR) circuitry. The BOR is active in all power modes except
Shutdown mode, and cannot be disabled.
Five BOR thresholds can be selected through option bytes.
During power-on, the BOR keeps the device under reset until the supply voltage VDD
reaches the specified VBORx threshold. When VDD drops below the selected threshold, a
device reset is generated. When VDD is above the VBORx upper limit, the device reset is
released and the system can start.
For more details on the brown-out reset thresholds, refer to the electrical characteristics
section in the datasheet.

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Figure 12. Brown-out reset waveform

VDD
VBOR0 (rising edge)

hysteresis
VBOR0 (falling edge)

Temporization
tRSTTEMPO

Reset
MS31444V5

1. The reset temporization tRSTTEMPO is present only for the BOR lowest threshold (VBOR0).

5.2.2 Programmable voltage detector (PVD)

You can use the PVD to monitor the VDD power supply by comparing it to a threshold
selected by the PLS[2:0] bits in the Power control register 2 (PWR_CR2).
The PVD is enabled by setting the PVDE bit.
A PVDO flag is available, in the Power status register 2 (PWR_SR2), to indicate if VDD is
higher or lower than the PVD threshold. This event is internally connected to the EXTI line16
and can generate an interrupt if enabled through the EXTI registers. The rising/falling edge
sensitivity of the EXTI Line16 should be configured according to PVD output behavior i.e. if
the EXTI line 16 is configured to rising edge sensitivity, the interrupt will be generated when
VDD drops below the PVD threshold. As an example the service routine could perform
emergency shutdown tasks.

Figure 13. PVD thresholds

V DD

V PVD threshold 100 mV

hysteresis

PVD output

MS31445V2

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5.2.3 Peripheral Voltage Monitoring (PVM)

Only VDD is monitored by default, as it is the only supply required for all system-related
functions. The other supplies (VDDA, VDDIO2 and VDDUSB) can be independent from VDD
and can be monitored with four Peripheral Voltage Monitoring (PVM).
Each of the four PVMx (x=1, 2, 3, 4) is a comparator between a fixed threshold VPVMx and
the selected power supply. PVMOx flags indicate if the independent power supply is higher
or lower than the PVMx threshold: PVMOx flag is cleared when the supply voltage is above
the PVMx threshold, and is set when the supply voltage is below the PVMx threshold.
Each PVM output is connected to an EXTI line and can generate an interrupt if enabled
through the EXTI registers. The PVMx output interrupt is generated when the independent
power supply drops below the PVMx threshold and/or when it rises above the PVMx
threshold, depending on EXTI line rising/falling edge configuration.
Each PVM can remain active in Stop 0, Stop 1 and Stop 2 modes, and the PVM interrupt
can wake up from the Stop mode.

Table 25. PVM features

PVM Power supply PVM threshold EXTI line

PVM1 VDDUSB VPVM1 (around 1.2 V) 35

PVM2 VDDIO2 VPVM2 (around 0.9 V) 36
PVM3 VDDA VPVM3 (around 1.65 V) 37
PVM4 VDDA VPVM4 (around 2.2 V) 38

The independent supplies (VDDA, VDDIO2 and VDDUSB) are not considered as present by
default, and a logical and electrical isolation is applied to ignore any information coming
from the peripherals supplied by these dedicated supplies.
• If these supplies are shorted externally to VDD, the application should assume they are
available without enabling any Peripheral Voltage Monitoring.
• If these supplies are independent from VDD, the Peripheral Voltage Monitoring (PVM)
can be enabled to confirm whether the supply is present or not.
The following sequence must be done before using the USB OTG peripheral:
1. If VDDUSB is independent from VDD:
a) Enable the PVM1 by setting PVME1 bit in the Power control register 2
(PWR_CR2).
b) Wait for the PVM1 wakeup time
c) Wait until PVMO1 bit is cleared in the Power status register 2 (PWR_SR2).
d) Optional: Disable the PVM1 for consumption saving.
2. Set the USV bit in the Power control register 2 (PWR_CR2) to remove the VDDUSB
power isolation.
The following sequence must be done before using any I/O from PG[15:2]:

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1. If VDDIO2 is independent from VDD:

a) Enable the PVM2 by setting PVME2 bit in the Power control register 2
(PWR_CR2).
b) Wait for the PVM2 wakeup time
c) Wait until PVMO2 bit is cleared in the Power status register 2 (PWR_SR2).
d) Optional: Disable the PVM2 for consumption saving.
2. Set the IOSV bit in the Power control register 2 (PWR_CR2) to remove the VDDIO2
power isolation.
The following sequence must be done before using any of these analog peripherals: analog
to digital converters, digital to analog converters, comparators, operational amplifiers,
voltage reference buffer:
1. If VDDA is independent from VDD:
a) Enable the PVM3 (or PVM4) by setting PVME3 (or PVME4) bit in the Power
control register 2 (PWR_CR2).
b) Wait for the PVM3 (or PVM4) wakeup time
c) Wait until PVMO3 (or PVMO4) bit is cleared in the Power status register 2
(PWR_SR2).
d) Optional: Disable the PVM3 (or PVM4) for consumption saving.
2. Enable the analog peripheral, which automatically removes the VDDA isolation.

5.3 Low-power modes

By default, the microcontroller is in Run mode after a system or a power Reset. Several low-
power modes are available to save power when the CPU does not need to be kept running,
for example when waiting for an external event. It is up to the user to select the mode that
gives the best compromise between low-power consumption, short startup time and
available wakeup sources.
The device features seven low-power modes:
• Sleep mode: CPU clock off, all peripherals including Cortex®-M4 core peripherals such
as NVIC, SysTick, etc. can run and wake up the CPU when an interrupt or an event
occurs. Refer to Section 5.3.4: Sleep mode.
• Low-power run mode: This mode is achieved when the system clock frequency is
reduced below 2 MHz. The code is executed from the SRAM or the Flash memory. The
regulator is in low-power mode to minimize the regulator's operating current. Refer to
Section 5.3.2: Low-power run mode (LP run).
• Low-power sleep mode: This mode is entered from the Low-power run mode: Cortex®-
M4 is off. Refer to Section 5.3.5: Low-power sleep mode (LP sleep).
• Stop 0, Stop 1 and Stop 2 modes: SRAM1, SRAM2, SRAM3 and all registers content
are retained. All clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI16
and the HSE are disabled. The LSI and the LSE can be kept running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals with the wakeup capability can enable the HSI16 RC during the Stop
mode to detect their wakeup condition.
In Stop 2 mode, most of the VCORE domain is put in a lower leakage mode.To further
reduce the current consumption during Stop 2, it is possible to switch OFF the SRAM3:
– Stop 2 mode with SRAM3 content lost when the RRSTP bit is cleared in

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PWR_CR1 register (default setting).

Stop 2 mode with SRAM3 retention when the RRSTP bit is set in PWR_CR1 register.
Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller
wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator
remains ON, which allows the fastest wakeup time but with much higher consumption.
The active peripherals and wakeup sources are the same as in Stop 1 mode.
The system clock, when exiting from Stop 0, Stop 1 or Stop 2 mode, can be either MSI
up to 48 MHz or HSI16, depending on the software configuration.
Refer to Section 5.3.6: Stop 0 mode and Section 5.3.8: Stop 2 mode.
• Standby mode: VCORE domain is powered off. However, it is possible to preserve the
SRAM2 contents:
For STM32L4Rxxx and STM32L4Sxxx devices:
– Standby mode with SRAM2 retention when the bit RRS is set in PWR_CR3
register. In this case, SRAM2 is supplied by the low-power regulator.
– Standby mode when the bit RRS is cleared in PWR_CR3 register. In this case the
main regulator and the low-power regulator are powered off.
For STM32L4P5xx and STM32L4Q5xx devices:
– Standby mode with full or only the upper 4 Kbytes of SRAM2 retention when the
RRS[1:0] bits are set to ‘01’ or ‘10’ respectively in the PWR_CR3 register. In this
case, the SRAM2 is supplied by the low-power regulator.
– Standby mode when the RRS[1:0] bits are cleared in PWR_CR3 register. In this
case the main regulator and the low-power regulator are powered off.
All clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI16 and the HSE
are disabled. The LSI and the LSE can be kept running.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The system clock, when exiting Standby modes, is MSI from 1 MHz up to 8 MHz.
Refer to Section 5.3.9: Standby mode.
• Shutdown mode: VCORE domain is powered off. All clocks in the VCORE domain are
stopped, the PLL, the MSI, the HSI16, the LSI and the HSE are disabled. The LSE can
be kept running. The system clock, when exiting the Shutdown mode, is MSI at 4 MHz.
In this mode, the supply voltage monitoring is disabled and the product behavior is not
guaranteed in case of a power voltage drop. Refer to Section 5.3.10: Shutdown mode.
In addition, the power consumption in Run mode can be reduced by one of the following
means:
• Slowing down the system clocks
• Gating the clocks to the APB and AHB peripherals when they are unused.

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Figure 14. Low-power modes possible transitions

Low power sleep mode

Sleep mode Low power run mode Shutdown mode

Stop 1 mode Run mode Standby mode

Stop 0 mode Stop 2 mode

MS33361V2

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Table 26. Low-power mode summary

Voltage
Wakeup Wakeup regulators
Mode name Entry Effect on clocks
source(1) system clock
MR LPR

Sleep WFI or Return Same as before CPU clock OFF

Any interrupt
(Sleep-now or from ISR entering Sleep no effect on other clocks ON ON
Sleep-on-exit) WFE Wakeup event mode or analog clock sources

Low-power Same as Low-

Set LPR bit Clear LPR bit None OFF ON
run power run clock
Set LPR bit +
WFI or Return Any interrupt Same as before CPU clock OFF OFF ON
Low-power from ISR entering Low-
sleep no effect on other clocks
power sleep
Set LPR bit + or analog clock sources
Wakeup event mode OFF ON
WFE

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Table 26. Low-power mode summary (continued)

Voltage
Wakeup Wakeup regulators
Mode name Entry Effect on clocks
source(1) system clock
MR LPR

LPMS=”000” +
SLEEPDEEP bit
Stop 0 ON
+ WFI or Return
HSI16 when
from ISR or WFE
Any EXTI line STOPWUCK=1 in
LPMS=”001” + (configured in the RCC_CFGR
SLEEPDEEP bit EXTI registers) MSI with the
Stop 1 + WFI or Return Specific frequency before
from ISR or WFE peripherals entering the Stop
events mode when
LPMS=”010” +
STOPWUCK=0.
SLEEPDEEP bit
Stop 2 + WFI or Return
from ISR or WFE
LPMS=”011”+
WKUP pin edge,
Set RRS[1:0] bits
Standby with RTC event,
to “10” +
SRAM2 external reset in
SLEEPDEEP bit ON
4 Kbytes(2) NRST pin, IWDG
+ WIFI or Return
reset
from ISR or WFE
All clocks OFF except OFF
LPMS=”011”+ LSI and LSE
Set RSS bit for
STM32L4Rxxx
and
STM32L4Sxxx
devices and set WKUP pin edge,
Standby with RSS[1:0] bits to RTC event, MSI from 1 MHz
SRAM2 “01” for external reset in up to 8 MHz
64 Kbytes STM32L4P5xx NRST pin,
and IWDG reset
STM32L4Q5xx
devices +
SLEEPDEEP bit
+ WFI or Return
from ISR or WFE
LPMS=”011” + WKUP pin edge,
Clear RRS bit + RTC event,
Standby SLEEPDEEP bit external reset in OFF OFF
+ WFI or Return NRST pin,
from ISR or WFE IWDG reset

LPMS=”1--” + WKUP pin edge,

SLEEPDEEP bit RTC event, All clocks OFF except
Shutdown MSI 4 MHz OFF OFF
+ WFI or Return external reset in LSE
from ISR or WFE NRST pin
1. Refer to Table 27: Functionalities depending on the working mode.
2. SRAM2 4 Kbytes retention in Standby mode is only available for STM32L4P5xx and STM32L4Q5xx devices.

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Table 27. Functionalities depending on the working mode(1)

Stop 0/1 Stop 2 Standby Shutdown

Low-power sleep
Low-power run

Wakeup capability

Wakeup capability

Wakeup capability

Wakeup capability
Peripheral Run Sleep VBAT
- - - -

CPU Y - Y - - - - - - - - - -
(2) (2) (2) (2)
Flash memory (2 Mbytes) O O O O - - - - - - - - -
SRAM1
(192 Kbytes for
STM32L4Rxxx and
STM32L4Sxxx) Y Y(3) Y Y(3) Y - Y - - - - - -
(128 Kbytes for
STM32L4P5xx and
STM32L4Q5xx)
SRAM2 (64 Kbytes) Y Y(3) Y Y(3) Y - Y - O(4) - - - -
SRAM3
(384 Kbytes for
STM32L4Rxxx and
STM32L4Sxxx) Y Y(3) Y Y(3) Y - Y - - - - - -
(128 Kbytes for
STM32L4P5xx and
STM32L4Q5xx)
FSMC O O O O - - - - - - - - -
OCTOSPIx (x=1,2) O O O O - - - - - - - - -
Backup registers Y Y Y Y Y - Y - Y - Y - Y
Brown-out reset (BOR) Y Y Y Y Y Y Y Y Y Y - - -
Programmable voltage
O O O O O O O O - - - - -
detector (PVD)
Peripheral voltage monitor
O O O O O O O O - - - - -
(PVMx; x=1,2,3,4)
DMA O O O O - - - - - - - - -
DMA2D O O O O - - - - - - - - -
Oscillator HSI16 O O O O (5) (5)
- - - - - - -
Oscillator HSI48 O O - - - - - - - - - - -

High speed external (HSE) O O O O - - - - - - - - -

Low speed internal (LSI) O O O O O - O - O - - - -

Low speed external (LSE) O O O O O - O - O - O - O

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Table 27. Functionalities depending on the working mode(1) (continued)

Stop 0/1 Stop 2 Standby Shutdown

Low-power sleep
Low-power run

Wakeup capability

Wakeup capability

Wakeup capability

Wakeup capability
Peripheral Run Sleep VBAT
- - - -

Multi-speed internal (MSI) O O O O - - - - - - - - -

Clock security system

O O O O - - - - - - - - -
(CSS)
Clock security system on
O O O O O O O O O O - - -
LSE
RTC / Auto wakeup O O O O O O O O O O O O O
Number of RTC tamper pins 3 3 3 3 3 O 3 O 3 O 3 O 3
DCMI/PSSI(6) O O O O - - - - - - - - -
LCD-TFT O O - - - - - - - - - - -
GFXMMU Y Y(3) Y Y(3) Y - Y - - - - - -
DSIHOST O O - - - - - - - - - - -
(10)
USB OTG FS O O(10) - - - O - - - - - - -
O O
USARTx (x=1,2,3,4,5) O O O O (7) (7) - - - - - - -

Low-power UART O O O
O O O O (7) (7) O(7) (7) - - - - -
(LPUART1)
O O
I2Cx (x=1,2,4) O O O O (8) (8) - - - - - - -

O O O O
I2C3 O O O O (8) (8) (8) (8) - - - - -

SPIx (x=1,2,3) O O O O - - - - - - - - -
CAN1 O O O O - - - - - - - - -
SDMMC1 O O O O - - - - - - - - -
SDMMC2 O O O O - - - - - - - - -
SAIx (x=1,2) O O O O - - - - - - - - -
DFSDM1 O O O O - - - - - - - - -
ADCx (x=1,2) O O O O - - - - - - - - -
DACx (x=1,2) O O O O O - - - - - - - -
VREFBUF O O O O O - - - - - - - -
OPAMPx (x=1,2) O O O O O - - - - - - - -
COMPx (x=1,2) O O O O O O O O - - - - -

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Table 27. Functionalities depending on the working mode(1) (continued)

Stop 0/1 Stop 2 Standby Shutdown

Low-power sleep
Low-power run

Wakeup capability

Wakeup capability

Wakeup capability

Wakeup capability
Peripheral Run Sleep VBAT
- - - -

Temperature sensor O O O O - - - - - - - - -
Timers (TIMx) O O O O - - - - - - - - -
Low-power timer 1
O O O O O O O O - - - - -
(LPTIM1)
Low-power timer 2
O O O O O O O(9) O(9) - - - - -
(LPTIM2)
Independent watchdog
O O O O O O O O O O - - -
(IWDG)

Window watchdog (WWDG) O O O O - - - - - - - - -

SysTick timer O O O O - - - - - - - - -
Touch sensing controller
O O O O - - - - - - - - -
(TSC)
Random number generator
O(10) O(10) - - - - - - - - - - -
(RNG)
AES hardware accelerator O O O O - - - - - - - - -
Public key accelerator
O O O O - - - - - - - - -
(PKA)
HASH hardware accelerator O O O O - - - - - - - - -
CRC calculation unit O O O O - - - - - - - - -
5 5
GPIOs O O O O O O O O (11) (13)
pins pins -
(12) (12)

1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available. wakeup
highlighted in gray.
2. The Flash can be configured in Power-down mode. By default, it is not in Power-down mode.
3. The SRAM clock can be gated on or off.
4. For STM32L4Rxxx and STM32L4Sxxx, SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register. For
STM32L4P5xx and STM32L4Q5xx, 4 Kbytes or full SRAM2 content is preserved depending on RRS[1:0] bits configuration
in PWR_CR3 register.
5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by
the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not
need it anymore.
6. PSSI is available only on STM32L4P5xx and STM32L4Q5xx devices.
7. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or
received frame event.
8. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
9. Only for STM32L4P5xx and STM32L4Q5xx devices.

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10. Voltage scaling Range 1 only.

11. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
12. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.
13. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.

Debug mode
By default, the debug connection is lost if the application puts the MCU in Stop 0, Stop1,
Stop 2, Standby or Shutdown mode while the debug features are used. This is due to the
fact that the Cortex®-M4 core is no longer clocked.
However, by setting some configuration bits in the DBGMCU_CR register, the software can
be debugged even when using the low-power modes extensively. For more details, refer to
Section 57.16.1: Debug support for low-power modes.

5.3.1 Run mode

Slowing down system clocks
In Run mode, the speed of the system clocks (SYSCLK, HCLK, PCLK) can be reduced by
programming the prescaler registers. These prescalers can also be used to slow down the
peripherals before entering the Sleep mode.
For more details, refer to Section 6.4.3: Clock configuration register (RCC_CFGR).

Peripheral clock gating

In Run mode, the HCLK and PCLK for individual peripherals and memories can be stopped
at any time to reduce the power consumption.
To further reduce the power consumption in Sleep mode, the peripheral clocks can be
disabled prior to executing the WFI or WFE instructions.
The peripheral clock gating is controlled by the RCC_AHBxENR and RCC_APBxENR
registers.
Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting
the corresponding bit in the RCC_AHBxSMENR and RCC_APBxSMENR registers.

5.3.2 Low-power run mode (LP run)

To further reduce the consumption when the system is in Run mode, the regulator can be
configured in low-power mode. In this mode, the system frequency should not exceed
2 MHz.
Please refer to the product datasheet for more details on voltage regulator and peripherals
operating conditions.

I/O states in Low-power run mode

In Low-power run mode, all I/O pins keep the same state as in Run mode.

Entering the Low-power run mode

To enter the Low-power run mode, proceed as follows:

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1. Optional: Jump into the SRAM and power-down the Flash by setting the RUN_PD bit in
the Flash access control register (FLASH_ACR).
2. Decrease the system clock frequency below 2 MHz.
3. Force the regulator in low-power mode by setting the LPR bit in the PWR_CR1 register.
Refer to Table 28: Low-power run on how to enter the Low-power run mode.

Exiting the Low-power run mode

To exit the Low-power run mode, proceed as follows:
1. Force the regulator in main mode by clearing the LPR bit in the PWR_CR1 register.
2. Wait until REGLPF bit is cleared in the PWR_SR2 register.
3. Increase the system clock frequency.
Refer to Table 28: Low-power run on how to exit the Low-power run mode.

Table 28. Low-power run

Low-power run mode Description

Decrease the system clock frequency below 2 MHz

Mode entry
LPR = 1
LPR = 0
Mode exit Wait until REGLPF = 0
Increase the system clock frequency
Wakeup latency Regulator wakeup time from low-power mode

5.3.3 Low-power modes

Entering low-power mode
Low-power modes are entered by the MCU by executing the WFI (Wait For Interrupt), or
WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in the Cortex®-M4
System Control register is set on Return from ISR.
Entering Low-power mode through WFI or WFE will be executed only if no interrupt is
pending or no event is pending.

Exiting low-power mode

From Sleep modes, and Stop modes the MCU exit low-power mode depending on the way
the low-power mode was entered:
• If the WFI instruction or Return from ISR was used to enter the low-power mode, any
peripheral interrupt acknowledged by the NVIC can wake up the device.
• If the WFE instruction is used to enter the low-power mode, the MCU exits the low-
power mode as soon as an event occurs. The wakeup event can be generated either
by:
– NVIC IRQ interrupt.
- When SEVONPEND = 0 in the Cortex®-M4 System Control register. By enabling
an interrupt in the peripheral control register and in the NVIC. When the MCU
resumes from WFE, the peripheral interrupt pending bit and the NVIC peripheral

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IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be
cleared.
Only NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.
- When SEVONPEND = 1 in the Cortex®-M4 System Control register.
By enabling an interrupt in the peripheral control register and optionally in the
NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and
when enabled the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt
clear pending register) have to be cleared.
All NVIC interrupts will wakeup the MCU, even the disabled ones. Only enabled
NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.
– Event
Configuring a EXTI line in event mode. When the CPU resumes from WFE, it is
not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ
channel pending bit as the pending bits corresponding to the event line is not set.
It may be necessary to clear the interrupt flag in the peripheral.
From Standby modes, and Shutdown modes the MCU exit low-power mode through an
external reset (NRST pin), an IWDG reset, a rising edge on one of the enabled WKUPx pins
or a RTC event occurs (see Figure 456: RTC block diagrams).
After waking up from Standby or Shutdown mode, program execution restarts in the same
way as after a Reset (boot pin sampling, option bytes loading, reset vector is fetched, etc.).

5.3.4 Sleep mode

I/O states in Sleep mode
In Sleep mode, all I/O pins keep the same state as in Run mode.

Entering the Sleep mode

The Sleep mode is entered according Section : Entering low-power mode, when the
SLEEPDEEP bit in the Cortex®-M4 System Control register is clear.
Refer to Table 29: Sleep for details on how to enter the Sleep mode.

Exiting the Sleep mode

The Sleep mode is exit according Section : Exiting low-power mode.
Refer to Table 29: Sleep for more details on how to exit the Sleep mode.

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Table 29. Sleep

Sleep-now mode Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP = 0
– No interrupt (for WFI) or event (for WFE) is pending
Refer to the Cortex®-M4 System Control register.
Mode entry On return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
– No interrupt is pending
Refer to the Cortex®-M4 System Control register.
If WFI or return from ISR was used for entry
Interrupt: refer to Table 76: STM32L4Rxxx and STM32L4Sxxx vector
table
If WFE was used for entry and SEVONPEND = 0:
Mode exit Wakeup event: refer to Section 16.3.2: Wakeup event management
If WFE was used for entry and SEVONPEND = 1:
Interrupt even when disabled in NVIC: refer to Table 76: STM32L4Rxxx
and STM32L4Sxxx vector table or Wakeup event: refer to
Section 16.3.2: Wakeup event management
Wakeup latency None

5.3.5 Low-power sleep mode (LP sleep)

Please refer to the product datasheet for more details on voltage regulator and peripherals
operating conditions.

I/O states in Low-power sleep mode

In Low-power sleep mode, all I/O pins keep the same state as in Run mode.

Entering the Low-power sleep mode

The Low-power sleep mode is entered from Low-power run mode according Section :
Entering low-power mode, when the SLEEPDEEP bit in the Cortex®-M4 System Control
register is clear.
Refer to Table 30: Low-power sleep for details on how to enter the Low-power sleep mode.

Exiting the Low-power sleep mode

The low-power Sleep mode is exit according Section : Exiting low-power mode. When
exiting the Low-power sleep mode by issuing an interrupt or an event, the MCU is in Low-
power run mode.
Refer to Table 30: Low-power sleep for details on how to exit the Low-power sleep mode.

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Table 30. Low-power sleep

Low-power sleep-now
Description
mode

Low-power sleep mode is entered from the Low-power run mode.

WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP = 0
– No interrupt (for WFI) or event (for WFE) is pending
Refer to the Cortex®-M4 System Control register.
Mode entry Low-power sleep mode is entered from the Low-power run mode.
On return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
– No interrupt is pending
Refer to the Cortex®-M4 System Control register.
If WFI or Return from ISR was used for entry
Interrupt: refer to Table 76: STM32L4Rxxx and STM32L4Sxxx vector
table
If WFE was used for entry and SEVONPEND = 0:
Wakeup event: refer to Section 16.3.2: Wakeup event management
Mode exit If WFE was used for entry and SEVONPEND = 1:
Interrupt even when disabled in NVIC: refer to Table 76: STM32L4Rxxx
and STM32L4Sxxx vector table
Wakeup event: refer to Section 16.3.2: Wakeup event management
After exiting the Low-power sleep mode, the MCU is in Low-power run
mode.
Wakeup latency None

5.3.6 Stop 0 mode

The Stop 0 mode is based on the Cortex®-M4 Deepsleep mode combined with the
peripheral clock gating. The voltage regulator is configured in main regulator mode. In Stop
0 mode, all clocks in the VCORE domain are stopped; the PLL, the MSI, the HSI16 and the
HSE oscillators are disabled. Some peripherals with the wakeup capability (I2Cx (x=1,2,3),
U(S)ARTx(x=1,2...5) and LPUART) can switch on the HSI16 to receive a frame, and switch
off the HSI16 after receiving the frame if it is not a wakeup frame. In this case, the HSI16
clock is propagated only to the peripheral requesting it.
SRAM1, SRAM2, SRAM3 and register contents are preserved.
The BOR is always available in Stop 0 mode. The consumption is increased when
thresholds higher than VBOR0 are used.

I/O states in Stop 0 mode

In the Stop 0 mode, all I/O pins keep the same state as in the Run mode.

Entering the Stop 0 mode

The Stop 0 mode is entered according Section : Entering low-power mode, when the
SLEEPDEEP bit in the Cortex®-M4 System Control register is set.

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Refer to Table 31: Stop 0 mode for details on how to enter the Stop 0 mode.
If Flash memory programming is ongoing, the Stop 0 mode entry is delayed until the
memory access is finished.
If an access to the APB domain is ongoing, The Stop 0 mode entry is delayed until the APB
access is finished.
In Stop 0 mode, the following features can be selected by programming individual control
bits:
• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started, it cannot be stopped except by a Reset. See
Section 44.3: IWDG functional description.
• real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain
control register (RCC_BDCR)
• Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
• External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup
domain control register (RCC_BDCR).
Several peripherals can be used in Stop 0 mode and can add consumption if they are
enabled and clocked by LSI or LSE, or when they request the HSI16 clock: LPTIM1,
LPTIM2, I2Cx (x=1,2,3,4) U(S)ARTx(x=1,2...5), LPUART.
The DACx (x=1,2), the OPAMPs and the comparators can be used in Stop 0 mode, the
PVMx (x=1,2,3,4) and the PVD as well. If they are not needed, they must be disabled by
software to save their power consumptions.
The ADCx (x=1,2,3), temperature sensor and VREFBUF buffer can consume power during
the Stop 0 mode, unless they are disabled before entering this mode.

Exiting the Stop 0 mode

The Stop 0 mode is exit according Section : Entering low-power mode.
Refer to Table 31: Stop 0 mode for details on how to exit Stop 0 mode.
When exiting Stop 0 mode by issuing an interrupt or a wakeup event, the HSI16 oscillator is
selected as system clock if the bit STOPWUCK is set in Clock configuration register
(RCC_CFGR). The MSI oscillator is selected as system clock if the bit STOPWUCK is
cleared. The wakeup time is shorter when HSI16 is selected as wakeup system clock. The
MSI selection allows wakeup at higher frequency, up to 48 MHz.
When the voltage regulator operates in low-power mode, an additional startup delay is
incurred when waking up from Stop 0 mode with HSI16. By keeping the internal regulator
ON during Stop 0 mode, the consumption is higher although the startup time is reduced.
When exiting the Stop 0 mode, the MCU is either in Run mode (Range 1 or Range 2
depending on VOS bit in PWR_CR1) or in Low-power run mode if the bit LPR is set in the
PWR_CR1 register.

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Table 31. Stop 0 mode

Stop 0 mode Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP bit is set in Cortex®-M4 System Control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = “000” in PWR_CR1

On Return from ISR while:

– SLEEPDEEP bit is set in Cortex®-M4 System Control register
Mode entry – SLEEPONEXIT = 1
– No interrupt is pending
– LPMS = “000” in PWR_CR1
Note: To enter Stop 0 mode, all EXTI Line pending bits (in Pending
register 1 (EXTI_PR1)), and the peripheral flags generating wakeup
interrupts must be cleared. Otherwise, the Stop 0 mode entry
procedure is ignored and program execution continues.
If WFI or Return from ISR was used for entry
Any EXTI Line configured in interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer to
Table 76: STM32L4Rxxx and STM32L4Sxxx vector table.
If WFE was used for entry and SEVONPEND = 0:
Mode exit Any EXTI Line configured in event mode. Refer to Section 16.3.2:
Wakeup event management.
If WFE was used for entry and SEVONPEND = 1:
Any EXTI Line configured in interrupt mode (even if the corresponding
EXTI Interrupt vector is disabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer
toTable 76: STM32L4Rxxx and STM32L4Sxxx vector table.
Wakeup event: refer to Section 16.3.2: Wakeup event management
Longest wakeup time between: MSI or HSI16 wakeup time and Flash
Wakeup latency
wakeup time from Stop 0 mode.

5.3.7 Stop 1 mode

The Stop 1 mode is the same as Stop 0 mode except that the main regulator is OFF, and
only the low-power regulator is ON. Stop 1 mode can be entered from Run mode and from
Low-power run mode.
Refer to Table 32: Stop 1 mode for details on how to enter and exit Stop 1 mode.

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Table 32. Stop 1 mode

Stop 1 mode Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP bit is set in Cortex®-M4 System Control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = “001” in PWR_CR1

On Return from ISR while:

– SLEEPDEEP bit is set in Cortex®-M4 System Control register
Mode entry – SLEEPONEXIT = 1
– No interrupt is pending
– LPMS = “001” in PWR_CR1
Note: To enter Stop 1 mode, all EXTI Line pending bits (in Pending
register 1 (EXTI_PR1)), and the peripheral flags generating wakeup
interrupts must be cleared. Otherwise, the Stop 1 mode entry
procedure is ignored and program execution continues.
If WFI or Return from ISR was used for entry
Any EXTI Line configured in interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer to
Table 76: STM32L4Rxxx and STM32L4Sxxx vector table.
If WFE was used for entry and SEVONPEND = 0:
Mode exit Any EXTI Line configured in event mode. Refer to Section 16.3.2:
Wakeup event management.
If WFE was used for entry and SEVONPEND = 1:
Any EXTI Line configured in interrupt mode (even if the corresponding
EXTI Interrupt vector is disabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer
toTable 76: STM32L4Rxxx and STM32L4Sxxx vector table.
Wakeup event: refer to Section 16.3.2: Wakeup event management
Longest wakeup time between: MSI or HSI16 wakeup time and regulator
Wakeup latency wakeup time from Low-power mode + Flash wakeup time from Stop 1
mode.

5.3.8 Stop 2 mode

The Stop 2 mode is based on the Cortex®-M4 Deepsleep mode combined with peripheral
clock gating. In Stop 2 mode, all clocks in the VCORE domain are stopped, the PLL, the MSI,
the HSI16 and the HSE oscillators are disabled. Some peripherals with wakeup capability
(I2C3 and LPUART) can switch on the HSI16 to receive a frame, and switch off the HSI16
after receiving the frame if it is not a wakeup frame. In this case the HSI16 clock is
propagated only to the peripheral requesting it.
SRAM1, SRAM2, SRAM3 and register contents are preserved. The SRAM3 content is
preserved or lost following the RRSTP bit configuration in the PWR_CR1 register. By
default, after reset, the RRSTP bit is reset thus the SRAM3 content is lost during Stop 2.
The BOR is always available in Stop 2 mode. The consumption is increased when
thresholds higher than VBOR0 are used.

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Note: The comparators outputs, the LPUART outputs and the LPTIM1 outputs are forced to low
speed (OSPEEDy=00) during the Stop 2 mode.

I/O states in Stop 2 mode

In the Stop 2 mode, all I/O pins keep the same state as in the Run mode.

Entering Stop 2 mode

The Stop 2 mode is entered according Section : Entering low-power mode, when the
SLEEPDEEP bit in the Cortex®-M4 System Control register is set.
Refer to Table 33: Stop 2 mode for details on how to enter the Stop 2 mode.
Stop 2 mode can only be entered from Run mode. It is not possible to enter Stop 2 mode
from the Low-power run mode.
If Flash memory programming is ongoing, the Stop 2 mode entry is delayed until the
memory access is finished.
If an access to the APB domain is ongoing, The Stop 2 mode entry is delayed until the APB
access is finished.
In Stop 2 mode, the following features can be selected by programming individual control
bits:
• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a Reset. See
Section 44.3: IWDG functional description in Section 44: Independent watchdog
(IWDG).
• Real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain
control register (RCC_BDCR)
• Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
• External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup
domain control register (RCC_BDCR).
Several peripherals can be used in Stop 2 mode and can add consumption if they are
enabled and clocked by LSI or LSE, or when they request the HSI16 clock: LPTIM1, I2C3,
LPUART.
The comparators can be used in Stop 2 mode, the PVMx (x=1,2,3,4) and the PVD as well. If
they are not needed, they must be disabled by software to save their power consumptions.
The ADCx, OPAMPx, DACx, temperature sensor and VREFBUF buffer can consume power
during Stop 2 mode, unless they are disabled before entering this mode.
All the peripherals which cannot be enabled in Stop 2 mode must be either disabled by
clearing the Enable bit in the peripheral itself, or put under reset state by setting the
corresponding bit in the AHB1 peripheral reset register (RCC_AHB1RSTR), AHB2
peripheral reset register (RCC_AHB2RSTR), AHB3 peripheral reset register
(RCC_AHB3RSTR), APB1 peripheral reset register 1 (RCC_APB1RSTR1), APB1
peripheral reset register 2 (RCC_APB1RSTR2), APB2 peripheral reset register
(RCC_APB2RSTR).

Exiting Stop 2 mode

The Stop 2 mode is exit according Section : Exiting low-power mode.

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Refer to Table 33: Stop 2 mode for details on how to exit Stop 2 mode.
When exiting Stop 2 mode by issuing an interrupt or a wakeup event, the HSI16 oscillator is
selected as system clock if the bit STOPWUCK is set in Clock configuration register
(RCC_CFGR). The MSI oscillator is selected as system clock if the bit STOPWUCK is
cleared. The wakeup time is shorter when HSI16 is selected as wakeup system clock. The
MSI selection allows wakeup at higher frequency, up to 48 MHz.
When exiting the Stop 2 mode, the MCU is in Run mode (Range 1 or Range 2 depending on
VOS bit in PWR_CR1).

Table 33. Stop 2 mode

Stop 2 mode Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP bit is set in Cortex®-M4 System Control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = “010” in PWR_CR1

On return from ISR while:

– SLEEPDEEP bit is set in Cortex®-M4 System Control register
Mode entry – SLEEPONEXIT = 1
– No interrupt is pending
– LPMS = “010” in PWR_CR1
Note: To enter Stop 2 mode, all EXTI Line pending bits (in Pending
register 1 (EXTI_PR1)), and the peripheral flags generating wakeup
interrupts must be cleared. Otherwise, the Stop mode entry
procedure is ignored and program execution continues.
If WFI or Return from ISR was used for entry:
Any EXTI Line configured in interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer to
Table 76: STM32L4Rxxx and STM32L4Sxxx vector table.
If WFE was used for entry and SEVONPEND = 0:
Any EXTI Line configured in event mode. Refer to Section 16.3.2:
Mode exit Wakeup event management.
If WFE was used for entry and SEVONPEND = 1:
Any EXTI Line configured in interrupt mode (even if the corresponding
EXTI Interrupt vector is disabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer to
Table 76: STM32L4Rxxx and STM32L4Sxxx vector table.
Any EXTI Line configured in event mode. Refer to Section 16.3.2:
Wakeup event management.
Longest wakeup time between: MSI or HSI16 wakeup time and regulator
Wakeup latency wakeup time from Low-power mode + Flash wakeup time from Stop 2
mode.

5.3.9 Standby mode

The Standby mode allows to achieve the lowest power consumption with BOR. It is based
on the Cortex®-M4 Deepsleep mode, with the voltage regulators disabled (except when

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SRAM2 content is preserved). The PLL, the HSI16, the MSI and the HSE oscillators are
also switched off.
SRAM1 and register contents are lost except for registers in the Backup domain and
Standby circuitry (see Figure 9). SRAM2 content can be partially (only for STM32L4P5xx
and STM32L4Q5xx) or fully preserved depending on RRS[1:0] bits configuration in
PWR_CR3 register. In this case the Low-power regulator is ON and provides the supply to
SRAM2 only.
The BOR is always available in Standby mode. The consumption is increased when
thresholds higher than VBOR0 are used.

I/O states in Standby mode

In the Standby mode, the IO’s are by default in floating state. If the APC bit of PWR_CR3
register has been set, the I/Os can be configured either with a pull-up (refer to
PWR_PUCRx registers (x=A,B,C,D,E,F,G,H)), or with a pull-down (refer to PWR_PDCRx
registers (x=A,B,C,D,E,F,G,H)), or can be kept in analog state if none of the PWR_PUCRx
or PWR_PDCRx register has been set. The pull-down configuration has highest priority over
pull-up configuration in case both PWR_PUCRx and PWR_PDCRx are set for the same IO.
Some I/Os (listed in Section 8.3.1: General-purpose I/O (GPIO)) are used for JTAG/SW
debug and can only be configured to their respective reset pull-up or pull-down state during
Standby mode setting their respective bit in the PWR_PUCRx or PWR_PDCRx registers to
‘1’, or will be configured to floating state if the bit is kept at ‘0’.
The RTC outputs on PC13 are functional in Standby mode. PC14 and PC15 used for LSE
are also functional. 5 wakeup pins (WKUPx, x=1,2...5) and the 3 RTC tampers are available.

Entering Standby mode

The Standby mode is entered according Section : Entering low-power mode, when the
SLEEPDEEP bit in the Cortex®-M4 System Control register is set.
Refer to Table 34: Standby mode for details on how to enter Standby mode.
In Standby mode, the following features can be selected by programming individual control
bits:
• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a reset. See
Section 44.3: IWDG functional description in Section 44: Independent watchdog
(IWDG).
• real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain
control register (RCC_BDCR)
• Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
• External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup
domain control register (RCC_BDCR)

Exiting Standby mode

The Standby mode is exited according Section : Entering low-power mode. The SBF status
flag in the Power control register 3 (PWR_CR3) indicates that the MCU was in Standby
mode. All registers are reset after wakeup from Standby except for Power control register 3
(PWR_CR3).

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Refer to Table 34: Standby mode for more details on how to exit Standby mode.
When exiting Standby mode, I/O’s that were configured with pull-up or pull-down during
Standby through registers PWR_PUCRx or PWR_PDCRx will keep this configuration upon
exiting Standby mode until the bit APC of PWR_CR3 register has been cleared. Once the bit
APC is cleared, they will be either configured to their reset values or to the pull-up/pull-down
state according the GPIOx_PUPDR registers. The content of the PWR_PUCRx or
PWR_PDCRx registers however is not lost and can be re-used for a sub-sequent entering
into Standby mode.
Some I/Os (listed in Section 8.3.1: General-purpose I/O (GPIO)) are used for JTAG/SW
debug and have internal pull-up or pull-down activated after reset so will be configured at
this reset value as well when exiting Standby mode.
For IO’s, with a pull-up or pull-down pre-defined after reset (some JTAG/SW IO’s) or with
GPIOx_PUPDR programming done after exiting from Standby, in case those programming
is different from the PWR_PUCRx or PWR_PDCRx programmed value during Standby, both
a pull-down and pull-up will be applied until the bit APC is cleared, releasing the
PWR_PUCRx or PWR_PDCRx programmed value.

Table 34. Standby mode

Standby mode Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP bit is set in Cortex®-M4 System Control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = “011” in PWR_CR1
– WUFx bits are cleared in power status register 1 (PWR_SR1)

On return from ISR while:

Mode entry – SLEEPDEEP bit is set in Cortex®-M4 System Control register
– SLEEPONEXIT = 1
– No interrupt is pending
– LPMS = “011” in PWR_CR1 and
– WUFx bits are cleared in power status register 1 (PWR_SR1)
– The RTC flag corresponding to the chosen wakeup source (RTC Alarm
A, RTC Alarm B, RTC wakeup, tamper or timestamp flags) is cleared
WKUPx pin edge, RTC event, external Reset in NRST pin, IWDG Reset,
Mode exit
BOR reset
Wakeup latency Reset phase

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5.3.10 Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. It is based on the
Deepsleep mode, with the voltage regulator disabled. The VCORE domain is consequently
powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also
switched off.
SRAM1, SRAM2, SRAM3 and register contents are lost except for registers in the Backup
domain. The BOR is not available in Shutdown mode. No power voltage monitoring is
possible in this mode, therefore the switch to Backup domain is not supported.

I/O states in Shutdown mode

In the Shutdown mode, are by default in floating state. If the APC bit of PWR_CR3 register
has been set, the I/Os can be configured either with a pull-up (refer to PWR_PUCRx
registers (x=A,B,C,D,E,F,G,H), or with a pull-down (refer to PWR_PDCRx registers
(x=A,B,C,D,E,F,G,H)), or can be kept in analog state if none of the PWR_PUCRx or
PWR_PDCRx register has been set. The pull-down configuration has highest priority over
pull-up configuration in case both PWR_PUCRx and PWR_PDCRx are set for the same IO.
However this configuration is lost when exiting the Shutdown mode due to the power-on
reset.
Some I/Os (listed in Section 8.3.1: General-purpose I/O (GPIO)) are used for JTAG/SW
debug and can only be configured to their respective reset pull-up or pull-down state during
Standby mode setting their respective bit in the PWR_PUCRx or PWR_PDCRx registers to
‘1’, or will be configured to floating state if the bit is kept at ‘0’.
The RTC outputs on PC13 are functional in Shutdown mode. PC14 and PC15 used for LSE
are also functional. 5 wakeup pins (WKUPx, x=1,2...5) and the 3 RTC tampers are available.

Entering Shutdown mode

The Shutdown mode is entered according Entering low-power mode, when the
SLEEPDEEP bit in the Cortex®-M4 System Control register is set.
Refer to Table 35: Shutdown mode for details on how to enter Shutdown mode.
In Shutdown mode, the following features can be selected by programming individual
control bits:
• real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain
control register (RCC_BDCR). Caution: in case of VDD power-down the RTC content
will be lost.
• external 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup
domain control register (RCC_BDCR)

Exiting Shutdown mode

The Shutdown mode is exit according Section : Exiting low-power mode. A power-on reset
occurs when exiting from Shutdown mode. All registers (except for the ones in the Backup
domain) are reset after wakeup from Shutdown.
Refer to Table 35: Shutdown mode for more details on how to exit Shutdown mode.
When exiting Shutdown mode, I/Os that were configured with pull-up or pull-down during
Shutdown through registers PWR_PUCRx or PWR_PDCRx will lose their configuration and

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will be configured in floating state or to their pull-up pull-down reset value (for some I/Os
listed in Section 8.3.1: General-purpose I/O (GPIO)).

Table 35. Shutdown mode

Shutdown mode Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP bit is set in Cortex®-M4 System Control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = “1XX” in PWR_CR1
– WUFx bits are cleared in power status register 1 (PWR_SR1)

On return from ISR while:

Mode entry – SLEEPDEEP bit is set in Cortex®-M4 System Control register
– SLEEPONEXT = 1
– No interrupt is pending
– LPMS = “1XX” in PWR_CR1 and
– WUFx bits are cleared in power status register 1 (PWR_SR1)
– The RTC flag corresponding to the chosen wakeup source (RTC
Alarm A, RTC Alarm B, RTC wakeup, tamper or timestamp flags) is
cleared
Mode exit WKUPx pin edge, RTC event, external Reset in NRST pin
Wakeup latency Reset phase

5.3.11 Auto-wakeup from low-power mode

The RTC can be used to wakeup the MCU from low-power mode without depending on an
external interrupt (Auto-wakeup mode). The RTC provides a programmable time base for
waking up from Stop (0, 1 or 2) or Standby mode at regular intervals. For this purpose, two
of the three alternative RTC clock sources can be selected by programming the
RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR):
• Low-power 32.768 kHz external crystal oscillator (LSE OSC)
This clock source provides a precise time base with very low-power consumption.
• Low-power internal RC Oscillator (LSI)
This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This
internal RC Oscillator is designed to add minimum power consumption.
To wakeup from Stop mode with an RTC alarm event (or RTC SSRU event which is only
available on STM32L4P5xx and STM32L4Q5xx devices), it is necessary to:
• Configure the EXTI Line 18 to be sensitive to rising edge
• Configure the RTC to generate the RTC alarm
To wakeup from Standby mode, there is no need to configure the EXTI Line 18.
To wakeup from Stop mode with an RTC wakeup event, it is necessary to:
• Configure the EXTI Line 20 to be sensitive to rising edge
• Configure the RTC to generate the RTC alarm
To wakeup from Standby mode, there is no need to configure the EXTI Line 20.

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5.4 PWR registers

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

5.4.1 Power control register 1 (PWR_CR1)

Address offset: 0x00
Reset value: 0x0000 0200 (This register is reset after wakeup from Standby mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. LPR Res. Res. Res. VOS[1:0] DBP Res. Res. Res. RRSTP Res. LPMS[2:0]

rw rw rw rw rw rw rw rw

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 LPR: Low-power run
When this bit is set, the regulator is switched from main mode (MR) to low-power mode
(LPR).
Note: Stop 2 mode cannot be entered when LPR bit is set. Stop 1 is entered instead.
Bits 13:11 Reserved, must be kept at reset value.
Bits 10:9 VOS: Voltage scaling range selection
00: Cannot be written (forbidden by hardware)
01: Range 1
10: Range 2
11: Cannot be written (forbidden by hardware)
Bit 8 DBP: Disable backup domain write protection
In reset state, the RTC and backup registers are protected against parasitic write access.
This bit must be set to enable write access to these registers.
0: Access to RTC and Backup registers disabled
1: Access to RTC and Backup registers enabled
Note: Depending on the APB1 prescaler, there is a delay between writing to DBP and the
effective disable/enable of the backup domain protection. Therefore, a dummy read
operation to PWR_CR1 register is needed just after writing to the DBP bit.
Bits 7:5 Reserved, must be kept at reset value.

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Bit 4 RRSTP: SRAM3 retention in Stop 2 mode

0: SRAM3 is powered off in Stop 2 mode (SRAM3 content is lost)
1: SRAM3 is powered in Stop 2 mode (RAM3 content is kept).
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 LPMS[2:0]: Low-power mode selection
These bits select the low-power mode entered when CPU enters the Deepsleep mode.
000: Stop 0 mode
001: Stop 1 mode
010: Stop 2 mode
011: Standby mode
1xx: Shutdown mode
Note: If LPR bit is set, Stop 2 mode cannot be selected and Stop 1 mode shall be entered
instead of Stop 2.
In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration
in PWR_CR3.

5.4.2 Power control register 2 (PWR_CR2)

Address offset: 0x04
Reset value: 0x0000 0000 (This register is reset when exiting the Standby mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. USV IOSV Res. PVME4 PVME3 PVME2 PVME1 PLS[2:0] PVDE

rw rw rw rw rw rw rw rw rw rw

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 USV: VDDUSB USB supply valid
This bit is used to validate the VDDUSB supply for electrical and logical isolation purpose.
Setting this bit is mandatory to use the USB OTG_FS peripheral. If VDDUSB is not always
present in the application, the PVM can be used to determine whether this supply is ready or
not.
0: VDDUSB is not present. Logical and electrical isolation is applied to ignore this supply.
1: VDDUSB is valid.
Bit 9 IOSV: VDDIO2 Independent I/Os supply valid
This bit is used to validate the VDDIO2 supply for electrical and logical isolation purpose.
Setting this bit is mandatory to use PG[15:2]. If VDDIO2 is not always present in the
application, the PVM can be used to determine whether this supply is ready or not.
0: VDDIO2 is not present. Logical and electrical isolation is applied to ignore this supply.
1: VDDIO2 is valid.
Bit 8 Reserved, must be kept at reset value.
Bit 7 PVME4: Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V
0: PVM4 (VDDA monitoring vs. 2.2V threshold) disable.
1: PVM4 (VDDA monitoring vs. 2.2V threshold) enable.

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Bit 6 PVME3: Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V

0: PVM3 (VDDA monitoring vs. 1.62V threshold) disable.
1: PVM3 (VDDA monitoring vs. 1.62V threshold) enable.
Bit 5 PVME2: Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V
0: PVM2 (VDDIO2 monitoring vs. 0.9V threshold) disable.
1: PVM2 (VDDIO2 monitoring vs. 0.9V threshold) enable.
Bit 4 PVME1: Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V
0: PVM1 (VDDUSB monitoring vs. 1.2V threshold) disable.
1: PVM1 (VDDUSB monitoring vs. 1.2V threshold) enable.
Bits 3:1 PLS[2:0]: Power voltage detector level selection.
These bits select the voltage threshold detected by the power voltage detector:
000: VPVD0 around 2.0 V
001: VPVD1 around 2.2 V
010: VPVD2 around 2.4 V
011: VPVD3 around 2.5 V
100: VPVD4 around 2.6 V
101: VPVD5 around 2.8 V
110: VPVD6 around 2.9 V
111: External input analog voltage PVD_IN (compared internally to VREFINT)
Note: These bits are write-protected when the bit PVDL (PVD Lock) is set in the
SYSCFG_CBR register.
These bits are reset only by a system reset.
Bit 0 PVDE: Power voltage detector enable
0: Power voltage detector disable.
1: Power voltage detector enable.
Note: This bit is write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR
register.
This bit is reset only by a system reset.

5.4.3 Power control register 3 (PWR_CR3)

Address offset: 0x08
Reset value: 0x0000 8000 (This register is not reset when exiting Standby modes and with
the PWRRST bit in the RCC_APB1RSTR1 register)
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSIPD EWUP EWUP EWUP EWUP EWUP
EIWUL Res. Res. ENULP APC RRS[1:0] Res. Res. Res.
EN 5 4 3 2 1
rw rw rw rw rw rw rw rw rw rw rw

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Power control (PWR) RM0432

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 EIWUL: Enable internal wakeup line
0: Internal wakeup line disable.
1: Internal wakeup line enable.
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 DSIPDEN: Enable Pull-down activation on DSI pins
1: Pull-Down is enabled on DSI pins.
0: Pull-Down is disabled on DSI pins.
Bit 11 ENULP: Enable ULP sampling
When this bit is set, the BORL, BORH and PVD are periodically sampled instead continuous
monitoring to reduce power consumption. Fast supply drop between two sample/compare
phases is not detected in this mode. This bit has impact only on STOP2 and Standby low
power modes.
Note: Available on STM32L4P5xx andSTM32L4Q5xx only.
Bit 10 APC: Apply pull-up and pull-down configuration
When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx
and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and
PWR_PDCRx registers are not applied to the I/Os, instead the I/Os will be in floating mode
during Standby or configured according GPIO controller GPIOx_PUPDR register during Run
mode.
Bit 9:8 RRS[1:0]: SRAM2 retention in Standby mode
For STM32L4Rxxx and STM32L4Sxxx devices bit 9 is reserved
0: SRAM2 is powered off in Standby mode (SRAM2 content is lost).
1: SRAM2 is powered by the low-power regulator in Standby mode (SRAM2 content is kept).
For STM32L4P5xx and STM32L4Q5xx devices:
00: SRAM2 is powered off in Standby mode (SRAM2 content is lost).
01: Full SRAM2 is powered by the low-power regulator in Standby mode (SRAM2 full content
is kept).
10: Only 4 Kbytes of SRAM2 is powered by the low-power regulator in Standby mode
(4 Kbytes of SRAM2 content is kept)
11: reserved.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 EWUP5: Enable Wakeup pin WKUP5
When this bit is set, the external wakeup pin WKUP5 is enabled and triggers a wakeup from
Standby or Shutdown event when a rising or a falling edge occurs.The active edge is
configured via the WP5 bit in the PWR_CR4 register.
Bit 3 EWUP4: Enable Wakeup pin WKUP4
When this bit is set, the external wakeup pin WKUP4 is enabled and triggers a wakeup from
Standby or Shutdown event when a rising or a falling edge occurs. The active edge is
configured via the WP4 bit in the PWR_CR4 register.

220/2301 RM0432 Rev 6

RM0432 Power control (PWR)

Bit 2 EWUP3: Enable Wakeup pin WKUP3

When this bit is set, the external wakeup pin WKUP3 is enabled and triggers a wakeup from
Standby or Shutdown event when a rising or a falling edge occurs. The active edge is
configured via the WP3 bit in the PWR_CR4 register.
Bit 1 EWUP2: Enable Wakeup pin WKUP2
When this bit is set, the external wakeup pin WKUP2 is enabled and triggers a wakeup from
Standby or Shutdown event when a rising or a falling edge occurs. The active edge is
configured via the WP2 bit in the PWR_CR4 register.
Bit 0 EWUP1: Enable Wakeup pin WKUP1
When this bit is set, the external wakeup pin WKUP1 is enabled and triggers a wakeup from
Standby or Shutdown event when a rising or a falling edge occurs. The active edge is
configured via the WP1 bit in the PWR_CR4 register.

5.4.4 Power control register 4 (PWR_CR4)

Address offset: 0x0C
Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with
the PWRRST bit in the RCC_APB1RSTR1 register)
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXT_S
Res. Res. MPS_O Res. Res. Res. VBRS VBE Res. Res. Res. WP5 WP4 WP3 WP2 WP1
N
rw rw rw rw rw rw rw rw

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 EXT_SMPS_ON: external SMPS on.
This bit informs the internal regulator about external SMPS switch status to decrease regulator
output to 0.95 V in Range 2, allowing the external SMPS output down to 1.00 V.
0: the external SMPS switch is open.
1: the external SMPS switch is closed, internal regulator output is set to 0.95 V.
Note: This bit is only available on STM32L4P5xx and STM32L4Q5xx devices.
Bits 12:10 Reserved, must be kept at reset value.
Bit 9 VBRS: VBAT battery charging resistor selection
0: Charge VBAT through a 5 kOhms resistor
1: Charge VBAT through a 1.5 kOhms resistor
Bit 8 VBE: VBAT battery charging enable
0: VBAT battery charging disable
1: VBAT battery charging enable
Bits 7:5 Reserved, must be kept at reset value.

RM0432 Rev 6 221/2301

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Power control (PWR) RM0432

Bit 4 WP5: Wakeup pin WKUP5 polarity

This bit defines the polarity used for an event detection on external wake-up pin, WKUP5
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
Bit 3 WP4: Wakeup pin WKUP4 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP4
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
Bit 2 WP3: Wakeup pin WKUP3 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP3
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
Bit 1 WP2: Wakeup pin WKUP2 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP2
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
Bit 0 WP1: Wakeup pin WKUP1 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP1
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)

5.4.5 Power status register 1 (PWR_SR1)

Address offset: 0x10
Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with
the PWRRST bit in the RCC_APB1RSTR1 register)
Access: 2 additional APB cycles are needed to read this register vs. a standard APB read.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXT_S
WUFI Res. MPS_R Res. Res. Res. Res. SBF Res. Res. Res. WUF5 WUF4 WUF3 WUF2 WUF1
DY
r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 WUFI: Wakeup flag internal
This bit is set when a wakeup is detected on the internal wakeup line. It is cleared when all
internal wakeup sources are cleared.
Bit 14 Reserved, must be kept at reset value.

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RM0432 Power control (PWR)

Bit 13 EXT_SMPS_RDY: External SMPS ready

This bit informs the state of regulator transition from Range 1 to Range 2
0: Internal regulator not ready in Range 2, the external SMPS cannot be connected
1: Internal regulator ready in Range 2, the external SMPS can be connected
Note: This bit is only available on STM32L4P5xx and STM32L4Q5xx devices.
Bits 12:9 Reserved, must be kept at reset value.
Bit 8 SBF: Standby flag
This bit is set by hardware when the device enters the Standby mode and is cleared by
setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the
system reset.
0: The device did not enter the Standby mode
1: The device entered the Standby mode
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 WUF5: Wakeup flag 5
This bit is set when a wakeup event is detected on wakeup pin, WKUP5. It is cleared by
writing ‘1’ in the CWUF5 bit of the PWR_SCR register.
Bit 3 WUF4: Wakeup flag 4
This bit is set when a wakeup event is detected on wakeup pin,WKUP4. It is cleared by
writing ‘1’ in the CWUF4 bit of the PWR_SCR register.
Bit 2 WUF3: Wakeup flag 3
This bit is set when a wakeup event is detected on wakeup pin, WKUP3. It is cleared by
writing ‘1’ in the CWUF3 bit of the PWR_SCR register.
Bit 1 WUF2: Wakeup flag 2
This bit is set when a wakeup event is detected on wakeup pin, WKUP2. It is cleared by
writing ‘1’ in the CWUF2 bit of the PWR_SCR register.
Bit 0 WUF1: Wakeup flag 1
This bit is set when a wakeup event is detected on wakeup pin, WKUP1. It is cleared by
writing ‘1’ in the CWUF1 bit of the PWR_SCR register.

5.4.6 Power status register 2 (PWR_SR2)

Address offset: 0x14
Reset value: 0x0000 0000 (This register is partially reset when exiting Standby/Shutdown
modes)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGLP REGLP
PVMO4 PVMO3 PVMO2 PVMO1 PVDO VOSF Res. Res. Res. Res. Res. Res. Res. Res.
F S
r r r r r r r r

RM0432 Rev 6 223/2301

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Power control (PWR) RM0432

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 PVMO4: Peripheral voltage monitoring output: VDDA vs. 2.2 V
0: VDDA voltage is above PVM4 threshold (around 2.2 V).
1: VDDA voltage is below PVM4 threshold (around 2.2 V).
Note: PVMO4 is cleared when PVM4 is disabled (PVME4 = 0). After enabling PVM4, the
PVM4 output is valid after the PVM4 wakeup time.
Bit 14 PVMO3: Peripheral voltage monitoring output: VDDA vs. 1.62 V
0: VDDA voltage is above PVM3 threshold (around 1.62 V).
1: VDDA voltage is below PVM3 threshold (around 1.62 V).
Note: PVMO3 is cleared when PVM3 is disabled (PVME3 = 0). After enabling PVM3, the
PVM3 output is valid after the PVM3 wakeup time.
Bit 13 PVMO2: Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V
0: VDDIO2 voltage is above PVM2 threshold (around 0.9 V).
1: VDDIO2 voltage is below PVM2 threshold (around 0.9 V).
Note: PVMO2 is cleared when PVM2 is disabled (PVME2 = 0). After enabling PVM2, the
PVM2 output is valid after the PVM2 wakeup time.
Bit 12 PVMO1: Peripheral voltage monitoring output: VDDUSB vs. 1.2 V
0: VDDUSB voltage is above PVM1 threshold (around 1.2 V).
1: VDDUSB voltage is below PVM1 threshold (around 1.2 V).
Note: PVMO1 is cleared when PVM1 is disabled (PVME1 = 0). After enabling PVM1, the
PVM1 output is valid after the PVM1 wakeup time.
Bit 11 PVDO: Power voltage detector output
0: VDD is above the selected PVD threshold
1: VDD is below the selected PVD threshold
Bit 10 VOSF: Voltage scaling flag
A delay is required for the internal regulator to be ready after the voltage scaling has been
changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits
of the PWR_CR1 register.
0: The regulator is ready in the selected voltage range
1: The regulator output voltage is changing to the required voltage level
Bit 9 REGLPF: Low-power regulator flag
This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits
from the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode.
A polling on this bit must be done before increasing the product frequency.
This bit is cleared by hardware when the regulator is ready.
0: The regulator is ready in main mode (MR)
1: The regulator is in low-power mode (LPR)
Bit 8 REGLPS: Low-power regulator started
This bit provides the information whether the low-power regulator is ready after a power-on
reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still
cleared, the wakeup from Standby mode time may be increased.
0: The low-power regulator is not ready
1: The low-power regulator is ready
Bits 7:0 Reserved, must be kept at reset value.

5.4.7 Power status clear register (PWR_SCR)

Address offset: 0x18

224/2301 RM0432 Rev 6

RM0432 Power control (PWR)

Reset value: 0x0000 0000

Access: 3 additional APB cycles are needed to write this register vs. a standard APB write.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CWUF CWUF CWUF CWUF CWUF
Res. Res. Res. Res. Res. Res. Res. CSBF Res. Res. Res.
5 4 3 2 1
w w w w w w

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 CSBF: Clear standby flag
Setting this bit clears the SBF flag in the PWR_SR1 register.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 CWUF5: Clear wakeup flag 5
Setting this bit clears the WUF5 flag in the PWR_SR1 register.
Bit 3 CWUF4: Clear wakeup flag 4
Setting this bit clears the WUF4 flag in the PWR_SR1 register.
Bit 2 CWUF3: Clear wakeup flag 3
Setting this bit clears the WUF3 flag in the PWR_SR1 register.
Bit 1 CWUF2: Clear wakeup flag 2
Setting this bit clears the WUF2 flag in the PWR_SR1 register.
Bit 0 CWUF1: Clear wakeup flag 1
Setting this bit clears the WUF1 flag in the PWR_SR1 register.

5.4.8 Power Port A pull-up control register (PWR_PUCRA)

Address offset: 0x20.
Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with
PWRRST bit in the RCC_APB1RSTR1 register)
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PU15 Res. PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Power control (PWR) RM0432

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 PU15: Port A pull-up bit 15
When set, this bit activates the pull-up on PA[15] when APC bit is set in PWR_CR3 register.
If the corresponding PD15 bit is also set, the pull-up is not activated and the pull-down is
activated instead with highest priority.
Bit 14 Reserved, must be kept at reset value.
Bits 13:0 PUy: Port A pull-up bit y (y=0...13)
When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register.
The pull-up is not activated if the corresponding PDy bit is also set.

5.4.9 Power Port A pull-down control register (PWR_PDCRA)

Address offset: 0x24.
Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with
PWRRST bit in the RCC_APB1RSTR1 register)
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. PD14 Res. PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 PD14: Port A pull-down bit 14
When set, this bit activates the pull-down on PA[14] when APC bit is set in PWR_CR3
register.
Bit 13 Reserved, must be kept at reset value.
Bits 12:0 PDy: Port A pull-down bit y (y=0..12)
When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.

5.4.10 Power Port B pull-up control register (PWR_PUCRB)

Address offset: 0x28.
Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with
PWRRST bit in the RCC_APB1RSTR1 register)
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

226/2301 RM0432 Rev 6

RM0432 Power control (PWR)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy: Port B pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
The pull-up is not activated if the corresponding PDy bit is also set.

5.4.11 Power Port B pull-down control register (PWR_PDCRB)

Address offset: 0x2C.
Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with
PWRRST bit in the RCC_APB1RSTR1 register)
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 Res. PD3 PD2 PD1 PD0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:5 PDy: Port B pull-down bit y (y=5..15)
When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
Bit 4 Reserved, must be kept at reset value.
Bits 3:0 PDy: Port B pull-down bit y (y=0..3)
When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.

5.4.12 Power Port C pull-up control register (PWR_PUCRC)

Address offset: 0x30.
Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with
PWRRST bit in the RCC_APB1RSTR1 register)
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

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Power control (PWR) RM0432

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy: Port C pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register.
The pull-up is not activated if the corresponding PDy bit is also set.

5.4.13 Power Port C pull-down control register (PWR_PDCRC)

Address offset: 0x34.
Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with
PWRRST bit in the RCC_APB1RSTR1 register)
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy: Port C pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.

5.4.14 Power Port D pull-up control register (PWR_PUCRD)

Address offset: 0x38.
Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with
PWRRST bit in the RCC_APB1RSTR1 register)
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

228/2301 RM0432 Rev 6

RM0432 Power control (PWR)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy: Port D pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register.
The pull-up is not activated if the corresponding PDy bit is also set.

5.4.15 Power Port D pull-down control register (PWR_PDCRD)

Address offset: 0x3C.
Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with
PWRRST bit in the RCC_APB1RSTR1 register)
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy: Port D pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.

5.4.16 Power Port E pull-up control register (PWR_PUCRE)

Address offset: 0x20.
Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with
PWRRST bit in the RCC_APB1RSTR1 register)
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

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Power control (PWR) RM0432

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy: Port E pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register.
The pull-up is not activated if the corresponding PDy bit is also set.

5.4.17 Power Port E pull-down control register (PWR_PDCRE)

Address offset: 0x44.
Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with
PWRRST bit in the RCC_APB1RSTR1 register)
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy: Port E pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.

5.4.18 Power Port F pull-up control register (PWR_PUCRF)

Address offset: 0x48.
Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with
PWRRST bit in the RCC_APB1RSTR1 register)
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

230/2301 RM0432 Rev 6

RM0432 Power control (PWR)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy: Port F pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register.
The pull-up is not activated if the corresponding PDy bit is also set.

5.4.19 Power Port F pull-down control register (PWR_PDCRF)

Address offset: 0x4C.
Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with
PWRRST bit in the RCC_APB1RSTR1 register)
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy: Port F pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register.

5.4.20 Power Port G pull-up control register (PWR_PUCRG)

Address offset: 0x50.
Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with
PWRRST bit in the RCC_APB1RSTR1 register)
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

RM0432 Rev 6 231/2301

237
Power control (PWR) RM0432

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy: Port G pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register.
The pull-up is not activated if the corresponding PDy bit is also set.

5.4.21 Power Port G pull-down control register (PWR_PDCRG)

Address offset: 0x54.
Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with
PWRRST bit in the RCC_APB1RSTR1 register)
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16
Reserved, must be kept at reset value.

Bits 15:0 PDy: Port G pull-down bit y (y=0..15)

When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register.

5.4.22 Power Port H pull-up control register (PWR_PUCRH)

Address offset: 0x58.
Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with
PWRRST bit in the RCC_APB1RSTR1 register)
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

232/2301 RM0432 Rev 6

RM0432 Power control (PWR)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy: Port H pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register.
The pull-up is not activated if the corresponding PDy bit is also set.

5.4.23 Power Port H pull-down control register (PWR_PDCRH)

Address offset: 0x5C.
Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with
PWRRST bit in the RCC_APB1RSTR1 register)
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy: Port H pull-down bit x (y =15...0)
When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register.

5.4.24 Power Port I pull-up control register (PWR_PUCRI)

Address offset: 0x60.
Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with
PWRRST bit in the RCC_APB1RSTR1 register)
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

RM0432 Rev 6 233/2301

237
Power control (PWR) RM0432

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 11:0 PUy: Port I pull-up bit y (y=0..11)
When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register.
The pull-up is not activated if the corresponding PDy bit is also set.

5.4.25 Power Port I pull-down control register (PWR_PDCRI)

Address offset: 0x64.
Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with
PWRRST bit in the RCC_APB1RSTR1 register)
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 11:0 PDy: Port I pull-down bit y (y=0..11)
When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register.

5.4.26 PWR control register (PWR_CR5)

Address offset: 0x80.
Reset value: 0x0000 0100 (This register is not reset after a wakeup from Standby mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. R1MODE Res. Res. Res. Res. Res. Res. Res. Res.

rw

234/2301 RM0432 Rev 6

RM0432 Power control (PWR)

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 R1MODE: Main regulator Range 1 mode
This bit is only valid for the main regulator in Range 1 and has no effect on Range 2. It is
recommended to reset this bit when the system frequency is greater than 80 MHz. Refer to
Table 24: Range 1 boost mode configuration.
0: Main regulator in Range 1 boost mode.
1: Main regulator in Range 1 normal mode.
Bits 7:0 Reserved, must be kept at reset value.

RM0432 Rev 6 235/2301

237
 0x034
0x030
0x028
0x024
0x020
0x018
0x014
0x010
0x008
0x004
0x000

0x02C
0x00C
Offset
5.4.27

236/2301
PWR_SR2
PWR_SR1
PWR_CR4
PWR_CR3
PWR_CR2
PWR_CR1

PWR_SCR
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

PWR_PDCRB
PWR_PUCRB
PWR_PDCRA
PWR_PUCRA

PWR_PDCRC
PWR_PUCRC
Power control (PWR)

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 18

RM0432 Rev 6
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 17
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 16
PWR register map and reset value table

0
0
0
0
0
0
0
0

PD15 PU15 PD15 PU15 Res. PU15 Res. PVMO4 WUFI Res. EIWUL Res. Res. 15

0
0
0
0
0
0
0

PD14 PU14 PD14 PU14 PD14 Res. Res. PVMO3 Res. Res. Res. Res. LPR 14

0
0
0
0
0
0
0
0

PD13 PU13 PD13 PU13 Res. PU13 Res. PVMO2 EXT_SMPS_RDY(1) EXT_SMPS_ON(1) Res. Res. Res. 13

0
0
0
0
0
0
0
1

PD12 PU12 PD12 PU12 PD12 PU12 Res. PVMO1 Res. Res. DSIPDEN. Res. Res. 12

0
0
0
0
0
0
0
1

PD11 PU11 PD11 PU11 PD11 PU11 Res. PVDO Res. Res. Res. Res.
Table 36. PWR register map and reset values

ENULP(1) 11

0
0
0
0
0
0
0
1
0
0

PD10 PU10 PD10 PU10 PD10 PU10 Res. VOSF Res. Res. APC USV 10
[1:0]
VOS

0
0
0
0
0
0
0
0
1
0
1

PD9 PU9 PD9 PU9 PD9 PU9 Res. REGLPF Res. VBRS IOSV 9
RRS(1)

0
0
0
0
0
0
0

0
0
0
1
0

PD8 PU8 PD8 PU8 PD8 PU8 CSBF REGLPS SBF VBE Res. DBP 8

0
0
0
0
0
0
0

PD7 PU7 PD7 PU7 PD7 PU7 Res. Res. Res. Res. Res. PVME4 Res. 7

0
0
0
0
0
0
0

PD6 PU6 PD6 PU6 PD6 PU6 Res. Res. Res. Res. Res. PVME3 Res. 6

0
0
0
0
0
0
0

PD5 PU5 PD5 PU5 PD5 PU5 Res. Res. Res. Res. Res. PVME2 Res. 5

0
0
0
0
0
0
0
0
0
0
0

PD4 PU4 Res. PU4 PD4 PU4 CWUF5 Res. WUF5 WP5 EWUP5 PVME1 RRSTP 4

0
0
0
0
0
0
0
0
0
0
0

PD3 PU3 PD3 PU3 PD3 PU3 CWUF4 Res. WUF4 WP4 EWUP4 Res. 3

0
0
0
0
0
0
0
0

0
0
0
0

PD2 PU2 PD2 PU2 PD2 PU2 CWUF3 Res. WUF3 WP3 EWUP3 2

0
0
0
0
0
0
0
0

0
0
0
0

PLS [2:0]

PD1 PU1 PD1 PU1 PD1 PU1 CWUF2 Res. WUF2 WP2 EWUP2 1
[2:0]
LPMS

0
0
0
0
0
0
0
0

0
0
0
0

PD0 PU0 PD0 PU0 PD0 PU0 CWUF1 Res. WUF1 WP1 EWUP1 PVDE 0
RM0432
 0x080
0x064
0x060
0x058
0x054
0x050
0x048
0x044
0x040
0x038

0x05C
0x04C
0x03C
Offset
RM0432

PWR_CR5
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

PWR_PDCRI
PWR_PUCRI
PWR_PDCRF
PWR_PUCRF
PWR_PDCRE
PWR_PUCRE

PWR_PDCRH
PWR_PUCRH
PWR_PDCRD
PWR_PUCRD

PWR_PDCRG
PWR_PUCRG

Availability of peripherals.
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 18

RM0432 Rev 6
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 17
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 16

0
0
0
0
0
0
0
0
0
0

Res. Res. Res. PD15 PU15 PD15 PU15 PD15 PU15 PD15 PU15 PD15 PU15 15

0
0
0
0
0
0
0
0
0
0

Res. Res. Res. PD14 PU14 PD14 PU14 PD14 PU14 PD14 PU14 PD14 PU14 14

0
0
0
0
0
0
0
0
0
0

Res. Res. Res. PD13 PU13 PD13 PU13 PD13 PU13 PD13 PU13 PD13 PU13 13

0
0
0
0
0
0
0
0
0
0

Res. Res. Res. PD12 PU12 PD12 PU12 PD12 PU12 PD12 PU12 PD12 PU12 12

0
0
0
0
0
0
0
0
0
0
0
0

Res. PD11 PU11 PD11 PU11 PD11 PU11 PD11 PU11 PD11 PU11 PD11 PU11 11

0
0
0
0
0
0
0
0
0
0
0
0

Res. PD10 PU10 PD10 PU10 PD10 PU10 PD10 PU10 PD10 PU10 PD10 PU10 10

0
0
0
0
0
0
0
0
0
0
0
0

Res. PD9 PU9 PD9 PU9 PD9 PU9 PD9 PU9 PD9 PU9 PD9 PU9 9

Refer to Section 2.2 on page 91 for the register boundary addresses.

Table 36. PWR register map and reset values (continued)

0
0
0
0
0
0
0
0
0
0
0

1
0
R1MODE PD8 PU8 PD8 PU8 PD8 PU8 PD8 PU8 PD8 PU8 PD8 PU8 8

0
0
0
0
0
0
0
0
0
0
0
0

Res. PD7 PU7 PD7 PU7 PD7 PU7 PD7 PU7 PD7 PU7 PD7 PU7 7

0
0
0
0
0
0
0
0
0
0
0
0

Res. PD6 PU6 PD6 PU6 PD6 PU6 PD6 PU6 PD6 PU6 PD6 PU6 6

0
0
0
0
0
0
0
0
0
0
0
0

Res. PD5 PU5 PD5 PU5 PD5 PU5 PD5 PU5 PD5 PU5 PD5 PU5 5

0
0
0
0
0
0
0
0
0
0
0
0

Res. PD4 PU4 PD4 PU4 PD4 PU4 PD4 PU4 PD4 PU4 PD4 PU4 4

1. The availability of this bit/bitfield depends on product part numbers. For additional information refer to Section 1.4:
0
0
0
0
0
0
0
0
0
0
0
0

Res. PD3 PU3 PD3 PU3 PD3 PU3 PD3 PU3 PD3 PU3 PD3 PU3 3

0
0
0
0
0
0
0
0
0
0
0
0

Res. PD2 PU2 PD2 PD2 PD2 PU2 PD2 PU2 PD2 PU2 PD2 PU2 2

0
0
0
0
0
0
0
0
0
0
0
0

Res. PD1 PU1 PD1 PU1 PD1 PU1 PD1 PU1 PD1 PU1 PD1 PU1 1
0
0
0
0
0
0
0
0
0
0
0
0

Res. PD0 PU0 PD0 PU0 PD0 PU0 PD0 PU0 PD0 PU0 PD0 PU0 0
Power control (PWR)

237/2301
237
Reset and clock control (RCC) RM0432

6 Reset and clock control (RCC)

6.1 Reset
There are three types of reset, defined as system reset, power reset and backup domain
reset.

6.1.1 Power reset

A power reset is generated when one of the following events occurs:
1. a Brown-out reset (BOR).
2. when exiting from Standby mode.
3. when exiting from Shutdown mode.
A Brown-out reset, including power-on or power-down reset (POR/PDR), sets all registers to
their reset values except the Backup domain.
When exiting Standby mode, all registers in the VCORE domain are set to their reset value.
Registers outside the VCORE domain (RTC, WKUP, IWDG, and Standby/Shutdown modes
control) are not impacted.
When exiting Shutdown mode, a Brown-out reset is generated, resetting all registers except
those in the Backup domain.

6.1.2 System reset

A system reset sets all registers to their reset values except the reset flags in the clock
control/status register (RCC_CSR) and the registers in the Backup domain.
A system reset is generated when one of the following events occurs:
1. A low level on the NRST pin (external reset)
2. Window watchdog event (WWDG reset)
3. Independent watchdog event (IWDG reset)
4. A firewall event (FIREWALL reset)
5. A software reset (SW reset) (see Software reset)
6. Low-power mode security reset (see Low-power mode security reset)
7. Option byte loader reset (see Option byte loader reset)
8. A Brown-out reset
The reset source can be identified by checking the reset flags in the Control/Status register,
RCC_CSR (see Section 6.4.30: Control/status register (RCC_CSR)).
These sources act on the NRST pin and it is always kept low during the delay phase. The
RESET service routine vector is fixed at address 0x0000_0004 in the memory map.
The system reset signal provided to the device is output on the NRST pin. The pulse
generator guarantees a minimum reset pulse duration of 20 µs for each internal reset
source. In case of an external reset, the reset pulse is generated while the NRST pin is
asserted low.
In case on an internal reset, the internal pull-up RPU is deactivated in order to save the
power consumption through the pull-up resistor.

238/2301 RM0432 Rev 6

RM0432 Reset and clock control (RCC)

Figure 15. Simplified diagram of the reset circuit

VDD
VDD / VDDA

RPU
RPU System reset

External
Filter System reset
reset NRST
WWDG reset
IWDG reset
Pulse Firewall reset
generator Software reset
(min 20 μs) Low-power manager reset
Option byte loader reset
BOR reset
MSv40966V1
MS33432V1

Software reset
The SYSRESETREQ bit in Cortex®-M4 Application Interrupt and Reset Control Register
must be set to force a software reset on the device (refer to the STM32F3, STM32F4,
STM32L4 and STM32L4+ Series Cortex®-M4 (PM0214)).

Low-power mode security reset

To prevent that critical applications mistakenly enter a low-power mode, two low-power
mode security resets are available. If enabled in option bytes, the resets are generated in
the following conditions:
1. Entering Standby mode: this type of reset is enabled by resetting nRST_STDBY bit in
User option Bytes. In this case, whenever a Standby mode entry sequence is
successfully executed, the device is reset instead of entering Standby mode.
2. Entering Stop mode: this type of reset is enabled by resetting nRST_STOP bit in User
option bytes. In this case, whenever a Stop mode entry sequence is successfully
executed, the device is reset instead of entering Stop mode.
3. Entering Shutdown mode: this type of reset is enabled by resetting nRST_SHDW bit in
User option bytes. In this case, whenever a Shutdown mode entry sequence is
successfully executed, the device is reset instead of entering Shutdown mode.
For further information on the User Option Bytes, refer to Section 3.4.1: Option bytes
description.

Option byte loader reset

The option byte loader reset is generated when the OBL_LAUNCH bit (bit 27) is set in the
FLASH_CR register. This bit is used to launch the option byte loading by software.

6.1.3 Backup domain reset

The backup domain has two specific resets.
A backup domain reset is generated when one of the following events occurs:

RM0432 Rev 6 239/2301

320
Reset and clock control (RCC) RM0432

1. Software reset, triggered by setting the BDRST bit in the Backup domain control
register (RCC_BDCR).
2. VDD or VBAT power on, if both supplies have previously been powered off.
A backup domain reset only affects the LSE oscillator, the RTC, the Backup registers and
the RCC Backup domain control register.

6.2 Clocks
Four different clock sources can be used to drive the system clock (SYSCLK):
• HSI16 (high speed internal)16 MHz RC oscillator clock
• MSI (multispeed internal) RC oscillator clock
• HSE oscillator clock, from 4 to 48 MHz
• PLL clock
The MSI is used as system clock source after startup from Reset, configured at 4 MHz.
The devices have the following additional clock sources:
• 32 kHz low speed internal RC (LSI RC) which drives the independent watchdog and
optionally the RTC used for Auto-wakeup from Stop and Standby modes.
• 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real-
time clock (RTCCLK).
• RC 48 MHz internal clock sources (HSI48) to potentially drive the USB FS, the
SDMMC and the RNG.
Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.
Several prescalers can be used to configure the AHB frequency, the APB1 and APB2
domains. The maximum frequency of the AHB, the APB1 and the APB2 domains is
120 MHz.

240/2301 RM0432 Rev 6

RM0432 Reset and clock control (RCC)

All the peripheral clocks are derived from their bus clock (HCLK, PCLK1 or PCLK2) except:
• The 48 MHz clock, used for USB OTG FS, SDMMC and RNG. This clock is derived
(selected by software) from one of the four following sources:
– main PLL VCO (PLL48M1CLK)
– PLLSAI1 VCO (PLL48M2CLK)
– MSI clock
– HSI48 internal oscillator
When the MSI clock is auto-trimmed with the LSE, it can be used by the USB OTG FS
device.
When available, the HSI48 48 MHz clock can be coupled to the clock recovery system
allowing adequate clock connection for the USB OTG FS (Crystal less solution).
• The ADCs clock which is derived (selected by software) from one of the following
sources:
– system clock (SYSCLK)
– PLLSAI1 VCO (PLLADC1CLK)
• The U(S)ARTs clocks which are derived (selected by software) from one of the four
following sources:
– system clock (SYSCLK)
– HSI16 clock
– LSE clock
– APB1 or APB2 clock (PCLK1 or PCLK2 depending on which APB is mapped the
U(S)ART)
The wakeup from Stop mode is supported only when the clock is HSI16 or LSE.
• The I2Cs clocks which are derived (selected by software) from one of the three
following sources:
– system clock (SYSCLK)
– HSI16 clock
– APB1 clock (PCLK1)
The wakeup from Stop mode is supported only when the clock is HSI16.
• The SAI1 and SAI2 clocks which are derived (selected by software) from one of the
following sources:
– an external clock mapped on SAI1_EXTCLK for SAI1 and SAI2_EXTCLK for SAI2
– PLLSAI1 VCO (PLLSAI1CLK)
– PLLSAI2 VCO (PLLSAI2CLK)
– main PLL VCO (PLLSAI3CLK)
– HSI16 clock
• The DFSDM audio clock which is derived (selected by software) from one of the
following sources:
– SAI1 clock
– HSI clock
– MSI clock
• The LTDC clock. The LTDC clock is generated from a specific PLL (PLLSAI2).
• The DSI clock. To generate the DSI clocks, the high-speed external crystal (HSE) must
be available.

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– The DSI lanebyteclk clock: DSI Lane byte clock (high-speed clock divided by 8)
which is output from the DSI-PHY or from a specific output of PLLSAI2 (frequency
lower than 62.5 MHz) in the case when the DSI-PHY is off.
– The DSI host rxclkesc clock. The DSI RX escape mode clock is output from DSI-
PHY (generated from DP0/DN0 even if the DSI-PHY is not clocked).
• The OctoSPI kernel clock which is derived (selected by software) from one of the
following sources:
– System clock,
– PLL48M1CLK
– MSI clock
• The low-power timers (LPTIMx) clock which are derived (selected by software) from
one of the five following sources:
– LSI clock
– LSE clock
– HSI16 clock
– APB1 clock (PCLK1)
– External clock mapped on LPTIMx_IN1
The functionality in Stop mode (including wakeup) is supported only when the clock is
LSI or LSE, or in external clock mode.
• The RTC clock which is derived (selected by software) from one of the three following
sources:
– LSE clock
– LSI clock
– HSE clock divided by 32
The functionality in Stop mode (including wakeup) is supported only when the clock is
LSI or LSE.
• The IWDG clock which is always the LSI clock.
The RCC feeds the Cortex® System Timer (SysTick) external clock with the AHB clock
(HCLK) divided by 8. The SysTick can work either with this clock or directly with the Cortex®
clock (HCLK), configurable in the SysTick Control and Status Register.
FCLK acts as Cortex®-M4 free-running clock. For more details refer to the STM32F3,
STM32F4, STM32L4 and STM32L4+ Series Cortex®-M4 programming manual (PM0214).

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Figure 16. Clock tree for STM32L4Rxxx and STM32L4Sxxx devices

to IWDG
LSI RC 32 kHz

LSCO

to RTC
OSC32_OUT
LSE OSC
/32
32.768 kHz
OSC32_IN
LSE to PWR
LSI
MSI to AHB bus, core, memory and DMA
MCO HSI16
/ 1→16 HSE AHB PRESC HCLK FCLK Cortex free running clock
SYSCLK / 1,2,..512
PLLCLK to Cortex system timer
HSI48 /8
Clock
source APB1 PRESC PCLK1
control / 1,2,4,8,16 to APB1 peripherals
OSC_OUT HSE OSC
4-48 MHz
HSE x1 or x2
to TIMx
OSC_IN Clock MSI x=2..7
SYSCLK
detector HSI16 LSE
HSI16 to USARTx
SYSCLK x=2..5
HSI RC to LPUART1
16 MHz

HSI16
MSI RC SYSCLK to I2Cx
100 kHz – 48 MHz x=1,2,3,4

RC 48 MHz LSI
LSE to LPTIMx
HSI16 x=1,2
MSI
PLL HSI16 MSI
/M
HSE OCTOSPI clock
/P PLLSAI3CLK

/Q PLL48M1CLK CRS clock

PLLCLK PCLK2
/R APB2 PRESC
to APB2 peripherals
/ 1,2,4,8,16
HSI16 x1 or x2
/M
PLLSAI1 to TIMx
PLLSAI1CLK x=1,8,15,16,17
/P
/Q PLL48M2CLK
LSE
PLLADC1CLK HSI16 to
/R SYSCLK USART1

SDMMC clock
HSI16 MSI
48 MHz clock to USB, RNG

SYSCLK
to ADC

DSIHOST
≤ 20 MHz rxclkesc clock
HSE DSI
PLL DSI - PHY ≤ 62.5 MHz
≤ 62.5 MHz DSIHOST
MSI byte lane clock
/M
PLLSAI2 HSI16
/P PLLSAI2CLK DFSDM
PLLDSICLK audio clock
/Q
PLLLCDCLK HSI16 to SAI1
/R

PLLSAI2DIVR LTDC clock

SAI1_EXTCLK
to SAI2
SAI2_EXTCLK
MSv45251V3

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1. For full details about the internal and external clock source characteristics, please refer to the “Electrical
characteristics” section in your device datasheet.
2. The ADC clock can be derived from the AHB clock of the ADC bus interface, divided by a programmable
factor (1, 2 or 4). When the programmable factor is ‘1’, the AHB prescaler must be equal to ‘1’.

Figure 17. DSI clock tree

/TXECKDIV txclkesc clock

20 MHz max
/TOCKDIV Timeout clock

DSIHOST

PLLDSICLK
(from PLLSAI2/Q) Peripheral
62.5 MHz clock enable
High max DSIHOST lane byte clock
Speed 62.5 MHz
62.5 MHz max

/IDF VCO /ODF

Clock /8 max
HSE Peripheral
500 MHz
clock enable
max
xNDIV DSIHOST rxclkesc clock
20 MHz 20 MHz max
PLL DSI PHY DSI max
RCC

DSI clock control bits (IDF, ODF, NDIV, TXECKDIV and TOCKDIV)
are configured by DSIHOST registers.
MSv43406V1

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Figure 18. Clock tree for STM32L4P5xx and STM32L4Q5xx devices

to IWDG
LSI RC 32 kHz

LSCO

to RTC
OSC32_OUT
LSE OSC
/32
32.768 kHz
OSC32_IN
LSE to PWR
LSI
MSI to AHB bus, core, memory and DMA
MCO HSI16
/ 1→16 HSE AHB PRESC HCLK FCLK Cortex free running clock
SYSCLK / 1,2,..512
PLLCLK to Cortex system timer
HSI48 /8
Clock
source APB1 PRESC PCLK1
control / 1,2,4,8,16 to APB1 peripherals
OSC_OUT HSE OSC
4-48 MHz
HSE x1 or x2
to TIMx
OSC_IN Clock MSI x=2..7
SYSCLK
detector HSI16 LSE
HSI16 to USARTx
SYSCLK X=2..5
HSI RC to LPUART1
16 MHz

HSI16
MSI RC SYSCLK to I2Cx
100 kHz – 48 MHz x=1,2,3,4

RC 48 MHz LSI
LSE to LPTIMx
HSI16 x=1,2
MSI
PLL HSI16 MSI
/M to OCTOSPIx
HSE
/P PLLSAI3CLK x=1,2

/Q PLL48M1CLK CRS clock

PLLCLK PCLK2
/R APB2 PRESC
to APB2 peripherals
/ 1,2,4,8,16
HSI16 x1 or x2
/M
PLLSAI1 to TIMx
PLLSAI1CLK x=1,8,15,16,17
/P
/Q PLL48M2CLK
LSE
PLLADC1CLK HSI16 to
/R SYSCLK USART1

to SDMMCx
x=1,2
HSI16 MSI
48 MHz clock to USB, RNG

SYSCLK to ADCx
X=1,2

MSI
/M
PLLSAI2 HSI16
/P PLLSAI2CLK DFSDM
audio clock
/Q
PLLLCDCLK HSI16 to SAI1
/R

PLLSAI2DIVR LTDC clock

SAI1_EXTCLK
to SAI2
SAI2_EXTCLK
MSv61129V2

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6.2.1 HSE clock

The high speed external clock signal (HSE) can be generated from two possible clock
sources:
• HSE external crystal/ceramic resonator
• HSE user external clock
The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.

Figure 19. HSE/ LSE clock sources

Clock source Hardware configuration

OSC_IN OSC_OUT
External clock
GPIO

External
source

OSC_IN OSC_OUT
Crystal/Ceramic
resonators

CL1 CL2
Load
capacitors

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External crystal/ceramic resonator (HSE crystal)

The 4 to 48 MHz external oscillator has the advantage of producing a very accurate rate on
the main clock.
The associated hardware configuration is shown in Figure 19. Refer to the electrical
characteristics section of the datasheet for more details.
The HSERDY flag in the Clock control register (RCC_CR) indicates if the HSE oscillator is
stable or not. At startup, the clock is not released until this bit is set by hardware. An
interrupt can be generated if enabled in the Clock interrupt enable register (RCC_CIER).
The HSE Crystal can be switched on and off using the HSEON bit in the Clock control
register (RCC_CR).

External source (HSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to
48 MHz. You select this mode by setting the HSEBYP and HSEON bits in the Clock control
register (RCC_CR). The external clock signal (square, sinus or triangle) with ~40-60 % duty
cycle depending on the frequency (refer to the datasheet) has to drive the OSC_IN pin while
the OSC_OUT pin can be used a GPIO. See Figure 19.

6.2.2 HSI16 clock

The HSI16 clock signal is generated from an internal 16 MHz RC Oscillator.
The HSI16 RC oscillator has the advantage of providing a clock source at low cost (no
external components). It also has a faster startup time than the HSE crystal oscillator
however, even with calibration the frequency is less accurate than an external crystal
oscillator or ceramic resonator.
The HSI16 clock can be selected as system clock after wakeup from Stop modes (Stop 0,
Stop 1 or Stop 2). Refer to Section 6.3: Low-power modes. It can also be used as a backup
clock source (auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 6.2.10: Clock
security system (CSS).

Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations, this is why each device is factory calibrated by ST for 1 % accuracy at TA=25°C.
After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Internal
clock sources calibration register (RCC_ICSCR).
If the application is subject to voltage or temperature variations this may affect the RC
oscillator speed. You can trim the HSI16 frequency in the application using the
HSITRIM[6:0] in the Internal clock sources calibration register (RCC_ICSCR).
For more details on how to measure the HSI16 frequency variation, refer to Section 6.2.17:
Internal/external clock measurement with TIM15/TIM16/TIM17.
The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI16 RC is stable
or not. At startup, the HSI16 RC output clock is not released until this bit is set by hardware.
The HSI16 RC can be switched on and off using the HSION bit in the Clock control register
(RCC_CR).

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The HSI16 signal can also be used as a backup source (Auxiliary clock) if the HSE crystal
oscillator fails. Refer to Section 6.2.10: Clock security system (CSS) on page 252.

6.2.3 MSI clock

The MSI clock signal is generated from an internal RC oscillator. Its frequency range can be
adjusted by software by using the MSIRANGE[3:0] bits in the Clock control register
(RCC_CR). Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz,
1 MHz, 2 MHz, 4 MHz (default value), 8 MHz, 16 MHz, 24 MHz, 32 MHz and 48 MHz.
The MSI clock is used as system clock after restart from Reset, wakeup from Standby and
Shutdown low-power modes. After restart from Reset, the MSI frequency is set to its default
value 4 MHz. Refer to Section 6.3: Low-power modes.
The MSI clock can be selected as system clock after a wakeup from Stop mode (Stop 0,
Stop 1 or Stop 2). Refer to Section 6.3: Low-power modes. It can also be used as a backup
clock source (auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 6.2.10: Clock
security system (CSS).
The MSI RC oscillator has the advantage of providing a low-cost (no external components)
low-power clock source. In addition, when used in PLL-mode with the LSE, it provides a
very accurate clock source which can be used by the USB OTG FS device, and feed the
main PLL to run the system at the maximum speed.
The MSIRDY flag in the Clock control register (RCC_CR) indicates wether the MSI RC is
stable or not. At startup, the MSI RC output clock is not released until this bit is set by
hardware. The MSI RC can be switched on and off by using the MSION bit in the Clock
control register (RCC_CR).

Hardware auto calibration with LSE (PLL-mode)

When a 32.768 kHz external oscillator is present in the application, it is possible to configure
the MSI in a PLL-mode by setting the MSIPLLEN bit in the Clock control register (RCC_CR).
When configured in PLL-mode, the MSI automatically calibrates itself thanks to the LSE.
This mode is available for all MSI frequency ranges. At 48 MHz, the MSI in PLL-mode can
be used for the USB OTG FS device, saving the need of an external high-speed crystal.

Software calibration
The MSI RC oscillator frequency can vary from one chip to another due to manufacturing
process variations, this is why each device is factory calibrated by ST for 1 % accuracy at an
ambient temperature, TA, of 25 °C. After reset, the factory calibration value is loaded in the
MSICAL[7:0] bits in the Internal clock sources calibration register (RCC_ICSCR). If the
application is subject to voltage or temperature variations, this may affect the RC oscillator
speed. You can trim the MSI frequency in the application by using the MSITRIM[7:0] bits in
the RCC_ICSCR register. For more details on how to measure the MSI frequency variation
please refer to Section 6.2.17: Internal/external clock measurement with
TIM15/TIM16/TIM17.

6.2.4 HSI48 clock

The HSI48 clock signal is generated from an internal 48 MHz RC oscillator and can be used
directly for USB and for random number generator (RNG) as well as SDMMC.
The internal 48 MHz RC oscillator is mainly dedicated to provide a high precision clock to
the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. The CRS

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can use the USB SOF signal, the LSE or an external signal to automatically and quickly
adjust the oscillator frequency on-fly. It is disabled as soon as the system enters Stop or
Standby mode. When the CRS is not used, the HSI48 RC oscillator runs on its default
frequency which is subject to manufacturing process variations.
For more details on how to configure and use the CRS peripheral please refer to Section 7:
Clock recovery system (CRS).
The HSI48RDY flag in the Clock recovery RC register (RCC_CRRCR) indicates whether the
HSI48 RC oscillator is stable or not. At startup, the HSI48 RC oscillator output clock is not
released until this bit is set by hardware.
The HSI48 can be switched on and off using the HSI48ON bit in the Clock recovery RC
register (RCC_CRRCR).

6.2.5 PLL
The device embeds 3 PLLs: PLL, PLLSAI1, PLLSAI2. Each PLL provides up to three
independent outputs. The internal PLLs can be used to multiply the HSI16, HSE or MSI
output clock frequency. The PLLs input frequency must be between 4 and 16 MHz. The
selected clock source is divided by a programmable factor PLLM from 1 to 8 to provide a
clock frequency in the requested input range. Refer to Figure 16: Clock tree for
STM32L4Rxxx and STM32L4Sxxx devicesand PLL configuration register
(RCC_PLLCFGR).
The PLLs configuration (selection of the input clock and multiplication factor) must be done
before enabling the PLL. Once the PLL is enabled, these parameters cannot be changed.
To modify the PLL configuration, proceed as follows:
1. Disable the PLL by setting PLLON to 0 in Clock control register (RCC_CR).
2. Wait until PLLRDY is cleared. The PLL is now fully stopped.
3. Change the desired parameter.
4. Enable the PLL again by setting PLLON to 1.
5. Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, PLLREN in PLL
configuration register (RCC_PLLCFGR).
An interrupt can be generated when the PLL is ready, if enabled in the Clock interrupt
enable register (RCC_CIER).
The same procedure is applied for changing the configuration of the PLLSAI1 or PLLSAI2:
1. Disable the PLLSAI1/PLLSAI2 by setting PLLSAI1ON/PLLSAI2ON to 0 in Clock control
register (RCC_CR).
2. Wait until PLLSAI1RDY/PLLSAI2RDY is cleared. The PLLSAI1/PLLSAI2 is now fully
stopped.
3. Change the desired parameter.
4. Enable the PLLSAI1/PLLSAI2 again by setting PLLSAI1ON/PLLSAI2ON to 1.
5. Enable the desired PLL outputs by configuring PLLSAI1PEN/PLLSAI2PEN,
PLLSAI1QEN/PLLSAI2QEN, PLLSAI1REN/PLLSAI2REN in PLLSAI1 configuration
register (RCC_PLLSAI1CFGR) and PLLSAI2 configuration register
(RCC_PLLSAI2CFGR).
The PLL output frequency must not exceed 120 MHz.

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The enable bit of each PLL output clock (PLLPEN, PLLQEN, PLLREN, PLLSAI1PEN,
PLLSAI1QEN, PLLSAI1REN, PLLSAI2PEN and PLLSAI2REN) can be modified at any time
without stopping the corresponding PLL. PLLREN cannot be cleared if PLLCLK is used as
system clock.

6.2.6 LSE clock

The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the
advantage of providing a low-power but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off using the LSEON bit in Backup domain control
register (RCC_BDCR). The crystal oscillator driving strength can be changed at runtime
using the LSEDRV[1:0] bits in the Backup domain control register (RCC_BDCR) to obtain
the best compromise between robustness and short start-up time on one side and low-
power-consumption on the other side. The LSE drive can be decreased to the lower drive
capability (LSEDRV=00) when the LSE is ON. However, once LSEDRV is selected, the
drive capability can not be increased if LSEON=1.
The LSERDY flag in the Backup domain control register (RCC_BDCR) indicates whether
the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released
until this bit is set by hardware. An interrupt can be generated if enabled in the Clock
interrupt enable register (RCC_CIER).

Distribution of the external 32 kHz clock (LSE) outside the RTC block could be disabled by
setting LSESYSDIS bit in Backup domain control register (RCC_BDCR) to reduce power
consumption. Propagation is stopped regardless the use of LSE by other peripherals. This
feature is present only on STM32L4P5xx and STM32L4Q5xx devices.

External source (LSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to
1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the AHB1 peripheral
clocks enable in Sleep and Stop modes register (RCC_AHB1SMENR). The external clock
signal (square, sinus or triangle) with ~50 % duty cycle has to drive the OSC32_IN pin while
the OSC32_OUT pin can be used as GPIO. See Figure 19.

6.2.7 LSI clock

The LSI RC acts as a low-power clock source that can be kept running in Stop and Standby
mode for the independent watchdog (IWDG) RTC. The clock frequency is 32 kHz. For more
details, refer to the electrical characteristics section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the Control/status register
(RCC_CSR).
The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the LSI oscillator is
stable or not. At startup, the clock is not released until this bit is set by hardware. An
interrupt can be generated if enabled in the Clock interrupt enable register (RCC_CIER).

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6.2.8 System clock (SYSCLK) selection

Four different clock sources can be used to drive the system clock (SYSCLK):
• MSI oscillator
• HSI16 oscillator
• HSE oscillator
• PLL
The system clock maximum frequency is 120 MHz. After a system reset, the MSI oscillator,
at 4 MHz, is selected as system clock. When a clock source is used directly or through the
PLL as a system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is
selected, the switch will occur when the clock source becomes ready. Status bits in the
Internal clock sources calibration register (RCC_ICSCR) indicate which clock(s) is (are)
ready and which clock is currently used as a system clock.
To switch from low speed to high speed or from high speed to low speed system clock, it is
recommended to use a transition state with medium speed clock, for at least 1us.
Clock source switching conditions:
• Switching from HSE or HSI or MSI to PLL with AHB frequency (HCLK) higher than
80 MHz
• Switching from PLL with HCLK higher than 80 MHz to HSE or HSI or MSI
Transition state:
• Set the AHB prescaler HPRE[3:0] bits to divide the system frequency by 2
• Switch system clock to PLL
• Wait for at least 1us and then reconfigure AHB prescaler bits to the needed HCLK
frequency

6.2.9 Clock source frequency versus voltage scaling

The following table gives the different clock source frequencies depending on the product
voltage range.

Table 37. Clock source frequency

Clock frequency
Product voltage
range
MSI HSI16 HSE PLL/PLLSAI1/PLLSAI2

Range 1 Boost mode 48 MHz 16 MHz 48 MHz 120 MHz

Range 1 Normal mode 48 MHz 16 MHz 48 MHz 80 MHz
Range 2 24 MHz range 16 MHz 26 MHz 26 MHz

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6.2.10 Clock security system (CSS)

Clock Security System can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
If a failure is detected on the HSE clock, the HSE oscillator is automatically disabled, a clock
failure event is sent to the break input of the advanced-control timers (TIM1/TIM8 and
TIM15/16/17) and an interrupt is generated to inform the software about the failure (Clock
Security System Interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI
is linked to the Cortex®-M4 NMI (Non-Maskable Interrupt) exception vector.
Note: Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and a NMI is
automatically generated. The NMI will be executed indefinitely unless the CSS interrupt
pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt
by setting the CSSC bit in the Clock interrupt clear register (RCC_CICR).
If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is
used as PLL input clock, and the PLL clock is used as system clock), a detected failure
causes a switch of the system clock to the MSI or the HSI16 oscillator depending on the
STOPWUCK configuration in the Clock configuration register (RCC_CFGR), and the
disabling of the HSE oscillator. If the HSE clock (divided or not) is the clock entry of the PLL
used as system clock when the failure occurs, the PLL is disabled too.

6.2.11 Clock security system on LSE

A Clock Security System on LSE can be activated by software writing the LSECSSON bit in
the Backup domain control register (RCC_BDCR). This bit can be disabled only by a
hardware reset or RTC software reset, or after a failure detection on LSE. LSECSSON must
be written after LSE and LSI are enabled (LSEON and LSION enabled) and ready (LSERDY
and LSIRDY set by hardware), and after the RTC clock has been selected by RTCSEL and
LSIPREDIV is disabled.
Note: LSIPREDIV bit is available only on STM32L4P5xx and STM32L4Q5xx devices.
The CSS on LSE is working in all modes except VBAT. It is working also under system reset
(excluding power on reset). If a failure is detected on the external 32 kHz oscillator, the LSE
clock is no longer supplied to the RTC but no hardware action is made to the registers. If the
MSI was in PLL-mode, this mode is disabled.
In Standby mode a wakeup is generated. In other modes an interrupt can be sent to wakeup
the software (see Clock interrupt enable register (RCC_CIER), Clock interrupt flag register
(RCC_CIFR), Clock interrupt clear register (RCC_CICR)).
The software MUST then disable the LSECSSON bit, stop the defective 32 kHz oscillator
(disabling LSEON), and change the RTC clock source (no clock or LSI or HSE, with
RTCSEL), or take any required action to secure the application.
The frequency of LSE oscillator have to be higher than 30 kHz to avoid false positive CSS
detection.

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6.2.12 ADC clock

The ADC clock is derived from the system clock, or from the PLLSAI1 output. It can reach
120 MHz and can be divided by the following prescalers values:
1,2,4,6,8,10,12,16,32,64,128 or 256 by configuring the ADC1_CCR register. It is
asynchronous to the AHB clock. Alternatively, the ADC clock can be derived from the AHB
clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). This
programmable factor is configured using the CKMODE bit fields in the ADC123_CCR.
If the programmed factor is ‘1’, the AHB prescaler must be set to ‘1’.

6.2.13 RTC clock

The RTCCLK clock source can be either the HSE/32, LSE or LSI clock. It is selected by
programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR).
This selection cannot be modified without resetting the Backup domain. The system must
always be configured so as to get a PCLK frequency greater then or equal to the RTCCLK
frequency for a proper operation of the RTC.
The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not.
Consequently:
• If LSE is selected as RTC clock:
– The RTC continues to work even if the VDD supply is switched off, provided the
VBAT supply is maintained.
• If LSI is selected as the RTC clock:
– The RTC state is not guaranteed if the VDD supply is powered off.
• If the HSE clock divided by a prescaler is used as the RTC clock:
– The RTC state is not guaranteed if the VDD supply is powered off or if the internal
voltage regulator is powered off (removing power from the VCORE domain).
When the RTC clock is LSE or LSI, the RTC remains clocked and functional under system
reset.

6.2.14 Timer clock

The timer clock frequencies are automatically defined by hardware. There are two cases:
1. If the APB prescaler equals 1, the timer clock frequencies are set to the same
frequency as that of the APB domain.
2. Otherwise, they are set to twice (×2) the frequency of the APB domain.

6.2.15 Watchdog clock

If the Independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.

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6.2.16 Clock-out capability

• MCO
The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin. One of eight clock signals can be selected as the MCO clock.
– LSI
– LSE
– SYSCLK
– HSI16
– HSI48
– HSE
– PLLCLK
– MSI
The selection is controlled by the MCOSEL[3:0] bits of the Clock configuration register
(RCC_CFGR). The selected clock can be divided with the MCOPRE[2:0] field of the
Clock configuration register (RCC_CFGR).
• LSCO
Another output (LSCO) allows a low speed clock to be output onto the external LSCO
pin:
– LSI
– LSE
This output remains available in Stop (Stop 0, Stop 1 and Stop 2) and Standby modes.
The selection is controlled by the LSCOSEL, and enabled with the LSCOEN in the
Backup domain control register (RCC_BDCR).
The MCO clock output requires the corresponding alternate function selected on the MCO
pin, the LSCO pin should be left in default POR state.

6.2.17 Internal/external clock measurement with TIM15/TIM16/TIM17

It is possible to indirectly measure the frequency of all on-board clock sources by mean of
the TIM15, TIM16 or TIM17 channel 1 input capture, as represented on Figure 20, Figure 21
and Figure 22.

Figure 20. Frequency measurement with TIM15 in capture mode

TIM 15

TI1_RMP

GPIO TI1

LSE

MS33433V1

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The input capture channel of the Timer 15 can be a GPIO line or an internal clock of the
MCU. This selection is performed through the TI1_RMP bit in the TIM15_OR register. The
possibilities are the following ones:
• TIM15 Channel1 is connected to the GPIO. Refer to the alternate function mapping in
the device datasheets.
• TIM15 Channel1 is connected to the LSE.

Figure 21. Frequency measurement with TIM16 in capture mode

TIM16

TI1_RMP[1:0]
GPIO
LSI
LSE TI1
RTC wakeup interrupt
MSI
HSE/32
MCO
NC
MSv63428V1

The input capture channel of the Timer 16 can be a GPIO line or an internal clock of the
MCU. This selection is performed through the TI1_RMP[1:0] bits in the TIM16_OR register.
The possibilities are the following ones:
• TIM16 Channel1 is connected to the GPIO. Refer to the alternate function mapping in
the device datasheets.
• TIM16 Channel1 is connected to the LSI clock.
• TIM16 Channel1 is connected to the LSE clock.
• TIM16 Channel1 is connected to the RTC wakeup interrupt signal. In this case the RTC
interrupt should be enabled.
• TIM16 Channel1 is connected to the MSI clock.
• TIM16 Channel1 is connected to the HSE/32 clock.
• TIM16 Channel1 is connected to the MCO clock.

Figure 22. Frequency measurement with TIM17 in capture mode

TIM17

TI1_RMP[1:0]
GPIO
TI1
MSI
HSE/32
MCO
MS33435V1

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The input capture channel of the Timer 17 can be a GPIO line or an internal clock of the
MCU. This selection is performed through the TI1_RMP[1:0] bits in the TIM17_OR register.
The possibilities are the following ones:
• TIM17 Channel1 is connected to the GPIO. Refer to the alternate function mapping in
the device datasheets.
• TIM17 Channel1 is connected to the MSI Clock.
• TIM17 Channel1 is connected to the HSE/32 Clock.
• TIM17 Channel1 is connected to the microcontroller clock output (MCO), this selection
is controlled by the MCOSEL[3:0] bits of the Clock configuration register (RCC_CFGR).

Calibration of the HSI16 and the MSI

For TIM15 and TIM16, the primary purpose of connecting the LSE to the channel 1 input
capture is to be able to precisely measure the HSI16 and MSI system clocks (for this, either
the HSI16 or MSI should be used as the system clock source). The number of HSI16 (MSI,
respectively) clock counts between consecutive edges of the LSE signal provides a
measure of the internal clock period. Taking advantage of the high precision of LSE crystals
(typically a few tens of ppm’s), it is possible to determine the internal clock frequency with
the same resolution, and trim the source to compensate for manufacturing, process,
temperature and/or voltage related frequency deviations.
The MSI and HSI16 oscillator both have dedicated user-accessible calibration bits for this
purpose.
The basic concept consists in providing a relative measurement (e.g. the HSI16/LSE ratio):
the precision is therefore closely related to the ratio between the two clock sources. The
higher the ratio is, the better the measurement will be.
If LSE is not available, HSE/32 will be the better option in order to reach the most precise
calibration possible.
It is however not possible to have a good enough resolution when the MSI clock is low
(typically below 1 MHz). In this case, it is advised to:
• accumulate the results of several captures in a row
• use the timer’s input capture prescaler (up to 1 capture every 8 periods)
• use the RTC wakeup interrupt signal (when the RTC is clocked by the LSE) as the
input for the channel1 input capture. This improves the measurement precision. For
this purpose the RTC wakeup interrupt must be enable.

Calibration of the LSI

The calibration of the LSI will follow the same pattern that for the HSI16, but changing the
reference clock. It will be necessary to connect LSI clock to the channel 1 input capture of
the TIM16. Then define the HSE as system clock source, the number of his clock counts
between consecutive edges of the LSI signal provides a measure of the internal low speed
clock period.
The basic concept consists in providing a relative measurement (e.g. the HSE/LSI ratio): the
precision is therefore closely related to the ratio between the two clock sources. The higher
the ratio is, the better the measurement will be.

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6.2.18 Peripheral clock enable register

(RCC_AHBxENR, RCC_APBxENRy)
Each peripheral clock can be enabled by the xxxxEN bit of the RCC_AHBxENR,
RCC_APBxENRy registers.
When the peripheral clock is not active, the peripheral registers read or write accesses are
not supported.
The enable bit has a synchronization mechanism to create a glitch free clock for the
peripheral. After the enable bit is set, there is a 2 clock cycles delay before the clock be
active.
Caution: Just after enabling the clock for a peripheral, software must wait for a delay before
accessing the peripheral registers.

6.3 Low-power modes

• AHB and APB peripheral clocks, including DMA clock, can be disabled by software.
• Sleep and Low Power Sleep modes stops the CPU clock. The memory interface clocks
(Flash, SRAM1, SRAM2 and SRAM3 interfaces) can be stopped by software during
sleep mode. The AHB to APB bridge clocks are disabled by hardware during Sleep
mode when all the clocks of the peripherals connected to them are disabled.
• Stop modes (Stop 0, Stop 1 and Stop 2) stops all the clocks in the VCORE domain and
disables the three PLL, the HSI16, the MSI and the HSE oscillators.
All U(S)ARTs, LPUARTs and I2Cs have the capability to enable the HSI16 oscillator
even when the MCU is in Stop mode (if HSI16 is selected as the clock source for that
peripheral).
All U(S)ARTs and LPUARTs can also be driven by the LSE oscillator when the system
is in Stop mode (if LSE is selected as clock source for that peripheral) and the LSE
oscillator is enabled (LSEON). In that case the LSE remains always ON in Stop mode
(they do not have the capability to turn on the LSE oscillator).
• Standby and Shutdown modes stops all the clocks in the VCORE domain and disables
the PLL, the HSI16, the MSI and the HSE oscillators.
The CPU’s deepsleep mode can be overridden for debugging by setting the DBG_STOP or
DBG_STANDBY bits in the DBGMCU_CR register.
When leaving the Stop modes (Stop 0, Stop 1 or Stop 2), the system clock is either MSI or
HSI16, depending on the software configuration of the STOPWUCK bit in the RCC_CFGR
register. The frequency (range and user trim) of the MSI oscillator is the one configured
before entering Stop mode. The user trim of HSI16 is kept. If the MSI was in PLL-mode
before entering Stop mode, the PLL-mode stabilization time must be waited for after wakeup
even if the LSE was kept ON during the Stop mode.
When leaving the Standby and Shutdown modes, the system clock is MSI. The MSI
frequency at wakeup from Standby mode is configured with the MSISRANGE is the
RCC_CSR register, from 1 to 8 MHz. The MSI frequency at wakeup from Shutdown mode is
4 MHz. The user trim is lost.
If a Flash memory programming operation is on going, Stop, Standby and Shutdown modes
entry is delayed until the Flash memory interface access is finished. If an access to the APB
domain is ongoing, Stop, Standby and Shutdown modes entry is delayed until the APB
access is finished.

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6.4 RCC registers

6.4.1 Clock control register (RCC_CR)

Address offset: 0x00
Reset value: 0x0000 0063. HSEBYP is not affected by reset.
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLSAI PLLSAI PLLSAI PLLSAI PLLRD CSS HSE HSE HSE
Res. Res. PLLON Res. Res. Res. Res.
2RDY 2ON 1RDY 1ON Y ON BYP RDY ON
r rw r rw r rw rs rw r rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSIAS HSIRD HSIKER MSIRG MSIPL MSI
Res. Res. Res. Res. HSION MSIRANGE[3:0] MSION
FS Y ON SEL LEN RDY
rw r rw rw rw rw rw rw rs rw r rw

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 PLLSAI2RDY: SAI2 PLL clock ready flag
Set by hardware to indicate that the PLLSAI2 is locked.
0: PLLSAI2 unlocked
1: PLLSAI2 locked
Bit 28 PLLSAI2ON: SAI2 PLL enable
Set and cleared by software to enable PLLSAI2.
Cleared by hardware when entering Stop, Standby or Shutdown mode.
0: PLLSAI2 OFF
1: PLLSAI2 ON
Bit 27 PLLSAI1RDY: SAI1 PLL clock ready flag
Set by hardware to indicate that the PLLSAI1 is locked.
0: PLLSAI1 unlocked
1: PLLSAI1 locked
Bit 26 PLLSAI1ON: SAI1 PLL enable
Set and cleared by software to enable PLLSAI1.
Cleared by hardware when entering Stop, Standby or Shutdown mode.
0: PLLSAI1 OFF
1: PLLSAI1 ON
Bit 25 PLLRDY: Main PLL clock ready flag
Set by hardware to indicate that the main PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON: Main PLL enable
Set and cleared by software to enable the main PLL.
Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be
reset if the PLL clock is used as the system clock.
0: PLL OFF
1: PLL ON
Bits 23:20 Reserved, must be kept at reset value.

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Bit 19 CSSON: Clock security system enable

Set by software to enable the clock security system. When CSSON is set, the clock detector
is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE
clock failure is detected. This bit is set only and is cleared by reset.
0: Clock security system OFF (clock detector OFF)
1: Clock security system ON (Clock detector ON if the HSE oscillator is stable, OFF if not).
Bit 18 HSEBYP: HSE crystal oscillator bypass
Set and cleared by software to bypass the oscillator with an external clock. The external
clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit
can be written only if the HSE oscillator is disabled.
0: HSE crystal oscillator not bypassed
1: HSE crystal oscillator bypassed with external clock
Bit 17 HSERDY: HSE clock ready flag
Set by hardware to indicate that the HSE oscillator is stable.
0: HSE oscillator not ready
1: HSE oscillator ready
Note: Once the HSEON bit is cleared, HSERDY goes low after 6 HSE clock cycles.
Bit 16 HSEON: HSE clock enable
Set and cleared by software.
Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown
mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system
clock.
0: HSE oscillator OFF
1: HSE oscillator ON
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 HSIASFS: HSI16 automatic start from Stop
Set and cleared by software. When the system wakeup clock is MSI, this bit is used to
wakeup the HSI16 is parallel of the system wakeup.
0: HSI16 oscillator is not enabled by hardware when exiting Stop mode with MSI as wakeup
clock.
1: HSI16 oscillator is enabled by hardware when exiting Stop mode with MSI as wakeup
clock.
Bit 10 HSIRDY: HSI16 clock ready flag
Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is
enabled by software by setting HSION.
0: HSI16 oscillator not ready
1: HSI16 oscillator ready
Note: Once the HSION bit is cleared, HSIRDY goes low after 6 HSI16 clock cycles.
Bit 9 HSIKERON: HSI16 always enable for peripheral kernels.
Set and cleared by software to force HSI16 ON even in Stop modes. The HSI16 can only
feed USARTs and I2Cs peripherals configured with HSI16 as kernel clock. Keeping the
HSI16 ON in Stop mode allows to avoid slowing down the communication speed because of
the HSI16 startup time. This bit has no effect on HSION value.
0: No effect on HSI16 oscillator.
1: HSI16 oscillator is forced ON even in Stop mode.

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Bit 8 HSION: HSI16 clock enable

Set and cleared by software.
Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby or Shutdown
mode.
Set by hardware to force the HSI16 oscillator ON when STOPWUCK=1 or HSIASFS = 1
when leaving Stop modes, or in case of failure of the HSE crystal oscillator.
This bit is set by hardware if the HSI16 is used directly or indirectly as system clock.
0: HSI16 oscillator OFF
1: HSI16 oscillator ON
Bits 7:4 MSIRANGE[3:0]: MSI clock ranges
These bits are configured by software to choose the frequency range of MSI when
MSIRGSEL is set.12 frequency ranges are available:
0000: range 0 around 100 kHz
0001: range 1 around 200 kHz
0010: range 2 around 400 kHz
0011: range 3 around 800 kHz
0100: range 4 around 1M Hz
0101: range 5 around 2 MHz
0110: range 6 around 4 MHz (reset value)
0111: range 7 around 8 MHz
1000: range 8 around 16 MHz
1001: range 9 around 24 MHz
1010: range 10 around 32 MHz
1011: range 11 around 48 MHz
others: not allowed (hardware write protection)
Note: Warning: MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is
ready (MSIRDY=1). MSIRANGE must NOT be modified when MSI is ON and NOT
ready (MSION=1 and MSIRDY=0)
Bit 3 MSIRGSEL: MSI clock range selection
Set by software to select the MSI clock range with MSIRANGE[3:0]. Write 0 has no effect.
After a standby or a reset MSIRGSEL is at 0 and the MSI range value is provided by
MSISRANGE in CSR register.
0: MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register
1: MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register
Bit 2 MSIPLLEN: MSI clock PLL enable
Set and cleared by software to enable/ disable the PLL part of the MSI clock source.
MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set
by hardware).There is a hardware protection to avoid enabling MSIPLLEN if LSE is not
ready.
This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the Clock
Security System on LSE detects a LSE failure (refer to RCC_CSR register).
0: MSI PLL OFF
1: MSI PLL ON
Bit 1 MSIRDY: MSI clock ready flag
This bit is set by hardware to indicate that the MSI oscillator is stable.
0: MSI oscillator not ready
1: MSI oscillator ready
Note: Once the MSION bit is cleared, MSIRDY goes low after 6 MSI clock cycles.

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RM0432 Reset and clock control (RCC)

Bit 0 MSION: MSI clock enable

This bit is set and cleared by software.
Cleared by hardware to stop the MSI oscillator when entering Stop, Standby or Shutdown
mode.
Set by hardware to force the MSI oscillator ON when exiting Standby or Shutdown mode.
Set by hardware to force the MSI oscillator ON when STOPWUCK=0 when exiting from Stop
modes, or in case of a failure of the HSE oscillator
Set by hardware when used directly or indirectly as system clock.
0: MSI oscillator OFF
1: MSI oscillator ON

6.4.2 Internal clock sources calibration register (RCC_ICSCR)

Address offset: 0x04
Reset value: 0x40XX 00XX where X is factory-programmed.
Access: no wait state, word, half-word and byte access.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. HSITRIM[6:0] HSICAL[7:0]
rw rw rw rw rw rw rw r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSITRIM[7:0] MSICAL[7:0]
rw rw rw rw rw rw rw rw r r r r r r r r

Bit 31 Reserved, must be kept at reset value.

Bits 30:24 HSITRIM[6:0]: HSI16 clock trimming
These bits provide an additional user-programmable trimming value that is added to the
HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature
that influence the frequency of the HSI16.
The default value is 16, which, when added to the HSICAL value, should trim the HSI16 to
16 MHz ± 1 %.
Bits 23:16 HSICAL[7:0]: HSI16 clock calibration
These bits are initialized at startup with the factory-programmed HSI16 calibration trim value.
When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim
value.
Bits 15:8 MSITRIM[7:0]: MSI clock trimming
These bits provide an additional user-programmable trimming value that is added to the
MSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature
that influence the frequency of the MSI.
Bits 7:0 MSICAL[7:0]: MSI clock calibration
These bits are initialized at startup with the factory-programmed MSI calibration trim value.
When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim
value.

6.4.3 Clock configuration register (RCC_CFGR)

Address offset: 0x08
Reset value: 0x0000 0000

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Access: 0 ≤ wait state ≤ 2, word, half-word and byte access

1 or 2 wait states inserted only if the access occurs during clock source switch.
From 0 to 15 wait states inserted if the access occurs when the APB or AHB prescalers
values update is on going.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. MCOPRE[2:0] MCOSEL[3:0] Res. Res. Res. Res. Res. Res. Res. Res.
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STOP
Res. PPRE2[2:0] PPRE1[2:0] HPRE[3:0] SWS[1:0] SW[1:0]
WUCK
rw rw rw rw rw rw rw rw rw rw rw r r rw rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:28 MCOPRE[2:0]: Microcontroller clock output prescaler
These bits are set and cleared by software.
It is highly recommended to change this prescaler before MCO output is enabled.
000: MCO is divided by 1
001: MCO is divided by 2
010: MCO is divided by 4
011: MCO is divided by 8
100: MCO is divided by 16
Others: not allowed
Bits 27:24 MCOSEL[3:0]: Microcontroller clock output
Set and cleared by software.
0000: MCO output disabled, no clock on MCO
0001: SYSCLK system clock selected
0010: MSI clock selected.
0011: HSI16 clock selected.
0100: HSE clock selected
0101: Main PLL clock selected
0110: LSI clock selected
0111: LSE clock selected
1000: Internal HSI48 clock selected
Others: Reserved
Note: This clock output may have some truncated cycles at startup or during MCO clock
source switching.
Bits 23:16 Reserved, must be kept at reset value.
Bit 15 STOPWUCK: Wakeup from Stop and CSS backup clock selection
Set and cleared by software to select the system clock used when exiting Stop mode.
The selected clock is also used as emergency clock for the Clock Security System on HSE.
Warning: STOPWUCK must not be modified when the Clock Security System is enabled by
HSECSSON in RCC_CR register and the system clock is HSE (SWS=”10”) or a switch on
HSE is requested (SW=”10”).
0: MSI oscillator selected as wakeup from stop clock and CSS backup clock.
1: HSI16 oscillator selected as wakeup from stop clock and CSS backup clock
Bit 14 Reserved, must be kept at reset value.

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Bits 13:11 PPRE2[2:0]: APB high-speed prescaler (APB2)

Set and cleared by software to control the division factor of the APB2 clock (PCLK2).
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16
Bits 10:8 PPRE1[2:0]:APB low-speed prescaler (APB1)
Set and cleared by software to control the division factor of the APB1 clock (PCLK1).
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16
Bits 7:4 HPRE[3:0]: AHB prescaler
Set and cleared by software to control the division factor of the AHB clock.
Caution: Depending on the device voltage range, the software has to set
correctly these bits to ensure that the system frequency does not
exceed the maximum allowed frequency (for more details please refer to
Section 5.1.8: Dynamic voltage scaling management). After a write
operation to these bits and before decreasing the voltage range, this
register must be read to be sure that the new value has been taken into
account.
0xxx: SYSCLK not divided
1000: SYSCLK divided by 2
1001: SYSCLK divided by 4
1010: SYSCLK divided by 8
1011: SYSCLK divided by 16
1100: SYSCLK divided by 64
1101: SYSCLK divided by 128
1110: SYSCLK divided by 256
1111: SYSCLK divided by 512
Bits 3:2 SWS[1:0]: System clock switch status
Set and cleared by hardware to indicate which clock source is used as system clock.
00: MSI oscillator used as system clock
01: HSI16 oscillator used as system clock
10: HSE used as system clock
11: PLL used as system clock
Bits 1:0 SW[1:0]: System clock switch
Set and cleared by software to select system clock source (SYSCLK).
Configured by HW to force MSI oscillator selection when exiting Standby or Shutdown mode.
Configured by HW to force MSI or HSI16 oscillator selection when exiting Stop mode or in
case of failure of the HSE oscillator, depending on STOPWUCK value.
00: MSI selected as system clock
01: HSI16 selected as system clock
10: HSE selected as system clock
11: PLL selected as system clock

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6.4.4 PLL configuration register (RCC_PLLCFGR)

Address offset: 0x0C
Reset value: 0x0000 1000
Access: no wait state, word, half-word and byte access
This register is used to configure the PLL clock outputs according to the formulas:
• f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
• f(PLL_P) = f(VCO clock) / PLLP
• f(PLL_Q) = f(VCO clock) / PLLQ
• f(PLL_R) = f(VCO clock) / PLLR

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLRE PLLQE PLLPE
PLLPDIV[4:0] PLLR[1:0] Res. PLLQ[1:0] Res. Res. PLLP
N N N
rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. PLLN[6:0] PLLM[3:0] Res. Res. PLLSRC[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:27 PLLPDIV[4:0]: Main PLLP division factor for PLLSAI3CLK

Set and cleared by software to control the SAI1 or SAI2 clock frequency. PLLSAI3CLK
output clock frequency = VCO frequency / PLLPDIV.
00000: PLLSAI3CLK is controlled by the bit PLLP
00001: Reserved.
00010: PLLSAI3CLK = VCO / 2
....
11111: PLLSAI3CLK = VCO / 31
Bits 26:25 PLLR[1:0]: Main PLL division factor for PLLCLK (system clock)
Set and cleared by software to control the frequency of the main PLL output clock PLLCLK.
This output can be selected as system clock. These bits can be written only if PLL is
disabled.
PLLCLK output clock frequency = VCO frequency / PLLR with PLLR = 2, 4, 6, or 8
00: PLLR = 2
01: PLLR = 4
10: PLLR = 6
11: PLLR = 8
Caution: The software has to set these bits correctly not to exceed 120 MHz on
this domain.
Bit 24 PLLREN: Main PLL PLLCLK output enable
Set and reset by software to enable the PLLCLK output of the main PLL (used as system
clock).
This bit cannot be written when PLLCLK output of the PLL is used as System Clock.
In order to save power, when the PLLCLK output of the PLL is not used, the value of
PLLREN should be 0.
0: PLLCLK output disable
1: PLLCLK output enable
Bit 23 Reserved, must be kept at reset value.

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RM0432 Reset and clock control (RCC)

Bits 22:21 PLLQ[1:0]: Main PLL division factor for PLL48M1CLK (48 MHz clock).
Set and cleared by software to control the frequency of the main PLL output clock
PLL48M1CLK. This output can be selected for USB, RNG, SDMMC (48 MHz clock). These
bits can be written only if PLL is disabled.
PLL48M1CLK output clock frequency = VCO frequency / PLLQ with PLLQ = 2, 4, 6, or 8
00: PLLQ = 2
01: PLLQ = 4
10: PLLQ = 6
11: PLLQ = 8
Caution: The software has to set these bits correctly not to exceed 120 MHz on
this domain.
Bit 20 PLLQEN: Main PLL PLL48M1CLK output enable
Set and reset by software to enable the PLL48M1CLK output of the main PLL.
In order to save power, when the PLL48M1CLK output of the PLL is not used, the value of
PLLQEN should be 0.
0: PLL48M1CLK output disable
1: PLL48M1CLK output enable
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 PLLP: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) or SDMMC clock.
Set and cleared by software to control the frequency of the main PLL output clock
PLLSAI3CLK. This output can be selected for SAI1 or SAI2 or SDMMC. These bits can be
written only if PLL is disabled.
When the PLLPDIV[4:0] is set to “00000”PLLSAI3CLK output clock frequency = VCO
frequency / PLLP with PLLP =7, or 17
0: PLLP = 7
1: PLLP = 17
Caution: The software has to set these bits correctly not to exceed 120 MHz on
this domain.
Bit 16 PLLPEN: Main PLL PLLSAI3CLK output enable
Set and reset by software to enable the PLLSAI3CLK output of the main PLL.
In order to save power, when the PLLSAI3CLK output of the PLL is not used, the value of
PLLPEN should be 0.
0: PLLSAI3CLK output disable
1: PLLSAI3CLK output enable
Bit 15 Reserved, must be kept at reset value.

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Bits 14:8 PLLN[6:0]: Main PLL multiplication factor for VCO

Set and cleared by software to control the multiplication factor of the VCO. These bits can be
written only when the PLL is disabled.
VCO output frequency = VCO input frequency x PLLN with 8 =< PLLN =< 127
0000000: PLLN = 0 wrong configuration
0000001: PLLN = 1 wrong configuration
...
0000111: PLLN = 7 wrong configuration
0001000: PLLN = 8
0001001: PLLN = 9
...
1111111: PLLN = 127
Caution: The software has to set correctly these bits to assure that the VCO
output frequency is between 64 and 344 MHz.
Bits 7:4 PLLM: Division factor for the main PLLinput clock
Set and cleared by software to divide the PLL input clock before the VCO. These bits can be
written only when all PLLs are disabled.
VCO input frequency = PLL input clock frequency / PLLM with 1 <= PLLM <= 16
0000: PLLM = 1
0001: PLLM = 2
0010: PLLM = 3
0011: PLLM = 4
0100: PLLM = 5
0101: PLLM = 6
0110: PLLM = 7
0111: PLLM = 8
Caution: The software has to set these bits correctly to ensure that the VCO input
frequency ranges from 2.66 MHz to 8 MHz.
Bits 3:2 Reserved, must be kept at reset value.
Bits 1:0 PLLSRC: Main PLL entry clock source
Set and cleared by software to select PLL clock source. These bits can be written only when
PLL disabled.
In order to save power, when no PLL is used, the value of PLLSRC should be 00.
00: No clock sent to PLL
01: MSI clock selected as PLL clock entry
10: HSI16 clock selected as PLL clock entry
11: HSE clock selected as PLL clock entry

6.4.5 PLLSAI1 configuration register (RCC_PLLSAI1CFGR)

Address offset: 0x10
Reset value: 0x0000 1000
Access: no wait state, word, half-word and byte access
This register is used to configure the PLLSAI1 clock outputs according to the formulas:
• f(VCOSAI1 clock) = f(PLL clock input) × (PLLSAI1N / PLLSAI1M)
• f(PLLSAI1_P) = f(VCOSAI1 clock) / PLLSAI1PDIV
• f(PLLSAI1_Q) = f(VCOSAI1 clock) / PLLSAI1Q

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RM0432 Reset and clock control (RCC)

• f(PLLSAI1_R) = f(VCOSAI1 clock) / PLLSAI1R

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLSAI PLLSAI PLLSAI PLLSAI
PLLSAI1PDIV[4:0] PLLSAI1R[1:0] Res. PLLSAI1Q[1:0] Res. Res.
1REN 1QEN 1P 1PEN
rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. PLLSAI1N[6:0] PLLSAI1M[3:0] Res. Res. Res. Res.
rw rw rw rw rw rw rw rw rw rw rw

Bits 31:27 PLLSAI1PDIV[4:0]: PLLSAI1 division factor for PLLSAI1CLK

Set and cleared by software to control the SAI1 or SAI2 clock frequency. PLLSAI1CLK output
clock frequency = VCOSAI1 frequency / PLLSAI1PDIV.
00000: PLLSAI1CLK is controlled by the bit PLLSAI1P
00001: Reserved.
00010: PLLSAI1CLK = VCOSAI1 / 2
....
11111: PLLSAI1CLK = VCOSAI1 / 31
Note: This bit can be written only when the PLLSAI1 is disabled.
Bits 26:25 PLLSAI1R[1:0]: PLLSAI1 division factor for PLLADC1CLK (ADC clock)
Set and cleared by software to control the frequency of the PLLSAI1 output clock
PLLADC1CLK. This output can be selected as ADC clock. These bits can be written only if
PLLSAI1 is disabled.
PLLADC1CLK output clock frequency = VCOSAI1 frequency / PLLSAI1R with PLLSAI1R =
2, 4, 6, or 8
00: PLLSAI1R = 2
01: PLLSAI1R = 4
10: PLLSAI1R = 6
11: PLLSAI1R = 8
Bit 24 PLLSAI1REN: PLLSAI1 PLLADC1CLK output enable
Set and reset by software to enable the PLLADC1CLK output of the PLLSAI1 (used as clock
for ADC).
In order to save power, when the PLLADC1CLK output of the PLLSAI1 is not used, the value
of PLLSAI1REN should be 0.
0: PLLADC1CLK output disable
1: PLLADC1CLK output enable
Bit 23 Reserved, must be kept at reset value.
Bits 22:21 PLLSAI1Q[1:0]: PLLSAI1 division factor for PLL48M2CLK (48 MHz clock)
Set and cleared by software to control the frequency of the PLLSAI1 output clock
PLL48M2CLK. This output can be selected for USB, RNG, SDMMC (48 MHz clock). These
bits can be written only if PLLSAI1 is disabled.
PLL48M2CLK output clock frequency = VCOSAI1 frequency / PLLSAI1Q with PLLSAI1Q =
2, 4, 6, or 8
00: PLLSAI1Q = 2
01: PLLSAI1Q = 4
10: PLLSAI1Q = 6
11: PLLSAI1Q = 8
Caution: The software has to set these bits correctly not to exceed 120 MHz on
this domain.

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Bit 20 PLLSAI1QEN: PLLSAI1 PLL48M2CLK output enable

Set and reset by software to enable the PLL48M2CLK output of the PLLSAI1.
In order to save power, when the PLL48M2CLK output of the PLLSAI1 is not used, the value
of PLLSAI1QEN should be 0.
0: PLL48M2CLK output disable
1: PLL48M2CLK output enable
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 PLLSAI1P: PLLSAI1 division factor for PLLSAI1CLK (SAI1 or SAI2 clock).
Set and cleared by software to control the frequency of the PLLSAI1 output clock
PLLSAI1CLK. This output can be selected for SAI1 or SAI2. These bits can be written only if
PLLSAI1 is disabled.
When the PLLSAI1PDIV[4:0] is set to “00000”,PLLSAI1CLK output clock frequency =
VCOSAI1 frequency / PLLSAI1P with PLLSAI1P =7, or 17
0: PLLSAI1P = 7
1: PLLSAI1P = 17
Bit 16 PLLSAI1PEN: PLLSAI1 PLLSAI1CLK output enable
Set and reset by software to enable the PLLSAI1CLK output of the PLLSAI1.
In order to save power, when the PLLSAI1CLK output of the PLLSAI1 is not used, the value
of PLLSAI1PEN should be 0.
0: PLLSAI1CLK output disable
1: PLLSAI1CLK output enable
Bit 15 Reserved, must be kept at reset value.

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RM0432 Reset and clock control (RCC)

Bits 14:8 PLLSAI1N[6:0]: PLLSAI1 multiplication factor for VCO

Set and cleared by software to control the multiplication factor of the VCO. These bits can be
written only when the PLLSAI1 is disabled.
VCOSAI1 output frequency = VCOSAI1 input frequency x PLLSAI1N
with 8 =< PLLSAI1N =< 127
0000000: PLLSAI1N = 0 wrong configuration
0000001: PLLSAI1N = 1 wrong configuration
...
0000111: PLLSAI1N = 7 wrong configuration
0001000: PLLSAI1N = 8
0001001: PLLSAI1N = 9
...
1111111: PLLSAI1N = 127
Caution: The software has to set correctly these bits to ensure that the VCO
output frequency is between 64 and 344 MHz.
Bits 7:4 PLLSAI1M: Division factor for PLLSAI1 input clock
Set and reset by software to divide the PLLSAI1 input clock before the VCO.
These bits can be written only when PLLSAI1 is disabled.
VCO input frequency = PLLSAI1 input clock frequency / PLLSAI1M with 1 <= PLLSAI1M <= 16
0000: PLLSAI1M = 1
0001: PLLSAI1M = 2
0010: PLLSAI1M = 3
0011: PLLSAI1M = 4
0100: PLLSAI1M = 5
0101: PLLSAI1M = 6
0110: PLLSAI1M = 7
0111: PLLSAI1M = 8
1000: PLLSAI1M = 9
...
1111: PLLSAI1M= 16
Caution: The software has to set these bits correctly to ensure that the VCO input
frequency ranges from 2.66 to 8 MHz.
Bits 3:0 Reserved, must be kept at reset value.

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6.4.6 PLLSAI2 configuration register (RCC_PLLSAI2CFGR)

Address offset: 0x14
Reset value: 0x0000 1000
Access: no wait state, word, half-word and byte access
This register is used to configure the PLLSAI2 clock outputs according to the formulas:
• f(VCOSAI2 clock) = f(PLL clock input) × (PLLSAI2N / PLLSAI2M)
• f(PLLSAI2_P) = f(VCOSAI2 clock) / PLLSAI2PDIV
• f(PLLSAI2_R) = f(VCOSAI2 clock) / PLLSAI2R

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLSAI PLLSAI PLLSAI PLLSAI
PLLSAI2PDIV[4:0] PLLSAI2R[1:0] Res. PLLSAI2Q Res. Res.
2REN 2QEN 2P 2PEN
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. PLLSAI2N[6:0] PLLSAI2M[3:0] Res. Res. Res. Res.
rw rw rw rw rw rw rw rw rw rw rw

Bits 31:27 PLLSAI2PDIV[4:0]: PLLSAI2 division factor for PLLSAI2CLK

Set and cleared by software to control the SAI1 or SAI2 clock frequency. PLLSAI2CLK
output clock
frequency = VCOSAI2 frequency / PLLSAI2PDIV.
00000: PLLSAI2CLK is controlled by the bit PLLSAI2P
00001: Reserved.
00010: PLLSAI2CLK = VCOSAI2 / 2
....
11111: PLLSAI2CLK = VCOSAI2 / 31
Bits 26:25 PLLSAI2R[1:0]: PLLSAI2 division factor for PLLLCDCLK (LTDC clock)
Set and cleared by software to control the frequency of the PLLSAI2 output clock
PLLLCDCLK. This output can be selected as ADC clock. These bits can be written only if
PLLSAI2 is disabled.
PLLLCDCLK output clock frequency = VCOSAI2 frequency / PLLSAI2R with PLLSAI2R = 2,
4, 6, or 8
00: PLLSAI2R = 2
01: PLLSAI2R = 4
10: PLLSAI2R = 6
11: PLLSAI2R = 8
Bit 24 PLLSAI2REN: PLLSAI2 PLLLCDCLK output enable
Set and reset by software to enable the PLLLCDCLK output of the PLLSAI2 (used as clock
for ADC).
In order to save power, when the PLLLCDCLK output of the PLLSAI2 is not used, the value
of PLLSAI2REN should be 0.
0: PLLLCDCLK output disable
1: PLLLCDCLK output enable
Bit 23 Reserved, must be kept at reset value.

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RM0432 Reset and clock control (RCC)

Bits 22:21 PLLSAI2Q[1:0]: PLLSAI2 PLLDSICLK output enable.

Set and cleared by software to control the frequency of the DSI clock.
These bits can be written only if PLLSAI2 is disabled.
PLLDSICLK output clock frequency = VCOSAI2 frequency / PLLSAI2Q with PLLSAI2Q = 2,
4, 6, or 8
00: PLLSAI2Q = 2
01: PLLSAI2Q = 4
10: PLLSAI2Q = 6
11: PLLSAI2Q = 8
Bit 20 PLLSAI2QEN: PLLSAI2 division factor for PLLDSICLK (DSI clock).
Set and reset by software to enable the PLLDSICLK (DSI clock) output of the PLLSAI2
(used as USB clock).
In order to save power, when the PLLDSICLK output of the PLLSAI2 is not used, the value of
PLLSAI2PEN should be 0.
0: PLLDSICLK output disable
1: PLLDSICLK output enable
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 PLLSAI2P: PLLSAI2 division factor for PLLSAI2CLK (SAI1 or SAI2 clock).
Set and cleared by software to control the frequency of the PLLSAI2 output clock
PLLSAI2CLK. This output can be selected for SAI1 or SAI2. These bits can be written only if
PLLSAI2 is disabled.
(when the PLLSAI2PDIV[4:0] is set to “00000”), PLLSAI2CLK output clock frequency =
VCOSAI2 frequency / PLLSAI2P with PLLSAI2P =7, or 17
0: PLLSAI2P = 7
1: PLLSAI2P = 17
Bit 16 PLLSAI2PEN: PLLSAI2 PLLSAI2CLK output enable
Set and reset by software to enable the PLLSAI2CLK output of the PLLSAI2.
In order to save power, when the PLLSAI2CLK output of the PLLSAI2 is not used, the value
of PLLSAI2PEN should be 0.
0: PLLSAI2CLK output disable
1: PLLSAI2CLK output enable
Bit 15 Reserved, must be kept at reset value.

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Reset and clock control (RCC) RM0432

Bits 14:8 PLLSAI2N[6:0]: PLLSAI2 multiplication factor for VCO

Set and cleared by software to control the multiplication factor of the VCO. These bits can be
written only when the PLLSAI2 is disabled.
VCOSAI2 output frequency = VCOSAI2 input frequency x PLLSAI2N
with 8 =< PLLSAI2N =< 127
0000000: PLLSAI2N = 0 wrong configuration
0000001: PLLSAI2N = 1 wrong configuration
...
0000111: PLLSAI2N = 7 wrong configuration
0001000: PLLSAI2N = 8
0001001: PLLSAI2N = 9
...
1111111: PLLSAI2N = 127
Caution: The software has to set correctly these bits to ensure that the VCO
output frequency is between 64 and 344 MHz.
Bits 7:4 PLLSAI2M: Division factor for PLLSAI2 input clock
Set and reset by software to divide the PLLSAI2 input clock before the VCO.
These bits can be written only when PLLSAI2 is disabled.
VCO input frequency = PLLSAI2 input clock frequency / PLLM with 1 <= PLLSAI2M <= 16
0000: PLLSAI2M = 1
0001: PLLSAI2M = 2
0010: PLLSAI2M = 3
0011: PLLSAI1M = 4
0100: PLLSAI2M = 5
0101: PLLSAI2M = 6
0110: PLLSAI2M = 7
0111: PLLSAI2M = 8
1000: PLLSAI2M = 9
...
1111: PLLSAI2M= 16
Caution: The software has to set these bits correctly to ensure that the VCO input
frequency ranges from 2.66 to 8 MHz.
Bits 3:0 Reserved, must be kept at reset value.

6.4.7 Clock interrupt enable register (RCC_CIER)

Address offset: 0x18
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLSAI PLLSAI
HSI48 LSECS PLL HSE HSI MSI LSE LSI
Res. Res. Res. Res. Res. Res. 2RDYI 1RDYI
RDYIE SIE RDYIE RDYIE RDYIE RDYIE RDYIE RDYIE
E E
rw rw rw rw rw rw rw rw rw rw

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RM0432 Reset and clock control (RCC)

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 HSI48RDYIE: HSI48 ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the internal HSI48
oscillator.
0: HSI48 ready interrupt disabled
1: HSI48 ready interrupt enabled
Bit 9 LSECSSIE: LSE clock security system interrupt enable
Set and cleared by software to enable/disable interrupt caused by the clock security system
on LSE.
0: Clock security interrupt caused by LSE clock failure disabled
1: Clock security interrupt caused by LSE clock failure enabled
Bit 8 Reserved, must be kept at reset value.
Bit 7 PLLSAI2RDYIE: PLLSAI2 ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLLSAI2 lock.
0: PLLSAI2 lock interrupt disabled
1: PLLSAI2 lock interrupt enabled
Bit 6 PLLSAI1RDYIE: PLLSAI1 ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLSAI1L lock.
0: PLLSAI1 lock interrupt disabled
1: PLLSAI1 lock interrupt enabled
Bit 5 PLLRDYIE: PLL ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
Bit 4 HSERDYIE: HSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSE oscillator
stabilization.
0: HSE ready interrupt disabled
1: HSE ready interrupt enabled
Bit 3 HSIRDYIE: HSI16 ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator
stabilization.
0: HSI16 ready interrupt disabled
1: HSI16 ready interrupt enabled

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Reset and clock control (RCC) RM0432

Bit 2 MSIRDYIE: MSI ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the MSI oscillator
stabilization.
0: MSI ready interrupt disabled
1: MSI ready interrupt enabled
Bit 1 LSERDYIE: LSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the LSE oscillator
stabilization.
0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
Bit 0 LSIRDYIE: LSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the LSI oscillator
stabilization.
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled

6.4.8 Clock interrupt flag register (RCC_CIFR)

Address offset: 0x1C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSI48 LSECS PLLSAI PLLSAI PLL HSE HSI MSI LSE LSI
Res. Res. Res. Res. Res. CSSF
RDYF SF 2RDYF 1RDYF RDYF RDYF RDYF RDYF RDYF RDYF
r r r r r r r r r r r

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 HSI48RDYF: HSI48 ready interrupt flag
Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set in a
response to setting the HSI48ON (refer to Clock recovery RC register (RCC_CRRCR)).
Cleared by software setting the HSI48RDYC bit.
0: No clock ready interrupt caused by the HSI48 oscillator
1: Clock ready interrupt caused by the HSI48 oscillator
Bit 9 LSECSSF: LSE Clock security system interrupt flag
Set by hardware when a failure is detected in the LSE oscillator.
Cleared by software setting the LSECSSC bit.
0: No clock security interrupt caused by LSE clock failure
1: Clock security interrupt caused by LSE clock failure
Bit 8 CSSF: Clock security system interrupt flag
Set by hardware when a failure is detected in the HSE oscillator.
Cleared by software setting the CSSC bit.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure

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RM0432 Reset and clock control (RCC)

Bit 7 PLLSAI2RDYF: PLLSAI2 ready interrupt flag

Set by hardware when the PLLSAI2 locks and PLLSAI2RDYDIE is set.
Cleared by software setting the PLLSAI2RDYC bit.
0: No clock ready interrupt caused by PLLSAI2 lock
1: Clock ready interrupt caused by PLLSAI2 lock
Bit 6 PLLSAI1RDYF: PLLSAI1 ready interrupt flag
Set by hardware when the PLLSAI1 locks and PLLSAI1RDYDIE is set.
Cleared by software setting the PLLSAI1RDYC bit.
0: No clock ready interrupt caused by PLLSAI1 lock
1: Clock ready interrupt caused by PLLSAI1 lock
Bit 5 PLLRDYF: PLL ready interrupt flag
Set by hardware when the PLL locks and PLLRDYDIE is set.
Cleared by software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
Bit 4 HSERDYF: HSE ready interrupt flag
Set by hardware when the HSE clock becomes stable and HSERDYDIE is set.
Cleared by software setting the HSERDYC bit.
0: No clock ready interrupt caused by the HSE oscillator
1: Clock ready interrupt caused by the HSE oscillator
Bit 3 HSIRDYF: HSI16 ready interrupt flag
Set by hardware when the HSI16 clock becomes stable and HSIRDYDIE is set in a
response to setting the HSION (refer to Clock control register (RCC_CR)). When HSION is
not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit
is not set and no interrupt is generated.
Cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the HSI16 oscillator
1: Clock ready interrupt caused by the HSI16 oscillator
Bit 2 MSIRDYF: MSI ready interrupt flag
Set by hardware when the MSI clock becomes stable and MSIRDYDIE is set.
Cleared by software setting the MSIRDYC bit.
0: No clock ready interrupt caused by the MSI oscillator
1: Clock ready interrupt caused by the MSI oscillator
Bit 1 LSERDYF: LSE ready interrupt flag
Set by hardware when the LSE clock becomes stable and LSERDYDIE is set.
Cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the LSE oscillator
1: Clock ready interrupt caused by the LSE oscillator
Bit 0 LSIRDYF: LSI ready interrupt flag
Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set.
Cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the LSI oscillator
1: Clock ready interrupt caused by the LSI oscillator

6.4.9 Clock interrupt clear register (RCC_CICR)

Address offset: 0x20
Reset value: 0x0000 0000

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Reset and clock control (RCC) RM0432

Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSI48 LSECS PLLSAI PLLSAI PLL HSER HSIRD MSIRD LSERD LSIRDY
Res. Res. Res. Res. Res. CSSC
RDYC SC 2RDYC 1RDYC RDYC DYC YC YC YC C
w w w w w w w w w w

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 HSI48RDYC: HSI48 oscillator ready interrupt clear
This bit is set by software to clear the HSI48RDYF flag.
0: No effect
1: Clear the HSI48RDYC flag
Bit 9 LSECSSC: LSE Clock security system interrupt clear
This bit is set by software to clear the LSECSSF flag.
0: No effect
1: Clear LSECSSF flag
Bit 8 CSSC: Clock security system interrupt clear
This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag
Bit 7 PLLSAI2RDYC: PLLSAI2 ready interrupt clear
This bit is set by software to clear the PLLSAI2RDYF flag.
0: No effect
1: Clear PLLSAI2RDYF flag
Bit 6 PLLSAI1RDYC: PLLSAI1 ready interrupt clear
This bit is set by software to clear the PLLSAI1RDYF flag.
0: No effect
1: Clear PLLSAI1RDYF flag
Bit 5 PLLRDYC: PLL ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: Clear PLLRDYF flag
Bit 4 HSERDYC: HSE ready interrupt clear
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: Clear HSERDYF flag
Bit 3 HSIRDYC: HSI16 ready interrupt clear
This bit is set software to clear the HSIRDYF flag.
0: No effect
1: Clear HSIRDYF flag

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RM0432 Reset and clock control (RCC)

Bit 2 MSIRDYC: MSI ready interrupt clear

This bit is set by software to clear the MSIRDYF flag.
0: No effect
1: MSIRDYF cleared
Bit 1 LSERDYC: LSE ready interrupt clear
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: LSERDYF cleared
Bit 0 LSIRDYC: LSI ready interrupt clear
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: LSIRDYF cleared

6.4.10 AHB1 peripheral reset register (RCC_AHB1RSTR)

Address offset: 0x28
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GFXMM DMA2 TSCR
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
URST DRST ST
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCR FLASH DMAMU DMA2 DMA1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ST RST X1RST RST RST
rw rw rw rw rw

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 GFXMMURST: GFXMMU reset
Set and cleared by software
0: No effect
1: Reset GFXMMU
Bit 17 DMA2DRST: DMA2D reset
Set and cleared by software
0: No effect
1: Reset DMA2D
Bit 16 TSCRST: Touch Sensing Controller reset
Set and cleared by software.
0: No effect
1: Reset TSC
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CRCRST: CRC reset
Set and cleared by software.
0: No effect
1: Reset CRC

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Reset and clock control (RCC) RM0432

Bits 11:9 Reserved, must be kept at reset value.

Bit 8 FLASHRST: Flash memory interface reset
Set and cleared by software. This bit can be activated only when the Flash memory is in
power down mode.
0: No effect
1: Reset Flash memory interface
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 DMAMUX1RST
Set and cleared by software.
0: No effect
1: Reset DMAMUX1
Bit 1 DMA2RST: DMA2 reset
Set and cleared by software.
0: No effect
1: Reset DMA2
Bit 0 DMA1RST: DMA1 reset
Set and cleared by software.
0: No effect
1: Reset DMA1

6.4.11 AHB2 peripheral reset register (RCC_AHB2RSTR)

Address offset: 0x2C
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMM SDMM OSPIM RNGR HASH AESR
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
C2RST C1RST RST ST RST ST
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PKAR ADCR OTGFS GPIOIR GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
DCMIRST Res. Res. Res.
ST ST RST ST RST RST RST RST RST RST RST RST
rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 SDMMC2RST: SDMMC2 reset
Set and cleared by software.
0: No effect
1: Reset SDMMC2
Bit 22 SDMMC1RST: SDMMC1 reset
Set and cleared by software.
0: No effect
1: Reset SDMMC1
Bit 21 Reserved, must be kept at reset value.

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RM0432 Reset and clock control (RCC)

Bit 20 OSPIMRST: OctoSPI IO manager reset

Set and cleared by software.
0: No effect
1: Reset OctoSPI IO manager
Bit 19 Reserved, must be kept at reset value.
Bit 18 RNGRST: Random number generator reset
Set and cleared by software.
0: No effect
1: Reset RNG
Bit 17 HASHRST: Hash reset
Set and cleared by software.
0: No effect
1: Reset HASH
Bit 16 AESRST: AES hardware accelerator reset
Set and cleared by software.
0: No effect
1: Reset AES
Bit 15 PKARST: PKA reset
Set and cleared by software.
0: No effect
1: Reset PKA
Bit 14 DCMIRST: DCMI or PSSI reset (DCMI or PSSI depending on which interface is active)
Set and cleared by software
0: No effect
1: Reset DCMI/PSSI interface
Bit 13 ADCRST: ADC reset
Set and cleared by software.
0: No effect
1: Reset ADC interface
Bit 12 OTGFSRST: USB OTG FS reset
Set and cleared by software.
0: No effect
1: Reset USB OTG FS
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 GPIOIRST: IO port I reset
Set and cleared by software
0: No effect
1: Reset IO port I
Bit 7 GPIOHRST: IO port H reset
Set and cleared by software.
0: No effect
1: Reset IO port H

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Bit 6 GPIOGRST: IO port G reset

Set and cleared by software.
0: No effect
1: Reset IO port G
Bit 5 GPIOFRST: IO port F reset
Set and cleared by software.
0: No effect
1: Reset IO port F
Bit 4 GPIOERST: IO port E reset
Set and cleared by software.
0: No effect
1: Reset IO port E
Bit 3 GPIODRST: IO port D reset
Set and cleared by software.
0: No effect
1: Reset IO port D
Bit 2 GPIOCRST: IO port C reset
Set and cleared by software.
0: No effect
1: Reset IO port C
Bit 1 GPIOBRST: IO port B reset
Set and cleared by software.
0: No effect
1: Reset IO port B
Bit 0 GPIOARST: IO port A reset
Set and cleared by software.
0: No effect
1: Reset IO port A

6.4.12 AHB3 peripheral reset register (RCC_AHB3RSTR)

Address offset: 0x30
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPI2 OSPI1R FMCR
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RST ST ST
rw rw rw

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RM0432 Reset and clock control (RCC)

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 OSPI2RST: OctoSPI2 memory interface reset
Set and cleared by software.
0: No effect
1: Reset OctoSPI2
Bit 8 OSPI1RST: OctoSPI1 memory interface reset
Set and cleared by software.
0: No effect
1: Reset OctoSPI1
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 FMCRST: Flexible memory controller reset
Set and cleared by software.
0: No effect
1: Reset FMC

6.4.13 APB1 peripheral reset register 1 (RCC_APB1RSTR1)

Address offset: 0x38
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1 OPAMP DAC1 PWRR CAN1R CRSRS I2C3R I2C2R I2C1R UART5 UART4 USART3 USART2
Res. Res. Res.
RST RST RST ST ST T ST ST ST RST RST RST RST
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3RS SPI2RS TIM7R TIM6R TIM5R TIM4RS TIM3RS TIM2R
Res. Res. Res. Res. Res. Res. Res. Res.
T T ST ST ST T T ST
rw rw rw rw rw rw rw rw

Bit 31 LPTIM1RST: Low Power Timer 1 reset

Set and cleared by software.
0: No effect
1: Reset LPTIM1
Bit 30 OPAMPRST: OPAMP interface reset
Set and cleared by software.
0: No effect
1: Reset OPAMP interface
Bit 29 DAC1RST: DAC1 interface reset
Set and cleared by software.
0: No effect
1: Reset DAC1 interface
Bit 28 PWRRST: Power interface reset
Set and cleared by software.
0: No effect
1: Reset PWR

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Bit 27:26 Reserved, must be kept at reset value.

Bit 25 CAN1RST: CAN1 reset
Set and reset by software.
0: No effect
1: Reset the CAN1
Bit 24 CRSRST: CRS reset
Set and cleared by software.
0: No effect
1: Reset the CRS
Bit 23 I2C3RST: I2C3 reset
Set and reset by software.
0: No effect
1: Reset I2C3
Bit 22 I2C2RST: I2C2 reset
Set and cleared by software.
0: No effect
1: Reset I2C2
Bit 21 I2C1RST: I2C1 reset
Set and cleared by software.
0: No effect
1: Reset I2C1
Bit 20 UART5RST: UART5 reset
Set and cleared by software.
0: No effect
1: Reset UART5
Bit 19 UART4RST: UART4 reset
Set and cleared by software.
0: No effect
1: Reset UART4
Bit 18 USART3RST: USART3 reset
Set and cleared by software.
0: No effect
1: Reset USART3
Bit 17 USART2RST: USART2 reset
Set and cleared by software.
0: No effect
1: Reset USART2
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3RST: SPI3 reset
Set and cleared by software.
0: No effect
1: Reset SPI3
Bit 14 SPI2RST: SPI2 reset
Set and cleared by software.
0: No effect
1: Reset SPI2

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RM0432 Reset and clock control (RCC)

Bits 13:6 Reserved, must be kept at reset value.

Bit 5 TIM7RST: TIM7 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM7
Bit 4 TIM6RST: TIM6 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM6
Bit 3 TIM5RST: TIM5 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM5
Bit 2 TIM4RST: TIM3 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM3
Bit 1 TIM3RST: TIM3 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM3
Bit 0 TIM2RST: TIM2 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM2

6.4.14 APB1 peripheral reset register 2 (RCC_APB1RSTR2)

Address offset: 0x3C
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPTIM2 I2C4 LPUART
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RST RST 1RST
rw rw rw

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 LPTIM2RST: Low-power timer 2 reset
Set and cleared by software.
0: No effect
1: Reset LPTIM2

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Bits 4:2 Reserved, must be kept at reset value.

Bit 1 I2C4RST: I2C4 reset
Set and cleared by software
0: No effect
1: Reset I2C4
Bit 0 LPUART1RST: Low-power UART 1 reset
Set and cleared by software.
0: No effect
1: Reset LPUART1

6.4.15 APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x40
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSIRS LTDCR DFSD SAI2R SAI1R TIM17 TIM16 TIM15
Res. Res. Res. Res. Res. Res. Res. Res.
T ST M1RST ST ST RST RST RST
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART TIM8R SPI1R TIM1R SYSCF
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1RST ST ST ST GRST
rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 DSIRST: DSI reset
Set and cleared by software.
0: No effect
1: Reset DSI
Bit 26 LTDCRST: LCD-TFT reset
Set and cleared by software.
0: No effect
1: Reset LCD-TFT
Bit 25 Reserved, must be kept at reset value.
Bit 24 DFSDM1RST: Digital filters for sigma-delta modulators (DFSDM1) reset
Set and cleared by software.
0: No effect
1: Reset DFSDM1
Bit 23 Reserved, must be kept at reset value.
Bit 22 SAI2RST: Serial audio interface 2 (SAI2) reset
Set and cleared by software.
0: No effect
1: Reset SAI2

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RM0432 Reset and clock control (RCC)

Bit 21 SAI1RST: Serial audio interface 1 (SAI1) reset

Set and cleared by software.
0: No effect
1: Reset SAI1
Bits 20:19 Reserved, must be kept at reset value.
Bit 18 TIM17RST: TIM17 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM17 timer
Bit 17 TIM16RST: TIM16 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM16 timer
Bit 16 TIM15RST: TIM15 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM15 timer
Bit 15 Reserved, must be kept at reset value.
Bit 14 USART1RST: USART1 reset
Set and cleared by software.
0: No effect
1: Reset USART1
Bit 13 TIM8RST: TIM8 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM8 timer
Bit 12 SPI1RST: SPI1 reset
Set and cleared by software.
0: No effect
1: Reset SPI1
Bit 11 TIM1RST: TIM1 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM1 timer
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGRST: SYSCFG + COMP + VREFBUF reset
0: No effect
1: Reset SYSCFG + COMP + VREFBUF

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6.4.16 AHB1 peripheral clock enable register (RCC_AHB1ENR)

Address offset: 0x48
Reset value: 0x0000 0100
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GFXM DMA2D TSCE
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
MUEN EN N
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLASH DMAM DMA2E DMA1
Res. Res. Res. CRCEN Res. Res. Res. Res. Res. Res. Res. Res.
EN UX1EN N EN
rw rw rw rw rw

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 GFXMMUEN: Graphic MMU clock enable
Set and reset by software
0: GFXMMU clock disabled
1: GFXMMU clock enabled
Bit 17 DMA2DEN: DMA2D clock enable
Set and cleared by software
0: DMA2D clock disabled
1: DMA2D clock enabled
Bit 16 TSCEN: Touch Sensing Controller clock enable
Set and cleared by software.
0: TSC clock disable
1: TSC clock enable
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CRCEN: CRC clock enable
Set and cleared by software.
0: CRC clock disable
1: CRC clock enable
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 FLASHEN: Flash memory interface clock enable
Set and cleared by software. This bit can be disabled only when the Flash is in power down
mode.
0: Flash memory interface clock disable
1: Flash memory interface clock enable
Bits 7:3 Reserved, must be kept at reset value.

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RM0432 Reset and clock control (RCC)

Bit 2 DMAMUX1EN: DMAMUX1 clock enable

Set and reset by software.
0: DMAMUX1 clock disabled
1: DMAMUX1 clock enabled
Bit 1 DMA2EN: DMA2 clock enable
Set and cleared by software.
0: DMA2 clock disable
1: DMA2 clock enable
Bit 0 DMA1EN: DMA1 clock enable
Set and cleared by software.
0: DMA1 clock disable
1: DMA1 clock enable

6.4.17 AHB2 peripheral clock enable register (RCC_AHB2ENR)

Address offset: 0x4C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMM SDMM OSPIM RNG HASHE
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AESEN
C2EN C1EN EN EN N
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCMIE OTGFS GPIOIE GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
PKAEN ADCEN Res. Res. Res.
N EN N EN EN EN EN EN EN EN EN
rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 SDMMC2EN: SDMMC2 clock enable
Set and cleared by software.
0: SDMMC2 clock disabled
1: SDMMC2 clock enabled
Bit 22 SDMMC1EN: SDMMC1 clock enable
Set and cleared by software.
0: SDMMC1 clock disabled
1: SDMMC1 clock enabled
Bit 21 Reserved, must be kept at reset value.
Bit 20 OSPIMEN: OctoSPI IO manager clock enable
Set and cleared by software.
0: OctoSPI IO manager clock disabled
1: OctoSPI IO manager clock enabled
Bit 19 Reserved, must be kept at reset value.

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Bit 18 RNGEN: Random Number Generator clock enable

Set and cleared by software.
0: Random Number Generator clock disabled
1: Random Number Generator clock enabled
Bit 17 HASHEN: HASH clock enable
Set and cleared by software
0: HASH clock disabled
1: HASH clock enabled
Bit 16 AESEN: AES accelerator clock enable
Set and cleared by software.
0: AES clock disabled
1: AES clock enabled
Bit 15 PKAEN: PKA clock enable
Set and cleared by software.
0: PKA clock disabled
1: PKA clock enabled
Bit 14 DCMIEN: DCMI or PSSI clock enable (DCMI or PSSI depending on which interface is active)
Set and cleared by software
0: DCMI/PSSI clock disabled
1: DCMI/PSSI clock enabled
Bit 13 ADCEN: ADC clock enable
Set and cleared by software.
0: ADC clock disabled
1: ADC clock enabled
Bit 12 OTGFSEN: OTG full speed clock enable
Set and cleared by software.
0: USB OTG full speed clock disabled
1: USB OTG full speed clock enabled
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 GPIOIEN: IO port I clock enable
Set and cleared by software
0: IO port I clock disabled
1: IO port I clock enabled
Bit 7 GPIOHEN: IO port H clock enable
Set and cleared by software.
0: IO port H clock disabled
1: IO port H clock enabled
Bit 6 GPIOGEN: IO port G clock enable
Set and cleared by software.
0: IO port G clock disabled
1: IO port G clock enabled
Bit 5 GPIOFEN: IO port F clock enable
Set and cleared by software.
0: IO port F clock disabled
1: IO port F clock enabled

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RM0432 Reset and clock control (RCC)

Bit 4 GPIOEEN: IO port E clock enable

Set and cleared by software.
0: IO port E clock disabled
1: IO port E clock enabled
Bit 3 GPIODEN: IO port D clock enable
Set and cleared by software.
0: IO port D clock disabled
1: IO port D clock enabled
Bit 2 GPIOCEN: IO port C clock enable
Set and cleared by software.
0: IO port C clock disabled
1: IO port C clock enabled
Bit 1 GPIOBEN: IO port B clock enable
Set and cleared by software.
0: IO port B clock disabled
1: IO port B clock enabled
Bit 0 GPIOAEN: IO port A clock enable
Set and cleared by software.
0: IO port A clock disabled
1: IO port A clock enabled

6.4.18 AHB3 peripheral clock enable register(RCC_AHB3ENR)

Address offset: 0x50
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPI2 OSPI1E FMCE
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EN N N
rw rw rw

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 OSPI2EN: OctoSPI2 memory interface clock enable
Set and cleared by software.
0: OctoSPI2 clock disable
1: OctoSPI2 clock enable

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Bit 8 OSPI1EN: OctoSPI1 memory interface clock enable

Set and cleared by software.
0: OctoSPI1 clock disable
1: OctoSPI1 clock enable
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 FMCEN: Flexible memory controller clock enable
Set and cleared by software.
0: FMC clock disable
1: FMC clock enable

6.4.19 APB1 peripheral clock enable register 1 (RCC_APB1ENR1)

Address: 0x58
Reset value: 0x0000 0400
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1 OPAMP DAC1 PWRE CAN1E I2C3E I2C2E I2C1E UART5E UART4E USART3 USART2
Res. Res. CRSEN Res.
EN EN EN N N N N N N N EN EN
rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WWD RTCA TIM7E TIM2E
SPI3EN SPI2EN Res. Res. Res. Res. Res. Res. TIM6EN TIM5EN TIM4EN TIM3EN
GEN PBEN N N
rw rw rs rw rw rw rw rw rw rw

Bit 31 LPTIM1EN: Low power timer 1 clock enable

Set and cleared by software.
0: LPTIM1 clock disabled
1: LPTIM1 clock enabled
Bit 30 OPAMPEN: OPAMP interface clock enable
Set and cleared by software.
0: OPAMP interface clock disabled
1: OPAMP interface clock enabled
Bit 29 DAC1EN: DAC1 interface clock enable
Set and cleared by software.
0: DAC1 interface clock disabled
1: DAC1 interface clock enabled
Bit 28 PWREN: Power interface clock enable
Set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enabled
Bit 27:26 Reserved, must be kept at reset value.

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RM0432 Reset and clock control (RCC)

Bit 25 CAN1EN: CAN1 clock enable

Set and cleared by software.
0: CAN1 clock disabled
1: CAN1 clock enabled
Bit 24 CRSEN: Clock Recovery System clock enable
Set and cleared by software
0: CRS clock disabled
1: CRS clock enabled
Bit 23 I2C3EN: I2C3 clock enable
Set and cleared by software.
0: I2C3 clock disabled
1: I2C3 clock enabled
Bit 22 I2C2EN: I2C2 clock enable
Set and cleared by software.
0: I2C2 clock disabled
1: I2C2 clock enabled
Bit 21 I2C1EN: I2C1 clock enable
Set and cleared by software.
0: I2C1 clock disabled
1: I2C1 clock enabled
Bit 20 UART5EN: UART5 clock enable
Set and cleared by software.
0: UART5 clock disabled
1: UART5 clock enabled
Bit 19 UART4EN: UART4 clock enable
Set and cleared by software.
0: UART4 clock disabled
1: UART4 clock enabled
Bit 18 USART3EN: USART3 clock enable
Set and cleared by software.
0: USART3 clock disabled
1: USART3 clock enabled
Bit 17 USART2EN: USART2 clock enable
Set and cleared by software.
0: USART2 clock disabled
1: USART2 clock enabled
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3EN: SPI3 clock enable
Set and cleared by software.
0: SPI3 clock disabled
1: SPI3 clock enabled
Bit 14 SPI2EN: SPI2 clock enable
Set and cleared by software.
0: SPI2 clock disabled
1: SPI2 clock enabled
Bits 13:12 Reserved, must be kept at reset value.

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Bit 11 WWDGEN: Window watchdog clock enable

Set by software to enable the window watchdog clock. Reset by hardware system reset.
This bit can also be set by hardware if the WWDG_SW option bit is reset.
0: Window watchdog clock disabled
1: Window watchdog clock enabled
Bit 10 RTCAPBEN: RTC APB clock enable
Set and cleared by software
0: RTC APB clock disabled
1: RTC APB clock enabled
Bits 9:6 Reserved, must be kept at reset value.
Bit 5 TIM7EN: TIM7 timer clock enable
Set and cleared by software.
0: TIM7 clock disabled
1: TIM7 clock enabled
Bit 4 TIM6EN: TIM6 timer clock enable
Set and cleared by software.
0: TIM6 clock disabled
1: TIM6 clock enabled
Bit 3 TIM5EN: TIM5 timer clock enable
Set and cleared by software.
0: TIM5 clock disabled
1: TIM5 clock enabled
Bit 2 TIM4EN: TIM4 timer clock enable
Set and cleared by software.
0: TIM4 clock disabled
1: TIM4 clock enabled
Bit 1 TIM3EN: TIM3 timer clock enable
Set and cleared by software.
0: TIM3 clock disabled
1: TIM3 clock enabled
Bit 0 TIM2EN: TIM2 timer clock enable
Set and cleared by software.
0: TIM2 clock disabled
1: TIM2 clock enabled

6.4.20 APB1 peripheral clock enable register 2 (RCC_APB1ENR2)

Address offset: 0x5C
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.

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RM0432 Reset and clock control (RCC)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPTIM2 LPUAR
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. I2C4EN
EN T1EN
rw rw

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 LPTIM2EN Low power timer 2 clock enable
Set and cleared by software.
0: LPTIM2 clock disable
1: LPTIM2 clock enable
Bits 4:2 Reserved, must be kept at reset value.
Bit 1 I2C4EN: I2C4 clock enable
Set and cleared by software
0: I2C4 clock disabled
1: I2C4 clock enabled
Bit 0 LPUART1EN: Low power UART 1 clock enable
Set and cleared by software.
0: LPUART1 clock disable
1: LPUART1 clock enable

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6.4.21 APB2 peripheral clock enable register (RCC_APB2ENR)

Address: 0x60
Reset value: 0x0000 0000
Access: word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LTDCE DFSD SAI2E SAI1E TIM17E TIM16E TIM15E
Res. Res. Res. Res. DSIEN Res. Res. Res. Res.
N M1EN N N N N N
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART TIM8E SPI1E TIM1E SYSCF
Res. Res. Res. Res. FWEN Res. Res. Res. Res. Res. Res.
1EN N N N GEN
rw rw rw rw rs rw

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 DSIEN: DSI clock enable
Set and cleared by software.
0: DSI clock disabled
1: DSI clock enable
Bit 26 LTDCEN: LCD-TFT clock enable
Set and cleared by software.
0: LTDC clock disabled
1: LTDC clock enable
Bit 25 Reserved, must be kept at reset value.
Bit 24 DFSDM1EN: DFSDM1 timer clock enable
Set and cleared by software.
0: DFSDM1 clock disabled
1: DFSDM1 clock enabled
Bit 23 Reserved, must be kept at reset value.
Bit 22 SAI2EN: SAI2 clock enable
Set and cleared by software.
0: SAI2 clock disabled
1: SAI2 clock enabled
Bit 21 SAI1EN: SAI1 clock enable
Set and cleared by software.
0: SAI1 clock disabled
1: SAI1 clock enabled
Bits 20:19 Reserved, must be kept at reset value.
Bit 18 TIM17EN: TIM17 timer clock enable
Set and cleared by software.
0: TIM17 timer clock disabled
1: TIM17 timer clock enabled

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RM0432 Reset and clock control (RCC)

Bit 17 TIM16EN: TIM16 timer clock enable

Set and cleared by software.
0: TIM16 timer clock disabled
1: TIM16 timer clock enabled
Bit 16 TIM15EN: TIM15 timer clock enable
Set and cleared by software.
0: TIM15 timer clock disabled
1: TIM15 timer clock enabled
Bit 15 Reserved, must be kept at reset value.
Bit 14 USART1EN: USART1clock enable
Set and cleared by software.
0: USART1clock disabled
1: USART1clock enabled
Bit 13 TIM8EN: TIM8 timer clock enable
Set and cleared by software.
0: TIM8 timer clock disabled
1: TIM8 timer clock enabled
Bit 12 SPI1EN: SPI1 clock enable
Set and cleared by software.
0: SPI1 clock disabled
1: SPI1 clock enabled
Bit 11 TIM1EN: TIM1 timer clock enable
Set and cleared by software.
0: TIM1 timer clock disabled
1: TIM1P timer clock enabled
Bits 10:8 Reserved, must be kept at reset value.
Bit 7 FWEN: Firewall clock enable
Set by software, reset by hardware. Software can only write 1. A write at 0 has no effect.
0: Firewall clock disabled
1: Firewall clock enabled
Bits 6:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGEN: SYSCFG + COMP + VREFBUF clock enable
Set and cleared by software.
0: SYSCFG + COMP + VREFBUF clock disabled
1: SYSCFG + COMP + VREFBUF clock enabled

6.4.22 AHB1 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB1SMENR)
Address offset: 0x68
Reset value: 0x0007 1307
Access: no wait state, word, half-word and byte access

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GFXM
DMA2D TSCS
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MUSM
SMEN MEN
EN
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAM
SRAM1 FLASH DMA2S DMA1
Res. Res. Res. CRCSMEN Res. Res. Res. Res. Res. Res. Res. UX1S
SMEN SMEN MEN SMEN
MEN
rw rw rw rw rw

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 GFXMMUSMEN: GFXMMU clock enable during Sleep and Stop modes.
Set and cleared by software
0: GFXMMU clocks disabled by the clock gating(1) during Sleep and Stop modes
1: GFXMMU clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 17 DMA2DSMEN: DMA2D clock enable during Sleep and Stop modes
Set and cleared by software
0: DMA2D clocks disabled by the clock gating(1) during Sleep and Stop modes
1: DMA2D clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 16 TSCSMEN: Touch Sensing Controller clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TSC clocks disabled by the clock gating(1) during Sleep and Stop modes
1: TSC clocks enabled by the clock gating(1) during Sleep and Stop modes
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CRCSMEN: CRC clocks enable during Sleep and Stop modes
Set and cleared by software.
0: CRC clocks disabled by the clock gating(1) during Sleep and Stop modes
1: CRC clocks enabled by the clock gating(1) during Sleep and Stop modes
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 SRAM1SMEN: SRAM1 interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SRAM1 interface clocks disabled by the clock gating(1) during Sleep and Stop modes
1: SRAM1 interface clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 8 FLASHSMEN: Flash memory interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: Flash memory interface clocks disabled by the clock gating(1) during Sleep and Stop
modes
1: Flash memory interface clocks enabled by the clock gating(1) during Sleep and Stop
modes
Bits 7:3 Reserved, must be kept at reset value.

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Bit 2 DMAMUX1SMEN: DMAMUX1 clock enable during Sleep and Stop modes.
Set and cleared by software.
0: DMAMUX1 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: DMAMUX1 clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 1 DMA2SMEN: DMA2 clocks enable during Sleep and Stop modes
Set and cleared by software during Sleep mode.
0: DMA2 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: DMA2 clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 0 DMA1SMEN: DMA1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: DMA1 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: DMA1 clocks enabled by the clock gating(1) during Sleep and Stop modes
1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.

6.4.23 AHB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB2SMENR)
Address offset: 0x6C
Reset value: 0x0057 77FF
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMM SDMM
OSPIM RNGS HASHS AESSM
Res. Res. Res. Res. Res. Res. Res. Res. C2SME C1SME Res. Res.
SMEN MEN MEN EN
N N
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PKASM DCMIS ADCS OTGFS SRAM3 SRAM2 GPIOIS GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Res.
EN MEN MEN SMEN SMEN SMEN MEN SMEN SMEN SMEN SMEN SMEN SMEN SMEN SMEN
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 SDMMC2SMEN: SDMMC2 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SDMMC2 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: SDMMC2 clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 22 SDMMC1SMEN: SDMMC1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SDMMC1 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: SDMMC1 clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 21 Reserved, must be kept at reset value.
Bit 20 OSPIMSMEN: OctoSPI IO manager clocks enable during Sleep and Stop modes
Set and cleared by software.
0: OCTOSPIM clocks disabled by the clock gating(1) during Sleep and Stop modes
1: OCTOSPIM clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 19 Reserved, must be kept at reset value.

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Bit 18 RNGSMEN: Random Number Generator clocks enable during Sleep and Stop modes
Set and cleared by software.
0: Random Number Generator clocks disabled by the clock gating during Sleep and Stop
modes
1: Random Number Generator clocks enabled by the clock gating during Sleep and Stop
modes
Bit 17 HASHSMEN: HASH clock enable during Sleep and Stop modes
Set and cleared by software
0: HASH clocks disabled by the clock gating(1) during Sleep and Stop modes
1: HASH clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 16 AESSMEN: AES accelerator clocks enable during Sleep and Stop modes
Set and cleared by software.
0: AES clocks disabled by the clock gating(1) during Sleep and Stop modes
1: AES clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 15 PKASMEN: PKA clocks enable during Sleep and Stop modes
Set and cleared by software.
0: PKA clocks disabled by the clock gating(1) during Sleep and Stop modes
1: PKA clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 14 DCMISMEN: DCMI or PSSI clock enable during Sleep and Stop modes. (DCMI or PSSI
depending on which interface is active)
Set and cleared by software
0: DCMI/PSSI clocks disabled by the clock gating(1) during Sleep and Stop modes
1: DCMI/PSSI clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 13 ADCSMEN: ADC clocks enable during Sleep and Stop modes
Set and cleared by software.
0: ADC clocks disabled by the clock gating(1) during Sleep and Stop modes
1: ADC clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 12 OTGFSSMEN: OTG full speed clocks enable during Sleep and Stop modes
Set and cleared by software.
0: USB OTG full speed clocks disabled by the clock gating(1) during Sleep and Stop modes
1: USB OTG full speed clocks enabled by the clock gating(1) during Sleep and Stop modes
Bits 11 Reserved, must be kept at reset value.
Bit 10 SRAM3SMEN: SRAM2 interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SRAM3 interface clocks disabled by the clock gating(1) during Sleep and Stop modes
1: SRAM3 interface clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 9 SRAM2SMEN: SRAM2 interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SRAM2 interface clocks disabled by the clock gating(1) during Sleep and Stop modes
1: SRAM2 interface clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 8 GPIOISMEN: IO port I clocks enable during Sleep and Stop modes
Set and cleared by software
0: IO port I clocks disabled by the clock gating(1) during Sleep and Stop modes
1: IO port I clocks enabled by the clock gating(1) during Sleep and Stop modes

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RM0432 Reset and clock control (RCC)

Bit 7 GPIOHSMEN: IO port H clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port H clocks disabled by the clock gating(1) during Sleep and Stop modes
1: IO port H clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 6 GPIOGSMEN: IO port G clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port G clocks disabled by the clock gating(1) during Sleep and Stop modes
1: IO port G clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 5 GPIOFSMEN: IO port F clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port F clocks disabled by the clock gating(1) during Sleep and Stop modes
1: IO port F clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 4 GPIOESMEN: IO port E clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port E clocks disabled by the clock gating(1) during Sleep and Stop modes
1: IO port E clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 3 GPIODSMEN: IO port D clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port D clocks disabled by the clock gating(1) during Sleep and Stop modes
1: IO port D clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 2 GPIOCSMEN: IO port C clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port C clocks disabled by the clock gating(1) during Sleep and Stop modes
1: IO port C clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 1 GPIOBSMEN: IO port B clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port B clocks disabled by the clock gating(1) during Sleep and Stop modes
1: IO port B clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 0 GPIOASMEN: IO port A clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port A clocks disabled by the clock gating(1) during Sleep and Stop modes
1: IO port A clocks enabled by the clock gating(1) during Sleep and Stop modes
1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.

6.4.24 AHB3 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB3SMENR)
Address offset: 0x70
Reset value: 0x00000 0301
Access: no wait state, word, half-word and byte access

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTOS OSPI1S FMCS
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
PI2 MEN MEN
rw rw rw

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 OCTOSPI2: OctoSPI2 memory interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: OctoSPI2 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: OctoSPI2 clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 8 OSPI1SMEN: OctoSPI1 memory interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: OctoSPI1 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: OctoSPI1 clocks enabled by the clock gating(1) during Sleep and Stop modes
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 FMCSMEN: Flexible memory controller clocks enable during Sleep and Stop modes
Set and cleared by software.
0: FMC clocks disabled by the clock gating(1) during Sleep and Stop modes
1: FMC clocks enabled by the clock gating(1) during Sleep and Stop modes
1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.

6.4.25 APB1 peripheral clocks enable in Sleep and Stop modes register 1
(RCC_APB1SMENR1)
Address: 0x78
Reset value: 0xF3FECC3F
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1 OPAMP DAC1 PWRS CAN1S CRSS I2C3S I2C2S I2C1S UART5S UART4S USART3 USART2
Res. Res. Res.
SMEN SMEN SMEN MEN MEN MEN MEN MEN MEN MEN MEN SMEN SMEN
rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCA
SPI3S SPI2S WWDG TIM7S TIM6SM TIM5SM TIM4SM TIM3SM TIM2S
Res. Res. PBSM Res. Res. Res. Res.
MEN MEN SMEN MEN EN EN EN EN MEN
EN
rw rw rw rw rw rw rw rw rw rw

Bit 31 LPTIM1SMEN: Low power timer 1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: LPTIM1 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: LPTIM1 clocks enabled by the clock gating(1) during Sleep and Stop modes

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RM0432 Reset and clock control (RCC)

Bit 30 OPAMPSMEN: OPAMP interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: OPAMP interface clocks disabled by the clock gating(1) during Sleep and Stop modes
1: OPAMP interface clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 29 DAC1SMEN: DAC1 interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: DAC1 interface clocks disabled by the clock gating(1) during Sleep and Stop modes
1: DAC1 interface clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 28 PWRSMEN: Power interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: Power interface clocks disabled by the clock gating(1) during Sleep and Stop modes
1: Power interface clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 27 Reserved, must be kept at reset value.
Bit 25 CAN1SMEN: CAN1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: CAN1 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: CAN1 clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 24 CRSSMEN: CRS clock enable during Sleep and Stop modes
Set and cleared by software.
0: CRS clocks disabled by the clock gating(1) during Sleep and Stop modes
1: CRS clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 23 I2C3SMEN: I2C3 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: I2C3 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: I2C3 clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 22 I2C2SMEN: I2C2 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: I2C2 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: I2C2 clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 21 I2C1SMEN: I2C1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: I2C1 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: I2C1 clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 20 UART5SMEN: UART5 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: UART5 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: UART5 clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 19 UART4SMEN: UART4 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: UART4 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: UART4 clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 18 USART3SMEN: USART3 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: USART3 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: USART3 clocks enabled by the clock gating(1) during Sleep and Stop modes

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Bit 17 USART2SMEN: USART2 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: USART2 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: USART2 clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3SMEN: SPI3 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SPI3 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: SPI3 clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 14 SPI2SMEN: SPI2 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SPI2 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: SPI2 clocks enabled by the clock gating(1) during Sleep and Stop modes
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGSMEN: Window watchdog clocks enable during Sleep and Stop modes
Set and cleared by software. This bit is forced to ‘1’ by hardware when the hardware WWDG
option is activated.
0: Window watchdog clocks disabled by the clock gating(1) during Sleep and Stop modes
1: Window watchdog clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 10 RTCAPBSMEN: RTC APB clock enable during Sleep and Stop modes
Set and cleared by software
0: RTC APB clock disabled by the clock gating(1) during Sleep and Stop modes
1: RTC APB clock enabled by the clock gating(1) during Sleep and Stop modes
Bits :6 Reserved, must be kept at reset value.
Bit 5 TIM7SMEN: TIM7 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM7 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: TIM7 clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 4 TIM6SMEN: TIM6 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM6 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: TIM6 clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 3 TIM5SMEN: TIM5 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM5 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: TIM5 clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 2 TIM4SMEN: TIM4 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM4 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: TIM4 clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 1 TIM3SMEN: TIM3 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM3 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: TIM3 clocks enabled by the clock gating(1) during Sleep and Stop modes

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RM0432 Reset and clock control (RCC)

Bit 0 TIM2SMEN: TIM2 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM2 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: TIM2 clocks enabled by the clock gating(1) during Sleep and Stop modes
1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.

6.4.26 APB1 peripheral clocks enable in Sleep and Stop modes register 2
(RCC_APB1SMENR2)
Address offset: 0x7C
Reset value: 0x0000 0023
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPTIM I2C4S LPUART
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
2SMEN MEN 1SMEN
rw rw rw

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 LPTIM2SMEN Low power timer 2 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: LPTIM2 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: LPTIM2 clocks enabled by the clock gating(1) during Sleep and Stop modes
Bits 4: Reserved, must be kept at reset value.
Bit 1 I2C4SMEN: I2C4 clocks enable during Sleep and Stop modes
Set and cleared by software
0: I2C4 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: I2C4 clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 0 LPUART1SMEN: Low power UART 1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: LPUART1 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: LPUART1 clocks enabled by the clock gating(1) during Sleep and Stop modes
1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.

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6.4.27 APB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_APB2SMENR)
Address: 0x80
Reset value: 0x0D67 7801
Access: word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSD
.DSISM LTDCS SAI2S SAI1S TIM17S TIM16S TIM15S
Res. Res. Res. Res. Res. M1SM Res. Res. Res.
EN MEN MEN MEN MEN MEN MEN
EN
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSCF
USART TIM8S SPI1S TIM1S
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. GSME
1SMEN MEN MEN MEN
N
rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 DSISMEN: DSI clocks enable during Sleep and Stop modes
Set and cleared by software.
0: DSI clocks disabled by the clock gating(1) during Sleep and Stop modes
1: DSI clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 26 LTDCSMEN: LCD-TFT timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: LCD-TFT clocks disabled by the clock gating(1) during Sleep and Stop modes
1: LCD-TFT clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 25 Reserved, must be kept at reset value.
Bit 24 DFSDM1SMEN: DFSDM1 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: DFSDM1 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: DFSDM1 clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 23 Reserved, must be kept at reset value.
Bit 22 SAI2SMEN: SAI2 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SAI2 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: SAI2 clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 21 SAI1SMEN: SAI1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SAI1 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: SAI1 clocks enabled by the clock gating(1) during Sleep and Stop modes
Bits 20:19 Reserved, must be kept at reset value.
Bit 18 TIM17SMEN: TIM17 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM17 timer clocks disabled by the clock gating(1) during Sleep and Stop modes
1: TIM17 timer clocks enabled by the clock gating(1) during Sleep and Stop modes

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RM0432 Reset and clock control (RCC)

Bit 17 TIM16SMEN: TIM16 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM16 timer clocks disabled by the clock gating(1) during Sleep and Stop modes
1: TIM16 timer clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 16 TIM15SMEN: TIM15 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM15 timer clocks disabled by the clock gating(1) during Sleep and Stop modes
1: TIM15 timer clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 15 Reserved, must be kept at reset value.
Bit 14 USART1SMEN: USART1clocks enable during Sleep and Stop modes
Set and cleared by software.
0: USART1clocks disabled by the clock gating(1) during Sleep and Stop modes
1: USART1clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 13 TIM8SMEN: TIM8 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM8 timer clocks disabled by the clock gating(1) during Sleep and Stop modes
1: TIM8 timer clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 12 SPI1SMEN: SPI1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SPI1 clocks disabled by the clock gating during(1) Sleep and Stop modes
1: SPI1 clocks enabled by the clock gating during(1) Sleep and Stop modes
Bit 11 TIM1SMEN: TIM1 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM1 timer clocks disabled by the clock gating(1) during Sleep and Stop modes
1: TIM1P timer clocks enabled by the clock gating(1) during Sleep and Stop modes
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGSMEN: SYSCFG + COMP + VREFBUF clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SYSCFG + COMP + VREFBUF clocks disabled by the clock gating(1) during Sleep and
Stop modes
1: SYSCFG + COMP + VREFBUF clocks enabled by the clock gating(1) during Sleep and
Stop modes
1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.

6.4.28 Peripherals independent clock configuration register (RCC_CCIPR)

Address: 0x88
Reset value: 0x0000 0000
Access: no wait states, word, half-word and byte access

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. ADCSEL[1:0] CLK48SEL[1:0] Res. LPTIM2SEL[1:0] LPTIM1SEL[1:0 I2C3SEL[1:0]
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPUART1SEL[1: USART3SEL[1:0 USART1SEL[1:0
I2C2SEL[1:0] I2C1SEL[1:0] UART5SEL[1:0] UART4SEL[1:0] USART2SEL[1:0]
0] ] ]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 Reserved, must be kept at reset value.

Bit 30 Reserved, must be kept at reset value.
Bits 29:28 ADCSEL[1:0]: ADCs clock source selection
These bits are set and cleared by software to select the clock source used by the ADC
interface.
00: No clock selected
01: PLLSAI1 “R” clock (PLLADC1CLK) selected as ADC clock
10: Reserved
11: System clock selected as ADCs clock
Bits 27:26 CLK48SEL[1:0]: 48 MHz clock source selection
These bits are set and cleared by software to select the 48 MHz clock source used by USB
OTG FS, RNG and SDMMC.
00: HSI48 clock selected as 48 MHz clock
01: PLLSAI1 “Q” clock (PLL48M2CLK) selected as 48 MHz clock
10: PLL “Q” clock (PLL48M1CLK) selected as 48 MHz clock
11: MSI clock selected as 48 MHz clock
Bits 22:25 Reserved, must be kept at reset value.
Bits 21:20 LPTIM2SEL[1:0]: Low power timer 2 clock source selection
These bits are set and cleared by software to select the LPTIM2 clock source.
00: PCLK selected as LPTIM2 clock
01: LSI clock selected as LPTIM2 clock
10: HSI16 clock selected as LPTIM2 clock
11: LSE clock selected as LPTIM2 clock
Bits 19:18 LPTIM1SEL[1:0]: Low power timer 1 clock source selection
These bits are set and cleared by software to select the LPTIM1 clock source.
00: PCLK selected as LPTIM1 clock
01: LSI clock selected as LPTIM1 clock
10: HSI16 clock selected as LPTIM1 clock
11: LSE clock selected as LPTIM1 clock
Bits 17:16 I2C3SEL[1:0]: I2C3 clock source selection
These bits are set and cleared by software to select the I2C3 clock source.
00: PCLK selected as I2C3 clock
01: System clock (SYSCLK) selected as I2C3 clock
10: HSI16 clock selected as I2C3 clock
11: Reserved

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RM0432 Reset and clock control (RCC)

Bits 15:14 I2C2SEL[1:0]: I2C2 clock source selection

These bits are set and cleared by software to select the I2C2 clock source.
00: PCLK selected as I2C2 clock
01: System clock (SYSCLK) selected as I2C2 clock
10: HSI16 clock selected as I2C2 clock
11: Reserved
Bits 13:12 I2C1SEL[1:0]: I2C1 clock source selection
These bits are set and cleared by software to select the I2C1 clock source.
00: PCLK selected as I2C1 clock
01: System clock (SYSCLK) selected as I2C1 clock
10: HSI16 clock selected as I2C1 clock
11: Reserved
Bits 11:10 LPUART1SEL[1:0]: LPUART1 clock source selection
These bits are set and cleared by software to select the LPUART1 clock source.
00: PCLK selected as LPUART1 clock
01: System clock (SYSCLK) selected as LPUART1 clock
10: HSI16 clock selected as LPUART1 clock
11: LSE clock selected as LPUART1 clock
Bits 9:8 UART5SEL[1:0]: UART5 clock source selection
These bits are set and cleared by software to select the UART5 clock source.
00: PCLK selected as UART5 clock
01: System clock (SYSCLK) selected as UART5 clock
10: HSI16 clock selected as UART5 clock
11: LSE clock selected as UART5 clock
Bits 7:6 UART4SEL[1:0]: UART4 clock source selection
This bit is set and cleared by software to select the UART4 clock source.
00: PCLK selected as UART4 clock
01: System clock (SYSCLK) selected as UART4 clock
10: HSI16 clock selected as UART4 clock
11: LSE clock selected as UART4 clock
Bits 5:4 USART3SEL[1:0]: USART3 clock source selection
This bit is set and cleared by software to select the USART3 clock source.
00: PCLK selected as USART3 clock
01: System clock (SYSCLK) selected as USART3 clock
10: HSI16 clock selected as USART3 clock
11: LSE clock selected as USART3 clock
Bits 3:2 USART2SEL[1:0]: USART2 clock source selection
This bit is set and cleared by software to select the USART2 clock source.
00: PCLK selected as USART2 clock
01: System clock (SYSCLK) selected as USART2 clock
10: HSI16 clock selected as USART2 clock
11: LSE clock selected as USART2 clock
Bits 1:0 USART1SEL[1:0]: USART1 clock source selection
This bit is set and cleared by software to select the USART1 clock source.
00: PCLK selected as USART1 clock
01: System clock (SYSCLK) selected as USART1 clock
10: HSI16 clock selected as USART1 clock
11: LSE clock selected as USART1 clock

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Reset and clock control (RCC) RM0432

6.4.29 Backup domain control register (RCC_BDCR)

Address offset: 0x90
Reset value: 0x0000 0000, reset by Backup domain Reset, except LSCOSEL, LSCOEN
and BDRST which are reset only by Backup domain power-on reset.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
Note: The bits of the Backup domain control register (RCC_BDCR) are outside of the VCORE
domain. As a result, after Reset, these bits are write-protected and the DBP bit in the
Section 5.4.1: Power control register 1 (PWR_CR1) has to be set before these can be
modified. Refer to Section 5.1.5: Battery backup domain on page 186 for further
information. These bits (except LSCOSEL, LSCOEN and BDRST) are only reset after a
Backup domain Reset (see Section 6.1.3: Backup domain reset). Any internal or external
Reset will not have any effect on these bits.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSCOS LSCOE
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BDRST
EL N
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTC LSESY LSE LSE LSE LSE
Res. Res. Res. Res. Res. RTCSEL[1:0] LSEDRV[1:0] LSEON
EN SDIS CSSD CSSON BYP RDY
rw rw rw rw r rw rw rw rw r rw

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 LSCOSEL: Low speed clock output selection
Set and cleared by software.
0: LSI clock selected
1: LSE clock selected
Bit 24 LSCOEN: Low speed clock output enable
Set and cleared by software.
0: Low speed clock output (LSCO) disable
1: Low speed clock output (LSCO) enable
Bits 23:17 Reserved, must be kept at reset value.
Bit 16 BDRST: Backup domain software reset
Set and cleared by software.
0: Reset not activated
1: Reset the entire Backup domain
Bit 15 RTCEN: RTC clock enable
Set and cleared by software.
0: RTC clock disabled
1: RTC clock enabled
Bits 14:10 Reserved, must be kept at reset value.

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RM0432 Reset and clock control (RCC)

Bits 9:8 RTCSEL[1:0]: RTC clock source selection

Set by software to select the clock source for the RTC. Once the RTC clock source has been
selected, it cannot be changed anymore unless the Backup domain is reset, or unless a
failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them.
00: No clock
01: LSE oscillator clock used as RTC clock
10: LSI oscillator clock used as RTC clock
11: HSE oscillator clock divided by 32 used as RTC clock
Bit 7 LSESYSDIS: Disable the Clock LSE propagation to the system
Set by software to disable the Clock LSE propagation to the system. Only RTC is clocked by
LSE when this bit is set.
1: No clock LSE propagation
0: Clock LSE propagation enabled
Note: This bit is available only on STM32L4P5xx and STM32L4Q5xx.
Bit 6 LSECSSD: CSS on LSE failure detection
Set by hardware to indicate when a failure has been detected by the clock security system
on the external 32 kHz oscillator (LSE).
0: No failure detected on LSE (32 kHz oscillator)
1: Failure detected on LSE (32 kHz oscillator)
Bit 5 LSECSSON: CSS on LSE enable
Set by software to enable the Clock Security System on LSE (32 kHz oscillator).
LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and
ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected and LSIPREDIV
(see note below) is disabled.
Once enabled this bit cannot be disabled, except after a LSE failure detection (LSECSSD
=1). In that case the software MUST disable the LSECSSON bit.
0: CSS on LSE (32 kHz external oscillator) OFF
1: CSS on LSE (32 kHz external oscillator) ON
Note: LSIPREDIV bit is available only on STM32L5P5xx and STM32L4Q5xx.
Bits 4:3 LSEDRV[1:0] LSE oscillator drive capability
Set by software to modulate the LSE oscillator’s drive capability.
00: ‘Xtal mode’ lower driving capability
01: ‘Xtal mode’ medium low driving capability
10: ‘Xtal mode’ medium high driving capability
11: ‘Xtal mode’ higher driving capability
The oscillator is in Xtal mode when it is not in bypass mode.

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Reset and clock control (RCC) RM0432

Bit 2 LSEBYP: LSE oscillator bypass

Set and cleared by software to bypass oscillator in debug mode. This bit can be written only
when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0).
0: LSE oscillator not bypassed
1: LSE oscillator bypassed
Bit 1 LSERDY: LSE oscillator ready
Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After
the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock
cycles.
0: LSE oscillator not ready
1: LSE oscillator ready
Bit 0 LSEON: LSE oscillator enable
Set and cleared by software.
0: LSE oscillator OFF
1: LSE oscillator ON

6.4.30 Control/status register (RCC_CSR)

Address: 0x94
Reset value: 0x0C00 0600, reset by system Reset, except reset flags by power Reset only.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPWR WWDG IWWG SFTRS BORR PINRS OBLRS FWRST
RMVF Res. Res. Res. Res. Res. Res. Res.
RSTF RSTF RSTF TF STF TF TF F
r r r r r r r r rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSIPR
Res. Res. Res. Res. MSISRANGE[3:0] Res. Res. Res. Res. Res. LSIRDY LSION
EDIV
rw rw rw rw rw r rw

Bit 31 LPWRRSTF: Low-power reset flag

Set by hardware when a reset occurs due to illegal Stop, Standby or Shutdown mode entry.
Cleared by writing to the RMVF bit.
0: No illegal mode reset occurred
1: Illegal mode reset occurred
Bit 30 WWDGRSTF: Window watchdog reset flag
Set by hardware when a window watchdog reset occurs.
Cleared by writing to the RMVF bit.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
Bit 29 IWDGRSTF: Independent window watchdog reset flag
Set by hardware when an independent watchdog reset domain occurs.
Cleared by writing to the RMVF bit.
0: No independent watchdog reset occurred
1: Independent watchdog reset occurred

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RM0432 Reset and clock control (RCC)

Bit 28 SFTRSTF: Software reset flag

Set by hardware when a software reset occurs.
Cleared by writing to the RMVF bit.
0: No software reset occurred
1: Software reset occurred
Bit 27 BORRSTF: BOR flag
Set by hardware when a BOR occurs.
Cleared by writing to the RMVF bit.
0: No BOR occurred
1: BOR occurred
Bit 26 PINRSTF: Pin reset flag
Set by hardware when a reset from the NRST pin occurs.
Cleared by writing to the RMVF bit.
0: No reset from NRST pin occurred
1: Reset from NRST pin occurred
Bit 25 OBLRSTF: Option byte loader reset flag
Set by hardware when a reset from the Option Byte loading occurs.
Cleared by writing to the RMVF bit.
0: No reset from Option Byte loading occurred
1: Reset from Option Byte loading occurred
Bit 24 FWRSTF: Firewall reset flag
Set by hardware when a reset from the firewall occurs.
Cleared by writing to the RMVF bit.
0: No reset from the firewall occurred
1: Reset from the firewall occurred
Bit 23 RMVF: Remove reset flag
Set by software to clear the reset flags.
0: No effect
1: Clear the reset flags
Bits 22:12 Reserved, must be kept at reset value.
Bits 11:8 MSISRANGE[3:0] MSI range after Standby mode
Set by software to chose the MSI frequency at startup. This range is used after exiting
Standby mode until MSIRGSEL is set. After a pad or a power-on reset, the range is always
4 MHz. MSISRANGE can be written only when MSIRGSEL = ‘1’.
0100: Range 4 around 1 MHz
0101: Range 5 around 2 MHz
0101: Range 6 around 4 MHz (reset value)
0111: Range 7 around 8 MHz
others: Reserved
Note: Changing the MSISRANGE does not change the current MSI frequency.
Bits 7:5 Reserved, must be kept at reset value.

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Reset and clock control (RCC) RM0432

Bit 4 LSIPREDIV: Internal low-speed oscillator predivided by 128

Set and reset by software. This bit is used to enable the internal clock divider (/128) of the
LSI clock. The software has to disable the LSI (LSION=0 and LSIRDY=0) before to change
this bit.
0: LSI PREDIV OFF
1: LSI PREDIV ON
Note: This bit is available only on STM32L4P5xx and STM32L4Q5xx devices.
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 LSIRDY: LSI oscillator ready
Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit
is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if
LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent
Watchdog or by the RTC.
0: LSI oscillator not ready
1: LSI oscillator ready
Bit 0 LSION: LSI oscillator enable
Set and cleared by software.
0: LSI oscillator OFF
1: LSI oscillator ON

6.4.31 Clock recovery RC register (RCC_CRRCR)

Address: 0x98
Reset value: 0x0000 XXX0 where X is factory-programmed.
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSI48R HSI48O
HSI48CAL[8:0] Res. Res. Res. Res. Res.
DY N
r r r r r r r r r r rw

Bits 31:16 Reserved, must be kept at reset value

Bits 15:7 HSI48CAL[8:0]: HSI48 clock calibration
These bits are initialized at startup with the factory-programmed HSI48 calibration trim value.
They are ready only.

312/2301 RM0432 Rev 6

RM0432 Reset and clock control (RCC)

Bits 6:2 Reserved, must be kept at reset value

Bit 1 HSI48RDY: HSI48 clock ready flag
Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is
enabled by software by setting HSI48ON.
0: HSI48 oscillator not ready
1: HSI48 oscillator ready
Bit 0 HSI48ON: HSI48 clock enable
Set and cleared by software.
Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes.
0: HSI48 oscillator OFF
1: HSI48 oscillator ON

6.4.32 Peripherals independent clock configuration register (RCC_CCIPR2)

Address: 0x9C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLSAI2DIVR[1:
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OSPISEL[1:0] Res. Res.
0]
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMMC DSISE ADFSDMSEL[1: DFSD
Res. Res. Res. SAI2SEL[2:0] SAI1SEL[2:0] I2C4SEL[1:0]
SEL L 0] MSEL
rw rw rw rw rw rw rw

Bits 31:22 Reserved, must be kept at reset value.

Bits 21:20 OSPISEL: Octospi clock source selection
Set and reset by software.
00: system clock selected as OctoSPI kernel clock
01: MSI clock selected as OctoSPI kernel clock
10: PLL48M1CLK clock selected as OctoSPI kernel clock
11: reserved
Bits 19:18 Reserved, must be kept at reset value.
Bits 17:16 PLLSAI2DIVR: division factor for LTDC clock
Set and reset by software to control the frequency of LTDC clock.
These bits can only be written when PLLSAI2 is disabled.
LTDC clock frequency = f(PLLSAI2_R) / PLLSAI2DIVR with 2 <= PLLSAI2DIVR <= 16
00: PLLSAI2DIVR = /2
01: PLLSAI2DIVR = /4
10: PLLSAI2DIVR = /8
11: PLLSAI2DIVR = /16
Bit 15 Reserved, must be kept at reset value.

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Reset and clock control (RCC) RM0432

Bit 14 SDMMCSEL: SDMMC clock selection

Set and reset by software.
This bit allows to select the SDMMC kernel clock source between PLLP clock (PLLSAI3CLK)
or clock from internal multiplexor.
It is recommended to change this bit only after reset and before enabling the SDMMC module.
0: 48 MHz clock is selected as SDMMC kernel clock
1: PLLSAI3CLK is selected as SDMMC kernel clock, used in case higher frequency than
48MHz is needed (for SDR50 mode).
Bit 13 Reserved, must be kept at reset value.
Bit 12 DSISEL clock selection
Set and reset by software.
This bit allows to select the DSI byte lane clock source between PLLDSICLK clock or clock
from DSI-PHY.
It is recommended to change this bit only after reset and before to enable the DSI module.
0: DSI-PHY is selected as DSI byte lane clock source (usual case)
1: PLLDSICLK is selected as DSI byte lane clock source, used in case DSI PLL and DSI-
PHY are off (low-power mode).
Bit 11 Reserved, must be kept at reset value.
Bits 10:8 SAI2SEL: SAI2 clock source selection
Set and reset by software.
If the selected clock is the external clock and this clock is stopped it is not possible to switch to
another clock. The user must switch to another clock before stopping the external clock.
000: PLLSAI1CLK clock is selected as SAI2 clock
001: PLLSAI2CLK clock is selected as SAI2 clock
010: PLLSAI3CLK clock is selected as SAI2 clock
011: External clock SAI2_EXTCLK clock selected as SAI2 clock
100: HSI clock selected as SAI2 clock
Other configuration are reserved
Bits 7:5 SAI1SEL: SAI1 clock source selection
Set and reset by software.
If the selected clock is the external clock and this clock is stopped it is not possible to switch to
another clock.
The user must switch to another clock before stopping the external clock.
000: PLLSAI1CLK clock is selected as SAI1 clock
001: PLLSAI2CLK clock is selected as SAI1 clock
010: PLLSAI3CLK clock is selected as SAI11 clock
011: External clock SAI1_EXTCLK is selected as SAI1 clock
100: HSI clock selected as SAI2 clock
Other configuration are reserved

314/2301 RM0432 Rev 6

RM0432 Reset and clock control (RCC)

Bits 4:3 ADFSDMSEL: Digital filter for sigma delta modulator audio clock source selection
Set and reset by software.
00: SAI1clock selected as DFSDM audio clock
01: HSI clock selected as DFSDM audio clock
10: MSI clock selected as DFSDM audio clock
11: reserved
Bit 2 DFSDMSEL: Digital filter for sigma delta modulator kernel clock source selection
Set and reset by software.
0: APB2 clock (PCLK2) selected as DFSDM kernel clock
1: System clock selected as DFSDM kernel clock
Bits 1:0 I2C4SEL[1:0]: I2C4 clock source selection
These bits are set and cleared by software to select the I2C4 clock source.
00: PCLK selected as I2C4 clock
01: System clock (SYSCLK) selected as I2C4 clock
10: HSI16 clock selected as I2C4 clock
11: reserved

6.4.33 OCTOSPI delay configuration register (RCC_DLYCFGR)

Address: 0xA4h
Reset value: 0x0000 0000h
Access: no wait state, word, half-word and byte access
This register allows to configure OCTOSPI’s delay cell.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. OCTOSPI2_DLY OCTOSPI1_DLY
rw rw rw rw rw rw rw rw

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Reset and clock control (RCC) RM0432

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 OCTOSPI2_DLY: Delay sampling configuration on OCTOSPI2 to be used for internal sampling
clock (called feedback clock) or for DQS data strobe.
Set and reset by software.
0000: 1 unitary delay
0001: 2 unitary delays
0010: 3 unitary delays
...
1111: 16 unitary delays
Bits 3:0 OCTOSPI1_DLY: Delay sampling configuration on OCTOSPI1 to be used for internal sampling
clock (called feedback clock) or for DQS data strobe.
Set and reset by software.
0000: 1 unitary delay
0001: 2 unitary delays
0010: 3 unitary delays
...
1111: 16 unitary delays

6.4.34 RCC register map

The following table gives the RCC register map and the reset values.

Table 38. RCC register map and reset values

Off- Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
set
PLLSAI2RDY

PLLSAI1RDY
PLLSAI2ON

PLLSAI1ON

HSIKERON

MSIRGSEL
MSIPLLEN
HSIASFS
HSERDY

MSIRANG
HSEBYP
PLLRDY

MSIRDY
HSIRDY
CSSON

HSEON
PLLON

MSION
HSION
Res.
Res.

Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.

RCC_CR E
0x00 [3:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1
Res.

0x04 RCC_ICSCR HSITRIM[6:0] HSICAL[7:0] MSITRIM[7:0] MSICAL[7:0]

Reset value 1 0 0 0 0 0 0 x x x x x x x x 0 0 0 0 0 0 0 0 x x x x x x x x
STOPWUCK

MCOP
MCOSEL PPRE2 PPRE1 SWS SW
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

0x08 RCC_CFGR RE HPRE[3:0]

[3:0] [2:0] [2:0] [1:0] [1:0]
[2:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PLL PLL
PLLQEN
PLLREN

PLLPEN

RCC_PLL PLLR PLLN PLLM

PLLP
Res.

Res.
Res.

Res.

Res.
Res.

PLLPDIV[4:0] Q SRC
0x0C CFGR [1:0] [6:0] [3:0]
[1:0] [1:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

316/2301 RM0432 Rev 6

 set
Off-

0x28
0x20
0x18
0x14
0x10

0x2C
0x1C
RM0432

RCC_
RCC_
RCC_
RCC_

CFGR
CFGR

PLLSAI2
PLLSAI1
Register

RCC_CIFR
RCC_CIER

RCC_CICR

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

AHB2RSTR
AHB1RSTR
Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. 30

V
V

Res. Res. Res. Res. Res. 29

[4:0]
[4:0]

Res. Res. Res. Res. Res. 28

PLLSAI2PDI
PLLSAI1PDI

Res. Res. Res. Res. Res. 27

Res. Res. Res. Res. Res. 26
R
R

PLL
PLL

[1:0]
[1:0]

SAI2
SAI1

Res. Res. Res. Res. Res. 25

0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0

Res. Res. Res. Res. Res. PLLSAI2REN PLLSAI1REN 24

SDMMC2RST Res. Res. Res. Res. Res. Res. 23

0 0
SDMMC1RST Res. Res. Res. Res. 22
PLLSAI2Q[1:0]
Q
PLL

[1:0]
SAI1

Res. Res. Res. Res. Res. 0 0 0 21

0 0 0

0
OSPIMRST Res. Res. Res. Res. PLLSAI2QEN PLLSAI1QEN 20
Res. Res. Res. Res. Res. Res. Res. 19
RNGRST. GFXMMURST Res. Res. Res. Res. Res. 18

RM0432 Rev 6
HASHRST DMA2DRST Res. Res. Res. PLLSAI2P PLLSAI1P 17
0 0
0 0

0 0 0
AESRST. TSCRST. Res. Res. Res. PLLSAI2PEN PLLSAI1PEN 16
PKARST Res. Res. Res. Res. Res. Res. 15
DCMIRST Res. Res. Res. Res. 14
ADCRST. Res. Res. Res. Res. 13

0 0 0 0 0 0 0
0
OTGFSRST CRCRST. Res. Res. Res. 12
Res. Res. Res. Res. Res. 11
[6:0]
[6:0]

Res. Res. HSI48RDYC HSI48RDYF HSI48RDYIE 10

PLLSAI2N
PLLSAI1N

0 0

Res. Res. LSECSSC LSECSSF LSECSSIE. 9

Table 38. RCC register map and reset values (continued)

0
GPIOIRST FLASHRST. CSSC CSSF Res. 8
GPIOHRST Res. PLLSAI2RDYC PLLSAI2RDYF PLLSAI2RDYIE 7
GPIOGRST Res. PLLSAI1RDYC PLLSAI1RDYF PLLSAI1RDYIE 6
[3:0]
[3:0]

GPIOFRST Res. PLLRDYC PLLRDYF PLLRDYIE 5

0 0 1 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 0 0

PLLSAI2M
PLLSAI1M

GPIOERST Res. HSERDYC HSERDYF HSERDYIE 4

GPIODRST Res. HSIRDYC HSIRDYF HSIRDYIE Res. Res. 3
GPIOCRST DMAMUX1RST MSIRDYC MSIRDYF MSIRDYIE Res. Res. 2
GPIOBRST DMA2RST LSERDYC LSERDYF LSERDYIE Res. Res. 1

0 0 0 0 0 0 0 0 0
0 0 0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Reset and clock control (RCC)

317/2301
GPIOARST DMA1RST LSIRDYC LSIRDYF LSIRDYIE Res. Res. 0

320
 set
Off-

0x58
0x50
0x48
0x40
0x30

0x4C

318/2301
ENR
ENR
ENR

RCC_
RCC_
RCC_
RCC_
RCC_
Register

APB1ENR1

Reset value
Reset value
Reset value
Reset value
Reset value
APB2RSTR
Reset value
Reset value
Reset value

RCC_AHB3
RCC_AHB2
RCC_AHB1
AHB3RSTR

0x3C APB1RSTR2
0x38 APB1RSTR1
LPTIM1EN Res. Res. Res. Res. Res. LPTIM1RST Res. 31
OPAMPEN Res. Res. Res. Res. Res. OPAMPRST Res. 30
DAC1EN Res. Res. Res. Res. Res. DAC1RST Res. 29

0 0 0 0
0 0 0 0
PWREN Res. Res. Res. Res. Res. PWRRST Res. 28
Reset and clock control (RCC)

Res. Res. Res. Res. DSIRST Res. Res. Res. 27

0 0
Res. Res. Res. Res. LTDCRST Res. Res. Res. 26
CAN1EN Res. Res. Res. Res. Res. CAN1RST Res. 25

0
CRSEN Res. Res. Res. DFSDM1RST Res. CRSRST Res. 24
I2C3EN Res. SDMMC2EN Res. Res. Res. I2C3RST Res. 23

0 0
I2C2EN Res. SDMMC1EN Res. SAI2RST Res. I2C2RST Res. 22

0 0
I2C1EN Res. Res. Res. SAI1RST Res. I2C1RST Res. 21

0
UART5EN Res. OSPIMEN Res. Res. Res. UART5RST Res. 20
UART4EN Res. Res. Res. Res. Res. UART4RST Res. 19
USART3EN Res. RNGEN GFXMMUEN TIM17RST Res. USART3RST Res. 18

RM0432 Rev 6
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0

USART2EN Res. HASHEN DMA2DEN TIM16RST Res. USART2RST Res. 17

0 0 0
0 0 0
Res. Res. AESEN TSCEN. TIM15RST Res. Res. Res. 16
SP3EN Res. PKAEN Res. Res. Res. SPI3RST Res. 15

0 0
0 0

SPI2EN Res. DCMIEN Res. USART1RST Res. SPI2RST Res. 14

Res. Res. ADCEN Res. TIM8RST Res. Res. Res. 13

0 0 0 0 0 0 0
0
Res. Res. OTGFSEN CRCEN SPI1RST Res. Res. Res. 12

0 0 0 0
WWDGEN Res. Res. Res. TIM1RST Res. Res. Res. 11

0 1
RTCAPBEN Res. Res. Res. Res. Res. Res. Res. 10
Res. OSPI2EN Res. Res. Res. Res. Res. OSPI2RST 9
Table 38. RCC register map and reset values (continued)

0 0
1
0 0

Res. OSPI1EN GPIOIEN FLASHEN Res. Res. Res. OSPI1RST 8

Res. Res. GPIOHEN Res. Res. Res. Res. Res. 7
Res. Res. GPIOGEN Res. Res. Res. Res. Res. 6
0

TIM7EN Res. GPIOFEN Res. Res. LPTIM2RST TIM7RST Res. 5

TIM6EN Res. GPIOEEN Res. Res. Res. TIM6RST Res. 4
TIM5EN Res. GPIODEN Res. Res. Res. TIM5RST Res. 3
TIM4EN Res. GPIOCEN DMAMUX1EN Res. Res. TIM4RST Res. 2
TIM3EN Res. GPIOBEN DMA2EN Res. I2C4RST TIM3RST Res. 1

0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0

0
0 0 0
0
0 0
0
RM0432

TIM2EN FMCEN GPIOAEN DMA1EN SYSCFGRST LPUART1RST TIM2RST FMCRST 0

 set
Off-

0x78
0x68
0x60

0x7C
0x5C
RM0432

ENR2
ENR1

RCC_
RCC_
RCC_
RCC_
RCC_
RCC_
RCC_
Register

APB1SM
APB1SM
APB2ENR
APB1ENR2

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

0x70 AHB3SMENR
0x6C AHB2SMENR
AHB1SMENR
Res. LPTIM1SMEN Res. Res. Res. Res. Res. 31
Res. OPAMPSMEN Res. Res. Res. Res. Res. 30
Res. DAC1SMEN Res. Res. Res. Res. Res. 29

1 1 1 1
Res. PWRSMEN Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. DSIEN Res. 27

0 0
Res. Res. Res. Res. Res. LTDCEN Res. 26
Res. CAN1SMEN Res. Res. Res. Res. Res. 25

0
Res. CRSSMEN Res. Res. Res. DFSDM1EN Res. 24
Res. I2C3SMEN Res. SDMMC2SMEN Res. Res. Res. 23

1 1
Res. I2C2SMEN Res. SDMMC1SMEN Res. 0 0 SAI2EN Res. 22
Res. I2C1SMEN Res. Res. Res. SAI1EN Res. 21

1
Res. UART5SMEN Res. OSPIMSMEN Res. Res. Res. 20
Res. UART4SMEN Res. Res. Res. Res. Res. 19
Res. USART3SMEN Res. RNGSMEN GFXMMUSMEN TIM17EN Res. 18

RM0432 Rev 6
1 1 1 1 1 1 1 1 1
Res. USART2SMEN Res. HASHSMEN DMA2DSMEN TIM16EN Res. 17

1 1 1
0 0 0

Res. Res. Res. AESSMEN TSCSMEN. TIM15EN Res. 16

Res. SP3SMEN Res. PKASMEN Res. Res. Res. 15

1 1
Res. SPI2SMEN Res. DCMISMEN Res. USART1EN Res. 14
Res. Res. Res. ADCFSSMEN Res. TIM8EN Res. 13

1 1 1 1 1 1 1
1

Res. Res. Res. OTGFSSMEN CRCSMEN SPI1EN Res. 12

0 0 0 0

Res. WWDGSMEN Res. Res. Res. TIM1EN Res. 11

1 1
Res. RTCAPBSMEN Res. SRAM3SMEN Res. Res. Res. 10
Res. Res. OSPI2SMEN SRAM2SMEN SRAM1SMEN Res. Res. 9
Table 38. RCC register map and reset values (continued)

1 1
1 1

Res. Res. OSPI1SMEN. GPIOISMEN FLASHSMEN Res. Res. 8

0

Res. Res. Res. GPIOHSMEN Res. FWEN Res. 7

Res. Res. Res. GPIOGSMEN Res. Res. Res. 6

1
0

LPTIM2SMEN TIM7SMEN Res. GPIOFSMEN Res. Res. LPTIM2EN 5

Res. TIM6SMEN Res. GPIOESMEN Res. Res. Res. 4
Res. TIM5SMEN Res. GPIODSMEN Res. Res. Res. 3
Res. TIM4SMEN Res. GPIOCSMEN DMAMUX1SMEN Res. Res. 2
I2C4SMEN TIM3SMEN Res. GPIOBSMEN DMA2SMEN Res. I2C4EN 1

1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1

1 1
1
1 1 1
0
0 0
Reset and clock control (RCC)

319/2301
LPUART1SMEN TIM2SMEN FMCSMEN GPIOASMEN DMA1SMEN SYSCFGEN LPUART1EN 0

320
 set
Off-

0x98
0x94
0x90
0x88

0x9C

0xA4h

320/2301
GR
RCC_
Register

RCC_CSR

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

RCC_BDCR
RCC_CCIPR

RCC_DLYCF
0x80 APB2SMENR

RCC_CRRCR

RCC_CCIPR2
Res. Res. Res. LPWRRSTF Res. Res. Res. 31
Res. Res. Res. WWDGRSTF Res. Res. Res. 30
Res. Res. Res. IWDGRSTF Res. ADCSEL Res. 29
Res. Res. Res. SFTRSTF Res. Res. 28
Reset and clock control (RCC)

Res. Res. Res. BORRSTF Res. CLK48SEL DSISMEN 27

0 0 0 0
1 1
Res. Res. Res. PINRSTF Res. LTDCSMEN 26
Res. Res. Res. OBLRSTF LSCOSEL Res. Res. 25

0 0
1

Res. Res. Res. FIREWALLRSTF LSCOEN Res. DFSDM1SMEN 24

0 0 0 0 0 0 0 0 0
Res. Res. Res. RMVF Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. SAI2SMEN 22
1 1

Res. OSPISEL Res. Res. Res. SAI1SMEN 21

LPTIM2SEL

0 0
Res. [1:0] Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. LPTIM1SEL Res. 19
Res. Res. Res. Res. Res. TIM17SMEN 18

RM0432 Rev 6
Res. PLLSAI2DIVR Res. Res. Res. I2C3SEL TIM16SMEN 17

0 0
1 1 1

Res. [1:0] Res. Res. BDRST TIM15SMEN 16

Res. Res. Res. 0 0 RTCEN Res. 15
I2C2SEL

0
Res. SDMMCSEL Res. Res. USART1SMEN 14
Res. Res. Res. Res. I2C1SEL TIM8SMEN 13

0
Res. DSISEL Res. Res. SPI1SMEN 12
1 1 1 1

Res. Res. Res. LPUART1SE TIM1SMEN 11

Res. Res. L Res. 10
SAI2SEL
[3:0]
Res. Res. 9
MSIS

HSI48CAL[8:0]
[2:0] UART5SEL

Refer to Section 2.2 on page 91 for the register boundary addresses.

RANGE
Table 38. RCC register map and reset values (continued)

0 1 1 0
SEL
[1:0]
RTC

Res. Res. 8

x x x x x x x x x
SAI1SEL Res. LSESYSDIS UART4SEL Res. 7
[2:0] Res. Res. LSECSSD Res. 6
Res. Res. LSECSSON Res. 5

2_DLY
USART3SEL
0

ADFSDMSEL Res. LSIPREDIV Res. 4

LSE

[1:0]
DRV

[1:0] Res. Res. USART2SEL Res. 3

DFSDMSEL Res. Res. LSEBYP Res. 2
I2C4SEL HSI48RDY LSIRDY LSERDY Res. 1

1_DLY
USART1SEL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0
0 0

0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
1

0 0

OCTOSPI OCTOSPI
[1:0]
RM0432

HSI48ON LSION LSEON SYSCFGSMEN 0

RM0432 Clock recovery system (CRS)

7 Clock recovery system (CRS)

7.1 Introduction
The clock recovery system (CRS) is an advanced digital controller acting on the internal
fine-granularity trimmable RC oscillator HSI48. The CRS provides powerful means for
oscillator output frequency evaluation, based on comparison with a selectable
synchronization signal. It is capable of doing automatic adjustment of oscillator trimming
based on the measured frequency error value, while keeping the possibility of a manual
trimming.
The CRS is ideally suited to provide a precise clock to the USB peripheral. In such case, the
synchronization signal can be derived from the start-of-frame (SOF) packet signalization on
the USB bus, which is sent by a USB host at 1 ms intervals.
The synchronization signal can also be derived from the LSE oscillator output or it can be
generated by user software.

7.2 CRS main features

• Selectable synchronization source with programmable prescaler and polarity:
– External pin
– LSE oscillator output
– USB SOF packet reception
• Possibility to generate synchronization pulses by software
• Automatic oscillator trimming capability with no need of CPU action
• Manual control option for faster start-up convergence
• 16-bit frequency error counter with automatic error value capture and reload
• Programmable limit for automatic frequency error value evaluation and status reporting
• Maskable interrupts/events:
– Expected synchronization (ESYNC)
– Synchronization OK (SYNCOK)
– Synchronization warning (SYNCWARN)
– Synchronization or trimming error (ERR)

7.3 CRS implementation

Table 39. CRS features
Feature STM32L4P5xx/STM32L4Q5xx STM32L4Sxx/STM32L4Rxx

TRIM width 7 bits 6 bits

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331
Clock recovery system (CRS) RM0432

7.4 CRS functional description

7.4.1 CRS block diagram

Figure 23. CRS block diagram

CRS_SYNC
GPIO

SYNCSRC SWSYNC

OSC32_IN
SYNC divider
LSE
(/1, /2, /4,…, /128)
OSC32_OUT
SYNC

USB_DP
FELIM
USB
USB_DM

TRIM FEDIR FECAP

RCC
RC 48 MHz 16-bit counter

RELOAD

HSI48
To peripherals
MS52498V1

7.4.2 Synchronization input

The CRS synchronization (SYNC) source, selectable through the CRS_CFGR register, can
be the signal from the LSE clock or the USB SOF signal. For a better robustness of the
SYNC input, a simple digital filter (2 out of 3 majority votes, sampled by the RC48 clock) is
implemented to filter out any glitches. This source signal also has a configurable polarity
and can then be divided by a programmable binary prescaler to obtain a synchronization
signal in a suitable frequency range (usually around 1 kHz).
For more information on the CRS synchronization source configuration, refer to
Section 7.7.2: CRS configuration register (CRS_CFGR).
It is also possible to generate a synchronization event by software, by setting the SWSYNC
bit in the CRS_CR register.

322/2301 RM0432 Rev 6

RM0432 Clock recovery system (CRS)

7.4.3 Frequency error measurement

The frequency error counter is a 16-bit down/up counter which is reloaded with the RELOAD
value on each SYNC event. It starts counting down till it reaches the zero value, where the
ESYNC (expected synchronization) event is generated. Then it starts counting up to the
OUTRANGE limit where it eventually stops (if no SYNC event is received) and generates a
SYNCMISS event. The OUTRANGE limit is defined as the frequency error limit (FELIM field
of the CRS_CFGR register) multiplied by 128.
When the SYNC event is detected, the actual value of the frequency error counter and its
counting direction are stored in the FECAP (frequency error capture) field and in the FEDIR
(frequency error direction) bit of the CRS_ISR register. When the SYNC event is detected
during the downcounting phase (before reaching the zero value), it means that the actual
frequency is lower than the target (and so, that the TRIM value must be incremented), while
when it is detected during the upcounting phase it means that the actual frequency is higher
(and that the TRIM value must be decremented).

Figure 24. CRS counter behavior

CRS counter value

RELOAD

ESYNC

Down Up

Frequency
OUTRANGE error counter
(128 x FELIM) stopped

WARNING LIMIT
(3 x FELIM)
TOLERANCE LIMIT
(FELIM)

Trimming action: 0 +2 +1 0 -1 -2 0
CRS event: SYNCERR SYNCWARN SYNCOK SYNCWARN

SYNCMISS
MSv32122V1

RM0432 Rev 6 323/2301

331
Clock recovery system (CRS) RM0432

7.4.4 Frequency error evaluation and automatic trimming

The measured frequency error is evaluated by comparing its value with a set of limits:
– TOLERANCE LIMIT, given directly in the FELIM field of the CRS_CFGR register
– WARNING LIMIT, defined as 3 * FELIM value
– OUTRANGE (error limit), defined as 128 * FELIM value
The result of this comparison is used to generate the status indication and also to control the
automatic trimming which is enabled by setting the AUTOTRIMEN bit in the CRS_CR
register:
• When the frequency error is below the tolerance limit, it means that the actual trimming
value in the TRIM field is the optimal one, hence no trimming action is needed.
– SYNCOK status indicated
– TRIM value not changed in AUTOTRIM mode
• When the frequency error is below the warning limit but above or equal to the tolerance
limit, it means that some trimming action is necessary but that adjustment by one
trimming step is enough to reach the optimal TRIM value.
– SYNCOK status indicated
– TRIM value adjusted by one trimming step in AUTOTRIM mode
• When the frequency error is above or equal to the warning limit but below the error
limit, it means that a stronger trimming action is necessary, and there is a risk that the
optimal TRIM value will not be reached for the next period.
– SYNCWARN status indicated
– TRIM value adjusted by two trimming steps in AUTOTRIM mode
• When the frequency error is above or equal to the error limit, it means that the
frequency is out of the trimming range. This can also happen when the SYNC input is
not clean or when some SYNC pulse is missing (for example when one USB SOF is
corrupted).
– SYNCERR or SYNCMISS status indicated
– TRIM value not changed in AUTOTRIM mode
Note: If the actual value of the TRIM field is so close to its limits that the automatic trimming would
force it to overflow or underflow, then the TRIM value is set just to the limit and the
TRIMOVF status is indicated.
In AUTOTRIM mode (AUTOTRIMEN bit set in the CRS_CR register), the TRIM field of
CRS_CR is adjusted by hardware and is read-only.

7.4.5 CRS initialization and configuration

RELOAD value
The RELOAD value must be selected according to the ratio between the target frequency
and the frequency of the synchronization source after prescaling. It is then decreased by
one to reach the expected synchronization on the zero value. The formula is the following:
RELOAD = (fTARGET / fSYNC) - 1
The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a
synchronization signal frequency of 1 kHz (SOF signal from USB).

324/2301 RM0432 Rev 6

RM0432 Clock recovery system (CRS)

FELIM value
The selection of the FELIM value is closely coupled with the HSI48 oscillator characteristics
and its typical trimming step size. The optimal value corresponds to half of the trimming step
size, expressed as a number of HSI48 oscillator clock ticks. The following formula can be
used:
FELIM = (fTARGET / fSYNC) * STEP[%] / 100% / 2
The result must be always rounded up to the nearest integer value to obtain the best
trimming response. If frequent trimming actions are not needed in the application, the
hysteresis can be increased by slightly increasing the FELIM value.
The reset value of the FELIM field corresponds to (fTARGET / fSYNC) = 48000 and to a typical
trimming step size of 0.14%.
Caution: There is no hardware protection from a wrong configuration of the RELOAD and FELIM
fields which can lead to an erratic trimming response. The expected operational mode
requires proper setup of the RELOAD value (according to the synchronization source
frequency), which is also greater than 128 * FELIM value (OUTRANGE limit).

7.5 CRS low-power modes

Table 40. Effect of low-power modes on CRS
Mode Description

Sleep No effect. CRS interrupts cause the device to exit the Sleep mode.
CRS registers are frozen. The CRS stops operating until the Stop mode is exited and the
Stop
HSI48 oscillator restarted.
Standby The CRS peripheral is powered down and must be reinitialized after exiting Standby mode.

7.6 CRS interrupts

Table 41. Interrupt control bits
Enable Clear
Interrupt event Event flag
control bit flag bit

Expected synchronization ESYNCF ESYNCIE ESYNCC

Synchronization OK SYNCOKF SYNCOKIE SYNCOKC
Synchronization warning SYNCWARNF SYNCWARNIE SYNCWARNC
Synchronization or trimming error
ERRF ERRIE ERRC
(TRIMOVF, SYNCMISS, SYNCERR)

RM0432 Rev 6 325/2301

331
Clock recovery system (CRS) RM0432

7.7 CRS registers

Refer to Section 1.2 on page 84 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed only by words (32-bit).

7.7.1 CRS control register (CRS_CR)

Address offset: 0x00
Reset value: 0x0000 X000 (X=4 for products supporting 7-bit TRIM width, otherwise X=2)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SW AUTO ESYNCI SYNC SYNC
Res. TRIM[6] TRIM[5:0] CEN Res. ERRIE
SYNC TRIMEN E WARNIE OKIE
rw rw rw rw rw rw rw rt_w1 rw rw rw rw rw rw

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 TRIM[6]: HSI48 oscillator smooth trimming
For product supporting the 7-bit TRIM width (see Section 7.3), the default value of the HSI48
oscillator smooth trimming is 64, which corresponds to the middle of the trimming interval.
For products supporting the 6-bit TRIM width (see Section 7.3) this bit is reserved, must be
kept at reset value.
Bits 13:8 TRIM[5:0]: HSI48 oscillator smooth trimming
These bits provide a user-programmable trimming value to the HSI48 oscillator. They can be
programmed to adjust to variations in voltage and temperature that influence the frequency
of the HSI48 oscillator.
The default value is 32, which corresponds to the middle of the trimming interval. The
trimming step is specified in the product datasheet. A higher TRIM value corresponds to a
higher output frequency.
When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only.
Bit 7 SWSYNC: Generate software SYNC event
This bit is set by software in order to generate a software SYNC event. It is automatically
cleared by hardware.
0: No action
1: A software SYNC event is generated.
Bit 6 AUTOTRIMEN: Automatic trimming enable
This bit enables the automatic hardware adjustment of TRIM bits according to the measured
frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The
TRIM value can be adjusted by hardware by one or two steps at a time, depending on the
measured frequency error value. Refer to Section 7.4.4 for more details.
0: Automatic trimming disabled, TRIM bits can be adjusted by the user.
1: Automatic trimming enabled, TRIM bits are read-only and under hardware control.
Bit 5 CEN: Frequency error counter enable
This bit enables the oscillator clock for the frequency error counter.
0: Frequency error counter disabled
1: Frequency error counter enabled
When this bit is set, the CRS_CFGR register is write-protected and cannot be modified.

326/2301 RM0432 Rev 6

RM0432 Clock recovery system (CRS)

Bit 4 Reserved, must be kept at reset value.

Bit 3 ESYNCIE: Expected SYNC interrupt enable
0: Expected SYNC (ESYNCF) interrupt disabled
1: Expected SYNC (ESYNCF) interrupt enabled
Bit 2 ERRIE: Synchronization or trimming error interrupt enable
0: Synchronization or trimming error (ERRF) interrupt disabled
1: Synchronization or trimming error (ERRF) interrupt enabled
Bit 1 SYNCWARNIE: SYNC warning interrupt enable
0: SYNC warning (SYNCWARNF) interrupt disabled
1: SYNC warning (SYNCWARNF) interrupt enabled
Bit 0 SYNCOKIE: SYNC event OK interrupt enable
0: SYNC event OK (SYNCOKF) interrupt disabled
1: SYNC event OK (SYNCOKF) interrupt enabled

7.7.2 CRS configuration register (CRS_CFGR)

This register can be written only when the frequency error counter is disabled (CEN bit is
cleared in CRS_CR). When the counter is enabled, this register is write-protected.
Address offset: 0x04
Reset value: 0x2022 BB7F

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNCPOL Res. SYNCSRC[1:0] Res. SYNCDIV[2:0] FELIM[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RELOAD[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 SYNCPOL: SYNC polarity selection

This bit is set and cleared by software to select the input polarity for the SYNC signal source.
0: SYNC active on rising edge (default)
1: SYNC active on falling edge
Bit 30 Reserved, must be kept at reset value.
Bits 29:28 SYNCSRC[1:0]: SYNC signal source selection
These bits are set and cleared by software to select the SYNC signal source.
00: GPIO selected as SYNC signal source
01: LSE selected as SYNC signal source
10: USB SOF selected as SYNC signal source (default).
11: Reserved
Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
periodic USB SOF is not generated by the host. No SYNC signal is therefore provided
to the CRS to calibrate the HSI48 oscillator on the run. To guarantee the required clock
precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
should be used as SYNC signal.
Bit 27 Reserved, must be kept at reset value.

RM0432 Rev 6 327/2301

331
Clock recovery system (CRS) RM0432

Bits 26:24 SYNCDIV[2:0]: SYNC divider

These bits are set and cleared by software to control the division factor of the SYNC signal.
000: SYNC not divided (default)
001: SYNC divided by 2
010: SYNC divided by 4
011: SYNC divided by 8
100: SYNC divided by 16
101: SYNC divided by 32
110: SYNC divided by 64
111: SYNC divided by 128
Bits 23:16 FELIM[7:0]: Frequency error limit
FELIM contains the value to be used to evaluate the captured frequency error value latched
in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section 7.4.4 for more details
about FECAP evaluation.
Bits 15:0 RELOAD[15:0]: Counter reload value
RELOAD is the value to be loaded in the frequency error counter with each SYNC event.
Refer to Section 7.4.3 for more details about counter behavior.

7.7.3 CRS interrupt and status register (CRS_ISR)

Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FECAP[15:0]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM SYNC SYNC SYNC SYNC
FEDIR Res. Res. Res. Res. Res. Res. Res. Res. ESYNCF ERRF
OVF MISS ERR WARNF OKF
r r r r r r r r

Bits 31:16 FECAP[15:0]: Frequency error capture

FECAP is the frequency error counter value latched in the time of the last SYNC event.
Refer to Section 7.4.4 for more details about FECAP usage.
Bit 15 FEDIR: Frequency error direction
FEDIR is the counting direction of the frequency error counter latched in the time of the last
SYNC event. It shows whether the actual frequency is below or above the target.
0: Upcounting direction, the actual frequency is above the target.
1: Downcounting direction, the actual frequency is below the target.
Bits 14:11 Reserved, must be kept at reset value.
Bit 10 TRIMOVF: Trimming overflow or underflow
This flag is set by hardware when the automatic trimming tries to over- or under-flow the
TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is
cleared by software by setting the ERRC bit in the CRS_ICR register.
0: No trimming error signalized
1: Trimming error signalized

328/2301 RM0432 Rev 6

RM0432 Clock recovery system (CRS)

Bit 9 SYNCMISS: SYNC missed

This flag is set by hardware when the frequency error counter reached value FELIM * 128
and no SYNC was detected, meaning either that a SYNC pulse was missed or that the
frequency error is too big (internal frequency too high) to be compensated by adjusting the
TRIM value, and that some other action has to be taken. At this point, the frequency error
counter is stopped (waiting for a next SYNC) and an interrupt is generated if the ERRIE bit is
set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR
register.
0: No SYNC missed error signalized
1: SYNC missed error signalized
Bit 8 SYNCERR: SYNC error
This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the
measured frequency error is greater than or equal to FELIM * 128. This means that the
frequency error is too big (internal frequency too low) to be compensated by adjusting the
TRIM value, and that some other action has to be taken. An interrupt is generated if the
ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in
the CRS_ICR register.
0: No SYNC error signalized
1: SYNC error signalized
Bits 7:4 Reserved, must be kept at reset value.
Bit 3 ESYNCF: Expected SYNC flag
This flag is set by hardware when the frequency error counter reached a zero value. An
interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by
software by setting the ESYNCC bit in the CRS_ICR register.
0: No expected SYNC signalized
1: Expected SYNC signalized
Bit 2 ERRF: Error flag
This flag is set by hardware in case of any synchronization or trimming error. It is the logical
OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE
bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit
in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits.
0: No synchronization or trimming error signalized
1: Synchronization or trimming error signalized
Bit 1 SYNCWARNF: SYNC warning flag
This flag is set by hardware when the measured frequency error is greater than or equal to
FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency
error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the
SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the
SYNCWARNC bit in the CRS_ICR register.
0: No SYNC warning signalized
1: SYNC warning signalized
Bit 0 SYNCOKF: SYNC event OK flag
This flag is set by hardware when the measured frequency error is smaller than FELIM * 3.
This means that either no adjustment of the TRIM value is needed or that an adjustment by
one trimming step is enough to compensate the frequency error. An interrupt is generated if
the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the
SYNCOKC bit in the CRS_ICR register.
0: No SYNC event OK signalized
1: SYNC event OK signalized

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7.7.4 CRS interrupt flag clear register (CRS_ICR)

Address offset: 0x0C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNC SYNC
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ESYNCC ERRC
WARNC OKC
rw rw rw rw

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 ESYNCC: Expected SYNC clear flag
Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register.
Bit 2 ERRC: Error clear flag
Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
the ERRF flag in the CRS_ISR register.
Bit 1 SYNCWARNC: SYNC warning clear flag
Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register.
Bit 0 SYNCOKC: SYNC event OK clear flag
Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register.

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RM0432 Clock recovery system (CRS)

7.7.5 CRS register map

Table 42. CRS register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
SYNCWARNIE
AUTOTRIMEN

SYNCOKIE
TRIM[6](1)

ESYNCIE
SWSYNC

ERRIE
CEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
CRS_CR TRIM[5:0]
0x00

Reset value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SYNCPOL

SYNC SYNC
Res.

Res.

CRS_CFGR SRC DIV FELIM[7:0] RELOAD[15:0]

0x04 [1:0] [2:0]

Reset value 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1

SYNCWARNF
SYNCMISS
SYNCERR

SYNCOKF
TRIMOVF

ESYNCF
FEDIR

ERRF
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
CRS_ISR FECAP[15:0]
0x08

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYNCWARNC
SYNCOKC
ESYNCC
ERRC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CRS_ICR
0x0C

Reset value 0 0 0 0

1. The TRIM bitfield can be one bit less. Refer to Section 7.3: CRS implementation for details.

Refer to Section 2.2 on page 91 for the register boundary addresses.

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General-purpose I/Os (GPIO) RM0432

8 General-purpose I/Os (GPIO)

8.1 Introduction
Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers
(GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR). In addition
all GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function
selection registers (GPIOx_AFRH and GPIOx_AFRL).

8.2 GPIO main features

• Output states: push-pull or open drain + pull-up/down
• Output data from output data register (GPIOx_ODR) or peripheral (alternate function
output)
• Speed selection for each I/O
• Input states: floating, pull-up/down, analog
• Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)
• Bit set and reset register (GPIOx_ BSRR) for bitwise write access to GPIOx_ODR
• Locking mechanism (GPIOx_LCKR) provided to freeze the I/O port configurations
• Analog function
• Alternate function selection registers
• Fast toggle capable of changing every two clock cycles
• Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several
peripheral functions

8.3 GPIO functional description

Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in
several modes:
• Input floating
• Input pull-up
• Input-pull-down
• Analog
• Output open-drain with pull-up or pull-down capability
• Output push-pull with pull-up or pull-down capability
• Alternate function push-pull with pull-up or pull-down capability
• Alternate function open-drain with pull-up or pull-down capability
Each I/O port bit is freely programmable, however the I/O port registers have to be
accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR register is
to allow atomic read/modify accesses to any of the GPIOx_ODR registers. In this way, there
is no risk of an IRQ occurring between the read and the modify access.

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RM0432 General-purpose I/Os (GPIO)

Figure 25 and Figure 26 show the basic structures of a standard and a 5-Volt tolerant I/O
port bit, respectively. Table 43 gives the possible port bit configurations.

Figure 25. Basic structure of an I/O port bit

Analog
To on-chip
peripheral Alternate function input

Input data register on/off

Read
VDDIOxVDDIOx
Bit set/reset registers

Protection
trigger on/off
Pull diode
up
Input driver I/O pin
Output data register

Write

Output driver VDDIOx on/off Protection

Pull
down diode
P-MOS
VSS
Output VSS
control
N-MOS
Read/write
VSS
Push-pull,
From on-chip open-drain or
peripheral Alternate function output
disabled
Analog

MS31476V1

Figure 26. Basic structure of a 5-Volt tolerant I/O port bit

To on-chip
peripheral
Alternate function input

on/off
Input data register

Read (1)
VDDIOx VDD_FT

TTL Schmitt
Bit set/reset registers

Protection
trigger on/off
Pull diode
up
Input driver I/O pin
Write
Output data register

Output driver VDDIOx on/off Pull Protection

down
diode
P-MOS
Output VSS
VSS
control
Read/write N-MOS

From on-chip VSS

Push-pull,
peripheral Alternate function output open-drain or
disabled

ai15939d

1. VDD_FT is a potential specific to five-volt tolerant I/Os and different from VDD.

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Table 43. Port bit configuration table(1)

MODE(i) OSPEED(i) PUPD(i)
OTYPER(i) I/O configuration
[1:0] [1:0] [1:0]

0 0 0 GP output PP
0 0 1 GP output PP + PU
0 1 0 GP output PP + PD
0 SPEED 1 1 Reserved
01
1 [1:0] 0 0 GP output OD
1 0 1 GP output OD + PU
1 1 0 GP output OD + PD
1 1 1 Reserved (GP output OD)
0 0 0 AF PP
0 0 1 AF PP + PU
0 1 0 AF PP + PD
0 SPEED 1 1 Reserved
10
1 [1:0] 0 0 AF OD
1 0 1 AF OD + PU
1 1 0 AF OD + PD
1 1 1 Reserved
x x x 0 0 Input Floating
x x x 0 1 Input PU
00
x x x 1 0 Input PD
x x x 1 1 Reserved (input floating)
x x x 0 0 Input/output Analog
x x x 0 1
11
x x x 1 0 Reserved
x x x 1 1
1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate
function.

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RM0432 General-purpose I/Os (GPIO)

8.3.1 General-purpose I/O (GPIO)

During and just after reset, the alternate functions are not active and most of the I/O ports
are configured in analog mode.
The debug pins are in AF pull-up/pull-down after reset:
• PA15: JTDI in pull-up
• PA14: JTCK/SWCLK in pull-down
• PA13: JTMS/SWDAT in pull-up
• PB4: NJTRST in pull-up
• PB3: JTDO in floating state no pull-up/pull-down
PH3/BOOT0 is in input mode during the reset until at least the end of the option byte loading
phase. See Section 8.3.15: Using PH3 as GPIO.
When the pin is configured as output, the value written to the output data register
(GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull
mode or open-drain mode (only the low level is driven, high level is HI-Z).
The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB
clock cycle.
All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or
not depending on the value in the GPIOx_PUPDR register.

8.3.2 I/O pin alternate function multiplexer and mapping

The device I/O pins are connected to on-board peripherals/modules through a multiplexer
that allows only one peripheral alternate function (AF) connected to an I/O pin at a time. In
this way, there can be no conflict between peripherals available on the same I/O pin.
Each I/O pin has a multiplexer with up to sixteen alternate function inputs (AF0 to AF15) that
can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to
15) registers:
• After reset the multiplexer selection is alternate function 0 (AF0). The I/Os are
configured in alternate function mode through GPIOx_MODER register.
• The specific alternate function assignments for each pin are detailed in the device
datasheet.
In addition to this flexible I/O multiplexing architecture, each peripheral has alternate
functions mapped onto different I/O pins to optimize the number of peripherals available in
smaller packages.
To use an I/O in a given configuration, the user has to proceed as follows:
• Debug function: after each device reset these pins are assigned as alternate function
pins immediately usable by the debugger host
• GPIO: configure the desired I/O as output, input or analog in the GPIOx_MODER
register.
• Peripheral alternate function:
– Connect the I/O to the desired AFx in one of the GPIOx_AFRL or GPIOx_AFRH
register.
– Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER,
GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively.

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– Configure the desired I/O as an alternate function in the GPIOx_MODER register.

• Additional functions:
– For the ADC, DAC, OPAMP and COMP, configure the desired I/O in analog mode
in the GPIOx_MODER register and configure the required function in the ADC,
DAC, OPAMP, and COMP registers .
As indicated above, for the additional functions (such as DAC or OPAMP), the
output is controlled by the corresponding peripheral. Care must be taken to select
the I/O port analog function before enabling the additional function output in the
peripheral control register.
– For the additional functions like RTC, WKUPx and oscillators, configure the
required function in the related RTC, PWR and RCC registers. These functions
have priority over the configuration in the standard GPIO registers.
Refer to the “Alternate function mapping” table in the device datasheet for the detailed
mapping of the alternate function I/O pins.

8.3.3 I/O port control registers

Each of the GPIO ports has four 32-bit memory-mapped control registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The
GPIOx_MODER register is used to select the I/O mode (input, output, AF, analog). The
GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (push-
pull or open-drain) and speed. The GPIOx_PUPDR register is used to select the pull-
up/pull-down whatever the I/O direction.

8.3.4 I/O port data registers

Each GPIO has two 16-bit memory-mapped data registers: input and output data registers
(GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write
accessible. The data input through the I/O are stored into the input data register
(GPIOx_IDR), a read-only register.
See Section 8.4.5: GPIO port input data register (GPIOx_IDR) (x = A to I) and Section 8.4.6:
GPIO port output data register (GPIOx_ODR) (x = A to I) for the register descriptions.

8.3.5 I/O data bitwise handling

The bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to
set and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset
register has twice the size of GPIOx_ODR.
To each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BS(i) and BR(i).
When written to 1, bit BS(i) sets the corresponding ODR(i) bit. When written to 1, bit BR(i)
resets the ODR(i) corresponding bit.
Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in
GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set
action takes priority.
Using the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a
“one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always
be accessed directly. The GPIOx_BSRR register provides a way of performing atomic
bitwise handling.

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RM0432 General-purpose I/Os (GPIO)

There is no need for the software to disable interrupts when programming the GPIOx_ODR
at bit level: it is possible to modify one or more bits in a single atomic AHB write access.

8.3.6 GPIO locking mechanism

It is possible to freeze the GPIO control registers by applying a specific write sequence to
the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER,
GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When
the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used
to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must
be the same). When the LOCK sequence has been applied to a port bit, the value of the port
bit can no longer be modified until the next MCU reset or peripheral reset. Each
GPIOx_LCKR bit freezes the corresponding bit in the control registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
The LOCK sequence (refer to Section 8.4.8: GPIO port configuration lock register
(GPIOx_LCKR) (x = A to I)) can only be performed using a word (32-bit long) access to the
GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same
time as the [15:0] bits.
For more details refer to LCKR register description in Section 8.4.8: GPIO port configuration
lock register (GPIOx_LCKR) (x = A to I).

8.3.7 I/O alternate function input/output

Two registers are provided to select one of the alternate function inputs/outputs available for
each I/O. With these registers, the user can connect an alternate function to some other pin
as required by the application.
This means that a number of possible peripheral functions are multiplexed on each GPIO
using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can
thus select any one of the possible functions for each I/O. The AF selection signal being
common to the alternate function input and alternate function output, a single channel is
selected for the alternate function input/output of a given I/O.
To know which functions are multiplexed on each GPIO pin, refer to the device datasheet.

8.3.8 External interrupt/wakeup lines

All ports have external interrupt capability. To use external interrupt lines, the port can be
configured in input, output or alternate function mode (the port must not be configured in
analog mode).
Refer to Section 16: Extended interrupts and events controller (EXTI) and to Section 16.3.2:
Wakeup event management.

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8.3.9 Input configuration

When the I/O port is programmed as input:
• The output buffer is disabled
• The Schmitt trigger input is activated
• The pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register
• The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
• A read access to the input data register provides the I/O state
Figure 27 shows the input configuration of the I/O port bit.

Figure 27. Input floating/pull up/pull down configurations

Input data register

on
Read
VDDIOx VDDIOx
Bit set/reset registers

TTL Schmitt on/off

trigger protection
pull diode
Write up
Output data register

input driver I/O pin

on/off
output driver
pull protection
down diode
VSS VSS
Read/write

MS31477V1

8.3.10 Output configuration

When the I/O port is programmed as output:
• The output buffer is enabled:
– Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1”
in the Output register leaves the port in Hi-Z (the P-MOS is never activated)
– Push-pull mode: A “0” in the Output register activates the N-MOS whereas a “1” in
the Output register activates the P-MOS
• The Schmitt trigger input is activated
• The pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register
• The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
• A read access to the input data register gets the I/O state
• A read access to the output data register gets the last written value
Figure 28 shows the output configuration of the I/O port bit.

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RM0432 General-purpose I/Os (GPIO)

Figure 28. Output configuration

Input data register

on
Read

TTL Schmitt VDDIOx VDDIOx

Bit set/reset registers

trigger
on/off
Write protection
Input driver diode

Output data register

pull
up
I/O pin
Output driver VDDIOx on/off

P-MOS pull protection

Output down diode
Read/write control VSS
N-MOS VSS
Push-pull or
VSS Open-drain
MS31478V1

8.3.11 Alternate function configuration

When the I/O port is programmed as alternate function:
• The output buffer can be configured in open-drain or push-pull mode
• The output buffer is driven by the signals coming from the peripheral (transmitter
enable and data)
• The Schmitt trigger input is activated
• The weak pull-up and pull-down resistors are activated or not depending on the value
in the GPIOx_PUPDR register
• The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
• A read access to the input data register gets the I/O state
Figure 29 shows the Alternate function configuration of the I/O port bit.

Figure 29. Alternate function configuration

To on-chip Alternate function input

peripheral
Input data register

on

Read
VDDIOxVDDIOx
TTL Schmitt on/off
Bit set/reset registers

trigger protection
Pull diode
Input driver up
Write
Output data register

I/O pin
Output driver VDD on/off

Pull protection
P-MOS down diode
Output
control VSS VSS
N-MOS
Read/write
VSS push-pull or
open-drain
From on-chip
peripheral Alternate function output

MSv34756V1

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8.3.12 Analog configuration

When the I/O port is programmed as analog configuration:
• The output buffer is disabled
• The Schmitt trigger input is deactivated, providing zero consumption for every analog
value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0).
• The weak pull-up and pull-down resistors are disabled by hardware
• Read access to the input data register gets the value “0”
Figure 30 shows the high-impedance, analog-input configuration of the I/O port bits.

Figure 30. High impedance-analog configuration

Analog
To on-chip
peripheral
Input data register

Read off
0
VDDIOx
Bit set/reset registers

TTL Schmitt
trigger protection
Write diode
Output data register

Input driver
I/O pin

protection
diode

Read/write VSS

From on-chip Analog

peripheral MS31480V1

8.3.13 Using the HSE or LSE oscillator pins as GPIOs

When the HSE or LSE oscillator is switched OFF (default state after reset), the related
oscillator pins can be used as normal GPIOs.
When the HSE or LSE oscillator is switched ON (by setting the HSEON or LSEON bit in the
RCC_CSR register) the oscillator takes control of its associated pins and the GPIO
configuration of these pins has no effect.
When the oscillator is configured in a user external clock mode, only the pin is reserved for
clock input and the OSC_OUT or OSC32_OUT pin can still be used as normal GPIO.

8.3.14 Using the GPIO pins in the RTC supply domain

The PC13/PC14/PC15 GPIO functionality is lost when the core supply domain is powered
off (when the device enters Standby mode). In this case, if their GPIO configuration is not
bypassed by the RTC configuration, these pins are set in an analog input mode.
For details about I/O control by the RTC, refer to Section 46.3: RTC functional description.

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RM0432 General-purpose I/Os (GPIO)

8.3.15 Using PH3 as GPIO

PH3 may be used as boot pin (BOOT0) or as a GPIO. Depending on the nSWBOOT0 bit in
the user option byte, it switches from the input mode to the analog input mode:
• After the option byte loading phase if nSWBOOT0 = 1.
• After reset if nSWBOOT0 = 0.

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8.4 GPIO registers

This section gives a detailed description of the GPIO registers.
For a summary of register bits, register address offsets and reset values, refer to Table 44.
The peripheral registers can be written in word, half word or byte mode.

8.4.1 GPIO port mode register (GPIOx_MODER)

(x =A to I)
Address offset:0x00
Reset value: 0xABFF FFFF (for port A)
Reset value: 0xFFFF FEBF (for port B)
Reset value: 0xFFFF FFFF (for ports C..G), I
Reset value: 0x0000 000F (for port H)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MODE15[1:0] MODE14[1:0] MODE13[1:0] MODE12[1:0] MODE11[1:0] MODE10[1:0] MODE9[1:0] MODE8[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MODE7[1:0] MODE6[1:0] MODE5[1:0] MODE4[1:0] MODE3[1:0] MODE2[1:0] MODE1[1:0] MODE0[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MODE[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O mode.
00: Input mode
01: General purpose output mode
10: Alternate function mode
11: Analog mode (reset state)

8.4.2 GPIO port output type register (GPIOx_OTYPER)

(x = A to I)
Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15 OT14 OT13 OT12 OT11 OT10 OT9 OT8 OT7 OT6 OT5 OT4 OT3 OT2 OT1 OT0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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RM0432 General-purpose I/Os (GPIO)

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OT[15:0]: Port x configuration I/O pin y (y = 15 to 0)
These bits are written by software to configure the I/O output type.
0: Output push-pull (reset state)
1: Output open-drain

8.4.3 GPIO port output speed register (GPIOx_OSPEEDR)

(x = A to I)
Address offset: 0x08
Reset value: 0x0C00 0000 (for port A)
Reset value: 0x0000 0000 (for the other ports)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEED15 OSPEED14 OSPEED13 OSPEED12 OSPEED11 OSPEED10 OSPEED9 OSPEED8
[1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEED7 OSPEED6 OSPEED5 OSPEED4 OSPEED3 OSPEED2 OSPEED1 OSPEED0
[1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 OSPEED[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O output speed.
00: Low speed
01: Medium speed
10: High speed
11: Very high speed
Note: Refer to the device datasheet for the frequency specifications and the power supply
and load conditions for each speed..

8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR)

(x = A to I)
Address offset: 0x0C
Reset value: 0x6400 0000 (for port A)
Reset value: 0x0000 0100 (for port B)
Reset value: 0x0000 0000 (for other ports)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPD15[1:0] PUPD14[1:0] PUPD13[1:0] PUPD12[1:0] PUPD11[1:0] PUPD10[1:0] PUPD9[1:0] PUPD8[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPD7[1:0] PUPD6[1:0] PUPD5[1:0] PUPD4[1:0] PUPD3[1:0] PUPD2[1:0] PUPD1[1:0] PUPD0[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RM0432 Rev 6 343/2301

350
General-purpose I/Os (GPIO) RM0432

Bits 31:0 PUPD[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O pull-up or pull-down
00: No pull-up, pull-down
01: Pull-up
10: Pull-down
11: Reserved

8.4.5 GPIO port input data register (GPIOx_IDR)

(x = A to I)
Address offset: 0x10
Reset value: 0x0000 XXXX

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 ID[15:0]: Port x input data I/O pin y (y = 15 to 0)
These bits are read-only. They contain the input value of the corresponding I/O port.

8.4.6 GPIO port output data register (GPIOx_ODR)

(x = A to I)
Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OD[15:0]: Port output data I/O pin y (y = 15 to 0)
These bits can be read and written by software.
Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the
GPIOx_BSRR register (x = A..FA to H).

8.4.7 GPIO port bit set/reset register (GPIOx_BSRR)

(x = A to I)
Address offset: 0x18

344/2301 RM0432 Rev 6

RM0432 General-purpose I/Os (GPIO)

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15 BS14 BS13 BS12 BS11 BS10 BS9 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0
w w w w w w w w w w w w w w w w

Bits 31:16 BR[15:0]: Port x reset I/O pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODx bit
1: Resets the corresponding ODx bit
Note: If both BSx and BRx are set, BSx has priority.
Bits 15:0 BS[15:0]: Port x set I/O pin y (y = 15 to 0)
These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODx bit
1: Sets the corresponding ODx bit

8.4.8 GPIO port configuration lock register (GPIOx_LCKR)

(x = A to I)
This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the
LOCK sequence has been applied on a port bit, the value of this port bit can no longer be
modified until the next MCU reset or peripheral reset.
Note: A specific write sequence is used to write to the GPIOx_LCKR register. Only word access
(32-bit long) is allowed during this locking sequence.
Each lock bit freezes a specific configuration register (control and alternate function
registers).
Address offset: 0x1C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RM0432 Rev 6 345/2301

350
General-purpose I/Os (GPIO) RM0432

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 LCKK: Lock key
This bit can be read any time. It can only be modified using the lock key write sequence.
0: Port configuration lock key not active
1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU
reset or peripheral reset.
LOCK key write sequence:
WR LCKR[16] = ‘1’ + LCKR[15:0]
WR LCKR[16] = ‘0’ + LCKR[15:0]
WR LCKR[16] = ‘1’ + LCKR[15:0]
RD LCKR
RD LCKR[16] = ‘1’ (this read operation is optional but it confirms that the lock is active)
Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.
Any error in the lock sequence aborts the lock.
After the first lock sequence on any bit of the port, any read access on the LCKK bit
returns ‘1’ until the next MCU reset or peripheral reset.

Bits 15:0 LCK[15:0]: Port x lock I/O pin y (y = 15 to 0)

These bits are read/write but can only be written when the LCKK bit is ‘0.
0: Port configuration not locked
1: Port configuration locked

8.4.9 GPIO alternate function low register (GPIOx_AFRL)

(x = A to I)
Address offset: 0x20
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7[3:0] AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

346/2301 RM0432 Rev 6

RM0432 General-purpose I/Os (GPIO)

Bits 31:0 AFSEL[7:0][3:0]: Alternate function selection for port x I/O pin y (y = 7 to 0)
These bits are written by software to configure alternate function I/Os.
0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
1000: AF8
1001: AF9
1010: AF10
1011: AF11
1100: AF12
1101: AF13
1110: AF14
1111: AF15

8.4.10 GPIO alternate function high register (GPIOx_AFRH)

(x = A to I)
Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15[3:0] AFSEL14[3:0] AFSEL13[3:0] AFSEL12[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11[3:0] AFSEL10[3:0] AFSEL9[3:0] AFSEL8[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RM0432 Rev 6 347/2301

350
General-purpose I/Os (GPIO) RM0432

Bits 31:0 AFSEL[15:8][3:0]: Alternate function selection for port x I/O pin y (y = 15 to 8)
These bits are written by software to configure alternate function I/Os.
0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
1000: AF8
1001: AF9
1010: AF10
1011: AF11
1100: AF12
1101: AF13
1110: AF14
1111: AF15

8.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A to I)

Address offset: 0x28
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0
w w w w w w w w w w w w w w w w

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 BR[15:0]: Port x reset IO pin y (y = 15 to 0)
These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODx bit
1: Reset the corresponding ODx bit

348/2301 RM0432 Rev 6

 0x10
0x08
0x08
0x04
0x00
0x00
0x00

0x0C
0x0C
0x0C
8.4.12
RM0432

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

GPIOx_IDR
(where x = A..I)
(where x = A..I)

(where x = C..I)
(where x = C..I)

GPIOx_PUPDR
(where x = B..H)

GPIOB_PUPDR
GPIOA_PUPDR
GPIOx_MODER
GPIOB_MODER
GPIOA_MODER

GPIOx_OTYPER

GPIOx_OSPEEDR
GPIOA_OSPEEDR
Offset Register name

0
0
0
0
0
1
1
1
Res. Res. 31
PUPD15[1:0] PUPD15[1:0] PUPD15[1:0] OSPEED15[1:0] OSPEED15[1:0] MODE15[1:0] MODE15[1:0] MODE15[1:0]

0
0
1
0
0
1
1
0
Res. Res. 30

0
0
1
0
0
1
1
1
Res. Res. 29
PUPD14[1:0] PUPD14[1:0] PUPD14[1:0] OSPEED14[1:0] OSPEED14[1:0] MODE14[1:0] MODE14[1:0] MODE14[1:0]

0
0
0
0
0
1
1
0
Res. Res. 28

0
0
0
0
1
1
1
1
Res. Res. 27
PUPD13[1:0] PUPD13[1:0] PUPD13[1:0] OSPEED13[1:0] OSPEED13[1:0] MODE13[1:0] MODE13[1:0] MODE13[1:0]
GPIO register map

0
0
1
0
1
1
1
Res. Res. 0
26

0
0
0
0
0
1
1
1
Res. Res. 25
PUPD12[1:0] PUPD12[1:0] PUPD12[1:0] OSPEED12[1:0] OSPEED12[1:0] MODE12[1:0] MODE12[1:0] MODE12[1:0]

0
0
0
0
0
1
1
1

Res. Res. 24

0
0
0
0
0
1
1
1

Res. Res. 23
PUPD11[1:0] PUPD11[1:0] PUPD11[1:0] OSPEED11[1:0] OSPEED11[1:0] MODE11[1:0] MODE11[1:0] MODE11[1:0]

0
0
0
0
0
1
1
1

Res. Res. 22

0
0
0
0
0
1
1
1

Res. Res. 21
PUPD10[1:0] PUPD10[1:0] PUPD10[1:0] OSPEED10[1:0] OSPEED10[1:0] MODE10[1:0] MODE10[1:0] MODE10[1:0]

0
0
0
0
0
1
1
1

Res. Res. 20

0
0
0
0
0
1
1
1

Res. Res. 19
PUPD9[1:0] PUPD9[1:0] PUPD9[1:0] OSPEED9[1:0] OSPEED9[1:0] MODE9[1:0] MODE9[1:0] MODE9[1:0]

0
0
0
0
0
1
1
1

Res. Res. 18

RM0432 Rev 6
0
0
0
0
0
1
1
1

Res. Res. 17
PUPD8[1:0] PUPD8[1:0] PUPD8[1:0] OSPEED8[1:0] OSPEED8[1:0] MODE8[1:0] MODE8[1:0] MODE8[1:0]

0
0
0
0
0
1
1
1

Res. Res. 16

x
0
0
0
0
0
1
1
1

0
ID15 OT15 15
PUPD7[1:0] PUPD7[1:0] PUPD7[1:0] OSPEED7[1:0] OSPEED7[1:0] MODE7[1:0] MODE7[1:0] MODE7[1:0]

x
0
0
0
0
0
1
1
1

0
ID14 OT14 14

x
0
0
0
0
0
1
1
1

0
ID13 OT13 13
PUPD6[1:0] PUPD6[1:0] PUPD6[1:0] OSPEED6[1:0] OSPEED6[1:0] MODE6[1:0] MODE6[1:0] MODE6[1:0]

x
0
0
0
0
0
1
1
1

0
ID12 OT12 12

x
0
0
0
0
0
1
1
1

ID11 OT11
Table 44. GPIO register map and reset values

PUPD5[1:0] PUPD5[1:0] PUPD5[1:0] OSPEED5[1:0] OSPEED5[1:0] MODE5[1:0] MODE5[1:0] MODE5[1:0]

11

x
0
0
0
0
0
1
1
1

ID10 OT10 10
The following table gives the GPIO register map and reset values.

x
0
0
0
0
0
1
1
1

ID9 OT9 9
PUPD4[1:0] PUPD4[1:0] PUPD4[1:0] OSPEED4[1:0] OSPEED4[1:0] MODE4[1:0] MODE4[1:0] MODE4[1:0]

x
0
1
0
0
0
1
0
1

ID8 OT8 8

x
0
0
0
0
0
1
1
1

ID7 OT7 7
PUPD3[1:0] PUPD3[1:0] PUPD3[1:0] OSPEED3[1:0] OSPEED3[1:0] MODE3[1:0] MODE3[1:0] MODE3[1:0]

x
0
0
0
0
0
1
0
1

ID6 OT6 6

x
0

0
0
0
0
0
1
1
1

ID5 OT5 5
PUPD2[1:0] PUPD2[1:0] PUPD2[1:0] OSPEED2[1:0] OSPEED2[1:0] MODE2[1:0] MODE2[1:0] MODE2[1:0]

x
0

0
0
0
0
0
1
1
1

ID4 OT4 4

x
0

0
0
0
0
0
1
1
1

ID3 OT3 3
PUPD1[1:0] PUPD1[1:0] PUPD1[1:0] OSPEED1[1:0] OSPEED1[1:0] MODE1[1:0] MODE1[1:0] MODE1[1:0]

x
0

0
0
0
0
0
1
1
1

ID2 OT2 2

x
0

0
0
0
0
0
1
1
1

ID1 OT1 1
PUPD0[1:0] PUPD0[1:0] PUPD0[1:0] OSPEED0[1:0] OSPEED0[1:0] MODE0[1:0] MODE0[1:0] MODE0[1:0]

x
0

0
0
0
0
0
1
1
1

ID0 OT0 0

349/2301
General-purpose I/Os (GPIO)

350
General-purpose I/Os (GPIO) RM0432

Table 44. GPIO register map and reset values (continued)

Offset Register name

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
GPIOx_ODR

OD15
OD14
OD13
OD12

OD10
OD11
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
0x14 (where x = A..I)
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_BSRR BR15
BR14
BR13
BR12

BR10

BS15
BS14
BS13
BS12

BS10
BR11

BS11
BR9
BR8
BR7
BR6
BR5
BR4
BR3
BR2
BR1
BR0

BS9
BS8
BS7
BS6
BS5
BS4
BS3
BS2
BS1
BS0
0x18 (where x = A..I)
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LCK15
LCK14
LCK13
LCK12

LCK10
LCK11
GPIOx_LCKR

LCKK

LCK9
LCK8
LCK7
LCK6
LCK5
LCK4
LCK3
LCK2
LCK1
LCK0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x1C (where x = A..I)

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_AFRL
AFSEL7[3:0] AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0] AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0]
0x20 (where x = A..I)
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_AFRH AFSEL15[3:0 AFSEL14[3:0 AFSEL13[3:0 AFSEL12[3:0 AFSEL11[3:0
AFSEL10[3:0] AFSEL9[3:0] AFSEL8[3:0]
0x24 (where x = A..I) ] ] ] ] ]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_BRR

BR15
BR14
BR13
BR12

BR10
BR11
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

BR9
BR8
BR7
BR6
BR5
BR4
BR3
BR2
BR1
BR0
0x28 (where x = A..I))
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 91 for the register boundary addresses.

350/2301 RM0432 Rev 6

RM0432 System configuration controller (SYSCFG)

9 System configuration controller (SYSCFG)

9.1 SYSCFG main features

The STM32L4+ Series devices feature a set of configuration registers. The main purposes
of the system configuration controller are the following:
• Remapping memory areas
• Managing the external interrupt line connection to the GPIOs
• Managing robustness feature
• Setting SRAM2 write protection and software erase
• Configuring FPU interrupts
• Enabling the firewall
• Enabling /disabling I2C Fast-mode Plus driving capability on some I/Os and voltage
booster for I/Os analog switches.

9.2 SYSCFG registers

9.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP)

This register is used for specific configurations on memory remap.
Address offset: 0x00
Reset value: 0x0000 000X (X is the memory mode selected by the BOOT0 pin and BOOT1
option bit)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB_
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MEM_MODE[2:0]
MODE
rw rw rw rw

RM0432 Rev 6 351/2301

365
System configuration controller (SYSCFG) RM0432

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 FB_MODE: Flash Bank mode selection
For 2 Mbytes devices:
0: Flash Bank 1 mapped at 0x0800 0000 (and aliased @0x0000 0000(1))
and Flash Bank 2 mapped at 0x0810 0000 (and aliased at 0x0010 0000)
1: Flash Bank 2 mapped at 0x0800 0000 (and aliased @0x0000 0000(1))
and Flash Bank 1 mapped at 0x0810 0000 (and aliased at 0x0010 0000)
For 1 Mbyte devices:
0: Flash Bank 1 mapped at 0x0800 0000 (and aliased @0x0000 0000(1))
and Flash Bank 2 mapped at 0x0808 0000 (and aliased at 0x0008 0000)
1: Flash Bank2 mapped at 0x0800 0000 (and aliased @0x0000 0000(1))
and Flash Bank 1 mapped at 0x0808 0000 (and aliased at 0x0008 0000)
For 512 Kbytes devices:
0: Flash Bank 1 mapped at 0x0800 0000 (and aliased @0x0000 0000(1))
and Flash Bank 2 mapped at 0x0804 0000 (and aliased at 0x0004 0000)
1: Flash Bank2 mapped at 0x0800 0000 (and aliased @0x0000 0000(1))
and Flash Bank 1 mapped at 0x0804 0000 (and aliased at 0x0004 0000)
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 MEM_MODE: Memory mapping selection
These bits control the memory internal mapping at address 0x0000 0000. These bits are
used to select the physical remap by software and so, bypass the BOOT pin and the option
bit setting. After reset these bits take the value selected by BOOT0 pin (or option bit
depending on nSWBOOT0 option bit) and BOOT1 option bit.
000: Main Flash memory mapped at 0x00000000(1).
001: System Flash memory mapped at 0x00000000.
010: FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.
011: SRAM1 mapped at 0x00000000.
100: OCTOSPI1 memory mapped at 0x00000000
101: OCTOSPI2 memory mapped at 0x00000000
111: Reserved
1. When BFB2 bit is set, the system memory remains aliased at @0x0000 0000.

Note: When the FSMC is remapped at address 0x0000 0000, only the first two regions of Bank 1
memory controller (Bank1 NOR/PSRAM 1 and NOR/PSRAM 2) can be remapped. In remap
mode, the CPU can access the external memory via ICode bus instead of System bus
which boosts up the performance.

9.2.2 SYSCFG configuration register 1 (SYSCFG_CFGR1)

Address offset: 0x04
Reset value: 0x7C00 0001

352/2301 RM0432 Rev 6

RM0432 System configuration controller (SYSCFG)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I2C_ I2C_ I2C_ I2C_
I2C4_ I2C3_ I2C2_ I2C1_
FPU_IE[5:0] Res. Res. PB9_ PB8_ PB7_ PB6_
FMP FMP FMP FMP
FMP FMP FMP FMP
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ANAS BOOST
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FWDIS
WVDD EN
rw rw rc_w0

Bits 31:26 FPU_IE[5..0]: Floating point unit interrupts enable bits

FPU_IE[5]: Inexact interrupt enable
FPU_IE[4]: Input denormal interrupt enable
FPU_IE[3]: Overflow interrupt enable
FPU_IE[2]: underflow interrupt enable
FPU_IE[1]: Divide-by-zero interrupt enable
FPU_IE[0]: Invalid operation interrupt enable
Bits 25:24 Reserved, must be kept at reset value.
Bit 23 I2C4_FMP: Fast-mode Plus driving capability activation
This bit enables the Fm+ driving mode on I2C4 pins selected through AF selection bits.
0: Fm+ mode is not enabled on I2C4 pins selected through AF selection bits
1: Fm+ mode is enabled on I2C4 pins selected through AF selection bits.
Bit 22 I2C3_FMP: I2C3 Fast-mode Plus driving capability activation
This bit enables the Fm+ driving mode on I2C3 pins selected through AF selection bits.
0: Fm+ mode is not enabled on I2C3 pins selected through AF selection bits
1: Fm+ mode is enabled on I2C3 pins selected through AF selection bits.
Bit 21 I2C2_FMP: I2C2 Fast-mode Plus driving capability activation
This bit enables the Fm+ driving mode on I2C2 pins selected through AF selection bits.
0: Fm+ mode is not enabled on I2C2 pins selected through AF selection bits
1: Fm+ mode is enabled on I2C2 pins selected through AF selection bits.
Bit 20 I2C1_FMP: I2C1 Fast-mode Plus driving capability activation
This bit enables the Fm+ driving mode on I2C1 pins selected through AF selection bits.
0: Fm+ mode is not enabled on I2C1 pins selected through AF selection bits
1: Fm+ mode is enabled on I2C1 pins selected through AF selection bits.
Bit 19 I2C_PB9_FMP: Fast-mode Plus (Fm+) driving capability activation on PB9
This bit enables the Fm+ driving mode for PB9.
0: PB9 pin operates in standard mode.
1: Fm+ mode enabled on PB9 pin, and the Speed control is bypassed.
Bit 18 I2C_PB8_FMP: Fast-mode Plus (Fm+) driving capability activation on PB8
This bit enables the Fm+ driving mode for PB8.
0: PB8 pin operates in standard mode.
1: Fm+ mode enabled on PB8 pin, and the Speed control is bypassed.
Bit 17 I2C_PB7_FMP: Fast-mode Plus (Fm+) driving capability activation on PB7
This bit enables the Fm+ driving mode for PB7.
0: PB7 pin operates in standard mode.
1: Fm+ mode enabled on PB7 pin, and the Speed control is bypassed.

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System configuration controller (SYSCFG) RM0432

Bit 16 I2C_PB6_FMP: Fast-mode Plus (Fm+) driving capability activation on PB6

This bit enables the Fm+ driving mode for PB6.
0: PB6 pin operates in standard mode.
1: Fm+ mode enabled on PB6 pin, and the Speed control is bypassed.
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 ANASWVDD: GPIO analog switch control voltage selection
0: I/O analog switches supplied by VDDA or booster when booster is ON
1: I/O analog switches supplied by VDD.
Refer to Table 45 for bit 9 setting.
Bit 8 BOOSTEN: I/O analog switch voltage booster enable
0: I/O analog switches are supplied by VDDA voltage. This is the recommended configuration
when using the ADC in high VDDA voltage operation.
1: I/O analog switches are supplied by a dedicated voltage booster (supplied by VDD). This is
the recommended configuration when using the ADC in low VDDA voltage operation.
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 FWDIS: Firewall disable
This bit is cleared by software to protect the access to the memory segments according to
the Firewall configuration. Once enabled, the firewall cannot be disabled by software. Only a
system reset set the bit.
0: Firewall protection enabled
1: Firewall protection disabled

Table 45 describes when the bit 9 (ANASWVDD) and the bit 8 (BOOSTEN) should be set or
reset depending on the voltage settings.

Table 45. BOOSTEN and ANASWVDD set/reset

VDD VDDA BOOSTEN ANASWVDD

- > 2.4 V 0 0
> 2.4 V < 2.4 V 0 1
< 2.4 V < 2.4 V 1 0

9.2.3 SYSCFG external interrupt configuration register 1

(SYSCFG_EXTICR1)
Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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RM0432 System configuration controller (SYSCFG)

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:12 EXTI3[3:0]: EXTI 3 configuration bits
These bits are written by software to select the source input for the EXTI3
external interrupt.
0000: PA[3] pin
0001: PB[3] pin
0010: PC[3] pin
0011: PD[3] pin
0100: PE[3] pin
0101: PF[3] pin
0110: PG[3] pin
0111: PH[3] pin
1000: PI[3] pin
Bits 11:8 EXTI2[3:0]: EXTI 2 configuration bits
These bits are written by software to select the source input for the EXTI2
external interrupt.
0000: PA[2] pin
0001: PB[2] pin
0010: PC[2] pin
0011: PD[2] pin
0100: PE[2] pin
0101: PF[2] pin
0110: PG[2] pin
0111: PH[2] pin
1000: PI[2] pin
Bits 7:4 EXTI1[3:0]: EXTI 1 configuration bits
These bits are written by software to select the source input for the EXTI1
external interrupt.
0000: PA[1] pin
0001: PB[1] pin
0010: PC[1] pin
0011: PD[1] pin
0100: PE[1] pin
0101: PF[1] pin
0110: PG[1] pin
0111: PH[1] pin
1000: PI[1] pin
Bits 3:0 EXTI0[3:0]: EXTI 0 configuration bits
These bits are written by software to select the source input for the EXTI0
external interrupt.
0000: PA[0] pin
0001: PB[0] pin
0010: PC[0] pin
0011: PD[0] pin
0100: PE[0] pin
0101: PF[0] pin
0110: PG[0] pin
0111: PH[0] pin
1000: PI[0] pin

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System configuration controller (SYSCFG) RM0432

9.2.4 SYSCFG external interrupt configuration register 2

(SYSCFG_EXTICR2)
Address offset: 0x0C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:12 EXTI7[3:0]: EXTI 7 configuration bits
These bits are written by software to select the source input for the EXTI7
external interrupt.
0000: PA[7] pin
0001: PB[7] pin
0010: PC[7] pin
0011: PD[7] pin
0100: PE[7] pin
0101: PF[7] pin
0110: PG[7] pin
0111: PH[7] pin
1000: PI[7] pin

356/2301 RM0432 Rev 6

RM0432 System configuration controller (SYSCFG)

Bits 11:8 EXTI6[3:0]: EXTI 6 configuration bits

These bits are written by software to select the source input for the EXTI6
external interrupt.
0000: PA[6] pin
0001: PB[6] pin
0010: PC[6] pin
0011: PD[6] pin
0100: PE[6] pin
0101: PF[6] pin
0110: PG[6] pin
0111: PH[6] pin
1000: PI[6] pin
Bits 7:4 EXTI5[3:0]: EXTI 5 configuration bits
These bits are written by software to select the source input for the EXTI5
external interrupt.
0000: PA[5] pin
0001: PB[5] pin
0010: PC[5] pin
0011: PD[5] pin
0100: PE[5] pin
0101: PF[5] pin
0110: PG[5] pin
0111: PH[5] pin
1000: PI[5] pin
Bits 3:0 EXTI4[3:0]: EXTI 4 configuration bits
These bits are written by software to select the source input for the EXTI4
external interrupt.
0000: PA[4] pin
0001: PB[4] pin
0010: PC[4] pin
0011: PD[4] pin
0100: PE[4] pin
0101: PF[4] pin
0110: PG[4] pin
0111: PH[4] pin
1000: PI[4] pin

Note: Some of the I/O pins mentioned in the above register may not be available on small
packages.

9.2.5 SYSCFG external interrupt configuration register 3

(SYSCFG_EXTICR3)
Address offset: 0x10
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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System configuration controller (SYSCFG) RM0432

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:12 EXTI11[3:0]: EXTI 11 configuration bits
These bits are written by software to select the source input for the EXTI11
external interrupt.
0000: PA[11] pin
0001: PB[11] pin
0010: PC[11] pin
0011: PD[11] pin
0100: PE[11] pin
0101: PF[11] pin
0110: PG[11] pin
0111: PH[11] pin
1000: PI[11] pin
Bits 11:8 EXTI10[3:0]: EXTI 10 configuration bits
These bits are written by software to select the source input for the EXTI10
external interrupt.
0000: PA[10] pin
0001: PB[10] pin
0010: PC[10] pin
0011: PD[10] pin
0100: PE[10] pin
0101: PF[10] pin
0110: PG[10] pin
0111: PH[10] pin
1000: PI[10] pin
Bits 7:4 EXTI9[3:0]: EXTI 9 configuration bits
These bits are written by software to select the source input for the EXTI9
external interrupt.
0000: PA[9] pin
0001: PB[9] pin
0010: PC[9] pin
0011: PD[9] pin
0100: PE[9] pin
0101: PF[9] pin
0110: PG[9] pin
0111: PH[9] pin
1000: PI[9] pin
Bits 3:0 EXTI8[3:0]: EXTI 8 configuration bits
These bits are written by software to select the source input for the EXTI8
external interrupt.
0000: PA[8] pin
0001: PB[8] pin
0010: PC[8] pin
0011: PD[8] pin
0100: PE[8] pin
0101: PF[8] pin
0110: PG[8] pin
0111: PH[8] pin
1000: PI[8] pin

Note: Some of the I/O pins mentioned in the above register may not be available on small
packages.

358/2301 RM0432 Rev 6

RM0432 System configuration controller (SYSCFG)

9.2.6 SYSCFG external interrupt configuration register 4

(SYSCFG_EXTICR4)
Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:12 EXTI15[3:0]: EXTI 15 configuration bits
These bits are written by software to select the source input for the EXTI15 external
interrupt.
0000: PA[15] pin
0001: PB[15] pin
0010: PC[15] pin
0011: PD[15] pin
0100: PE[15] pin
0101: PF[15] pin
0110: PG[15] pin
0111: PH[15] pin
1000: Reserved

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System configuration controller (SYSCFG) RM0432

Bits 11:8 EXTI14[3:0]: EXTI 14 configuration bits

These bits are written by software to select the source input for the EXTI14 external
interrupt.
0000: PA[14] pin
0001: PB[14] pin
0010: PC[14] pin
0011: PD[14] pin
0100: PE[14] pin
0101: PF[14] pin
0110: PG[14] pin
0111: PH[14] pin
1000: Reserved
Bits 7:4 EXTI13[3:0]: EXTI 13 configuration bits
These bits are written by software to select the source input for the EXTI13 external
interrupt.
0000: PA[13] pin
0001: PB[13] pin
0010: PC[13] pin
0011: PD[13] pin
0100: PE[13] pin
0101: PF[13] pin
0110: PG[13] pin
0111: PH[13] pin
1000: Reserved
Bits 3:0 EXTI12[3:0]: EXTI 12 configuration bits
These bits are written by software to select the source input for the EXTI12 external
interrupt.
0000: PA[12] pin
0001: PB[12] pin
0010: PC[12] pin
0011: PD[12] pin
0100: PE[12] pin
0101: PF[12] pin
0110: PG[12] pin
0111: PH[12] pin
1000: Reserved

Note: Some of the I/O pins mentioned in the above register may not be available on small
packages.

9.2.7 SYSCFG SRAM2 control and status register (SYSCFG_SCSR)

Address offset: 0x18
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM2 SRAM2
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
BSY ER
r rw

360/2301 RM0432 Rev 6

RM0432 System configuration controller (SYSCFG)

Bits 31:2 Reserved, must be kept at reset value

Bit 1 SRAM2BSY: SRAM2 busy by erase operation
0: No SRAM2 erase operation is on going.
1: SRAM2 erase operation is on going.
Bit 0 SRAM2ER: SRAM2 Erase
Setting this bit starts a hardware SRAM2 erase operation. This bit is
automatically cleared at the end of the SRAM2 erase operation.
Note: This bit is write-protected: setting this bit is possible only after the correct
key sequence is written in the SYSCFG_SKR register.

9.2.8 SYSCFG configuration register 2 (SYSCFG_CFGR2)

Address offset: 0x1C
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. SPF Res. Res. Res. Res. ECCL PVDL SPL CLL
rc_w1 rs rs rs rs

Bits 31:9 Reserved, must be kept at reset value

Bit 8 SPF: SRAM2 parity error flag
This bit is set by hardware when an SRAM2 parity error is detected. It is cleared
by software by writing ‘1’.
0: No SRAM2 parity error detected
1: SRAM2 parity error detected
Bits 7:4 Reserved, must be kept at reset value
Bit 3 ECCL: ECC Lock
This bit is set by software and cleared only by a system reset. It can be used to
enable and lock the Flash ECC error connection to TIM1/8/15/16/17 Break input.
0: ECC error disconnected from TIM1/8/15/16/17 Break input.
1: ECC error connected to TIM1/8/15/16/17 Break input.

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System configuration controller (SYSCFG) RM0432

Bit 2 PVDL: PVD lock enable bit

This bit is set by software and cleared only by a system reset. It can be used to
enable and lock the PVD connection to TIM1/8/15/16/17 Break input, as well as
the PVDE and PLS[2:0] in the PWR_CR2 register.
0: PVD interrupt disconnected from TIM1/8/15/16/17 Break input. PVDE and
PLS[2:0] bits can be programmed by the application.
1: PVD interrupt connected to TIM1/8/15/16/17 Break input, PVDE and PLS[2:0]
bits are read only.
Bit 1 SPL: SRAM2 parity lock bit
This bit is set by software and cleared only by a system reset. It can be used to
enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17
Break inputs.
0: SRAM2 parity error signal disconnected from TIM1/8/15/16/17 Break inputs
1: SRAM2 parity error signal connected to TIM1/8/15/16/17 Break inputs
Bit 0 CLL: Cortex®-M4 LOCKUP (Hardfault) output enable bit
This bit is set by software and cleared only by a system reset. It can be used to
enable and lock the connection of Cortex®-M4 LOCKUP (Hardfault) output to
TIM1/8/15/16/17 Break input
0: Cortex®-M4 LOCKUP output disconnected from TIM1/8/15/16/17 Break inputs
1: Cortex®-M4 LOCKUP output connected to TIM1/8/15/16/17 Break inputs

9.2.9 SYSCFG SRAM2 write protection register (SYSCFG_SWPR)

Address offset: 0x20
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31WP P30WP P29WP P28WP P27WP P26WP P25WP P24WP P23WP P22WP P21WP P20WP P19WP P18WP P17WP P16WP
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15WP P14WP P13WP P12WP P11WP P10WP P9WP P8WP P7WP P6WP P5WP P4WP P3WP P2WP P1WP P0WP
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs

Bits 31:0 PxWP (x = 0 to 31): SRAM2 page x write protection

These bits are set by software and cleared only by a system reset.
0: Write protection of SRAM2 page x is disabled.
1: Write protection of SRAM2 page x is enabled.

9.2.10 SYSCFG SRAM2 key register (SYSCFG_SKR)

Address offset: 0x24
System reset value: 0x0000 0000

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RM0432 System configuration controller (SYSCFG)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. KEY[7:0]
w w w w w w w w

Bits 31:8 Reserved, must be kept at reset value

Bits 7:0 KEY[7:0]: SRAM2 write protection key for software erase
The following steps are required to unlock the write protection of the SRAM2ER
bit in the SYSCFG_CFGR2 register.
1. Write "0xCA” into Key[7:0]
2. Write "0x53” into Key[7:0]
Writing a wrong key reactivates the write protection.

9.2.11 SYSCFG SRAM2 write protection register 2 (SYSCFG_SWPR2)

Address offset: 0x28
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P63WP P62WP P61WP P60WP P59WP P58WP P57WP P56WP P55WP P54WP P53WP P52WP P51WP P50WP P49WP P48WP
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P47WP P46WP P45WP P44WP P43WP P42WP P41WP P40WP P39WP P38WP P37WP P36WP P35WP P34WP P33WP P32WP
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs

Bits 31:0 PxWP (x= 32 to 63): SRAM2 page x write protection

These bits are set by software and cleared only by a system reset.
0: Write protection of SRAM2 page x is disabled.
1: Write protection of SRAM2 page x is enabled.

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 0x29
0x24
0x20
0x18
0x14
0x10
0x08
0x04
0x00

0x1C
0x0C
Offset
9.2.12

364/2301
MEMRMP
SYSCFG_
Register

Reset value
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

SYSCFG_SKR
SYSCFG_SCSR

SYSCFG_SWPR
SYSCFG_CFGR2
SYSCFG_CFGR1

SYSCFG_SWPR2
SYSCFG_EXTICR4
SYSCFG_EXTICR3
SYSCFG_EXTICR2
SYSCFG_EXTICR1

0
0
0
P63WP Res. P31WP Res. Res. Res. Res. Res. Res. Res. 31

0
0
1
P62WP Res. P30WP Res. Res. Res. Res. Res. Res. Res. 30

0
0
1
P61WP Res. P29WP Res. Res. Res. Res. Res. Res. Res. 29

0
0
1
P60WP Res. P28WP Res. Res. Res. Res. Res. Res. Res. 28

0
0
1
FPU_IE[5..0]
P59WP Res. P27WP Res. Res. Res. Res. Res. Res. Res. 27

0
0
1
P58WP Res. P26WP Res. Res. Res. Res. Res. Res. Res. 26

0
0
P57WP Res. P25WP Res. Res. Res. Res. Res. Res. Res. Res. 25
SYSCFG register map

0
0
P56WP Res. P24WP Res. Res. Res. Res. Res. Res. Res. Res. 24

0
0
0
P55WP Res. P23WP Res. Res. Res. Res. Res. Res. I2C4_FMP Res.
System configuration controller (SYSCFG)

23

0
0
0
P54WP Res. P22WP Res. Res. Res. Res. Res. Res. I2C3_FMP Res. 22

0
0
0
P53WP Res. P21WP Res. Res. Res. Res. Res. Res. I2C2_FMP Res. 21

0
0
0
P52WP Res. P20WP Res. Res. Res. Res. Res. Res. I2C1_FMP Res. 20

0
0
0
P51WP Res. P19WP Res. Res. Res. Res. Res. Res. I2C_PB9_FMP Res. 19

0
0
0
P50WP Res. P18WP Res. Res. Res. Res. Res. Res. I2C_PB8_FMP Res. 18

RM0432 Rev 6
0
0
0
P49WP Res. P17WP Res. Res. Res. Res. Res. Res. I2C_PB7_FMP Res. 17

0
0
0
P48WP Res. P16WP Res. Res. Res. Res. Res. Res. I2C_PB6_FMP Res. 16

0
0
0
0
0
0
P47WP Res. P15WP Res. Res. Res. Res. 15

0
0
0
0
0
0
P46WP Res. P14WP Res. Res. Res. Res. 14

[3:0]
[3:0]
[3:0]
[3:0]

0
0
0
0
0
0
P45WP Res. P13WP Res. Res. Res. Res.
EXTI7
EXTI3

13

EXTI11

EXTI15

0
0
0
0
0
0

P44WP Res. P12WP Res. Res. Res. Res. 12

0
0
0
0
0
0

P43WP Res. P11WP Res. Res. Res. Res. 11

0
0
0
0
0
0
Table 46. SYSCFG register map and reset values

P42WP Res. P10WP Res. Res. Res. Res. 10

[3:0]
[3:0]
[3:0]
[3:0]

0
0
0
0
0
0
0

P41WP Res. P9WP Res. Res. ANASWVDD Res.

EXTI6
EXTI2

EXTI14
EXTI10

0
0
0
0
0
0
0

0
0

P40WP Res. P8WP SPF Res. BOOSTEN FB_MODE 8

0
0
0
0
0
0

0
The following table gives the SYSCFG register map and the reset values.

P39WP P7WP Res. Res. Res. Res. 7

0
0
0
0
0
0

0
P38WP P6WP Res. Res. Res. Res. 6
[3:0]
[3:0]
[3:0]
[3:0]

0
0
0
0
0
0

0
P37WP P5WP Res. Res. Res. Res.
EXTI9
EXTI5
EXTI1

5
EXTI13

0
0
0
0
0
0

0
P36WP P4WP Res. Res. Res. Res. 4

KEY

0
0
0
0
0
0
0

0
0
P35WP P3WP ECCL Res. Res. Res. 3
x

0
0
0
0
0
0
0

0
0
P34WP P2WP PVDL Res. Res. 2
[3:0]
[3:0]
[3:0]
[3:0]
x

0
0
0
0
0
0
0

0
0
0
P33WP P1WP SPL SRAM2BS Res.
EXTI8
EXTI4
EXTI0

1
EXTI12
MEM_
MODE

0
0
0
0
0
0
1

0
0
0
P32WP P0WP CLL SRAM2ER FWDIS
RM0432

0
RM0432 System configuration controller (SYSCFG)

Refer to Section 2.2 on page 91 for the register boundary addresses.

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Peripherals interconnect matrix RM0432

10 Peripherals interconnect matrix

10.1 Introduction
Several peripherals have direct connections between them.
This allows autonomous communication and or synchronization between peripherals,
saving CPU resources thus power supply consumption.
In addition, these hardware connections remove software latency and allow design of
predictable system.
Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power
run and sleep, Stop 0, Stop 1 and Stop 2 modes.

10.2 Connection summary

Table 47. STM32L4+ Series peripherals interconnect matrix(1) (2)
Destination

OPAMP1

OPAMP2
DFSDM1
Source

ADC2(3)
LPTIM1

LPTIM2

COMP1

COMP2
TIM15

TIM16

TIM17

IRTIM
ADC1

DAC1

DAC2
TIM1

TIM8

TIM2

TIM3

TIM4

TIM5

TIM6

TIM7

TIM1 - 1 1 1 1 - - - 1 - - - - 2 2 5 - - - - 9 - -
TIM8 - - 1 - 1 1 - - - - - - - 2 2 5 - - 4 4 - 9 -
TIM2 1 1 - 1 1 1 - - - - - - - 2 2 - - - 4 4 9 - -
TIM3 1 - 1 - 1 1 - - 1 - - - - 2 2 5 - - - - 9 9 -
TIM4 1 1 1 1 - 1 - - - - - - - 2 2 5 - - 4 4 - - -
TIM5 - 1 - - - - - - - - - - - - - - - - 4 4 - - -
TIM6 - - - - - - - - - - - - - 2 2 5 - - 4 4 - - -
TIM7 - - - - - - - - - - - - - - - 5 - - 4 4 - - -
TIM15 1 - - 1 - - - - - - - - - 2 2 - - - - - - 9 -
TIM16 - - - - - - - - 1 - - - - - - 5 - - - - - - 15
TIM17 - - - - - - - - 1 - - - - - - - - - - - - - 15
LPTIM1 - - - - - - - - - - - - - - - 5 - - - - - - -
LPTIM2 - - - - - - - - - - - - - - - 5 - - - - - - -
ADC1 3 - - - - - - - - - - - - - 10 16 - - - - - - -
(3)
ADC2 - 3 - - - - - - - - - - - - - 16 - - - - - - -
DFSDM1 6 6 - - - - - - 6 6 6 - - - - - - - - - - - -
T. Sensor - - - - - - - - - - - - - 12 - - - - - - - - -
VBAT - - - - - - - - - - - - - 12 - - - - - - - - -
VREFINT - - - - - - - - - - - - - 12 - - - - - - - - -

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Table 47. STM32L4+ Series peripherals interconnect matrix(1) (2)

Destination

OPAMP1

OPAMP2
DFSDM1
Source

ADC2(3)
LPTIM1

LPTIM2

COMP1

COMP2
TIM15

TIM16

TIM17

IRTIM
ADC1

DAC1

DAC2
TIM1

TIM8

TIM2

TIM3

TIM4

TIM5

TIM6

TIM7
OPAMP1 - - - - - - - - - - - - - 12 12 - - - - - - - -
OPAMP2 - - - - - - - - - - - - - 12 12 - - - - - - - -
DAC1 - - - - - - - - - - - - - - 12 - 12 12 - - - - -
DAC2 - - - - - - - - - - - - - - 12 - - - - - - - -
HSE - - - - - - - - - - 7 - - - - - - - - - - - -
LSE - - 7 - - - - - 7 7 - - - - - - - - - - - - -
MSI - - - - - - - - - - 7 - - - - - - - - - - - -
LSI - - - - - - - - - 7 - - - - - - - - - - - - -
MCO - - - - - - - - - - 7 - - - - - - - - - - - -
EXTI - - - - - - - - - - - - - 2 2 5 - - 4 4 - - -
RTC - - - - - - - - - 7 - 8 8 - - - - - - - - - -
COMP1 13 13 13 13 - - - - 13 13 13 8 8 - - - - - - - - - -
COMP2 13 13 13 13 - - - - 13 13 13 8 8 - - - - - - - - - -
SYST ERR 14 14 - - - - - - 14 14 14 - - - - - - - - - - - -
USB - - 11 - - - - - - - - - - - - - - - - - - - -
1. Numbers in table are links to corresponding detailed sub-section in Section 10.3: Interconnection details.
2. The “-” symbol in grayed cells means no interconnect.
3. ADC2 is only available on STM32L4P5xx and STM32L4Q5xx devices.

10.3 Interconnection details

10.3.1 From timer (TIM1/TIM2/TIM3/TIM4/TIM5/TIM8/TIM15/TIM16/TIM17)

to timer (TIM1/TIM2/TIM3/TIM4/TIM5/TIM8/TIM15)
Purpose
Some of the TIMx timers are linked together internally for timer synchronization or chaining.
When one timer is configured in Master Mode, it can reset, start, stop or clock the counter of
another timer configured in Slave Mode.
A description of the feature is provided in: Section 38.3.19: Timer synchronization.

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The modes of synchronization are detailed in:

• Section 37.3.26: Timer synchronization for advanced-control timers (TIM1/TIM8)
• Section 38.3.18: Timers and external trigger synchronization for general-purpose
timers (TIM2/TIM3/TIM4/TIM5)
• Section 39.4.19: External trigger synchronization (TIM15 only) for general-purpose
timer (TIM15)

Triggering signals
The output (from Master) is on signal TIMx_TRGO (and TIMx_TRGO2 for TIM1/TIM8)
following a configurable timer event.
The input (to slave) is on signals TIMx_ITR0/ITR1/ITR2/ITR3
The input and output signals for TIM1/TIM8 are shown in Figure 283: Advanced-control
timer block diagram.
The possible master/slave connections are given in:
• Table 275: TIMx internal trigger connection
• Table 280: TIMx internal trigger connection
• Table 284: TIMx Internal trigger connection

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.2 From timer (TIM1/TIM2/TIM3/TIM4/TIM6/TIM8/TIM15) and EXTI

to ADC (ADC1)
Purpose
General-purpose timers (TIM2/TIM3/TIM4), basic timer (TIM6), advanced-control timers
(TIM1/TIM8), general-purpose timer (TIM15) and EXTI can be used to generate an ADC
triggering event.
TIMx synchronization is described in: Section 37.3.27: ADC synchronization (TIM1/TIM8).
ADC synchronization is described in: Section 21.4.18: Conversion on external trigger and
trigger polarity (EXTSEL, EXTEN,JEXTSEL, JEXTEN).

Triggering signals
The output (from timer) is on signal TIMx_TRGO, TIMx_TRGO2 or TIMx_CCx event.
The input (to ADC) is on signal EXT[15:0], JEXT[15:0].
The connection between timers and ADC is provided in:
• Table 130: ADC1 - External triggers for regular channels
• Table 131: ADC1 - External trigger for injected channels

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

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10.3.3 From ADC to timer (TIM1/TIM8)

Purpose
ADC1 can provide trigger event through watchdog signals to advanced-control timers
(TIM1/TIM8).
A description of the ADC analog watchdog setting is provided in: Section 21.4.29: Analog
window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH,
AWD_HTx, AWD_LTx, AWDx).
Trigger settings on the timer are provided in: Section 37.3.4: External trigger input.

Triggering signals
The output (from ADC) is on signals ADCn_AWDx_OUT n = 1, 2 (for ADC1, 2) x = 1, 2, 3 (3
watchdog per ADC) and the input (to timer) on signal TIMx_ETR (external trigger).

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.4 From timer (TIM2/TIM4/TIM5/TIM6/TIM7/TIM8) and EXTI to DAC

(DAC1/DAC2)
Purpose
General-purpose timers (TIM2/TIM4/TIM5), basic timers (TIM6, TIM7), advanced-control
timers (TIM8) and EXTI can be used as triggering event to start a DAC conversion.

Triggering signals
The output (from timer) is on signal TIMx_TRGO directly connected to corresponding DAC
inputs.
Selection of input triggers on DAC is provided in Section 22.4.6: DAC trigger selection
(single and dual mode).

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.5 From timer (TIM1/TIM3/TIM4/TIM6/TIM7/TIM8/TIM16/LPTIM1/LPTIM2)

and EXTI to DFSDM1
Purpose
General-purpose timers (TIM3/TIM4), basic timers (TIM6/TIM7), advanced-control timers
(TIM1/TIM8), general-purpose timer (TIM16), low power timers (LPTIM1/LPTIM2) and EXTI
can be used to generate a triggering event on DFSDM1 module (on each possible data
block DFSDM1_FLT0/DFSDM1_FLT1/DFSDM1_FLT2/DFSDM1_FLT3) and start an ADC
conversion.
DFSDM triggered conversion feature is described in: Section 28.4.15: Launching
conversions.

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Triggering signals
The output (from timer) is on signal TIMx_TRGO/TIMx_TRGO2 or TIM16_OC1.
The input (on DFSDM1) is on signal DFSDM1_INTRG[0:8].
The connection between timers, EXTI and DFSDM1 is provided in Table 186: DFSDM
triggers connection.

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.6 From DFSDM1 to timer (TIM1/TIM8/TIM15/TIM16/TIM17)

Purpose
DFSDM1 can generate a timer break on advanced-control timers (TIM1/TIM8) and general-
purpose timers (TIM15/TIM16/TIM17) when a watchdog is activated (minimum or maximum
threshold value crossed by analog signal) or when a short-circuit detection is made.
DFSDM1 watchdog is described in Section 28.4.10: Analog watchdog.
DFSDM1 short-circuit detection is described in Section 28.4.11: Short-circuit detector.
Timer break is described in:
• Section 37.3.16: Using the break function (TIM1/TIM8)
• Section 39.4.13: Using the break function (TIM15/TIM16/TIM17)

Triggering signals
The output (from DFSDM1) is on signals dfsdm1_break[0:3] directly connected to timer and
‘Ored’ with other break input signals of the timer.

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.7 From HSE, LSE, LSI, MSI, MCO, RTC to timer

(TIM2/TIM15/TIM16/TIM17)
Purpose
External clocks (HSE, LSE), internal clocks (LSI, MSI), microcontroller output clock (MCO),
GPIO and RTC wakeup interrupt can be used as input to general-purpose timer
(TIM15/16/17) channel 1.
This allows to calibrate the HSI16/MSI system clocks (with TIM15/TIM16 and LSE) or LSI
(with TIM16 and HSE). This is also used to precisely measure LSI (with TIM16 and HSI16)
or MSI (with TIM17 and HSI16) oscillator frequency.
When Low Speed External (LSE) oscillator is used, no additional hardware connections are
required.
This feature is described in Section 6.2.17: Internal/external clock measurement with
TIM15/TIM16/TIM17.

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External clock LSE can be used as input to general-purpose timers (TIM2) on TIM2_ETR
pin, see Section 38.4.22: TIM2 option register 1 (TIM2_OR1).

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.8 From RTC, COMP1, COMP2 to low-power timer (LPTIM1/LPTIM2)

Purpose
RTC alarm A/B, RTC_TAMP1/2/3 input detection, COMP1/2_OUT can be used as trigger to
start LPTIM counters (LPTIM1/2).

Triggering signals
This trigger feature is described in Section 41.4.7: Trigger multiplexer (and following
sections).
The input selection is described in Table 293: LPTIM1 external trigger connection.

Active power mode

Run, Sleep, Low-power run, Low-power sleep, Stop 0, Stop 1, Stop 2 (LPTIM1 only).

10.3.9 From timer (TIM1/TIM2/TIM3/TIM8/TIM15) to comparators

(COMP1/COMP2)
Purpose
Advanced-control timers (TIM1/TIM8), general-purpose timers (TIM2/TIM3) and general-
purpose timer (TIM15) can be used as blanking window input to COMP1/COMP2
The blanking function is described in Section 26.3.7: Comparator output blanking function.
The blanking sources are given in:
• Section 26.6.1: Comparator 1 control and status register (COMP1_CSR) bits 20:18
BLANKING[2:0]
• Section 26.6.2: Comparator 2 control and status register (COMP2_CSR) bits 20:18
BLANKING[2:0]

Triggering signals
Timer output signal TIMx_Ocx are the inputs to blanking source of COMP1/COMP2.

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.10 From ADC (ADC1) to ADC (ADC2)

Purpose
ADC1 can be used as a “master” to trigger ADC2 “slave” start of conversion.
In dual ADC mode, the converted data of the master and slave ADCs can be read in
parallel.

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A description of dual ADC mode is provided in: Section 21.4.31: Dual ADC modes.

Triggering signals
Internal to the ADCs.

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.11 From USB to timer (TIM2)

Purpose
USB (OTG_FS SOF) can generate a trigger to general-purpose timer (TIM2).
Connection of USB to TIM2 is described in Table 280: TIMx internal trigger connection.

Triggering signals
Internal signal generated by USB FS Start Of Frame.

Active power mode

Run, Sleep.

10.3.12 From internal analog source to ADC and OPAMP

(OPAMP1/OPAM2)
Purpose
Internal temperature sensor (VTS) and VBAT monitoring channel are connected to ADC1
input channels.
Internal reference voltage (VREFINT) is connected to ADC1 input channels.
OPAMP1 and OPAMP2 outputs can be connected to ADC1 input channels through the
GPIO.
DAC1_OUT1 can be connected to OPAMP1_VINP.
DAC1_OUT2 can be connected to OPAMP2_VINP.
This is according:
• Section 21.2: ADC main features
• Section 21.4.11: Channel selection (SQRx, JSQRx)
• Section Figure 90.: ADC1 connectivity
• Table 150: Operational amplifier possible connections

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

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10.3.13 From comparators (COMP1/COMP2) to timers

(TIM1/TIM2/TIM3/TIM8/TIM15/TIM16/TIM17)
Purpose
Comparators (COMP1/COMP2) output values can be connected to timers
(TIM1/TIM2/TIM3/TIM8/TIM15/TIM16/TIM17) input captures or TIMx_ETR signals.
The connection to ETR is described in Section 37.3.4: External trigger input.
Comparators (COMP1/COMP2) output values can also generate break input signals for
timers (TIM1/TIM8) on input pins TIMx_BKIN or TIMx_BKIN2 through GPIO alternate
function selection using open drain connection of IO, see Section 37.3.17: Bidirectional
break inputs.
The possible connections are given in:
• Section 37.4.23: TIM1 option register 1 (TIM1_OR1)
• Section 37.4.24: TIM8 option register 1 (TIM8_OR1)
• Section 38.4.22: TIM2 option register 1 (TIM2_OR1)
• Section 38.4.23: TIM3 option register 1 (TIM3_OR1)
• Section 38.4.26: TIMx register map
• Section 38.4.25: TIM3 option register 2 (TIM3_OR2)
• Section 39.3: TIM16/TIM17 main features

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.14 From system errors to timers (TIM1/TIM8/TIM15/TIM16/TIM17)

Purpose
CSS, CPU hardfault, RAM parity error, FLASH ECC double error detection, PVD can
generate system errors in the form of timer break toward timers
(TIM1/TIM8/TIM15/TIM16/TIM17).
The purpose of the break function is to protect power switches driven by PWM signals
generated by the timers.
List of possible source of break are described in:
• Section 37.3.16: Using the break function (TIM1/TIM8)
• Section 39.4.13: Using the break function (TIM15/TIM16/TIM17)
• Figure 393: TIM15 block diagram
• Figure 394: TIM16/TIM17 block diagram

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

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10.3.15 From timers (TIM16/TIM17) to IRTIM

Purpose
General-purpose timer (TIM16/TIM17) output channel TIMx_OC1 are used to generate the
waveform of infrared signal output.
The functionality is described in Section 43: Infrared interface (IRTIM).

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.16 From ADC (ADC1/ADC2) to DFSDM

Purpose
Up to 2 internal ADC results can be directly connected through a parallel bus to DFSDM
input in order to use DFSDM filtering capabilities.
The feature is described as part of DFSDM peripheral description in Section 28.4.6: Parallel
data inputs - Input from internal ADC
The possible connections are given in:
• Section 28.7.1: DFSDM channel y configuration register (DFSDM_CHyCFGR1)
– Bits 13:12 DATMPX[1:0]: Input data multiplexer for channel y
• Section 28.7.5: DFSDM channel y data input register (DFSDM_CHyDATINR)
– Bits 31:16 INDAT0[15:0]: Input data for channel y or channel y+1
– Bits 15:0 INDAT0[15:0]: Input data for channel y

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

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11 Direct memory access controller (DMA)

11.1 Introduction
The direct memory access (DMA) controller is a bus master and system peripheral.
The DMA is used to perform programmable data transfers between memory-mapped
peripherals and/or memories, upon the control of an off-loaded CPU.
The DMA controller features a single AHB master architecture.
There are two instances of DMA, DMA1 and DMA2.
Each channel is dedicated to managing memory access requests from one or more
peripherals. Each DMA includes an arbiter for handling the priority between DMA requests.

11.2 DMA main features

• Single AHB master
• Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to-
peripheral data transfers
• Access, as source and destination, to on-chip memory-mapped devices such as Flash
memory, SRAM, and AHB and APB peripherals
• All DMA channels independently configurable:
– Each channel is associated either with a DMA request signal coming from a
peripheral, or with a software trigger in memory-to-memory transfers. This
configuration is done by software.
– Priority between the requests is programmable by software (4 levels per channel:
very high, high, medium, low) and by hardware in case of equality (such as
request to channel 1 has priority over request to channel 2).
– Transfer size of source and destination are independent (byte, half-word, word),
emulating packing and unpacking. Source and destination addresses must be
aligned on the data size.
– Support of transfers from/to peripherals to/from memory with circular buffer
management
– Programmable number of data to be transferred: 0 to 216 - 1
• Generation of an interrupt request per channel. Each interrupt request is caused from
any of the three DMA events: transfer complete, half transfer, or transfer error.

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11.3 DMA implementation

11.3.1 DMA1 and DMA2

DMA1 and DMA2 are implemented with the hardware configuration parameters shown in
the table below.

Table 48. DMA1 and DMA2 implementation

Feature DMA1 DMA2

Number of channels 7 7

11.3.2 DMA request mapping

The DMA controller is connected to DMA requests from the AHB/APB peripherals through
the DMAMUX peripheral.
For the mapping of the different requests, refer to the Section 12.3: DMAMUX
implementation.

11.4 DMA functional description

11.4.1 DMA block diagram

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The DMA block diagram is shown in the figure below.

Figure 31. DMA block diagram

DMA1

Ch 1

32-bit AHB bus

Ch 2
AHB master interface

...
Ch 7

dma1_req [1..7] Arbiter

dma1_ack [1..7]

32-bit AHB bus

Interrupt AHB slave interface
interface

dma1_it[1..7]
DMAMUX

DMA2

Ch 1

32-bit AHB bus

Ch 2
AHB master interface
...

Ch 7

dma2_req [1..7], Arbiter

dma2_ack [1..7]
32-bit AHB bus

Interrupt AHB slave interface

interface

dma2_it[1..7]
MSv48190V1

The DMA controller performs direct memory transfer by sharing the AHB system bus with
other system masters. The bus matrix implements round-robin scheduling. DMA requests
may stop the CPU access to the system bus for a number of bus cycles, when CPU and
DMA target the same destination (memory or peripheral).

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According to its configuration through the AHB slave interface, the DMA controller arbitrates
between the DMA channels and their associated received requests. The DMA controller
also schedules the DMA data transfers over the single AHB port master.
The DMA controller generates an interrupt per channel to the interrupt controller.

11.4.2 DMA pins and internal signals

Table 49. DMA internal input/output signals

Signal name Signal type Description

dma_req[x] Input DMA channel x request

dma_ack[x] Output DMA channel x acknowledge
dma_it[x] Output DMA channel x interrupt

11.4.3 DMA transfers

The software configures the DMA controller at channel level, in order to perform a block
transfer, composed of a sequence of AHB bus transfers.
A DMA block transfer may be requested from a peripheral, or triggered by the software in
case of memory-to-memory transfer.
After an event, the following steps of a single DMA transfer occur:
1. The peripheral sends a single DMA request signal to the DMA controller.
2. The DMA controller serves the request, depending on the priority of the channel
associated to this peripheral request.
3. As soon as the DMA controller grants the peripheral, an acknowledge is sent to the
peripheral by the DMA controller.
4. The peripheral releases its request as soon as it gets the acknowledge from the DMA
controller.
5. Once the request is de-asserted by the peripheral, the DMA controller releases the
acknowledge.
The peripheral may order a further single request and initiate another single DMA transfer.
The request/acknowledge protocol is used when a peripheral is either the source or the
destination of the transfer. For example, in case of memory-to-peripheral transfer, the
peripheral initiates the transfer by driving its single request signal to the DMA controller. The
DMA controller reads then a single data in the memory and writes this data to the peripheral.
For a given channel x, a DMA block transfer consists of a repeated sequence of:
• a single DMA transfer, encapsulating two AHB transfers of a single data, over the DMA
AHB bus master:
– a single data read (byte, half-word or word) from the peripheral data register or a
location in the memory, addressed through an internal current peripheral/memory
address register.
The start address used for the first single transfer is the base address of the
peripheral or memory, and is programmed in the DMA_CPARx or DMA_CMARx
register.
– a single data write (byte, half-word or word) to the peripheral data register or a
location in the memory, addressed through an internal current peripheral/memory

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address register.
The start address used for the first transfer is the base address of the peripheral or
memory, and is programmed in the DMA_CPARx or DMA_CMARx register.
• post-decrementing of the programmed DMA_CNDTRx register
This register contains the remaining number of data items to transfer (number of AHB
‘read followed by write’ transfers).
This sequence is repeated until DMA_CNDTRx is null.
Note: The AHB master bus source/destination address must be aligned with the programmed size
of the transferred single data to the source/destination.

11.4.4 DMA arbitration

The DMA arbiter manages the priority between the different channels.
When an active channel x is granted by the arbiter (hardware requested or software
triggered), a single DMA transfer is issued (such as a AHB ‘read followed by write’ transfer
of a single data). Then, the arbiter considers again the set of active channels and selects the
one with the highest priority.
The priorities are managed in two stages:
• software: priority of each channel is configured in the DMA_CCRx register, to one of
the four different levels:
– very high
– high
– medium
– low
• hardware: if two requests have the same software priority level, the channel with the
lowest index gets priority. For example, channel 2 gets priority over channel 4.
When a channel x is programmed for a block transfer in memory-to-memory mode,
re arbitration is considered between each single DMA transfer of this channel x. Whenever
there is another concurrent active requested channel, the DMA arbiter automatically
alternates and grants the other highest-priority requested channel, which may be of lower
priority than the memory-to-memory channel.

11.4.5 DMA channels

Each channel may handle a DMA transfer between a peripheral register located at a fixed
address, and a memory address. The amount of data items to transfer is programmable.
The register that contains the amount of data items to transfer is decremented after each
transfer.
A DMA channel is programmed at block transfer level.

Programmable data sizes

The transfer sizes of a single data (byte, half-word, or word) to the peripheral and memory
are programmable through, respectively, the PSIZE[1:0] and MSIZE[1:0] fields of the
DMA_CCRx register.

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Pointer incrementation
The peripheral and memory pointers may be automatically incremented after each transfer,
depending on the PINC and MINC bits of the DMA_CCRx register.
If the incremented mode is enabled (PINC or MINC set to 1), the address of the next
transfer is the address of the previous one incremented by 1, 2 or 4, depending on the data
size defined in PSIZE[1:0] or MSIZE[1:0]. The first transfer address is the one programmed
in the DMA_CPARx or DMA_CMARx register. During transfers, these registers keep the
initially programmed value. The current transfer addresses (in the current internal
peripheral/memory address register) are not accessible by software.
If the channel x is configured in non-circular mode, no DMA request is served after the last
data transfer (once the number of single data to transfer reaches zero). The DMA channel
must be disabled in order to reload a new number of data items into the DMA_CNDTRx
register.
Note: If the channel x is disabled, the DMA registers are not reset. The DMA channel registers
(DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during
the channel configuration phase.
In circular mode, after the last data transfer, the DMA_CNDTRx register is automatically
reloaded with the initially programmed value. The current internal address registers are
reloaded with the base address values from the DMA_CPARx and DMA_CMARx registers.

Channel configuration procedure

The following sequence is needed to configure a DMA channel x:
1. Set the peripheral register address in the DMA_CPARx register.
The data is moved from/to this address to/from the memory after the peripheral event,
or after the channel is enabled in memory-to-memory mode.
2. Set the memory address in the DMA_CMARx register.
The data is written to/read from the memory after the peripheral event or after the
channel is enabled in memory-to-memory mode.
3. Configure the total number of data to transfer in the DMA_CNDTRx register.
After each data transfer, this value is decremented.
4. Configure the parameters listed below in the DMA_CCRx register:
– the channel priority
– the data transfer direction
– the circular mode
– the peripheral and memory incremented mode
– the peripheral and memory data size
– the interrupt enable at half and/or full transfer and/or transfer error
5. Activate the channel by setting the EN bit in the DMA_CCRx register.
A channel, as soon as enabled, may serve any DMA request from the peripheral connected
to this channel, or may start a memory-to-memory block transfer.
Note: The two last steps of the channel configuration procedure may be merged into a single
access to the DMA_CCRx register, to configure and enable the channel.

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Channel state and disabling a channel

A channel x in active state is an enabled channel (read DMA_CCRx.EN = 1). An active
channel x is a channel that must have been enabled by the software (DMA_CCRx.EN set
to 1) and afterwards with no occurred transfer error (DMA_ISR.TEIFx = 0). In case there is a
transfer error, the channel is automatically disabled by hardware (DMA_CCRx.EN = 0).
The three following use cases may happen:
• Suspend and resume a channel
This corresponds to the two following actions:
– An active channel is disabled by software (writing DMA_CCRx.EN = 0 whereas
DMA_CCRx.EN = 1).
– The software enables the channel again (DMA_CCRx.EN set to 1) without
reconfiguring the other channel registers (such as DMA_CNDTRx, DMA_CPARx
and DMA_CMARx).
This case is not supported by the DMA hardware, that does not guarantee that the
remaining data transfers are performed correctly.
• Stop and abort a channel
If the application does not need any more the channel, this active channel can be
disabled by software. The channel is stopped and aborted but the DMA_CNDTRx
register content may not correctly reflect the remaining data transfers versus the
aborted source and destination buffer/register.
• Abort and restart a channel
This corresponds to the software sequence: disable an active channel, then
reconfigure the channel and enable it again.
This is supported by the hardware if the following conditions are met:
– The application guarantees that, when the software is disabling the channel, a
DMA data transfer is not occurring at the same time over its master port. For
example, the application can first disable the peripheral in DMA mode, in order to
ensure that there is no pending hardware DMA request from this peripheral.
– The software must operate separated write accesses to the same DMA_CCRx
register: First disable the channel. Second reconfigure the channel for a next block
transfer including the DMA_CCRx if a configuration change is needed. There are
read-only DMA_CCRx register fields when DMA_CCRx.EN=1. Finally enable
again the channel.
When a channel transfer error occurs, the EN bit of the DMA_CCRx register is cleared by
hardware. This EN bit can not be set again by software to re-activate the channel x, until the
TEIFx bit of the DMA_ISR register is set.

Circular mode (in memory-to-peripheral/peripheral-to-memory transfers)

The circular mode is available to handle circular buffers and continuous data flows (such as
ADC scan mode). This feature is enabled using the CIRC bit in the DMA_CCRx register.
Note: The circular mode must not be used in memory-to-memory mode. Before enabling a
channel in circular mode (CIRC = 1), the software must clear the MEM2MEM bit of the
DMA_CCRx register. When the circular mode is activated, the amount of data to transfer is

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automatically reloaded with the initial value programmed during the channel configuration
phase, and the DMA requests continue to be served.
In order to stop a circular transfer, the software needs to stop the peripheral from generating
DMA requests (such as quit the ADC scan mode), before disabling the DMA channel.
The software must explicitly program the DMA_CNDTRx value before starting/enabling a
transfer, and after having stopped a circular transfer.

Memory-to-memory mode
The DMA channels may operate without being triggered by a request from a peripheral. This
mode is called memory-to-memory mode, and is initiated by software.
If the MEM2MEM bit in the DMA_CCRx register is set, the channel, if enabled, initiates
transfers. The transfer stops once the DMA_CNDTRx register reaches zero.
Note: The memory-to-memory mode must not be used in circular mode. Before enabling a
channel in memory-to-memory mode (MEM2MEM = 1), the software must clear the CIRC
bit of the DMA_CCRx register.

Peripheral-to-peripheral mode
Any DMA channel can operate in peripheral-to-peripheral mode:
• when the hardware request from a peripheral is selected to trigger the DMA channel
This peripheral is the DMA initiator and paces the data transfer from/to this peripheral
to/from a register belonging to another memory-mapped peripheral (this one being not
configured in DMA mode).
• when no peripheral request is selected and connected to the DMA channel
The software configures a register-to-register transfer by setting the MEM2MEM bit of
the DMA_CCRx register.

Programming transfer direction, assigning source/destination

The value of the DIR bit of the DMA_CCRx register sets the direction of the transfer, and
consequently, it identifies the source and the destination, regardless the source/destination
type (peripheral or memory):
• DIR = 1 defines typically a memory-to-peripheral transfer. More generally, if DIR = 1:
– The source attributes are defined by the DMA_MARx register, the MSIZE[1:0]
field and MINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘memory’ register, field and bit are used to
define the source peripheral in peripheral-to-peripheral mode.
– The destination attributes are defined by the DMA_PARx register, the PSIZE[1:0]
field and PINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘peripheral’ register, field and bit are used
to define the destination memory in memory-to-memory mode.
• DIR = 0 defines typically a peripheral-to-memory transfer. More generally, if DIR = 0:
– The source attributes are defined by the DMA_PARx register, the PSIZE[1:0] field
and PINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘peripheral’ register, field and bit are used
to define the source memory in memory-to-memory mode
– The destination attributes are defined by the DMA_MARx register, the
MSIZE[1:0] field and MINC bit of the DMA_CCRx register.

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Regardless of their usual naming, these ‘memory’ register, field and bit are used to
define the destination peripheral in peripheral-to-peripheral mode.

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11.4.6 DMA data width, alignment and endianness

When PSIZE[1:0] and MSIZE[1:0] are not equal, the DMA controller performs some data
alignments as described in the table below.

Table 50. Programmable data width and endian behavior (when PINC = MINC = 1)
Source Destinat
port ion port Destination
Number Source content:
width width content:
of data address / data
(MSIZE (PSIZE address / data
items to (DMA_CMARx if DMA transfers
if if (DMA_CPARx if
transfer DIR = 1, else
DIR = 1, DIR = 1, DIR = 1, else
(NDT) DMA_CPARx)
else else DMA_CMARx)
PSIZE) MSIZE)

@0x0 / B0 1: read B0[7:0] @0x0 then write B0[7:0] @0x0 @0x0 / B0

@0x1 / B1 2: read B1[7:0] @0x1 then write B1[7:0] @0x1 @0x1 / B1
8 8 4
@0x2 / B2 3: read B2[7:0] @0x2 then write B2[7:0] @0x2 @0x2 / B2
@0x3 / B3 4: read B3[7:0] @0x3 then write B3[7:0] @0x3 @0x3 / B3

@0x0 / B0 1: read B0[7:0] @0x0 then write 00B0[15:0] @0x0 @0x0 / 00B0
@0x1 / B1 2: read B1[7:0] @0x1 then write 00B1[15:0] @0x2 @0x2 / 00B1
8 16 4
@0x2 / B2 3: read B2[7:0] @0x2 then write 00B2[15:0] @0x4 @0x4 / 00B2
@0x3 / B3 4: read B3[7:0] @0x3 then write 00B3[15:0] @0x6 @0x6 / 00B3

@0x0 / B0 1: read B0[7:0] @0x0 then write 000000B0[31:0] @0x0 @0x0 / 000000B0
@0x1 / B1 2: read B1[7:0] @0x1 then write 000000B1[31:0] @0x4 @0x4 / 000000B1
8 32 4
@0x2 / B2 3: read B2[7:0] @0x2 then write 000000B2[31:0] @0x8 @0x8 / 000000B2
@0x3 / B3 4: read B3[7:0] @0x3 then write 000000B3[31:0] @0xC @0xC / 000000B3

@0x0 / B1B0 1: read B1B0[15:0] @0x0 then write B0[7:0] @0x0 @0x0 / B0
@0x2 / B3B2 2: read B3B2[15:0] @0x2 then write B2[7:0] @0x1 @0x1 / B2
16 8 4
@0x4 / B5B4 3: read B5B4[15:0] @0x4 then write B4[7:0] @0x2 @0x2 / B4
@0x6 / B7B6 4: read B7B6[15:0] @0x6 then write B6[7:0] @0x3 @0x3 / B6

@0x0 / B1B0 1: read B1B0[15:0] @0x0 then write B1B0[15:0] @0x0 @0x0 / B1B0
@0x2 / B3B2 2: read B3B2[15:0] @0x2 then write B3B2[15:0] @0x2 @0x2 / B3B2
16 16 4
@0x4 / B5B4 3: read B5B4[15:0] @0x4 then write B5B4[15:0] @0x4 @0x4 / B5B4
@0x6 / B7B6 4: read B7B6[15:0] @0x6 then write B7B6[15:0] @0x6 @0x6 / B7B6

@0x0 / B1B0 1: read B1B0[15:0] @0x0 then write 0000B1B0[31:0] @0x0 @0x0 / 0000B1B0
@0x2 / B3B2 2: read B3B2[15:0] @0x2 then write 0000B3B2[31:0] @0x4 @0x4 / 0000B3B2
16 32 4
@0x4 / B5B4 3: read B5B4[15:0] @0x4 then write 0000B5B4[31:0] @0x8 @0x8 / 0000B5B4
@0x6 / B7B6 4: read B7B6[15:0] @0x6 then write 0000B7B6[31:0] @0xC @0xC / 0000B7B6

@0x0 / B3B2B1B0 1: read B3B2B1B0[31:0] @0x0 then write B0[7:0] @0x0 @0x0 / B0
@0x4 / B7B6B5B4 2: read B7B6B5B4[31:0] @0x4 then write B4[7:0] @0x1 @0x1 / B4
32 8 4
@0x8 / BBBAB9B8 3: read BBBAB9B8[31:0] @0x8 then write B8[7:0] @0x2 @0x2 / B8
@0xC / BFBEBDBC 4: read BFBEBDBC[31:0] @0xC then write BC[7:0] @0x3 @0x3 / BC

@0x0 / B3B2B1B0 1: read B3B2B1B0[31:0] @0x0 then write B1B0[15:0] @0x0 @0x0 / B1B0
@0x4 / B7B6B5B4 2: read B7B6B5B4[31:0] @0x4 then write B5B4[15:0] @0x2 @0x2 / B5B4
32 16 4
@0x8 / BBBAB9B8 3: read BBBAB9B8[31:0] @0x8 then write B9B8[15:0] @0x4 @0x4 / B9B8
@0xC / BFBEBDBC 4: read BFBEBDBC[31:0] @0xC then write BDBC[15:0] @0x6 @0x6 / BDBC

@0x0 / B3B2B1B0 1: read B3B2B1B0[31:0] @0x0 then write B3B2B1B0[31:0] @0x0 @0x0 / B3B2B1B0
@0x4 / B7B6B5B4 2: read B7B6B5B4[31:0] @0x4 then write B7B6B5B4[31:0] @0x4 @0x4 / B7B6B5B4
32 32 4
@0x8 / BBBAB9B8 3: read BBBAB9B8[31:0] @0x8 then write BBBAB9B8[31:0] @0x8 @0x8 / BBBAB9B8
@0xC / BFBEBDBC 4: read BFBEBDBC[31:0] @0xC then write BFBEBDBC[31:0] @0xC @0xC / BFBEBDBC

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Addressing AHB peripherals not supporting byte/half-word write transfers

When the DMA controller initiates an AHB byte or half-word write transfer, the data are
duplicated on the unused lanes of the AHB master 32-bit data bus (HWDATA[31:0]).
When the AHB slave peripheral does not support byte or half-word write transfers and does
not generate any error, the DMA controller writes the 32 HWDATA bits as shown in the two
examples below:
• To write the half-word 0xABCD, the DMA controller sets the HWDATA bus to
0xABCDABCD with a half-word data size (HSIZE = HalfWord in AHB master bus).
• To write the byte 0xAB, the DMA controller sets the HWDATA bus to 0xABABABAB
with a byte data size (HSIZE = Byte in the AHB master bus).
Assuming the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take into
account the HSIZE data, any AHB byte or half-word transfer is changed into a 32-bit APB
transfer as described below:
• An AHB byte write transfer of 0xB0 to one of the 0x0, 0x1, 0x2 or 0x3 addresses, is
converted to an APB word write transfer of 0xB0B0B0B0 to the 0x0 address.
• An AHB half-word write transfer of 0xB1B0 to the 0x0 or 0x2 addresses, is converted to
an APB word write transfer of 0xB1B0B1B0 to the 0x0 address.

11.4.7 DMA error management

A DMA transfer error is generated when reading from or writing to a reserved address
space. When a DMA transfer error occurs during a DMA read or write access, the faulty
channel x is automatically disabled through a hardware clear of its EN bit in the
corresponding DMA_CCRx register.
The TEIFx bit of the DMA_ISR register is set. An interrupt is then generated if the TEIE bit of
the DMA_CCRx register is set.
The EN bit of the DMA_CCRx register can not be set again by software (channel x re-
activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of
the DMA_IFCR register).
When the software is notified with a transfer error over a channel which involves a
peripheral, the software has first to stop this peripheral in DMA mode, in order to disable any
pending or future DMA request. Then software may normally reconfigure both DMA and the
peripheral in DMA mode for a new transfer.

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11.5 DMA interrupts

An interrupt can be generated on a half transfer, transfer complete or transfer error for each
DMA channel x. Separate interrupt enable bits are available for flexibility.

Table 51. DMA interrupt requests

Interrupt
Interrupt request Interrupt event Event flag
enable bit

Half transfer on channel x HTIFx HTIEx

Transfer complete on channel x TCIFx TCIEx
Channel x interrupt
Transfer error on channel x TEIFx TEIEx
Half transfer or transfer complete or transfer error on channel x GIFx -

11.6 DMA registers

Refer to Section 1.2 for a list of abbreviations used in register descriptions.
The DMA registers have to be accessed by words (32-bit).

11.6.1 DMA interrupt status register (DMA_ISR)

Address offset: 0x00
Reset value: 0x0000 0000
Every status bit is cleared by hardware when the software sets the corresponding clear bit
or the corresponding global clear bit CGIFx, in the DMA_IFCR register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. TEIF7 HTIF7 TCIF7 GIF7 TEIF6 HTIF6 TCIF6 GIF6 TEIF5 HTIF5 TCIF5 GIF5
r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF4 HTIF4 TCIF4 GIF4 TEIF3 HTIF3 TCIF3 GIF3 TEIF2 HTIF2 TCIF2 GIF2 TEIF1 HTIF1 TCIF1 GIF1
r r r r r r r r r r r r r r r r

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 TEIF7: transfer error (TE) flag for channel 7
0: no TE event
1: a TE event occurred
Bit 26 HTIF7: half transfer (HT) flag for channel 7
0: no HT event
1: a HT event occurred
Bit 25 TCIF7: transfer complete (TC) flag for channel 7
0: no TC event
1: a TC event occurred
Bit 24 GIF7: global interrupt flag for channel 7
0: no TE, HT or TC event
1: a TE, HT or TC event occurred

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Bit 23 TEIF6: transfer error (TE) flag for channel 6

0: no TE event
1: a TE event occurred
Bit 22 HTIF6: half transfer (HT) flag for channel 6
0: no HT event
1: a HT event occurred
Bit 21 TCIF6: transfer complete (TC) flag for channel 6
0: no TC event
1: a TC event occurred
Bit 20 GIF6: global interrupt flag for channel 6
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 19 TEIF5: transfer error (TE) flag for channel 5
0: no TE event
1: a TE event occurred
Bit 18 HTIF5: half transfer (HT) flag for channel 5
0: no HT event
1: a HT event occurred
Bit 17 TCIF5: transfer complete (TC) flag for channel 5
0: no TC event
1: a TC event occurred
Bit 16 GIF5: global interrupt flag for channel 5
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 15 TEIF4: transfer error (TE) flag for channel 4
0: no TE event
1: a TE event occurred
Bit 14 HTIF4: half transfer (HT) flag for channel 4
0: no HT event
1: a HT event occurred
Bit 13 TCIF4: transfer complete (TC) flag for channel 4
0: no TC event
1: a TC event occurred
Bit 12 GIF4: global interrupt flag for channel 4
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 11 TEIF3: transfer error (TE) flag for channel 3
0: no TE event
1: a TE event occurred
Bit 10 HTIF3: half transfer (HT) flag for channel 3
0: no HT event
1: a HT event occurred
Bit 9 TCIF3: transfer complete (TC) flag for channel 3
0: no TC event
1: a TC event occurred

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Bit 8 GIF3: global interrupt flag for channel 3

0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 7 TEIF2: transfer error (TE) flag for channel 2
0: no TE event
1: a TE event occurred
Bit 6 HTIF2: half transfer (HT) flag for channel 2
0: no HT event
1: a HT event occurred
Bit 5 TCIF2: transfer complete (TC) flag for channel 2
0: no TC event
1: a TC event occurred
Bit 4 GIF2: global interrupt flag for channel 2
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 3 TEIF1: transfer error (TE) flag for channel 1
0: no TE event
1: a TE event occurred
Bit 2 HTIF1: half transfer (HT) flag for channel 1
0: no HT event
1: a HT event occurred
Bit 1 TCIF1: transfer complete (TC) flag for channel 1
0: no TC event
1: a TC event occurred
Bit 0 GIF1: global interrupt flag for channel 1
0: no TE, HT or TC event
1: a TE, HT or TC event occurred

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11.6.2 DMA interrupt flag clear register (DMA_IFCR)

Address offset: 0x04
Reset value: 0x0000 0000
Setting the global clear bit CGIFx of the channel x in this DMA_IFCR register, causes the
DMA hardware to clear the corresponding GIFx bit and any individual flag among TEIFx,
HTIFx, TCIFx, in the DMA_ISR register.
Setting any individual clear bit among CTEIFx, CHTIFx, CTCIFx in this DMA_IFCR register,
causes the DMA hardware to clear the corresponding individual flag and the global flag
GIFx in the DMA_ISR register, provided that none of the two other individual flags is set.
Writing 0 into any flag clear bit has no effect.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHTIF7

CTCIF7

CHTIF6

CTCIF6

CHTIF5

CTCIF5
CTEIF7

CTEIF6

CTEIF5
CGIF7

CGIF6

CGIF5
Res. Res. Res. Res.

w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHTIF4

CTCIF4

CHTIF3

CTCIF3

CHTIF2

CTCIF2

CHTIF1

CTCIF1
CTEIF4

CTEIF3

CTEIF2

CTEIF1
CGIF4

CGIF3

CGIF2

CGIF1
w w w w w w w w w w w w w w w w

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 CTEIF7: transfer error flag clear for channel 7
Bit 26 CHTIF7: half transfer flag clear for channel 7
Bit 25 CTCIF7: transfer complete flag clear for channel 7
Bit 24 CGIF7: global interrupt flag clear for channel 7
Bit 23 CTEIF6: transfer error flag clear for channel 6
Bit 22 CHTIF6: half transfer flag clear for channel 6
Bit 21 CTCIF6: transfer complete flag clear for channel 6
Bit 20 CGIF6: global interrupt flag clear for channel 6
Bit 19 CTEIF5: transfer error flag clear for channel 5
Bit 18 CHTIF5: half transfer flag clear for channel 5
Bit 17 CTCIF5: transfer complete flag clear for channel 5
Bit 16 CGIF5: global interrupt flag clear for channel 5
Bit 15 CTEIF4: transfer error flag clear for channel 4
Bit 14 CHTIF4: half transfer flag clear for channel 4
Bit 13 CTCIF4: transfer complete flag clear for channel 4
Bit 12 CGIF4: global interrupt flag clear for channel 4
Bit 11 CTEIF3: transfer error flag clear for channel 3
Bit 10 CHTIF3: half transfer flag clear for channel 3
Bit 9 CTCIF3: transfer complete flag clear for channel 3

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Bit 8 CGIF3: global interrupt flag clear for channel 3

Bit 7 CTEIF2: transfer error flag clear for channel 2
Bit 6 CHTIF2: half transfer flag clear for channel 2
Bit 5 CTCIF2: transfer complete flag clear for channel 2
Bit 4 CGIF2: global interrupt flag clear for channel 2
Bit 3 CTEIF1: transfer error flag clear for channel 1
Bit 2 CHTIF1: half transfer flag clear for channel 1
Bit 1 CTCIF1: transfer complete flag clear for channel 1
Bit 0 CGIF1: global interrupt flag clear for channel 1

11.6.3 DMA channel x configuration register (DMA_CCRx)

Address offset: 0x08 + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000
The register fields/bits MEM2MEM, PL[1:0], MSIZE[1:0], PSIZE[1:0], MINC, PINC, and DIR
are read-only when EN = 1.
The states of MEM2MEM and CIRC bits must not be both high at the same time.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2
Res. PL[1:0] MSIZE[1:0] PSIZE[1:0] MINC PINC CIRC DIR TEIE HTIE TCIE EN
MEM
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 MEM2MEM: memory-to-memory mode
0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bits 13:12 PL[1:0]: priority level
00: low
01: medium
10: high
11: very high
Note: this field is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).

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Bits 11:10 MSIZE[1:0]: memory size

Defines the data size of each DMA transfer to the identified memory.
In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the
memory destination if DIR = 0.
In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the
peripheral destination if DIR = 0.
00: 8 bits
01: 16 bits
10: 32 bits
11: reserved
Note: this field is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bits 9:8 PSIZE[1:0]: peripheral size
Defines the data size of each DMA transfer to the identified peripheral.
In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the
memory source if DIR = 0.
In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and
the peripheral source if DIR = 0.
00: 8 bits
01: 16 bits
10: 32 bits
11: reserved
Note: this field is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 7 MINC: memory increment mode
Defines the increment mode for each DMA transfer to the identified memory.
In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the
memory destination if DIR = 0.
In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the
peripheral destination if DIR = 0.
0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 6 PINC: peripheral increment mode
Defines the increment mode for each DMA transfer to the identified peripheral.
n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the
memory source if DIR = 0.
In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and
the peripheral source if DIR = 0.
0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).

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Bit 5 CIRC: circular mode

0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).
Bit 4 DIR: data transfer direction
This bit must be set only in memory-to-peripheral and peripheral-to-memory modes.
0: read from peripheral
– Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register.
This is still valid in a memory-to-memory mode.
– Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx
register. This is still valid in a peripheral-to-peripheral mode.
1: read from memory
– Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx
register. This is still valid in a memory-to-memory mode.
– Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register.
This is still valid in a peripheral-to-peripheral mode.
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 3 TEIE: transfer error interrupt enable
0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).
Bit 2 HTIE: half transfer interrupt enable
0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).
Bit 1 TCIE: transfer complete interrupt enable
0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).
Bit 0 EN: channel enable
When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again
by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by
setting the CTEIFx bit of the DMA_IFCR register).
0: disabled
1: enabled
Note: this bit is set and cleared by software.

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RM0432 Direct memory access controller (DMA)

11.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx)

Address offset: 0x0C + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 NDT[15:0]: number of data to transfer (0 to 216 - 1)
This field is updated by hardware when the channel is enabled:
– It is decremented after each single DMA ‘read followed by write’ transfer, indicating
the remaining amount of data items to transfer.
– It is kept at zero when the programmed amount of data to transfer is reached, if the
channel is not in circular mode (CIRC = 0 in the DMA_CCRx register).
– It is reloaded automatically by the previously programmed value, when the transfer
is complete, if the channel is in circular mode (CIRC = 1).
If this field is zero, no transfer can be served whatever the channel status (enabled or not).
Note: this field is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).

11.6.5 DMA channel x peripheral address register (DMA_CPARx)

Address offset: 0x10 + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RM0432 Rev 6 393/2301

396
Direct memory access controller (DMA) RM0432

Bits 31:0 PA[31:0]: peripheral address

It contains the base address of the peripheral data register from/to which the data will be
read/written.
When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned
to a half-word address.
When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically
aligned to a word address.
In memory-to-memory mode, this register identifies the memory destination address if
DIR = 1 and the memory source address if DIR = 0.
In peripheral-to-peripheral mode, this register identifies the peripheral destination address
DIR = 1 and the peripheral source address if DIR = 0.
Note: this register is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).

11.6.6 DMA channel x memory address register (DMA_CMARx)

Address offset: 0x14 + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MA[31:0]: peripheral address

It contains the base address of the memory from/to which the data will be read/written.
When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned
to a half-word address.
When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically
aligned to a word address.
In memory-to-memory mode, this register identifies the memory source address if DIR = 1
and the memory destination address if DIR = 0.
In peripheral-to-peripheral mode, this register identifies the peripheral source address
DIR = 1 and the peripheral destination address if DIR = 0.
Note: this register is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).

11.6.7 DMA register map

The table below gives the DMA register map and reset values.

Table 52. DMA register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
HTIF7
TCIF7

HTIF6
TCIF6

HTIF5
TCIF5

HTIF4
TCIF4

HTIF3
TCIF3

HTIF2
TCIF2

HTIF1
TCIF1
TEIF7

TEIF6

TEIF5

TEIF4

TEIF3

TEIF2

TEIF1
GIF7

GIF6

GIF5

GIF4

GIF3

GIF2

GIF1
Res.
Res.
Res.
Res.

DMA_ISR
0x000
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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RM0432 Direct memory access controller (DMA)

Table 52. DMA register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
CTCIF7

CTCIF6

CTCIF5

CTCIF4

CTCIF3

CTCIF2

CTCIF1
CHTIF7

CHTIF6

CHTIF5

CHTIF4

CHTIF3

CHTIF2

CHTIF1
CTEIF7

CTEIF6

CTEIF5

CTEIF4

CTEIF3

CTEIF2

CTEIF1
CGIF7

CGIF6

CGIF5

CGIF4

CGIF3

CGIF2

CGIF1
Res.
Res.
Res.
Res.
DMA_IFCR
0x004
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
DMA_CCR1
0x008

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CNDTR1 NDTR[15:0]
0x00C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR1 PA[31:0]
0x010
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR1 MA[31:0]
0x014
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x018 Reserved Reserved.

MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
DMA_CCR2
0x01C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA_CNDTR2 NDTR[15:0]
0x020
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR2 PA[31:0]
0x024
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR2 MA[31:0]
0x028
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x02C Reserved Reserved.
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
DMA_CCR3
0x030

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA_CNDTR3 NDTR[15:0]
0x034
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR3 PA[31:0]
0x038
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR3 MA[31:0]
0x03C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x040 Reserved Reserved.
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN

DMA_CCR4
0x044

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA_CNDTR4 NDTR[15:0]
0x048
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR4 PA[31:0]
0x04C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR4 MA[31:0]
0x050
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x054 Reserved Reserved.

RM0432 Rev 6 395/2301

396
Direct memory access controller (DMA) RM0432

Table 52. DMA register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
DMA_CCR5
0x058

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CNDTR5 NDTR[15:0]
0x05C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR5 PA[31:0]
0x060
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR5 MA[31:0]
0x064
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x068 Reserved Reserved.

MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
DMA_CCR6
0x06C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CNDTR6 NDTR[15:0]
0x070
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR6 PA[31:0]
0x074
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR6 MA[31:0]
0x078
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x07C Reserved Reserved.
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
DMA_CCR7
0x080

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA_CNDTR7 NDTR[15:0]
0x084
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR7 PA[31:0]
0x088
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR7 MA[31:0]
0x08C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 for the register boundary addresses.

396/2301 RM0432 Rev 6

RM0432 DMA request multiplexer (DMAMUX)

12 DMA request multiplexer (DMAMUX)

12.1 Introduction
A peripheral indicates a request for DMA transfer by setting its DMA request signal. The
DMA request is pending until it is served by the DMA controller that generates a DMA
acknowledge signal, and the corresponding DMA request signal is deasserted.
In this document, the set of control signals required for the DMA request/acknowledge
protocol is not explicitly shown or described, and it is referred to as DMA request line.
The DMAMUX request multiplexer enables routing a DMA request line between the
peripherals and the DMA controllers of the product. The routing function is ensured by a
programmable multi-channel DMA request line multiplexer. Each channel selects a unique
DMA request line, unconditionally or synchronously with events from its DMAMUX
synchronization inputs. The DMAMUX may also be used as a DMA request generator from
programmable events on its input trigger signals.
The number of DMAMUX instances and their main characteristics are specified in
Section 12.3.1.
The assignment of DMAMUX request multiplexer inputs to the DMA request lines from
peripherals and to the DMAMUX request generator outputs, the assignment of DMAMUX
request multiplexer outputs to DMA controller channels, and the assignment of DMAMUX
synchronizations and trigger inputs to internal and external signals depend on the product
implementation, and are detailed inSection 12.3.2.

RM0432 Rev 6 397/2301

415
DMA request multiplexer (DMAMUX) RM0432

12.2 DMAMUX main features

• 14-channel programmable DMA request line multiplexer output
• 4-channel DMA request generator
• 26 trigger inputs to DMA request generator
• 26 synchronization inputs
• Per DMA request generator channel:
– DMA request trigger input selector
– DMA request counter
– Event overrun flag for selected DMA request trigger input
• Per DMA request line multiplexer channel output:
– 89 (STM32L4Rxxx and STM32L4Sxxx devices) or 90 (STM32L4P5xx and
STM32L4Q5xx devices) input DMA request lines from peripherals
– One DMA request line output
– Synchronization input selector
– DMA request counter
– Event overrun flag for selected synchronization input
– One event output, for DMA request chaining

12.3 DMAMUX implementation

12.3.1 DMAMUX instantiation

DMAMUX is instantiated with the hardware configuration parameters listed in the following
table.

Table 53. DMAMUX instantiation

Feature DMAMUX

Number of DMAMUX output request channels 14

Number of DMAMUX request generator channels 4
Number of DMAMUX request trigger inputs 26
Number of DMAMUX synchronization inputs 26
89 (STM32L4Rxxx and
STM32L4Sxxx devices)
Number of DMAMUX peripheral request inputs
90 (STM32L4P5xx and
STM32L4Q5xx devices)

12.3.2 DMAMUX mapping

The mapping of resources to DMAMUX is hardwired.

DMAMUX is used with DMA1 and DMA2:

• DMAMUX channels 0 to 6 are connected to DMA1 channels 0 to 6
• DMAMUX channels 7 to 13 are connected to DMA2 channels 0 to 6

398/2301 RM0432 Rev 6

RM0432 DMA request multiplexer (DMAMUX)

Table 54. DMAMUX: assignment of multiplexer inputs to resources

(STM32L4Rxxx and STM32L4Sxxx devices)
DMA DMA DMA
request Resource request Resource request Resource
MUX input MUX input MUX input

1 dmamux_req_gen0 44 TIM1_CH3 87 DFSDM1_FLT1

2 dmamux_req_gen1 45 TIM1_CH4 88 DFSDM1_FLT2
3 dmamux_req_gen2 46 TIM1_UP 89 DFSDM1_FLT3
4 dmamux_req_gen3 47 TIM1_TRIG 90 DCMI
5 ADC1 48 TIM1_COM 91 AES_IN
6 DAC1 49 TIM8_CH1 92 AES_OUT
7 DAC2 50 TIM8_CH2 93 HASH_IN
8 TIM6_UP 51 TIM8_CH3 94 Reserved
9 TIM7_UP 52 TIM8_CH4 95 Reserved
10 SPI1_RX 53 TIM8_UP 96 Reserved
11 SPI1_TX 54 TIM8_TRIG 97 Reserved
12 SPI2_RX 55 TIM8_COM 98 Reserved
13 SPI2_TX 56 TIM2_CH1 99 Reserved
14 SPI3_RX 57 TIM2_CH2 100 Reserved
15 SPI3_TX 58 TIM2_CH3 101 Reserved
16 I2C1_RX 59 TIM2_CH4 102 Reserved
17 I2C1_TX 60 TIM2_UP 103 Reserved
18 I2C2_RX 61 TIM3_CH1 104 Reserved
19 I2C2_TX 62 TIM3_CH2 105 Reserved
20 I2C3_RX 63 TIM3_CH3 106 Reserved
21 I2C3_TX 64 TIM3_CH4 107 Reserved
22 I2C4_RX 65 TIM3_UP 108 Reserved
23 I2C4_TX 66 TIM3_TRIG 109 Reserved
24 USART1_RX 67 TIM4_CH1 110 Reserved
25 USART1_TX 68 TIM4_CH2 111 Reserved
26 USART2_RX 69 TIM4_CH3 112 Reserved
27 USART2_TX 70 TIM4_CH4 113 Reserved
28 USART3_RX 71 TIM4_UP 114 Reserved
29 USART3_TX 72 TIM5_CH1 115 Reserved
30 UART4_RX 73 TIM5_CH2 116 Reserved
31 UART4_TX 74 TIM5_CH3 117 Reserved
32 UART5_RX 75 TIM5_CH4 118 Reserved
33 UART5_TX 76 TIM5_UP 119 Reserved
34 LPUART1_RX 77 TIM5_TRIG 120 Reserved
35 LPUART1_TX 78 TIM15_CH1 121 Reserved
36 SAI1_A 79 TIM15_UP 122 Reserved

RM0432 Rev 6 399/2301

415
DMA request multiplexer (DMAMUX) RM0432

Table 54. DMAMUX: assignment of multiplexer inputs to resources

(STM32L4Rxxx and STM32L4Sxxx devices) (continued)
DMA DMA DMA
request Resource request Resource request Resource
MUX input MUX input MUX input

37 SAI1_B 80 TIM15_TRIG 123 Reserved

38 SAI2_A 81 TIM15_COM 124 Reserved
39 SAI2_B 82 TIM16_CH1 125 Reserved
40 OCTOSPI1 83 TIM16_UP 126 Reserved
41 OCTOSPI2 84 TIM17_CH1 127 Reserved
42 TIM1_CH1 85 TIM17_UP - -
43 TIM1_CH2 86 DFSDM1_FLT0 - -

Table 55. DMAMUX: assignment of multiplexer inputs to resources

(STM32L4P5xx and STM32L4Q5xx devices)
DMA DMA DMA
request Resource request Resource request Resource
MUX input MUX input MUX input

1 dmamux_req_gen0 44 TIM1_CH2 87 DFSDM1_FLT0

2 dmamux_req_gen1 45 TIM1_CH3 88 DFSDM1_FLT1
3 dmamux_req_gen2 46 TIM1_CH4 89 Reserved
4 dmamux_req_gen3 47 TIM1_UP 90 Reserved
5 ADC1 48 TIM1_TRIG 91 DCMI_PSSI
6 ADC2 49 TIM1_COM 92 AES_IN
7 DAC1 50 TIM8_CH1 93 AES_OUT
8 DAC2 51 TIM8_CH2 94 HASH_IN
9 TIM6_UP 52 TIM8_CH3 95 Reserved
10 TIM7_UP 53 TIM8_CH4 96 Reserved
11 SPI1_RX 54 TIM8_UP 97 Reserved
12 SPI1_TX 55 TIM8_TRIG 98 Reserved
13 SPI2_RX 56 TIM8_COM 99 Reserved
14 SPI2_TX 57 TIM2_CH1 100 Reserved
15 SPI3_RX 58 TIM2_CH2 101 Reserved
16 SPI3_TX 59 TIM2_CH3 102 Reserved
17 I2C1_RX 60 TIM2_CH4 103 Reserved
18 I2C1_TX 61 TIM2_UP 104 Reserved
19 I2C2_RX 62 TIM3_CH1 105 Reserved
20 I2C2_TX 63 TIM3_CH2 106 Reserved
21 I2C3_RX 64 TIM3_CH3 107 Reserved
22 I2C3_TX 65 TIM3_CH4 108 Reserved
23 I2C4_RX 66 TIM3_UP 109 Reserved

400/2301 RM0432 Rev 6

RM0432 DMA request multiplexer (DMAMUX)

Table 55. DMAMUX: assignment of multiplexer inputs to resources

(STM32L4P5xx and STM32L4Q5xx devices) (continued)
DMA DMA DMA
request Resource request Resource request Resource
MUX input MUX input MUX input

24 I2C4_TX 67 TIM3_TRIG 110 Reserved

25 USART1_RX 68 TIM4_CH1 111 Reserved
26 USART1_TX 69 TIM4_CH2 112 Reserved
27 USART2_RX 70 TIM4_CH3 113 Reserved
28 USART2_TX 71 TIM4_CH4 114 Reserved
29 USART3_RX 72 TIM4_UP 115 Reserved
30 USART3_TX 73 TIM5_CH1 116 Reserved
31 UART4_RX 74 TIM5_CH2 117 Reserved
32 UART4_TX 75 TIM5_CH3 118 Reserved
33 UART5_RX 76 TIM5_CH4 119 Reserved
34 UART5_TX 77 TIM5_UP 120 Reserved
35 LPUART1_RX 78 TIM5_TRIG 121 Reserved
36 LPUART1_TX 79 TIM15_CH1 122 Reserved
37 SAI1_A 80 TIM15_UP 123 Reserved
38 SAI1_B 81 TIM15_TRIG 124 Reserved
39 SAI2_A 82 TIM15_COM 125 Reserved
40 SAI2_B 83 TIM16_CH1 126 Reserved
41 OCTOSPI1 84 TIM16_UP 127 Reserved
42 OCTOSPI2 85 TIM17_CH1 - -
43 TIM1_CH1 86 TIM17_UP - -

Table 56. DMAMUX: assignment of trigger inputs to resources

(STM32L4Rxxx and STM32L4Sxxx devices)
Trigger input Resource Trigger input Resource

0 EXTI LINE0 16 dmamux_evt0

1 EXTI LINE1 17 dmamux_evt1
2 EXTI LINE2 18 dmamux_evt2
3 EXTI LINE3 19 dmamux_evt3
4 EXTI LINE4 20 LPTIM1_OUT
5 EXTI LINE5 21 LPTIM2_OUT
6 EXTI LINE6 22 DSI Tearing Effect
7 EXTI LINE7 23 DSI End of refresh
8 EXTI LINE8 24 DMA2D End of Transfer
9 EXTI LINE9 25 LTDC Line interrupt
10 EXTI LINE10 26 Reserved

RM0432 Rev 6 401/2301

415
DMA request multiplexer (DMAMUX) RM0432

Table 56. DMAMUX: assignment of trigger inputs to resources

(STM32L4Rxxx and STM32L4Sxxx devices) (continued)
Trigger input Resource Trigger input Resource

11 EXTI LINE11 27 Reserved

12 EXTI LINE12 28 Reserved
13 EXTI LINE13 29 Reserved
14 EXTI LINE14 30 Reserved
15 EXTI LINE15 31 Reserved

Table 57. DMAMUX: assignment of trigger inputs to resources

(STM32L4P5xx and STM32L4Q5xx devices)
Trigger input Resource Trigger input Resource

0 EXTI LINE0 16 dmamux_evt0

1 EXTI LINE1 17 dmamux_evt1
2 EXTI LINE2 18 dmamux_evt2
3 EXTI LINE3 19 dmamux_evt3
4 EXTI LINE4 20 LPTIM1_OUT
5 EXTI LINE5 21 LPTIM2_OUT
6 EXTI LINE6 22 Reserved
7 EXTI LINE7 23 Reserved
8 EXTI LINE8 24 DMA2D End of Transfer
9 EXTI LINE9 25 LTDC Line interrupt
10 EXTI LINE10 26 Reserved
11 EXTI LINE11 27 Reserved
12 EXTI LINE12 28 Reserved
13 EXTI LINE13 29 Reserved
14 EXTI LINE14 30 Reserved
15 EXTI LINE15 31 Reserved

Table 58. DMAMUX: assignment of synchronization inputs to resources

(STM32L4Rxxx and STM32L4Sxxx devices)
Sync. input Resource Sync. input Resource

0 EXTI LINE0 16 dmamux_evt0

1 EXTI LINE1 17 dmamux_evt1
2 EXTI LINE2 18 dmamux_evt2
3 EXTI LINE3 19 dmamux_evt3
4 EXTI LINE4 20 LPTIM1_OUT
5 EXTI LINE5 21 LPTIM2_OUT
6 EXTI LINE6 22 DSI Tearing Effect

402/2301 RM0432 Rev 6

RM0432 DMA request multiplexer (DMAMUX)

Table 58. DMAMUX: assignment of synchronization inputs to resources

(STM32L4Rxxx and STM32L4Sxxx devices) (continued)
Sync. input Resource Sync. input Resource

7 EXTI LINE7 23 DSI End of refresh

8 EXTI LINE8 24 DMA2D End of Transfer
9 EXTI LINE9 25 LTDC Line interrupt
10 EXTI LINE10 26 Reserved
11 EXTI LINE11 27 Reserved
12 EXTI LINE12 28 Reserved
13 EXTI LINE13 29 Reserved
14 EXTI LINE14 30 Reserved
15 EXTI LINE15 31 Reserved

Table 59. DMAMUX: assignment of synchronization inputs to resources

(STM32L4P5xx and STM32L4Q5xx devices)
Sync. input Resource Sync. input Resource

0 EXTI LINE0 16 dmamux_evt0

1 EXTI LINE1 17 dmamux_evt1
2 EXTI LINE2 18 dmamux_evt2
3 EXTI LINE3 19 dmamux_evt3
4 EXTI LINE4 20 LPTIM1_OUT
5 EXTI LINE5 21 LPTIM2_OUT
6 EXTI LINE6 22 Reserved
7 EXTI LINE7 23 Reserved
8 EXTI LINE8 24 DMA2D End of Transfer
9 EXTI LINE9 25 LTDC Line interrupt
10 EXTI LINE10 26 Reserved
11 EXTI LINE11 27 Reserved
12 EXTI LINE12 28 Reserved
13 EXTI LINE13 29 Reserved
14 EXTI LINE14 30 Reserved
15 EXTI LINE15 31 Reserved

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DMA request multiplexer (DMAMUX) RM0432

12.4 DMAMUX functional description

12.4.1 DMAMUX block diagram

Figure 32 shows the DMAMUX block diagram.

Figure 32. DMAMUX block diagram

32-bit AHB bus
dmamux_hclk

DMAMUX Request multiplexer

AHB slave
interface Channel m
DMAMUX_CmCR

p Channel 1
Channel 0

x
DMA requests eq
_r
DMAMUX_C0CR
from peripherals: 1
ux
am

dmamux_req_inx Channel Ctrl

0
dm

select
n+p+2 m DMA requests
1 to DMA controllers:
0
Request generator dmamux_req_outx
n+3
Channel n n
Sync
dmamux_req_genx

DMAMUX_RGCnCR n+2 m
DMA channels
1 events:
n+1 0
dmamux_evtx
s 1 0
Channel 1 1 2
DMAMUX_RGC1CR
1
Channel 0 0
DMAMUX_RGC0CR

Interrupt
interface
t 1 0 s 1 0

Control registers Trigger inputs: Interrupt: Synchronization inputs:

dmamux_trgx dmamux_ovr_it dmamux_syncx
MSv39745V1

DMAMUX features two main sub-blocks: the request line multiplexer and the request line
generator.
The implementation assigns:
• DMAMUX request multiplexer sub-block inputs (dmamux_reqx) from peripherals
(dmamux_req_inx) and from channels of the DMAMUX request generator sub-block
(dmamux_req_genx)
• DMAMUX request outputs to channels of DMA controllers (dmamux_req_outx)
• Internal or external signals to DMA request trigger inputs (dmamux_trgx)
• Internal or external signals to synchronization inputs (dmamux_syncx)

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RM0432 DMA request multiplexer (DMAMUX)

12.4.2 DMAMUX signals

Table 60 lists the DMAMUX signals.

Table 60. DMAMUX signals

Signal name Description

dmamux_hclk DMAMUX AHB clock

dmamux_req_inx DMAMUX DMA request line inputs from peripherals
dmamux_trgx DMAMUX DMA request triggers inputs (to request generator sub-block)
dmamux_req_genx DMAMUX request generator sub-block channels outputs
DMAMUX request multiplexer sub-block inputs (from peripheral
dmamux_reqx
requests and request generator channels)
dmamux_syncx DMAMUX synchronization inputs (to request multiplexer sub-block)
dmamux_req_outx DMAMUX requests outputs (to DMA controllers)
dmamux_evtx DMAMUX events outputs
dmamux_ovr_it DMAMUX overrun interrupts

12.4.3 DMAMUX channels

A DMAMUX channel is a DMAMUX request multiplexer channel that may include,
depending on the selected input of the request multiplexer, an additional DMAMUX request
generator channel.
A DMAMUX request multiplexer channel is connected and dedicated to one single channel
of DMA controller(s).

Channel configuration procedure

Follow the sequence below to configure both a DMAMUX x channel and the related DMA
channel y:
1. Set and configure completely the DMA channel y, except enabling the channel y.
2. Set and configure completely the related DMAMUX y channel.
3. Last, activate the DMA channel y by setting the EN bit in the DMA y channel register.

12.4.4 DMAMUX request line multiplexer

The DMAMUX request multiplexer with its multiple channels ensures the actual routing of
DMA request/acknowledge control signals, named DMA request lines.
Each DMA request line is connected in parallel to all the channels of the DMAMUX request
line multiplexer.
A DMA request is sourced either from the peripherals or from the DMAMUX request
generator.
The DMAMUX request line multiplexer channel x selects the DMA request line number as
configured by the DMAREQ_ID field in the DMAMUX_CxCR register.

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Note: The null value in the field DMAREQ_ID corresponds to no DMA request line selected. It is
not allowed to configure a same non-null DMAREQ_ID to two different channels of the
DMAMUX request line multiplexer.
On top of the DMA request selection, the synchronization mode and/or the event generation
may be configured and enabled, if required.

Synchronization mode and channel event generation

Each DMAMUX request line multiplexer channel x can be individually synchronized by
setting the synchronization enable (SE) bit in the DMAMUX_CxCR register.
DMAMUX has multiple synchronization inputs. The synchronization inputs are connected in
parallel to all the channels of the request multiplexer.
The synchronization input is selected via the SYNC_ID field in the DMAMUX_CxCR register
of a given channel x.
When a channel is in this synchronization mode, the selected input DMA request line is
propagated to the multiplexer channel output, once is detected a programmable
rising/falling edge on the selected input synchronization signal, via the SPOL[1:0] field of the
DMAMUX_CxCR register.
Additionally, there is a programmable DMA request counter, internally to the DMAMUX
request multiplexer, which may be used for the channel request output generation and also
possibly for an event generation. An event generation on the channel x output is enabled
through the EGE bit (event generation enable) of the DMAMUX_CxCR register.
As shown in Figure 34, upon the detected edge of the synchronization input, the pending
selected input DMA request line is connected to the DMAMUX multiplexer channel x output.
Note: If a synchronization event occurs while there is no pending selected input DMA request line,
it is discarded. The following asserted input request lines is not connected to the DMAMUX
multiplexer channel output until a synchronization event occurs again.
From this point on, each time the connected DMAMUX request is served by the DMA
controller (a served request is deasserted), the DMAMUX request counter is decremented.
At its underrun, the DMA request counter is automatically loaded with the value in NBREQ
field of the DMAMUX_CxCR register and the input DMA request line is disconnected from
the multiplexer channel x output.
Thus, the number of DMA requests transferred to the multiplexer channel x output following
a detected synchronization event, is equal to the value in NBREQ field, plus one.
Note: The NBREQ field value shall only be written by software when both synchronization enable
bit SE and event generation enable EGE bit of the corresponding multiplexer channel x are
disabled.

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RM0432 DMA request multiplexer (DMAMUX)

Figure 33. Synchronization mode of the DMAMUX request line multiplexer channel

Selected DMA request line transferred to the output

DMA requests served

DMA request pending

Selected
dmamux_reqx
Not pending

dmamux_syncx

dmamux_req_outx

DMA request counter 4 3 2 1 0 4

dmamux_evtx

DMA request counter underrun

Synchronization event
DMA request counter auto-reload to NBREQ
Input DMA request line connected to output
Input DMA request line disconnected from output

Example: DMAMUX_CCRx configured with: NBREQ=4, SE=1, EGE=1, SPOL=01 (rising edge)

MSv41974V1

Figure 34. Event generation of the DMA request line multiplexer channel

Selected DMA request line transferred to the output

DMA request pending

Selected
dmamux_reqx Not pending

dmamux_req_outx

DMA request counter 3 2 1 0 3 2 1 0 3 2 1 0

SE

EGE

dmamux_evtx

DMA request counter reaches zero

Event is generated on the output
DMA request counter auto-reloads with NBREQ value

Example with: DMAMUX_CCRx configured with: NBREQ=3, SE=0, EGE=1

MSv41975V1

If EGE is enabled, the multiplexer channel generates a channel event, as a pulse of one
AHB clock cycle, when its DMA request counter is automatically reloaded with the value of
the programmed NBREQ field, as shown in Figure 33 and Figure 34.

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Note: If EGE is enabled and NBREQ = 0, an event is generated after each served DMA request.
Note: A synchronization event (edge) is detected if the state following the edge remains stable for
more than two AHB clock cycles.
Upon writing into DMAMUX_CxCR register, the synchronization events are masked during
three AHB clock cycles.

Synchronization overrun and interrupt

If a new synchronization event occurs before the request counter underrun (the internal
request counter programmed via the NBREQ field of the DMAMUX_CxCR register), the
synchronization overrun flag bit SOFx is set in the DMAMUX_CSR status register.
Note: The request multiplexer channel x synchronization must be disabled
(DMAMUX_CxCR.SE = 0) at the completion of the use of the related channel of the DMA
controller. Else, upon a new detected synchronization event, there is a synchronization
overrun due to the absence of a DMA acknowledge (that is, no served request) received
from the DMA controller.
The overrun flag SOFx is reset by setting the associated clear synchronization overrun flag
bit CSOFx in the DMAMUX_CFR register.
Setting the synchronization overrun flag generates an interrupt if the synchronization
overrun interrupt enable bit SOIE is set in the DMAMUX_CxCR register.

12.4.5 DMAMUX request generator

The DMAMUX request generator produces DMA requests following trigger events on its
DMA request trigger inputs.
The DMAMUX request generator has multiple channels. DMA request trigger inputs are
connected in parallel to all channels.
The outputs of DMAMUX request generator channels are inputs to the DMAMUX request
line multiplexer.
Each DMAMUX request generator channel x has an enable bit GE (generator enable) in the
corresponding DMAMUX_RGxCR register.
The DMA request trigger input for the DMAMUX request generator channel x is selected
through the SIG_ID (trigger signal ID) field in the corresponding DMAMUX_RGxCR register.
Trigger events on a DMA request trigger input can be rising edge, falling edge or either
edge. The active edge is selected through the GPOL (generator polarity) field in the
corresponding DMAMUX_RGxCR register.
Upon the trigger event, the corresponding generator channel starts generating DMA
requests on its output. Each time the DMAMUX generated request is served by the
connected DMA controller (a served request is deasserted), a built-in (inside the DMAMUX
request generator) DMA request counter is decremented. At its underrun, the request
generator channel stops generating DMA requests and the DMA request counter is
automatically reloaded to its programmed value upon the next trigger event.
Thus, the number of DMA requests generated after the trigger event is GNBREQ + 1.

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RM0432 DMA request multiplexer (DMAMUX)

Note: The GNBREQ field value must be written by software only when the enable GE bit of the
corresponding generator channel x is disabled.
A trigger event (edge) is detected if the state following the edge remains stable for more
than two AHB clock cycles.
Upon writing into DMAMUX_RGxCR register, the trigger events are masked during three
AHB clock cycles.

Trigger overrun and interrupt

If a new DMA request trigger event occurs before the DMAMUX request generator counter
underrun (the internal counter programmed via the GNBREQ field of the DMAMUX_RGxCR
register), and if the request generator channel x was enabled via GE, then the request
trigger event overrun flag bit OFx is asserted by the hardware in the status
DMAMUX_RGSR register.
Note: The request generator channel x must be disabled (DMAMUX_RGxCR.GE = 0) at the
completion of the usage of the related channel of the DMA controller. Else, upon a new
detected trigger event, there is a trigger overrun due to the absence of an acknowledge (that
is, no served request) received from the DMA.
The overrun flag OFx is reset by setting the associated clear overrun flag bit COFx in the
DMAMUX_RGCFR register.
Setting the DMAMUX request trigger overrun flag generates an interrupt if the DMA request
trigger event overrun interrupt enable bit OIE is set in the DMAMUX_RGxCR register.

12.5 DMAMUX interrupts

An interrupt can be generated upon:
• a synchronization event overrun in each DMA request line multiplexer channel
• a trigger event overrun in each DMA request generator channel
For each case, per-channel individual interrupt enable, status and clear flag register bits are
available.

Table 61. DMAMUX interrupts

Interrupt signal Interrupt event Event flag Clear bit Enable bit

Synchronization event overrun

on channel x of the SOFx CSOFx SOIE
DMAMUX request line multiplexer
dmamuxovr_it
Trigger event overrun
on channel x of the OFx COFx OIE
DMAMUX request generator

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12.6 DMAMUX registers

Refer to the table containing register boundary addresses for the DMAMUX base address.
DMAMUX registers may be accessed per (8-bit) byte, (16-bit) half-word, or (32-bit) word.
The address must be aligned with the data size.

12.6.1 DMAMUX request line multiplexer channel x configuration register

(DMAMUX_CxCR)
Address offset: 0x000 + 0x04 * x (x = 0 to 13)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. SYNC_ID[4:0] NBREQ[4:0] SPOL[1:0] SE
rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. EGE SOIE Res. DMAREQ_ID[6:0]
rw rw rw rw rw rw rw rw rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:24 SYNC_ID[4:0]: Synchronization identification
Selects the synchronization input (see Table 58: DMAMUX: assignment of synchronization
inputs to resources (STM32L4Rxxx and STM32L4Sxxx devices) and Table 59: DMAMUX:
assignment of synchronization inputs to resources (STM32L4P5xx and STM32L4Q5xx
devices)).
Bits 23:19 NBREQ[4:0]: Number of DMA requests minus 1 to forward
Defines the number of DMA requests to forward to the DMA controller after a synchronization
event, and/or the number of DMA requests before an output event is generated.
This field shall only be written when both SE and EGE bits are low.
Bits 18:17 SPOL[1:0]: Synchronization polarity
Defines the edge polarity of the selected synchronization input:
00: no event, i.e. no synchronization nor detection.
01: rising edge
10: falling edge
11: rising and falling edge
Bit 16 SE: Synchronization enable
0: synchronization disabled
1: synchronization enabled
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 EGE: Event generation enable
0: event generation disabled
1: event generation enabled
Bit 8 SOIE: Synchronization overrun interrupt enable
0: interrupt disabled
1: interrupt enabled

410/2301 RM0432 Rev 6

RM0432 DMA request multiplexer (DMAMUX)

Bit 7 Reserved, must be kept at reset value.

Bits 6:0 DMAREQ_ID[6:0]: DMA request identification
Selects the input DMA request. See the DMAMUX table about assignments of multiplexer
inputs to resources.

12.6.2 DMAMUX request line multiplexer interrupt channel status register

(DMAMUX_CSR)
Address offset: 0x080
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. SOF13 SOF12 SOF11 SOF10 SOF9 SOF8 SOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0
r r r r r r r r r r r r r r

Bits 31:14 Reserved, must be kept at reset value.

Bits 13:0 SOF[13:0]: Synchronization overrun event flag
The flag is set when a synchronization event occurs on a DMA request line multiplexer
channel x, while the DMA request counter value is lower than NBREQ.
The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.

12.6.3 DMAMUX request line multiplexer interrupt clear flag register

(DMAMUX_CFR)
Address offset: 0x084
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF
13 12 11 10 9 8 7 6 5 4 3 2 1 0
w w w w w w w w w w w w w w

Bits 31:14 Reserved, must be kept at reset value.

Bits 13:0 CSOF[13:0]: Clear synchronization overrun event flag
Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR
register.

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DMA request multiplexer (DMAMUX) RM0432

12.6.4 DMAMUX request generator channel x configuration register

(DMAMUX_RGxCR)
Address offset: 0x100 + 0x04 * x (x = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. GNBREQ[4:0] GPOL[1:0] GE
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. OIE Res. Res. Res. SIG_ID[4:0]
rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:19 GNBREQ[4:0]: Number of DMA requests to be generated (minus 1)
Defines the number of DMA requests to be generated after a trigger event. The actual
number of generated DMA requests is GNBREQ +1.
Note: This field shall only be written when GE bit is disabled.
Bits 18:17 GPOL[1:0]: DMA request generator trigger polarity
Defines the edge polarity of the selected trigger input
00: no event. I.e. none trigger detection nor generation.
01: rising edge
10: falling edge
11: rising and falling edge
Bit 16 GE: DMA request generator channel x enable
0: DMA request generator channel x disabled
1: DMA request generator channel x enabled
Bits 15:9 Reserved, must be kept at reset value.
Bit 8 OIE: Trigger overrun interrupt enable
0: interrupt on a trigger overrun event occurrence is disabled
1: interrupt on a trigger overrun event occurrence is enabled
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 SIG_ID[4:0]: Signal identification
Selects the DMA request trigger input used for the channel x of the DMA request generator

412/2301 RM0432 Rev 6

RM0432 DMA request multiplexer (DMAMUX)

12.6.5 DMAMUX request generator interrupt status register

(DMAMUX_RGSR)
Address offset: 0x140
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OF3 OF2 OF1 OF0
r r r r

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 OF[3:0]: Trigger overrun event flag
The flag is set when a new trigger event occurs on DMA request generator channel x, before
the request counter underrun (the internal request counter programmed via the GNBREQ
field of the DMAMUX_RGxCR register).
The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR
register.

12.6.6 DMAMUX request generator interrupt clear flag register

(DMAMUX_RGCFR)
Address offset: 0x144
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. COF3 COF2 COF1 COF0
w w w w

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 COF[3:0]: Clear trigger overrun event flag
Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR
register.

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DMA request multiplexer (DMAMUX) RM0432

12.6.7 DMAMUX register map

The following table summarizes the DMAMUX registers and reset values. Refer to the
register boundary address table for the DMAMUX register base address.

Table 62. DMAMUX register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
DMAMUX_C0CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

SE
0x000
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE
DMAMUX_C1CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]
0x004
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE
DMAMUX_C2CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]
0x008
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
DMAMUX_C3CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

SE
0x00C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
DMAREQ_ID[6:0]

SE
DMAMUX_C4CR SYNC_ID[4:0] NBREQ[4:0]
0x010
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE
DMAMUX_C5CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]
0x014
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]

DMAMUX_C6CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

SE

0x018
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE

DMAMUX_C7CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

0x01C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE

DMAMUX_C8CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

0x020
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]

DMAMUX_C9CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

SE

0x024
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE

DMAMUX_C10CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

0x028
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE

DMAMUX_C11CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

0x02C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE

DMAMUX_C12CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

0x030
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE

DMAMUX_C13CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

0x034
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x038 -
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SOF13 Res.
SOF12 Res.
SOF11 Res.
SOF10 Res.
SOF9 Res.
SOF8 Res.
SOF7 Res.
SOF6 Res.
SOF5 Res.
SOF4 Res.
SOF3 Res.
SOF2 Res.
SOF1 Res.
SOF0 Res.

Reserved
0x07C
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMAMUX_CSR
0x080
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CSOF13
CSOF12

CSOF10
CSOF11

CSOF9
CSOF8
CSOF7
CSOF6
CSOF5
CSOF4
CSOF3
CSOF2
CSOF1
CSOF0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMAMUX_CFR
0x084

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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 0x144
0x140
0x108
0x104
0x100

0x13C
0x10C

0x3FC
0x0FC

0x110 -
Offset

0x148 -
0x088 -
RM0432

Reserved
Reserved
Reserved
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

DMAMUX_RGSR
DMAMUX_RG3CR
DMAMUX_RG2CR
DMAMUX_RG1CR
DMAMUX_RG0CR

DMAMUX_RGCFR
Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
0
0
0
0

Res. Res. Res. Res. Res. 23

0
0
0
0

Res. Res. Res. Res. Res. 22

0
0
0
0

Res. Res. Res. Res. Res. 21

0
0
0
0

Res. Res. Res. Res. Res. 20

GNBREQ[4:0]
GNBREQ[4:0]
GNBREQ[4:0]
GNBREQ[4:0]

0
0
0
0

Res. Res. Res. Res. Res. 19

0
0
0
0

Res. Res. Res. Res. GPOL GPOL GPOL GPOL Res. 18

RM0432 Rev 6
[1:0] [1:0] [1:0]
0
0
0
0

Res. Res. Res. Res. [1:0] Res. 17

0
0
0
0

Res. Res. Res. Res. GE GE GE GE Res. 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. 15
Res. Res. Res. Res. Res. Res. Res. Res. Res. 14
Res. Res. Res. Res. Res. Res. Res. Res. Res. 13
Res. Res. Res. Res. Res. Res. Res. Res. Res. 12
Res. Res. Res. Res. Res. Res. Res. Res. Res. 11
Res. Res. Res. Res. Res. Res. Res. Res. Res. 10
Res. Res. Res. Res. Res. Res. Res. Res. Res. 9
Refer to Section 2.2 on page 91 for the register boundary addresses.
0
0
0
0

Res. Res. Res. Res. OIE OIE OIE OIE Res. 8

Table 62. DMAMUX register map and reset values (continued)

Res. Res. Res. Res. Res. Res. Res. Res. Res. 7

Res. Res. Res. Res. Res. Res. Res. Res. Res. 6
Res. Res. Res. Res. Res. Res. Res. Res. Res. 5
0
0
0
0

Res. Res. Res. Res. Res. 4

0
0
0
0

0
0

Res. COF3 OF3 Res. Res. 3

0
0
0
0

0
0

Res. COF2 OF2 Res. Res. 2

0
0
0
0

0
0

Res. COF1 OF1 Res. Res. 1

SIG_ID[4:0]
SIG_ID[4:0]
SIG_ID[4:0]
SIG_ID[4:0]

0
0
0
0

0
0

Res. COF0 OF0 Res. Res. 0

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Chrom-ART Accelerator controller (DMA2D) RM0432

13 Chrom-ART Accelerator controller (DMA2D)

13.1 DMA2D introduction

The Chrom-ART Accelerator (DMA2D) is a specialized DMA dedicated to image
manipulation. It can perform the following operations:
• Filling a part or the whole of a destination image with a specific color
• Copying a part or the whole of a source image into a part or the whole of a destination
image
• Copying a part or the whole of a source image into a part or the whole of a destination
image with a pixel format conversion
• Blending a part and/or two complete source images with different pixel format and copy
the result into a part or the whole of a destination image with a different color format.
All the classical color coding schemes are supported from 4-bit up to 32-bit per pixel with
indexed or direct color mode. The DMA2D has its own dedicated memories for CLUTs (color
look-up tables).

13.2 DMA2D main features

The main DMA2D features are:
• Single AHB master bus architecture.
• AHB slave programming interface supporting 8/16/32-bit accesses (except for CLUT
accesses which are 32-bit).
• User programmable working area size
• User programmable offset for sources and destination areas expressed in pixels or
bytes
• User programmable sources and destination addresses on the whole memory space
• Up to 2 sources with blending operation
• Alpha value can be modified (source value, fixed value or modulated value)
• User programmable source and destination color format
• Up to 11 color formats supported from 4-bit up to 32-bit per pixel with indirect or direct
color coding
• 2 internal memories for CLUT storage in indirect color mode
• Automatic CLUT loading or CLUT programming via the CPU
• User programmable CLUT size
• Internal timer to control AHB bandwidth
• 6 operating modes: register-to-memory, memory-to-memory, memory-to-memory with
pixel format conversion, memory-to-memory with pixel format conversion and blending,
memory-to memory with pixel format conversion, blending and fixed color foreground,
and memory-to memory with pixel format conversion, blending and fixed color
background.

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• Area filling with a fixed color

• Copy from an area to another
• Copy with pixel format conversion between source and destination images
• Copy from two sources with independent color format and blending
• Output buffer byte swapping to support refresh of displays through parallel interface
• Abort and suspend of DMA2D operations
• Watermark interrupt on a user programmable destination line
• Interrupt generation on bus error or access conflict
• Interrupt generation on process completion

13.3 DMA2D functional description

13.3.1 General description

The DMA2D controller performs direct memory transfer. As an AHB master, it can take the
control of the AHB bus matrix to initiate AHB transactions.
The DMA2D can operate in the following modes:
• Register-to-memory
• Memory-to-memory
• Memory-to-memory with Pixel Format Conversion
• Memory-to-memory with Pixel Format Conversion and Blending
• Memory-to memory with pixel format conversion, blending and fixed color foreground
• Memory-to memory with pixel format conversion, blending and fixed color background
The AHB slave port is used to program the DMA2D controller.
The block diagram of the DMA2D is shown in Figure 35: DMA2D block diagram.

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Figure 35. DMA2D block diagram

AHB MASTER

FG PFC
Dmode

Color mode 8-bit D

D 32
FG 32 D 8 X
Expander
FIFO
32 RGB BLENDER OUT PFC
Color
CLUT itf 32 D Color mode
32
Red Converter OUT
256x32-bit FIFO
Green 32/24/16
RAM 32

Blue
BG PFC
Dmode

Color mode 8-bit D

D 32
BG 32 D 8 X
Expander
FIFO
32 RGB

CLUT itf

256x32-bit
RAM AHB SLAVE

MS30439V1

13.3.2 DMA2D control

The DMA2D controller is configured through the DMA2D Control Register (DMA2D_CR)
which allows selecting:
The user application can perform the following operations:
• Select the operating mode
• Enable/disable the DMA2D interrupt
• Start/suspend/abort ongoing data transfers

13.3.3 DMA2D foreground and background FIFOs

The DMA2D foreground (FG) FG FIFO and background (BG) FIFO fetch the input data to
be copied and/or processed.
The FIFOs fetch the pixels according to the color format defined in their respective pixel
format converter (PFC).

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They are programmed through a set of control registers:

• DMA2D foreground memory address register (DMA2D_FGMAR)
• DMA2D foreground offset register (DMA2D_FGOR)
• DMA2D background memory address register (DMA2D_BGMAR)
• DMA2D background offset register (DMA2D_BGBOR)
• DMA2D number of lines register (number of lines and pixel per lines) (DMA2D_NLR)
When the DMA2D operates in register-to-memory mode, none of the FIFOs is activated.
When the DMA2D operates in memory-to-memory mode (no pixel format conversion nor
blending operation), only the FG FIFO is activated and acts as a buffer.
When the DMA2D operates in memory-to-memory operation with pixel format conversion
(no blending operation), the BG FIFO is not activated.

13.3.4 DMA2D foreground and background pixel format converter (PFC)

DMA2D foreground pixel format converter (PFC) and background pixel format converter
perform the pixel format conversion to generate a 32-bit per pixel value. The PFC can also
modify the alpha channel.
The first stage of the converter converts the color format. The original color format of the
foreground pixel and background pixels are configured through the CM[3:0] bits of the
DMA2D_FGPFCCR and DMA2D_BGPFCCR, respectively.
The supported input formats are given in Table 63: Supported color mode in input.

Table 63. Supported color mode in input

CM[3:0] Color mode

0000 ARGB8888
0001 RGB888
0010 RGB565
0011 ARGB1555
0100 ARGB4444
0101 L8
0110 AL44
0111 AL88
1000 L4
1001 A8
1010 A4

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The color format are coded as follows:

• Alpha value field: transparency
0xFF value corresponds to an opaque pixel and 0x00 to a transparent one.
• R field for Red
• G field for Green
• B field for Blue
• L field: luminance
This field is the index to a CLUT to retrieve the three/four RGB/ARGB components.
If the original format was direct color mode (ARGB/RGB), then the extension to 8-bit per
channel is performed by copying the MSBs into the LSBs. This ensures a perfect linearity of
the conversion.
If the original format is indirect color mode (L/AL), a CLUT is required and each pixel format
converter is associated with a 256 entry 32-bit CLUT.
If the original format does not include an alpha channel, the alpha value is automatically set
to 0xFF (opaque).
For the specific alpha mode A4 and A8, no color information is stored nor indexed. The color
to be used for the image generation is fixed and is defined in the DMA2D_FGCOLR for
foreground pixels and in the DMA2D_BGCOLR register for background pixels.
The order of the fields in the system memory is defined in Table 64: Data order in memory.

Table 64. Data order in memory

Color Mode @+3 @+2 @+1 @+0

ARGB8888 A0[7:0] R0[7:0] G0[7:0] B0[7:0]

B1[7:0] R0[7:0] G0[7:0] B0[7:0]
RGB888 G2[7:0] B2[7:0] R1[7:0] G1[7:0]
R3[7:0] G3[7:0] B3[7:0] R2[7:0]
RGB565 R1[4:0]G1[5:3] G1[2:0]B1[4:0] R0[4:0]G0[5:3] G0[2:0]B0[4:0]
ARGB1555 A1[0]R1[4:0]G1[4:3] G1[2:0]B1[4:0] A0[0]R0[4:0]G0[4:3] G0[2:0]B0[4:0]
ARGB4444 A1[3:0]R1[3:0] G1[3:0]B1[3:0] A0[3:0]R0[3:0] G0[3:0]B0[3:0]
L8 L3[7:0] L2[7:0] L1[7:0] L0[7:0]
AL44 A3[3:0]L3[3:0] A2[3:0]L2[3:0] A1[3:0]L1[3:0] A0[3:0]L0[3:0]
AL88 A1[7:0] L1[7:0] A0[7:0] L0[7:0]
L4 L7[3:0]L6[3:0] L5[3:0]L4[3:0] L3[3:0]L2[3:0] L1[3:0]L0[3:0]
A8 A3[7:0] A2[7:0] A1[7:0] A0[7:0]
A4 A7[3:0]A6[3:0] A5[3:0]A4[3:0] A3[3:0]A2[3:0] A1[3:0]A0[3:0]

The 24-bit RGB888 aligned on 32-bit is supported through the ARGB8888 mode.
Once the 32-bit value is generated, the alpha channel can be modified according to the
AM[1:0] field of the DMA2D_FGPFCCR/DMA2D_BGPFCCR registers as shown in
Table 65: Alpha mode configuration.

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The alpha channel can be:

• kept as it is (no modification),
• replaced by the ALPHA[7:0] value of DMA2D_FGPFCCR/DMA2D_BGPFCCR,
• or replaced by the original alpha value multiplied by the ALPHA[7:0] value of
DMA2D_FGPFCCR/DMA2D_BGPFCCR divided by 255.

Table 65. Alpha mode configuration

AM[1:0] Alpha mode

00 No modification
01 Replaced by value in DMA2D_xxPFCCR
10 Replaced by original value multiplied by the value in DMA2D_xxPFCCR / 255
11 Reserved

Note: To support the alternate format, the incoming alpha value can be inverted setting the AI bit
of the DMA2D_FGPFCCR/DMA2D_BGPFCCR registers. This applies also to the Alpha
value stored in the DMA2D_FGPFCCR/DMA2D_BGPFCCR and in the CLUT.
The R and B fields can also be swapped setting the RBS bit of the
DMA2D_FGPFCCR/DMA2D_BGPFCCR registers. This applies also to the RGB order used
in the CLUT and in the DMA2D_FGCOLR/DMA2D_BGCOLR registers.

13.3.5 DMA2D foreground and background CLUT interface

The CLUT interface manages the CLUT memory access and the automatic loading of the
CLUT.
Three kinds of accesses are possible:
• CLUT read by the PFC during pixel format conversion operation
• CLUT accessed through the AHB slave port when the CPU is reading or writing data
into the CLUT
• CLUT written through the AHB master port when an automatic loading of the CLUT is
performed
The CLUT memory loading can be done in two different ways:
• Automatic loading
The following sequence must be followed to load the CLUT:
a) Program the CLUT address into the DMA2D_FGCMAR register (foreground
CLUT) or DMA2D_BGCMAR register (background CLUT)
b) Program the CLUT size in the CS[7:0] field of the DMA2D_FGPFCCR register
(foreground CLUT) or DMA2D_BGPFCCR register (background CLUT).
c) Set the START bit of the DMA2D_FGPFCCR register (foreground CLUT) or
DMA2D_BGPFCCR register (background CLUT) to start the transfer. During this
automatic loading process, the CLUT is not accessible by the CPU. If a conflict

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occurs, a CLUT access error interrupt is raised assuming CAEIE is set to ‘1’ in
DMA2D_CR.
• Manual loading
The application has to program the CLUT manually through the DMA2D AHB slave
port to which the local CLUT memory is mapped.The foreground CLUT is located at
address offset 0x0400 and the background CLUT at address offset 0x0800.
The CLUT format is 24 or 32 bits. It is configured through the CCM bit of the
DMA2D_FGPFCCR register (foreground CLUT) or DMA2D_BGPFCCR register
(background CLUT) as shown in Table 66: Supported CLUT color mode.

Table 66. Supported CLUT color mode

CCM CLUT color mode

0 32-bit ARGB8888
1 24-bit RGB888

The way the CLUT data are organized in the system memory is specified in Table 67: CLUT
data order in system memory.

Table 67. CLUT data order in system memory

CLUT Color Mode @+3 @+2 @+1 @+0
ARGB8888 A0[7:0] R0[7:0] G0[7:0] B0[7:0]
B1[7:0] R0[7:0] G0[7:0] B0[7:0]
RGB888 G2[7:0] B2[7:0] R1[7:0] G1[7:0]
R3[7:0] G3[7:0] B3[7:0] R2[7:0]

13.3.6 DMA2D blender

The DMA2D blender blends the source pixels by pair to compute the resulting pixel.
The blending is performed according to the following equation:

αFG . αBG
with αMult =
255

αOUT = αFG + αBG - αMult

CFG.αFG + CBG.αBG - CBG.αMult

COUT = with C = R or G or B
αOUT

Division is rounded to the nearest lower integer

No configuration register is required by the blender. The blender usage depends on the
DMA2D operating mode defined in MODE[2:0] field of the DMA2D_CR register.

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13.3.7 DMA2D output PFC

The output PFC performs the pixel format conversion from 32 bits to the output format
defined in the CM[2:0] field of the DMA2D output pixel format converter configuration
register (DMA2D_OPFCCR).
The supported output formats are given in Table 68: Supported color mode in output

Table 68. Supported color mode in output

CM[2:0] Color mode

000 ARGB8888
001 RGB888
010 RGB565
011 ARGB1555
100 ARGB4444

Note: To support the alternate format, the calculated alpha value is inverted setting the AI bit of the
DMA2D_OPFCCR registers. This applies also to the Alpha value used in the
DMA2D_OCOLR.
The R and B fields can also be swapped setting the RBS bit of the DMA2D_OPFCCR
registers. This applies also to the RGB order used in the DMA2D_OCOLR.

13.3.8 DMA2D output FIFO

The output FIFO programs the pixels according to the color format defined in the output
PFC.
The destination area is defined through a set of control registers:
• DMA2D output memory address register (DMA2D_OMAR)
• DMA2D output offset register (DMA2D_OOR)
• DMA2D number of lines register (number of lines and pixel per lines) (DMA2D_NLR)
If the DMA2D operates in register-to-memory mode, the configured output rectangle is filled
by the color specified in the DMA2D output color register (DMA2D_OCOLR) which contains
a fixed 32-bit, 24-bit or 16-bit value. The format is selected by the CM[2:0] field of the
DMA2D_OPFCCR register.
The data are stored into the memory in the order defined in Table 69: Data order in memory

Table 69. Data order in memory

Color Mode @+3 @+2 @+1 @+0

ARGB8888 A0[7:0] R0[7:0] G0[7:0] B0[7:0]

B1[7:0] R0[7:0] G0[7:0] B0[7:0]
RGB888 G2[7:0] B2[7:0] R1[7:0] G1[7:0]
R3[7:0] G3[7:0] B3[7:0] R2[7:0]
RGB565 R1[4:0]G1[5:3] G1[2:0]B1[4:0] R0[4:0]G0[5:3] G0[2:0]B0[4:0]

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Table 69. Data order in memory (continued)

Color Mode @+3 @+2 @+1 @+0

ARGB1555 A1[0]R1[4:0]G1[4:3] G1[2:0]B1[4:0] A0[0]R0[4:0]G0[4:3] G0[2:0]B0[4:0]

ARGB4444 A1[3:0]R1[3:0] G1[3:0]B1[3:0] A0[3:0]R0[3:0] G0[3:0]B0[3:0]

The RGB888 aligned on 32-bit is supported through the ARGB8888 mode.

13.3.9 DMA2D output FIFO byte reordering

The output FIFO bytes is reordered to support display frame buffer update through a parallel
interface (F(S)MC) directly from the DMA2D.
The reordering of bytes can be done using:
• RBS bit to swap Red and Blue component
• SB bit to swap byte two by two in the output FIFO
When the byte swapping is activated (SB field of the DMA2D_OPFCR is set), the number of
pixel per line (PL field of the DMA2D_NLR) must be even and the output memory address
(MA field of the DMA2D_OMAR) must be even, and the output line offset computed in bytes
(resulting from LOM field of DMA2D_CR and LO field of DMA2D_OOR values) must be
even. If not a configuration error is detected.

Table 70. Standard data order in memory

Color Mode @+3 @+2 @+1 @+0

B1[7:0] R0[7:0] G0[7:0] B0[7:0]

RGB888 G2[7:0] B2[7:0] R1[7:0] G1[7:0]
R3[7:0] G3[7:0] B3[7:0] R2[7:0]
RGB565 R1[4:0]G1[5:3] G1[2:0]B1[4:0] R0[4:0]G0[5:3] G0[2:0]B0[4:0]

16-bit mode (RGB565)

This mode is supported without byte reordering by the DMA2D.

Figure 36. Intel 8080 16-bit mode (RGB565)

16-bit Data

Data Bus D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Colors R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0
G5 B4 B3 B2 B1 B0

64K colors

MSv42078V2

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18/24-bit mode (RGB888)

This mode needs data reordering.
1. The Red and the Blue have to be swapped (setting the RBS bit)
2. The MSB and the LSB bytes of an half-word as to be swapped (setting the SB bit)

Figure 37. Intel 8080 18/24-bit mode (RGB888)

Transfer
1 2
Order
16-bit Data 16-bit Data

Data Bus D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Colors R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 R7 R6 R5 R4 R3 R2 R1 R0

16.7M colors
1st pixel 2nd pixel

MSv42079V2

Table 71. Output FIFO byte reordering steps

Steps @+3 @+2 @+1 @+0

B1[7:0] R0[7:0] G0[7:0] B0[7:0]

Original data ordering G2[7:0] B2[7:0] R1[7:0] G1[7:0]
R3[7:0] G3[7:0] B3[7:0] R2[7:0]
Setting the RBS bit
R1[7:0] B0[7:0] G0[7:0] R0[7:0]
Data ordering after red and blue
G2[7:0] R2[7:0] B1[7:0] G1[7:0]
swap (RBS set)
B3[7:0] G3[7:0] R3[7:0] B2[7:0]
Setting the SB bit
B0[7:0] R1[7:0] R0[7:0] G0[7:0]
Data ordering after byte swapping
R2[7:0] G2[7:0] G1[7:0] B1[7:0]
(SB set)
G3[7:0] B3[7:0] B2[7:0] R3[7:0]

13.3.10 DMA2D AHB master port timer

An 8-bit timer is embedded into the AHB master port to provide an optional limitation of the
bandwidth on the crossbar.
This timer is clocked by the AHB clock and counts a dead time between two consecutive
accesses. This limits the bandwidth usage.
The timer enabling and the dead time value are configured through the AHB master port
timer configuration register (DMA2D_AMPTCR).

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13.3.11 DMA2D transactions

DMA2D transactions consist of a sequence of a given number of data transfers. The
number of data and the width can be programmed by software.
Each DMA2D data transfer is composed of up to 4 steps:
1. Data loading from the memory location pointed by the DMA2D_FGMAR register and
pixel format conversion as defined in DMA2D_FGCR.
2. Data loading from a memory location pointed by the DMA2D_BGMAR register and
pixel format conversion as defined in DMA2D_BGCR.
3. Blending of all retrieved pixels according to the alpha channels resulting of the PFC
operation on alpha values.
4. Pixel format conversion of the resulting pixels according to the DMA2D_OCR register
and programming of the data to the memory location addressed through the
DMA2D_OMAR register.

13.3.12 DMA2D configuration

Both source and destination data transfers can target peripherals and memories in the
whole 4 Gbyte memory area, at addresses ranging between 0x0000 0000 and
0xFFFF FFFF.
The DMA2D can operate in any of the four following modes selected through MODE[2:0]
bits of the DMA2D_CR register:
• Register-to-memory
• Memory-to-memory
• Memory-to-memory with PFC
• Memory-to-memory with PFC and blending
• Memory-to-memory with PFC, blending and fixed FG color
• Memory-to-memory with PFC, blending and fixed BG color

Register-to-memory
The register-to-memory mode is used to fill a user defined area with a predefined color.
The color format is set in the DMA2D_OPFCCR.
The DMA2D does not perform any data fetching from any source. It just writes the color
defined in the DMA2D_OCOLR register to the area located at the address pointed by the
DMA2D_OMAR and defined in the DMA2D_NLR and DMA2D_OOR.

Memory-to-memory
In memory-to-memory mode, the DMA2D does not perform any graphical data
transformation. The foreground input FIFO acts as a buffer and the data are transferred
from the source memory location defined in DMA2D_FGMAR to the destination memory
location pointed by DMA2D_OMAR.
The color mode programmed in the CM[3:0] bits of the DMA2D_FGPFCCR register defines
the number of bits per pixel for both input and output.
The size of the area to be transferred is defined by the DMA2D_NLR and DMA2D_FGOR
registers for the source, and by DMA2D_NLR and DMA2D_OOR registers for the
destination.

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Memory-to-memory with PFC

In this mode, the DMA2D performs a pixel format conversion of the source data and stores
them in the destination memory location.
The size of the areas to be transferred are defined by the DMA2D_NLR and DMA2D_FGOR
registers for the source, and by DMA2D_NLR and DMA2D_OOR registers for the
destination.
Data are fetched from the location defined in the DMA2D_FGMAR register and processed
by the foreground PFC. The original pixel format is configured through the
DMA2D_FGPFCCR register.
If the original pixel format is direct color mode, then the color channels are all expanded to 8
bits.
If the pixel format is indirect color mode, the associated CLUT has to be loaded into the
CLUT memory.
The CLUT loading can be done automatically by following the sequence below:
1. Set the CLUT address into the DMA2D_FGCMAR.
2. Set the CLUT size in the CS[7:0] bits of the DMA2D_FGPFCCR register.
3. Set the CLUT format (24 or 32 bits) in the CCM bit of the DMA2D_FGPFCCR register.
4. Start the CLUT loading by setting the START bit of the DMA2D_FGPFCCR register.
Once the CLUT loading is complete, the CTCIF flag of the DMA2D_IFR register is raised,
and an interrupt is generated if the CTCIE bit is set in DMA2D_CR. The automatic CLUT
loading process can not work in parallel with classical DMA2D transfers.
The CLUT can also be filled by the CPU or by any other master through the APB port. The
access to the CLUT is not possible when a DMA2D transfer is ongoing and uses the CLUT
(indirect color format).
In parallel to the color conversion process, the alpha value is added or changed depending
on the value programmed in the DMA2D_FGPFCCR register. If the original image does not
have an alpha channel, a default alpha value of 0xFF is automatically added to obtain a fully
opaque pixel. The alpha value is modified according to the AM[1:0] bits of the
DMA2D_FGPFCCR register:
• It can be unchanged.
• It can be replaced by the value defined in the ALPHA[7:0] value of the
DMA2D_FGPFCCR register.
• It can be replaced by the original value multiplied by the ALPHA[7:0] value of the
DMA2D_FGPFCCR register divided by 255.
The resulting 32-bit data are encoded by the OUT PFC into the format specified by the
CM[2:0] field of the DMA2D_OPFCCR register. The output pixel format cannot be the
indirect mode since no CLUT generation process is supported.
The processed data are written into the destination memory location pointed by
DMA2D_OMAR.

Memory-to-memory with PFC and blending

In this mode, 2 sources are fetched in the foreground FIFO and background FIFO from the
memory locations defined by DMA2D_FGMAR and DMA2D_BGMAR.

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The two pixel format converters have to be configured as described in the memory-to-
memory mode. Their configurations can be different as each pixel format converter are
independent and have their own CLUT memory.
Once each pixel has been converted into 32 bits by their respective PFCs, they are blended
according to the equation below:
αFG . αBG
with αMult =
255

αOUT = αFG + αBG - αMult

CFG.αFG + CBG.αBG - CBG.αMult

COUT = with C = R or G or B
αOUT

Division are rounded to the nearest lower integer

The resulting 32-bit pixel value is encoded by the output PFC according to the specified
output format, and the data are written into the destination memory location pointed by
DMA2D_OMAR.

Memory-to-memory with PFC, blending and fixed color FG

In this mode, only 1 source is fetched in the background FIFO from the memory location
defined by DMA2D_BGMAR.
The value of the foreground color is given by the DMA2D_FGCOLR register and the alpha
value is set to 0xFF (opaque).
The alpha value can be replaced or modified according to the AM[1:0] and ALPHA[7:0]
fields of the DMA2D_FGPFCR.
The two pixel format converters have to be configured as described in the memory-to-
memory mode. Their configurations can be different as each pixel format converter are
independent and have their own CLUT memory
Once each pixel has been converted into 32 bits by their respective PFCs, they are blended
together, and the resulting 32-bit pixel value is encoded by the output PFC according to the
specified output format, and the data are written into the destination memory location
pointed by DMA2D_OMAR.

Memory-to-memory with PFC, blending and fixed color BG

In this mode, only 1 source is fetched in the foreground FIFO from the memory location
defined by DMA2D_FGMAR.
The value of the background color is given by the DMA2D_BGCOLR register and the alpha
value is set to 0xFF (opaque).
The alpha value can be replaced or modified according to the AM[1:0] and ALPHA[7:0]
fields of the DMA2D_BGPFCR.
The two pixel format converters have to be configured as described in the memory-to-
memory mode. Their configurations can be different as each pixel format converter are
independent and have their own CLUT memory

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Once each pixel has been converted into 32 bits by their respective PFCs, they are blended
together, and the resulting 32-bit pixel value is encoded by the output PFC according to the
specified output format, and the data are written into the destination memory location
pointed by DMA2D_OMAR.

Configuration error detection

The DMA2D checks that the configuration is correct before any transfer. The configuration
error interrupt flag is set by hardware when a wrong configuration is detected when a new
transfer/automatic loading starts. An interrupt is then generated if the CEIE bit of the
DMA2D_CR is set.
The wrong configurations that can be detected are listed below:
• Foreground CLUT automatic loading: MA bits of DMA2D_FGCMAR are not aligned
with CCM of DMA2D_FGPFCCR.
• Background CLUT automatic loading: MA bits of DMA2D_BGCMAR are not aligned
with CCM of DMA2D_BGPFCCR
• Memory transfer (except in register-to-memory mode and except in memory-to-
memory mode with blending and fixed color FG): MA bits of DMA2D_FGMAR are not
aligned with CM of DMA2D_FGPFCCR
• Memory transfer (except in register-to-memory mode and except in memory-to-
memory mode with blending and fixed color FG): CM bits of DMA2D_FGPFCCR are
invalid
• Memory transfer (except in register-to-memory mode and except in memory-to-
memory mode with blending and fixed color FG): PL bits of DMA2D_NLR are odd while
CM of DMA2D_FGPFCCR is A4 or L4
• Memory transfer (except in register-to-memory mode and except in memory-to-
memory mode with blending and fixed color FG): LO bits of DMA2D_FGOR are odd
while CM of DMA2D_FGPFCCR is A4 or L4 and LOM bit of the DMA2D_CR is pixel
mode
• Memory transfer (only in blending mode and except in memory-to-memory mode with
blending and fixed color FG): MA bits of DMA2D_BGMAR are not aligned with the CM
of DMA2D_BGPFCCR
• Memory transfer: (only in blending mode and in blending with fixed color FG mode) CM
bits of DMA2D_BGPFCCR are invalid
• Memory transfer (only in blending mode and in blending with fixed color FG mode): PL
bits of DMA2D_NLR odd while CM of DMA2D_BGPFCCR is A4 or L4
• Memory transfer (only in blending mode and in blending with fixed color FG mode): LO
bits of DMA2D_BGOR are odd while CM of DMA2D_BGPFCCR is A4 or L4 and LOM
bit of the DMA2D_CR is pixel mode
• Memory transfer (except in memory to memory mode): MA bits of DMA2D_OMAR are
not aligned with CM bits of DMA2D_OPFCCR.
• Memory transfer (except in memory to memory mode): CM bits of DMA2D_OPFCCR
are invalid
• Memory transfer with byte swapping: PL bits of DMA2D_NLR are odd or MA bits of the
DMA2D_OMAR are odd or LO in bytes (resulting from LOM bit of the DMA2D_CR and
LO bits of DMA2D_OOR values) are odd while SB bit of DMA2D_OPFCCR is set
• Memory transfer: NL bits of DMA2D_NLR = 0

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• Memory transfer: PL bits of DMA2D_NLR = 0

• Memory transfer: MODE bits of DMA2D_CR are invalid

13.3.13 DMA2D transfer control (start, suspend, abort and completion)

Once the DMA2D is configured, the transfer can be launched by setting the START bit of the
DMA2D_CR register. Once the transfer is completed, the START bit is automatically reset
and the TCIF flag of the DMA2D_ISR register is raised. An interrupt can be generated if the
TCIE bit of the DMA2D_CR is set.
The user application can suspend the DMA2D at any time by setting the SUSP bit of the
DMA2D_CR register. The transaction can then be aborted by setting the ABORT bit of the
DMA2D_CR register or can be restarted by resetting the SUSP bit of the DMA2D_CR
register.
The user application can abort at any time an ongoing transaction by setting the ABORT bit
of the DMA2D_CR register. In this case, the TCIF flag is not raised.
Automatic CLUT transfers can also be aborted or suspended by using the ABORT or the
SUSP bit of the DMA2D_CR register.

13.3.14 Watermark
A watermark can be programmed to generate an interrupt when the last pixel of a given line
has been written to the destination memory area.
The line number is defined in the LW[15:0] field of the DMA2D_LWR register.
When the last pixel of this line has been transferred, the TWIF flag of the DMA2D_ISR
register is raised and an interrupt is generated if the TWIE bit of the DMA2D_CR is set.

13.3.15 Error management

Two kind of errors can be triggered:
• AHB master port errors signaled by the TEIF flag of the DMA2D_ISR register.
• Conflicts caused by CLUT access (CPU trying to access the CLUT while a CLUT
loading or a DMA2D transfer is ongoing) signalled by the CAEIF flag of the
DMA2D_ISR register.
Both flags are associated to their own interrupt enable flag in the DMA2D_CR register to
generate an interrupt if need be (TEIE and CAEIE).

13.3.16 AHB dead time

To limit the AHB bandwidth usage, a dead time between two consecutive AHB accesses
can be programmed.
This feature can be enabled by setting the EN bit in the DMA2D_AMTCR register.
The dead time value is stored in the DT[7:0] field of the DMA2D_AMTCR register. This
value represents the guaranteed minimum number of cycles between two consecutive
transactions on the AHB bus.
The update of the dead time value while the DMA2D is running is taken into account for the
next AHB transfer.

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13.4 DMA2D interrupts

An interrupt can be generated on the following events:
• Configuration error
• CLUT transfer complete
• CLUT access error
• Transfer watermark reached
• Transfer complete
• Transfer error
Separate interrupt enable bits are available for flexibility.

Table 72. DMA2D interrupt requests

Interrupt event Event flag Enable control bit

Configuration error CEIF CEIE

CLUT transfer complete CTCIF CTCIE
CLUT access error CAEIF CAEIE
Transfer watermark TWF TWIE
Transfer complete TCIF TCIE
Transfer error TEIF TEIE

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13.5 DMA2D registers

13.5.1 DMA2D control register (DMA2D_CR)

Address offset: 0x0000
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MODE[2:0]

rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. CEIE CTCIE CAEIE TWIE TCIE TEIE Res. LOM Res. Res. Res. ABORT SUSP START

rw rw rw rw rw rw rw rs rw rs

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:16 MODE[2:0]: DMA2D mode
These bits are set and cleared by software. They cannot be modified while a transfer is
ongoing.
000: Memory-to-memory (FG fetch only)
001: Memory-to-memory with PFC (FG fetch only with FG PFC active)
010: Memory-to-memory with blending (FG and BG fetch with PFC and blending)
011: Register-to-memory (no FG nor BG, only output stage active)
100: Memory-to-memory with Blending and fixed color FG (BG fetch only with FG and
BG PFC active)
101: Memory-to-memory with Blending and fixed color BG (BG fetch only with FG and
BG PFC active)
others: meaningless
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 CEIE: Configuration Error Interrupt Enable
This bit is set and cleared by software.
0: CE interrupt disable
1: CE interrupt enable
Bit 12 CTCIE: CLUT transfer complete interrupt enable
This bit is set and cleared by software.
0: CTC interrupt disable
1: CTC interrupt enable
Bit 11 CAEIE: CLUT access error interrupt enable
This bit is set and cleared by software.
0: CAE interrupt disable
1: CAE interrupt enable
Bit 10 TWIE: Transfer watermark interrupt enable
This bit is set and cleared by software.
0: TW interrupt disable
1: TW interrupt enable

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Bit 9 TCIE: Transfer complete interrupt enable

This bit is set and cleared by software.
0: TC interrupt disable
1: TC interrupt enable
Bit 8 TEIE: Transfer error interrupt enable
This bit is set and cleared by software.
0: TE interrupt disable
1: TE interrupt enable
Bit 7 Reserved, must be kept at reset value.
Bit 6 LOM: Line Offset Mode
This bit configures how is expressed the line offset (pixels or bytes) for the foreground,
background and output.
This bit is set and cleared by software. It can not be modified while a transfer is on going.
0: Line offsets are expressed in pixels
1: Line offsets are expressed in bytes
Bits 5:3 Reserved, must be kept at reset value.
Bit 2 ABORT: Abort
This bit can be used to abort the current transfer. This bit is set by software and is
automatically reset by hardware when the START bit is reset.
0: No transfer abort requested
1: Transfer abort requested
Bit 1 SUSP: Suspend
This bit can be used to suspend the current transfer. This bit is set and reset by
software. It is automatically reset by hardware when the START bit is reset.
0: Transfer not suspended
1: Transfer suspended
Bit 0 START: Start
This bit can be used to launch the DMA2D according to the parameters loaded in the
various configuration registers. This bit is automatically reset by the following events:
– At the end of the transfer
– When the data transfer is aborted by the user application by setting the ABORT
bit in DMA2D_CR
– When a data transfer error occurs
– When the data transfer has not started due to a configuration error or another
transfer operation already ongoing (automatic CLUT loading).

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13.5.2 DMA2D interrupt status register (DMA2D_ISR)

Address offset: 0x0004
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CEIF CTCIF CAEIF TWIF TCIF TEIF

r r r r r r

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 CEIF: Configuration error interrupt flag
This bit is set when the START bit of DMA2D_CR, DMA2DFGPFCCR or
DMA2D_BGPFCCR is set and a wrong configuration has been programmed.
Bit 4 CTCIF: CLUT transfer complete interrupt flag
This bit is set when the CLUT copy from a system memory area to the internal DMA2D
memory is complete.
Bit 3 CAEIF: CLUT access error interrupt flag
This bit is set when the CPU accesses the CLUT while the CLUT is being automatically
copied from a system memory to the internal DMA2D.
Bit 2 TWIF: Transfer watermark interrupt flag
This bit is set when the last pixel of the watermarked line has been transferred.
Bit 1 TCIF: Transfer complete interrupt flag
This bit is set when a DMA2D transfer operation is complete (data transfer only).
Bit 0 TEIF: Transfer error interrupt flag
This bit is set when an error occurs during a DMA transfer (data transfer or automatic
CLUT loading).

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13.5.3 DMA2D interrupt flag clear register (DMA2D_IFCR)

Address offset: 0x0008
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CCEIF CCTCIF CAECIF CTWIF CTCIF CTEIF

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 CCEIF: Clear configuration error interrupt flag
Programming this bit to 1 clears the CEIF flag in the DMA2D_ISR register
Bit 4 CCTCIF: Clear CLUT transfer complete interrupt flag
Programming this bit to 1 clears the CTCIF flag in the DMA2D_ISR register
Bit 3 CAECIF: Clear CLUT access error interrupt flag
Programming this bit to 1 clears the CAEIF flag in the DMA2D_ISR register
Bit 2 CTWIF: Clear transfer watermark interrupt flag
Programming this bit to 1 clears the TWIF flag in the DMA2D_ISR register
Bit 1 CTCIF: Clear transfer complete interrupt flag
Programming this bit to 1 clears the TCIF flag in the DMA2D_ISR register
Bit 0 CTEIF: Clear Transfer error interrupt flag
Programming this bit to 1 clears the TEIF flag in the DMA2D_ISR register

13.5.4 DMA2D foreground memory address register (DMA2D_FGMAR)

Address offset: 0x000C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MA[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MA[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MA[31:0]: Memory address

Address of the data used for the foreground image. This register can only be written
when data transfers are disabled. Once the data transfer has started, this register is
read-only.
The address alignment must match the image format selected e.g. a 32-bit per pixel
format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-
bit per pixel format must be 8-bit aligned.

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13.5.5 DMA2D foreground offset register (DMA2D_FGOR)

Address offset: 0x0010
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LO[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 LO[15:0]: Line offset
The line offset used for the foreground image, expressed in pixel when the LOM bit is
reset and in byte when the LOM bit is set.
When expressed in pixels, only LO[13:0] is considered, LO[15:14] are ignored.
This value is used for the address generation. It is added at the end of each line to
determine the starting address of the next line.
These bits can only be written when data transfers are disabled. Once data transfer has
started, they become read-only.
If the image format is 4-bit per pixel, the line offset must be even.

13.5.6 DMA2D background memory address register (DMA2D_BGMAR)

Address offset: 0x0014
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MA[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MA[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MA[31:0]: Memory address

Address of the data used for the background image. This register can only be written
when data transfers are disabled. Once a data transfer has started, this register is read-
only.
The address alignment must match the image format selected e.g. a 32-bit per pixel
format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-
bit per pixel format must be 8-bit aligned.

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13.5.7 DMA2D background offset register (DMA2D_BGOR)

Address offset: 0x0018
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LO[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 LO[15:0]: Line offset
The line offset used for the background image, expressed in pixel when the LOM bit is
reset and in byte when the LOM bit is set.
When expressed in pixels, only LO[13:0] is considered, LO[15:14] are ignored.
This value is used for the address generation. It is added at the end of each line to
determine the starting address of the next line.
These bits can only be written when data transfers are disabled. Once data transfer has
started, they become read-only.
If the image format is 4-bit per pixel, the line offset must be even.

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13.5.8 DMA2D foreground PFC control register (DMA2D_FGPFCCR)

Address offset: 0x001C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ALPHA[7:0] Res. Res. RBS AI Res. Res. AM[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CS[7:0] Res. Res. START CCM CM[3:0]

rw rw rw rw rw rw rw rw rs rw rw rw rw rw

Bits 31:24 ALPHA[7:0]: Alpha value

These bits define a fixed alpha channel value which can replace the original alpha value
or be multiplied by the original alpha value according to the alpha mode selected
through the AM[1:0] bits.
These bits can only be written when data transfers are disabled. Once a transfer has
started, they become read-only.
Bits 23:22 Reserved, must be kept at reset value.
Bit 21 RBS: Red Blue Swap
This bit allows to swap the R & B to support BGR or ABGR color formats. Once the
transfer has started, this bit is read-only.
0: Regular mode (RGB or ARGB)
1: Swap mode (BGR or ABGR)
Bit 20 AI: AI: Alpha Inverted
This bit inverts the alpha value. Once the transfer has started, this bit is read-only.
0: Regular alpha
1: Inverted alpha
Bits 19:18 Reserved, must be kept at reset value.
Bits 17:16 AM[1:0]: Alpha mode
These bits select the alpha channel value to be used for the foreground image. They
can only be written data the transfer are disabled. Once the transfer has started, they
become read-only.
00: No modification of the foreground image alpha channel value
01: Replace original foreground image alpha channel value by ALPHA[7:0]
10: Replace original foreground image alpha channel value by ALPHA[7:0] multiplied
with original alpha channel value
other configurations are meaningless
Bits 15:8 CS[7:0]: CLUT size
These bits define the size of the CLUT used for the foreground image. Once the CLUT
transfer has started, this field is read-only.
The number of CLUT entries is equal to CS[7:0] + 1.
Bits 7:6 Reserved, must be kept at reset value.

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Bit 5 START: Start

This bit can be set to start the automatic loading of the CLUT. It is automatically reset:
– at the end of the transfer
– when the transfer is aborted by the user application by setting the ABORT bit in
DMA2D_CR
– when a transfer error occurs
– when the transfer has not started due to a configuration error or another
transfer operation already ongoing (data transfer or automatic background
CLUT transfer).
Bit 4 CCM: CLUT color mode
This bit defines the color format of the CLUT. It can only be written when the transfer is
disabled. Once the CLUT transfer has started, this bit is read-only.
0: ARGB8888
1: RGB888
others: meaningless
Bits 3:0 CM[3:0]: Color mode
These bits defines the color format of the foreground image. They can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.
0000: ARGB8888
0001: RGB888
0010: RGB565
0011: ARGB1555
0100: ARGB4444
0101: L8
0110: AL44
0111: AL88
1000: L4
1001: A8
1010: A4
others: meaningless

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13.5.9 DMA2D foreground color register (DMA2D_FGCOLR)

Address offset: 0x0020
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. RED[7:0]

rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GREEN[7:0] BLUE[7:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 RED[7:0]: Red value
These bits defines the red value for the A4 or A8 mode of the foreground image. They
can only be written when data transfers are disabled. Once the transfer has started,
they are read-only.
Used also for fixed color FG in memory-to-memory with blending and fixed color FG
(BG fetch only with FG and BG PFC active) mode.
Bits 15:8 GREEN[7:0]: Green value
These bits defines the green value for the A4 or A8 mode of the foreground image. They
can only be written when data transfers are disabled. Once the transfer has started,
They are read-only.
Used also for fixed color FG in memory-to-memory with blending and fixed color FG
(BG fetch only with FG and BG PFC active) mode.
Bits 7:0 BLUE[7:0]: Blue value
These bits defines the blue value for the A4 or A8 mode of the foreground image. They
can only be written when data transfers are disabled. Once the transfer has started,
They are read-only.
Used also for fixed color FG in memory-to-memory with blending and fixed color FG
(BG fetch only with FG and BG PFC active) mode.

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13.5.10 DMA2D background PFC control register (DMA2D_BGPFCCR)

Address offset: 0x0024
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ALPHA[7:0] Res. Res. RBS AI Res. Res. AM[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CS[7:0] Res. Res. START CCM CM[3:0]

rw rw rw rw rw rw rw rw rs rw rw rw rw rw

Bits 31:24 ALPHA[7:0]: Alpha value

These bits define a fixed alpha channel value which can replace the original alpha value
or be multiplied with the original alpha value according to the alpha mode selected with
bits AM[1:0]. These bits can only be written when data transfers are disabled. Once the
transfer has started, they are read-only.
Bits 23:22 Reserved, must be kept at reset value.
Bit 21 RBS: Red Blue Swap
This bit allows to swap the R & B to support BGR or ABGR color formats. Once the
transfer has started, this bit is read-only.
0: Regular mode (RGB or ARGB)
1: Swap mode (BGR or ABGR)
Bit 20 AI: AI: Alpha Inverted
This bit inverts the alpha value. Once the transfer has started, this bit is read-only.
0: Regular alpha
1: Inverted alpha
Bits 19:18 Reserved, must be kept at reset value.
Bits 17:16 AM[1:0]: Alpha mode
These bits define which alpha channel value to be used for the background image.
These bits can only be written when data transfers are disabled. Once the transfer has
started, they are read-only.
00: No modification of the foreground image alpha channel value
01: Replace original background image alpha channel value by ALPHA[7:0]
10: Replace original background image alpha channel value by ALPHA[7:0] multiplied
with original alpha channel value
others: meaningless
Bits 15:8 CS[7:0]: CLUT size
These bits define the size of the CLUT used for the BG. Once the CLUT transfer has
started, this field is read-only.
The number of CLUT entries is equal to CS[7:0] + 1.
Bits 7:6 Reserved, must be kept at reset value.

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Chrom-ART Accelerator controller (DMA2D) RM0432

Bit 5 START: Start

This bit is set to start the automatic loading of the CLUT. This bit is automatically reset:
– at the end of the transfer
– when the transfer is aborted by the user application by setting the ABORT bit in
the DMA2D_CR
– when a transfer error occurs
– when the transfer has not started due to a configuration error or another
transfer operation already on going (data transfer or automatic foreground
CLUT transfer).
Bit 4 CCM: CLUT Color mode
These bits define the color format of the CLUT. This register can only be written when
the transfer is disabled. Once the CLUT transfer has started, this bit is read-only.
0: ARGB8888
1: RGB888
others: meaningless
Bits 3:0 CM[3:0]: Color mode
These bits define the color format of the foreground image. These bits can only be
written when data transfers are disabled. Once the transfer has started, they are read-
only.
0000: ARGB8888
0001: RGB888
0010: RGB565
0011: ARGB1555
0100: ARGB4444
0101: L8
0110: AL44
0111: AL88
1000: L4
1001: A8
1010: A4
others: meaningless

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RM0432 Chrom-ART Accelerator controller (DMA2D)

13.5.11 DMA2D background color register (DMA2D_BGCOLR)

Address offset: 0x0028
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. RED[7:0]

rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GREEN[7:0] BLUE[7:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 RED[7:0]: Red value
These bits define the red value for the A4 or A8 mode of the background. These bits
can only be written when data transfers are disabled. Once the transfer has started,
they are read-only.
Used also for fixed color FG in memory-to-memory with blending and fixed color FG
(BG fetch only with FG and BG PFC active) mode.
Bits 15:8 GREEN[7:0]: Green value
These bits define the green value for the A4 or A8 mode of the background. These bits
can only be written when data transfers are disabled. Once the transfer has started,
they are read-only.
Used also for fixed color FG in memory-to-memory with blending and fixed color FG
(BG fetch only with FG and BG PFC active) mode.
Bits 7:0 BLUE[7:0]: Blue value
These bits define the blue value for the A4 or A8 mode of the background. These bits
can only be written when data transfers are disabled. Once the transfer has started,
they are read-only.
Used also for fixed color FG in memory-to-memory with blending and fixed color FG
(BG fetch only with FG and BG PFC active) mode.

13.5.12 DMA2D foreground CLUT memory address register

(DMA2D_FGCMAR)
Address offset: 0x002C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MA[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MA[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Chrom-ART Accelerator controller (DMA2D) RM0432

Bits 31:0 MA[31:0]: Memory Address

Address of the data used for the CLUT address dedicated to the foreground image. This
register can only be written when no transfer is ongoing. Once the CLUT transfer has
started, this register is read-only.
If the foreground CLUT format is 32-bit, the address must be 32-bit aligned.

13.5.13 DMA2D background CLUT memory address register

(DMA2D_BGCMAR)
Address offset: 0x0030
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MA[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MA[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MA[31:0]: Memory address

Address of the data used for the CLUT address dedicated to the background image.
This register can only be written when no transfer is on going. Once the CLUT transfer
has started, this register is read-only.
If the background CLUT format is 32-bit, the address must be 32-bit aligned.

13.5.14 DMA2D output PFC control register (DMA2D_OPFCCR)

Address offset: 0x0034
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RBS AI Res. Res. Res. Res.

rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. SB Res. Res. Res. Res. Res. Res. CM[2:0]

rw rw rw rw

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RM0432 Chrom-ART Accelerator controller (DMA2D)

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 RBS: Red Blue Swap
This bit allows to swap the R & B to support BGR or ABGR color formats. Once the
transfer has started, this bit is read-only.
0: Regular mode (RGB or ARGB)
1: Swap mode (BGR or ABGR)
Bit 20 AI: Alpha Inverted
This bit inverts the alpha value. Once the transfer has started, this bit is read-only.
0: Regular alpha
1: Inverted alpha
Bits 19:10 Reserved, must be kept at reset value.
Bit 9 SB: Swap Bytes
When set, the bytes in the output FIFO are swapped two by two.
When this bit is set, the number of pixel per line (PL) must be even, and the output
memory address (OMAR) must be even.
This register can only be written when the transfer is disabled. Once the transfer has
started, this register is read-only.
0: Bytes in regular order in the output FIFO
1: Bytes are swapped two by two in the output FIFO
Bits 8:3 Reserved, must be kept at reset value.
Bits 2:0 CM[2: 0]: Color mode
These bits define the color format of the output image. These bits can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.
000: ARGB8888
001: RGB888
010: RGB565
011: ARGB1555
100: ARGB4444
others: meaningless

13.5.15 DMA2D output color register (DMA2D_OCOLR)

Address offset: 0x0038
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ALPHA[7:0] RED[7:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GREEN[7:0] BLUE[7:0]

RED[4:0] GREEN[5:0] BLUE[4:0]

A RED[4:0] GREEN[4:0] BLUE[4:0]

ALPHA[3:0] RED[3:0] GREEN[3:0] BLUE[3:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Chrom-ART Accelerator controller (DMA2D) RM0432

ARGB8888 or RGB888 color mode

Bits 31:24 ALPHA[7:0]: Alpha channel value in ARGB8888 mode otherwise reserved
These bits define the alpha channel of the output color. These bits can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.
Bits 23:16 RED[7:0]: Red value in ARGB8888 or RGB888 mode otherwise reserved
These bits define the red value of the output image. These bits can only be written when
data transfers are disabled. Once the transfer has started, they are read-only.
Bits 15:8 GREEN[7:0]: Green value in ARGB8888 or RGB888
These bits define the green value of the output image. These bits can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.
Bits 7:0 BLUE[7:0]: Blue value in ARGB8888 or RGB888
These bits define the blue value of the output image. These bits can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.
RGB565 color mode
Bits 15:11 RED[4:0]: Red value in RGB565 mode
These bits define the red value of the output image. These bits can only be written when
data transfers are disabled. Once the transfer has started, they are read-only.
Bits 12:5 GREEN[5:0]: Green value in RGB565 mode
These bits define the green value of the output image. These bits can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.
Bits 4:0 BLUE[4:0]: Blue value in RGB565 mode
These bits define the blue value of the output image. These bits can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.
ARGB1555 color mode
Bit 15 A: Alpha channel value in ARGB1555 mode
This bit defines the alpha channel of the output color. This bit can only be written when
data transfers are disabled. Once the transfer has started, it is read-only.
Bits 14:10 RED[4:0]: Red value in ARGB1555 mode
These bits define the red value of the output image. These bits can only be written when
data transfers are disabled. Once the transfer has started, they are read-only.
Bits 9:5 GREEN[4:0]: Green value in ARGB1555 mode
These bits define the green value of the output image. These bits can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.
Bits 4:0 BLUE[4:0]: Blue value in ARGB1555 mode
These bits define the blue value of the output image. These bits can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.
ARGB4444 color mode
Bits 15:12 ALPHA[3:0]: Alpha channel value in ARGB4444
This bit defines the alpha channel of the output color. This bit can only be written when
data transfers are disabled. Once the transfer has started, it is read-only.

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RM0432 Chrom-ART Accelerator controller (DMA2D)

Bits 11:8 RED[3:0]: Red value in ARGB4444 mode

These bits define the red value of the output image. These bits can only be written when
data transfers are disabled. Once the transfer has started, they are read-only.
Bits 7:4 GREEN[3:0]: Green value in ARGB4444 mode
These bits define the green value of the output image. These bits can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.
Bits 3:0 BLUE[3:0]: Blue value in ARGB4444 mode
These bits define the blue value of the output image. These bits can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.

13.5.16 DMA2D output memory address register (DMA2D_OMAR)

Address offset: 0x003C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MA[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MA[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MA[31:0]: Memory Address

Address of the data used for the output FIFO. These bits can only be written when data
transfers are disabled. Once the transfer has started, they are read-only.
The address alignment must match the image format selected e.g. a 32-bit per pixel
format must be 32-bit aligned and a 16-bit per pixel format must be 16-bit aligned.

13.5.17 DMA2D output offset register (DMA2D_OOR)

Address offset: 0x0040
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LO[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 LO[15:0]: Line offset
The line offset used for the output expressed in pixel when the LOM bit is reset and in
byte when the LOM bit is set.
When expressed in pixels, only LO[13:0] is considered, LO[15:14] are ignored.
This value is used for the address generation. It is added at the end of each line to
determine the starting address of the next line.
These bits can only be written when data transfers are disabled. Once data transfer has
started, they become read-only.

13.5.18 DMA2D number of line register (DMA2D_NLR)

Address offset: 0x0044
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. PL[13:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NL[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:16 PL[13:0]: Pixel per lines
Number of pixels per lines of the area to be transferred. These bits can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.
If any of the input image format is 4-bit per pixel, pixel per lines must be even.
Bits 15:0 NL[15:0]: Number of lines
Number of lines of the area to be transferred. These bits can only be written when data
transfers are disabled. Once the transfer has started, they are read-only.

13.5.19 DMA2D line watermark register (DMA2D_LWR)

Address offset: 0x0048
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LW[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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RM0432 Chrom-ART Accelerator controller (DMA2D)

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 LW[15:0]: Line watermark
These bits allow to configure the line watermark for interrupt generation.
An interrupt is raised when the last pixel of the watermarked line has been transferred.
These bits can only be written when data transfers are disabled. Once the transfer has
started, they are read-only.

13.5.20 DMA2D AHB master timer configuration register (DMA2D_AMTCR)

Address offset: 0x004C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DT[7:0] Res. Res. Res. Res. Res. Res. Res. EN

rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:8 DT[7:0]: Dead Time
Dead time value in the AHB clock cycle inserted between two consecutive accesses on
the AHB master port. These bits represent the minimum guaranteed number of cycles
between two consecutive AHB accesses.
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 EN: Enable
Enables the dead time functionality.

13.5.21 DMA2D foreground CLUT (DMA2D_FGCLUT[y])

Address offset: 0x0400 + 4*y, y=0..255
Reset value: 0xXXXX XXXX

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ALPHA<y>[7:0] RED<y>[7:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GREEN<y>[7:0] BLUE<y>[7:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Chrom-ART Accelerator controller (DMA2D) RM0432

Bits 31:24 ALPHA<y>[7:0]: Alpha <y>

Alpha value for index <y> for the foreground.
Bits 23:16 RED<y>[7:0]: Red <y>
Red value for index <y> for the foreground.
Bits 15:8 GREEN<y>[7:0]: Green <y>
Green value for index <y> for the foreground.
Bits 7:0 BLUE<y>[7:0]: Blue <y>
Blue value for index <y> for the foreground.

13.5.22 DMA2D background CLUT (DMA2D_BGCLUT[y])

Address offset: 0x0800 + 4*y, y=0..255
Reset value: 0xXXXX XXXX
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ALPHA<y>[7:0] RED<y>[7:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GREEN<y>[7:0] BLUE<y>[7:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 ALPHA<y>[7:0]: Alpha <y>

Alpha value for index <y> for the background.
Bits 23:16 RED<y>[7:0]: Red <y>
Red value for index <y> for the background.
Bits 15:8 GREEN<y>[7:0]: Green <y>
Green value for index <y> for the background.
Bits 7:0 BLUE<y>[7:0]: Blue <y>
Blue value for index <y> for the background.

450/2301 RM0432 Rev 6

RM0432 Chrom-ART Accelerator controller (DMA2D)

13.5.23 DMA2D register map

The following table summarizes the DMA2D registers. Refer to Section 2.2: Memory
organization for the DMA2D register base address.

Table 73. DMA2D register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
MODE[2:0]

ABORT

START
CTCIE
CAEIE

SUSP
TWIE
CEIE

TCIE
TEIE

LOM
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

Res.

Res.
Res.
Res.
DMA2D_CR
0x0000

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0

CTCIF
CAEIF
TWIF
CEIF

TCIF
TEIF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA2D_ISR
0x0004

Reset value 0 0 0 0 0 0

CCTCIF
CAECIF
CTWIF
CCEIF

CTCIF
CTEIF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA2D_IFCR
0x0008

Reset value 0 0 0 0 0 0
DMA2D_FGMAR MA[31:0]
0x000C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA2D_FGOR LO[15:0]
0x0010
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA2D_BGMAR MA[31:0]
0x0014
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA2D_BGOR LO[15:0]
0x0018
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AM[1:0]

START
CCM
RBS
Res.
Res.

Res.
Res.

Res.
Res.
DMA2D_FGPFCCR ALPHA[7:0] CS[7:0] CM[3:0]
AI

0x001C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA2D_FGCOLR RED[7:0] GREEN[7:0] BLUE[7:0]

0x0020
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AM[1:0]

START
CCM
RBS
Res.
Res.

Res.
Res.

Res.
Res.

DMA2D_BGPFCCR ALPHA[7:0] CS[7:0] CM[3:0]

AI

0x0024

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA2D_BGCOLR RED[7:0] GREEN[7:0] BLUE[7:0]

0x0028
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA2D_FGCMAR MA[31:0]
0x002C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA2D_BGCMAR MA[31:0]
0x0030
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RBS
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

DMA2D_OPFCCR CM[2:0]
SB
AI

0x0034
Reset value 0 0 0 0 0 0

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Chrom-ART Accelerator controller (DMA2D) RM0432

Table 73. DMA2D register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
ALPHA[7:0] RED[7:0] GREEN[7:0] BLUE[7:0]

Res. Res. Res.

Res. Res. Res.
Res. Res. Res.
Res. Res. Res.
Res. Res. Res.
Res. Res. Res.
Res. Res. Res.
Res. Res. Res.
Res. Res. Res.
Res. Res. Res.
Res. Res. Res.
Res. Res. Res.
Res. Res. Res.
Res. Res. Res.
Res. Res. Res.
Res. Res. Res.
RED[4:0] GREEN[5:0] BLUE[4:0]
DMA2D_OCOLR
0x0038 A RED[4:0] GREEN[4:0] BLUE[4:0]

ALPHA[3:0] RED[3:0] GREEN[3:0] BLUE[3:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA2D_OMAR MA[31:0]
0x003C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA2D_OOR LO[15:0]
0x0040
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.

DMA2D_NLR PL[13:0] NL[15:0]

0x0044
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA2D_LWR LW[15:0]
0x0048
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA2D_AMTCR DT[7:0]

EN
0x004C
Reset value 0 0 0 0 0 0 0 0 0
0x0050-
Reserved Reserved
0x03FC

0x0400- DMA2D_FGCLUT ALPHA<y>[7:0] RED<y>[7:0] GREEN<y>[7:0] BLUE<y>[7:0]

0x07FC Reset value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X

0x0800- DMA2D_BGCLUT ALPHA<y>[7:0] RED<y>[7:0] GREEN<y>[7:0] BLUE<y>[7:0]

0x0BFC Reset value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X

Refer to Section 2.2 on page 91 for the register boundary addresses.

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14 Chrom-GRC™ (GFXMMU)

14.1 Introduction
The graphic MMU is a graphical oriented memory management unit aimed to optimize
memory usage according to the display shape.

14.2 Chrom-GRC™ main features

• Fully programmable display shape to physically store only the visible pixel
• Up to 4 virtual buffer
• Each virtual buffer have 3072 or 4096 bytes per line and 1024 lines
• Each virtual buffer can be physically mapped to any system memory
• Interrupt in case of buffer overflow (1 per buffer)
• Interrupt in case of memory transfer error

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14.3 Chrom-GRC™ functional and architectural description

The graphic MMU is responsible of address resolution to convert the virtual buffer address
into the physical buffer address.

Figure 38. Chrom-GRC™ block diagram

AHBSlaveAdd[23:0]

Status
registers
MMU
Control
registers

Add[23:22]

PhyAdd[22:0]
pBuffer3AddMSB[31:23]

pBuffer2AddMSB[31:23]

pBuffer1AddMSB[31:23]

pBuffer0AddMSB[31:23]

AHBMasterAdd[31:0]
MSv41698V1

14.3.1 Virtual memory

The graphic MMU provides a virtual memory space seen by all the system masters. This
virtual memory space is divided into four virtual buffers.

Virtual buffer
A virtual buffer is seen by any system master as a continuous memory space representing a
virtual frame buffer of 1024 lines.
Each line is divided into 192 or 256 16-byte blocks depending on the 192BM bit of the
graphic MMU configuration register (GFXMMU_CR).
Depending on the display shape and size, only the necessary blocks will be mapped to a
physical memory location. This mapping is done programming the LUT entry for each line:
• The enable of the line
• The number of the first “visible” block
• The number of the last “visible” block
• The address offset of the line within the physical buffer
The “visible” blocks can be arranged in the physical buffer in a continuous way programming
the address offset of each line.
The LUT is common to all the buffers i.e. all the buffers have the same “shape”.

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Figure 39. Virtual buffer

16-byte block Out screen block
192/256 blocks (3072/4096 Byte)
Line N first block on screen
Line N+1 last
block on screen
Virtual buffer
Configuration

1024 lines
192/256 x 16-byte blocks per line
1024 lines

Continuous memory locations

Physical buffer

Line N first block on Line N last block Line N+1 first Line N+1 last
screen on screen block on screen block on screen
MSv43800V1

Virtual buffer overview

For a frame buffer coded in 32bpp or 16bpp, the virtual buffer can be configured to have 192
or 256 blocks. This will result in a virtual frame buffer of 768 x 1024 or 1024 x 1024 pixels for
32bpp and 1536 x 1024 or 2048 x 1024 for 16bpp.
For a frame buffer coded in 24bpp, the virtual buffer shall be configured to have 192 blocks
to have an integer number of pixel per lines. This will result in a virtual frame buffer of
1024 x 1024 pixels for 24bpp.
Each buffer can be physically mapped anywhere in the physical memory thanks to:
• The physical buffer base address (PBBA) field of the graphic MMU buffer x
configuration register (GFXMMU_BxCR). It configures the physical location of the
8 MByte area where the buffer is mapped.
• The physical buffer location respective to the physical buffer base address is defined by
the physical buffer offset (PBO) field of the graphic MMU buffer x configuration register
(GFXMMU_BxCR).

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Figure 40. Virtual buffer and physical buffer memory map

Physical buffer

Virtual buffer
0xFF:FFFF
pBuffer3
0xDF:FFFF
0xYY:Y000 Physical buffer 3 offset
Virtual buffer 3
(3/4 Mbyte)
0xXX00:0000 Physical buffer 3 base address

0xC0:0000

0xAF:FFFF
pBuffer2
Virtual buffer 2 0xYY:Y000 Physical buffer 2 offset
(3/4 Mbyte)

0xXX00:0000 Physical buffer 2 base address

0x80:0000

0x6F:FFFF
Virtual buffer 1
(3/4 Mbyte)
pBuffer1
0xYY:Y000 Physical buffer 1 offset
0x40:0000
0xXX00:0000 Physical buffer 1 base address
0x2F:FFFF
Virtual buffer 0
(3/4 Mbyte)

pBuffer0
0x00:0000 0xYY:Y000 Physical buffer 0 offset

0xXX00:0000 Physical buffer 0 base address

MSv43801V2

The buffer can not overflow the 8 MByte boundary of the zone defined by its base address.
In case of overflow, the buffer x overflow flag (BxOF) of the graphic MMU status register
(GFXMMU_SR) is set and an interrupt is generated if the buffer x overflow interrupt enable
(BxOIE) bit of the graphic MMU configuration register (GFXMMU_CR) is set.

Virtual buffer application use case

As the physical locations are independently configurable, the four virtual buffers can be
physically mapped to non continuous locations. This would allow for example to have the
four buffers mapped on to four different SDRAM banks and avoid extra precharge cycles
accessing the SDRAM.
As a consequence, one buffer shall be used by the CPU/ChromART® for frame buffer
calculation while an other one shall be used by the LTDC.
The two remaining buffers can be used as a graphical library requiring extra drawing
buffers.

14.3.2 MMU architecture

The MMU block is responsible of the address resolution. It receives the 24-bit address and
returns the physical 23-bit address and a valid signals to indicate the address is physically
mapped or not. The MMU also checks overflow of a area boundary.

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The MMU LUT is implemented as a 1024 x 35-bit RAM

Figure 41. MMU block diagram

Block[7:0]
Line/block
Add[21:4] [21:4]
decoder +
Block0Offset[21:4] Overflow
Line[9:0] C
LookUp LineEnable
RAM + PhyAdd[22:4]
FirstBlock[7:0]
Add[23:4] Block Valid
1024 x 35-bit valid
LastBlock[7:0]
comp.

Add[23:22] pBufferOffset[22:4]
pBufferOffset

MSv43802V1

Line block decoder

The line block decoder is generating the block number and the line number according the
address.

Look up RAM
The look up RAM is a 1024 x 35-bit RAM with the following fields:
• 1-bit line enable
• 8-bit first valid block
• 8-bit last valid block
• 18-bit for line offset
As the RAM is bigger than a word, each entry is split into two words on the memory map.
The write access are done in two steps:
1. Write the first word with enable/first valid block/last valid block in the GFXMMU_LUTxL
memory location (internally buffered)
2. Write the second word with line offset in the GFXMMU_LUTxH memory location
(effective write into the memory together with the internally buffered value)
A write in the LUT can happen any time but it can lead to inconsistencies if a master is using
the MMU at the same time. As the CPU has the priority during LUT programming, this may
slow down MMU calculation.
There is no restriction during read operations, but this may slow down CPU as the MMU has
the priority on LUT accesses.

Block validation/comparator
This block is checking is the block is valid.

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A block is considered as valid i.e. physically mapped when

• Line is enable
• The block number is greater or equal to the first valid block
• The block number is lower or equal to the last valid block
When the block is valid, the physical address generated is considered as correct.
If the result of the MMU evaluation is not valid, the write operations are ignored, and read
operations return the default 32-bit value stored in the default value (DV) field of the graphic
MMU default value register (GFXMMU_DVR).

Block offset address calculation within the buffer

The block number is added to the line offset to get the offset of the block within the physical
buffer.
As a consequence, the line offset stored in the LUT is given by the following formula:
Line offset = [(Number of visible blocks already used) - (1st visible block)] x block size
with:
• The maximum value for the line offset is when all the block of all the line are used. As
the consequence the line offset for the last line can be maximum:
1023 x 256 x 6 = 0x3F:F00x
• The minimum value for the line offset is when the last block of the first line is the first
valid block: -255*16 = - 0xFFx i.e 0x3F:F01x
As the consequence the full range of the line offset entry of the LUT is used.
Carry is not taken into account as this stage to be able to perform negative offset
calculations (values from 0x3F:F01x to 0x3F:FFFx)
As the block offset is within a 4 MByte buffer, the address generated is 22-bit wide.

Block offset address calculation

Once the offset of the block within the buffer as been calculated, this value is added to the
offset of the block respective to the physical buffer base address.
The offset of the blocks are defined in registers as shown

Figure 42. Block validation/comparator implementation

Add[23:22] PBufferOffset

pBuffer0Offset[22:4]

pBuffer1Offset[22:4] pBufferOffset[22:4]
pBuffer2Offset[22:4]

pBuffer3Offset[22:4]

MSv43803V1

The resulting address and the buffer offset address shall be on 23-bit.
The carry is taken into account to trigger address overflow. The carry is propagated to the
graphic MMU status register (GFXMMU_SR) to set the buffer x overflow flag (BxOF).

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Example of calculation
We are considering the following configuration for virtual buffer 0
• First visible block of line 0: block 7
• Number of visible block in line 0: 10
• First visible block of line 1: block 6
• Number of visible block in line 1: 12
• Address of the physical buffer: 0xC020:0000
The configuration shall be:
• The base address of the physical buffer 0: 0xC000:0000
• The offset of buffer 0: 0x20:0000
• First visible block of line 0: block 7
• Last visible block of line 0: block 16
• Block 0 offset of line 0: (0 - 7) x 0x10 = -0x70 = 0x3F:FF90
• First visible block of line 1: block 6
• Last visible block of line 1: block 17
• Block 0 offset of line 1: (10 - 6) x 0x10 = (0xA - 0x6) x 0x10 = 0x40
As a consequence:
• the physical address of block 7 of line 0 is:
0xC000:0000 + 0x20:0000 + (0x3F:FF90 + 0x70 without carry) = 0xC020:0000
• the physical address of block 16 of line 0 is:
0xC000:0000 + 0x20:0000 + (0x3F:FF90 + 0x100 without carry) = 0xC020:0090
• the physical address of block 6 of line 1 is:
0xC000:0000 + 0x20:0000 + (0x40 + 0x60 without carry) = 0xC020:00A0
• the physical address of block 17 of line 1 is:
0xC000:0000 + 0x20:0000 + (0x40 + 0x110 without carry) = 0xC020:0150

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14.4 Graphic MMU interrupts

An interrupt can be produced on the following events:
• Buffer 0 overflow
• Buffer 1 overflow
• Buffer 2 overflow
• Buffer 3 overflow
• AHB master error
Separate interrupt enable bits are available for flexibility.

Table 74. Graphic MMU interrupt requests

Interrupt event Event flag Enable control bit

Buffer 0 overflow B0OF B0OIE

Buffer 1 overflow B1OF B1OIE
Buffer 2 overflow B2OF B2OIE
Buffer 3 overflow B3OF B3OIE
AHB master error AMEF AMEIE

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14.5 Graphic MMU registers

14.5.1 Graphic MMU configuration register (GFXMMU_CR)

Address offset: 0x0000
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. 192BM Res. AMEIE B3OIE B2OIE B1OIE B0OIE
rw rw rw rw rw rw

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 192BM: 192 Block mode
This bit defines the number of blocks per line
0: 256 blocks per line
1: 192 blocks per line
Bit 5 Reserved, must be kept at reset value.
Bit 4 AMEIE: AHB master error interrupt enable
This bit enables the AHB master error interrupt.
0: Interrupt disable
1: Interrupt enabled
Bit 3 B3OIE: Buffer 3 overflow interrupt enable
This bit enables the buffer 3 overflow interrupt.
0: Interrupt disable
1: Interrupt enabled
Bit 2 B2OIE: Buffer 2 overflow interrupt enable
This bit enables the buffer 2 overflow interrupt.
0: Interrupt disable
1: Interrupt enabled
Bit 1 B1OIE: Buffer 1 overflow interrupt enable
This bit enables the buffer 1 overflow interrupt.
0: Interrupt disable
1: Interrupt enabled
Bit 0 B0OIE: Buffer 0 overflow interrupt enable
This bit enables the buffer 0 overflow interrupt.
0: Interrupt disable
1: Interrupt enabled

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14.5.2 Graphic MMU status register (GFXMMU_SR)

Address offset: 0x0004
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AMEF B3OF B2OF B1OF B0OF
r r r r r

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 AMEF: AHB master error flag
This bit is set when an AHB error happens during a transaction. It is cleared by writing 1
to CAMEF.
Bit 3 B3OF: Buffer 3 overflow flag
This bit is set when an overflow occurs during the offset calculation of the buffer 3. It is
cleared by writing 1 to CB3OF.
Bit 2 B2OF: Buffer 2 overflow flag
This bit is set when an overflow occurs during the offset calculation of the buffer 2. It is
cleared by writing 1 to CB2OF.
Bit 1 B1OF: Buffer 1 overflow flag
This bit is set when an overflow occurs during the offset calculation of the buffer 1. It is
cleared by writing 1 to CB1OF.
Bit 0 B0OF: Buffer 0 overflow flag
This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is
cleared by writing 1 to CB0OF.

14.5.3 Graphic MMU flag clear register (GFXMMU_FCR)

Address offset: 0x0008
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CAMEF CB3OF CB2OF CB1OF CB0OF
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 CAMEF: Clear AHB master error flag
Writing 1 clears the AHB master error flag in the GFXMMU_SR register.
Bit 3 CB3OF: Clear buffer 3 overflow flag
Writing 1 clears the buffer 3 overflow flag in the GFXMMU_SR register.

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Bit 2 CB2OF: Clear buffer 2 overflow flag

Writing 1 clears the buffer 2 overflow flag in the GFXMMU_SR register.
Bit 1 CB1OF: Clear buffer 1 overflow flag
Writing 1 clears the buffer 1 overflow flag in the GFXMMU_SR register.
Bit 0 CB0OF: Clear buffer 0 overflow flag
Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register.

14.5.4 Graphic MMU default value register (GFXMMU_DVR)

Address offset: 0x0010
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DV[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DV[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 DV[31:0]: Default value

This field indicates the default 32-bit value which is returned when a master accesses a
virtual memory location not physically mapped.

14.5.5 Graphic MMU buffer 0 configuration register (GFXMMU_B0CR)

Address offset: 0x0020
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBBA[31:23] PBO[22:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBO[15:4] Res. Res. Res. Res.
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:23 PBBA[31:23]: Physical buffer base address

Base address MSB of the physical buffer.
Bits 22:4 PBO[22:4]: Physical buffer offset
Offset of the physical buffer.
Bits 3:0 Reserved, must be kept at reset value.

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14.5.6 Graphic MMU buffer 1 configuration register (GFXMMU_B1CR)

Address offset: 0x0024
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBBA[31:23] PBO[22:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBO[15:4] Res. Res. Res. Res.
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:23 PBBA[31:23]: Physical buffer base address

Base address MSB of the physical buffer.
Bits 22:4 PBO[22:4]: Physical buffer offset
Offset of the physical buffer.
Bits 3:0 Reserved, must be kept at reset value.

14.5.7 Graphic MMU buffer 2 configuration register (GFXMMU_B2CR)

Address offset: 0x0028
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBBA[31:23] PBO[22:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBO[15:4] Res. Res. Res. Res.
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:23 PBBA[31:23]: Physical buffer base address

Base address MSB of the physical buffer.
Bits 22:4 PBO[22:4]: Physical buffer offset
Offset of the physical buffer.
Bits 3:0 Reserved, must be kept at reset value.

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14.5.8 Graphic MMU buffer 3 configuration register (GFXMMU_B3CR)

Address offset: 0x002C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBBA[31:23] PBO[22:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBO[15:4] Res. Res. Res. Res.
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:23 PBBA[31:23]: Physical buffer base address

Base address MSB of the physical buffer.
Bits 22:4 PBO[22:4]: Physical buffer offset
Offset of the physical buffer.
Bits 3:0 Reserved, must be kept at reset value.

14.5.9 Graphic MMU LUT entry x low (GFXMMU_LUTxL)

Address offset: 0x1000 + 8 * x, x = 0...1023
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. LVB[7:0]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB[7:0] Res. Res. Res. Res. Res. Res. Res. EN
rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 LVB[7:0]: Last Valid Block
Number of the last valid block of line number X.
Bits 15:8 FVB[7:0]: First Valid Block
Number of the first valid block of line number x.
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 EN: Enable
Line enable.
0: Line is disabled (no MMU evaluation is performed)
1: Line is enabled (MMU evaluation is performed)

14.5.10 Graphic MMU LUT entry x high (GFXMMU_LUTxH)

Address offset: 0x1000 + 8 * x + 4, x = 0...1023
Reset value: 0x0000 0000

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LO[21:16]
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO[15:4] Res. Res. Res. Res.
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:22 Reserved, must be kept at reset value.

Bits 21:4 LO[21:4]: Line offset
Line offset of line number x (i.e. offset of block 0 of line x)
Bits 3:0 Reserved, must be kept at reset value.

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 0x1004
0x1000
0x0030
0x0028
0x0024
0x0020
0x0014
0x0010
0x0008
0x0004
0x0000

0x2FF8
0x0FF0
0x000C

0x002C
0x001C

0x2FFC
0x0FEC
Offset
RM0432

14.5.11

LUT0L

LUT0H
Reserved
Reserved
Reserved

LUT1023L

LUT1023H
GFXMMU_
GFXMMU_
GFXMMU_
GFXMMU_
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

GFXMMU_SR
GFXMMU_CR

GFXMMU_FCR

GFXMMU_DVR

GFXMMU_B3CR
GFXMMU_B2CR
GFXMMU_B1CR
GFXMMU_B0CR

0
0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31

0
0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30

0
0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29

0
0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28

0
0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27

0
0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26

PBBA[31:23]
PBBA[31:23]
PBBA[31:23]
PBBA[31:23]

0
0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25

0
0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24

0
0
0
0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. 23

0
0
0
0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. 22
Graphic MMU register map

0
0
0
0
0
0
0
0
0
Res. Res. Res. Res. Res. Res. 21

0
0
0
0
0
0
0
0
0
Res. Res. Res. Res. Res. Res. 20

...

0
0
0
0
0
0
0
0
0
Res. Res. Res. Res. Res. Res. 19

LVB[7:0]
LVB[7:0]

0
0
0
0
0
0
0
0
0
Res. Res. Res. Res. Res. Res. 18

0
0
0
0
0
0
0
0
0
Res. Res. Res. Res. Res. Res.

RM0432 Rev 6
17

0
0
0
0
0
0
0
0
Res. Res. 0 Res. Res. Res. Res. 16

0
0
0
0
0
0
0
0
0
Res. Res. Res. Res. Res. Res. 15
DV[31:0]

0
0
0
0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. 14

0
0
0
0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. 13

0
0
0
0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. 12

PBO[22:4]
PBO[22:4]
PBO[22:4]
PBO[22:4]
addresses table for the graphic MMU register base address.

LO[21:4]
LO[21:4]

0
0
0
0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. 11

FVB[7:0]
FVB[7:0]

0
0
0
0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. 10

0
0
0
0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. 9

Table 75. Graphic MMU register map and reset values

Refer to Section 2.2 on page 91 for the register boundary addresses.

0
0
0
0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. 8

0
0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 7

0
0
0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 192BM 6

0
0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 5

0
0
0
0
0
0
0
0
0
0

Res. Res. Res. Res. Res. CAMEF AMEF AMEIE 4

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CB3OF B3OF B3OIE 3
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CB2OF B2OF B2OIE 2
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CB1OF B1OF B1OIE 1
The following table summarizes the graphic MMU registers. Refer to the register boundary

0
0
0
0
0

Res. EN Res. EN Res. Res. Res. Res. Res. Res. Res. CB0OF B0OF B0OIE 0
Chrom-GRC™ (GFXMMU)

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15 Nested vectored interrupt controller (NVIC)

15.1 NVIC main features

• 95 maskable interrupt channels (not including the sixteen Cortex®-M4 with FPU
interrupt lines)
• 16 programmable priority levels (4 bits of interrupt priority are used)
• Low-latency exception and interrupt handling
• Power management control
• Implementation of System Control Registers
The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming, refer to the PM0214 programming manual for
CortexTM-M4 products.

15.2 SysTick calibration value register

The SysTick calibration value is set to 0x4000 3A97, which gives a reference time base of
1 ms with the SysTick clock set to 15 MHz (max fHCLK/8).

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RM0432 Nested vectored interrupt controller (NVIC)

15.3 Interrupt and exception vectors

The gray rows in Table 76 describe the vectors without specific position.

Table 76. STM32L4Rxxx and STM32L4Sxxx vector table

Position

Priority

Type of
Acronym Description Address
priority

- - - - Reserved 0x0000 0000

- -3 fixed Reset Reset 0x0000 0004
Non maskable interrupt. The RCC Clock
- -2 fixed NMI Security System (CSS) is linked to the NMI 0x0000 0008
vector.
- -1 fixed HardFault All classes of fault 0x0000 000C
- 0 settable MemManage Memory management 0x0000 0010
- 1 settable BusFault Pre-fetch fault, memory access fault 0x0000 0014
- 2 settable UsageFault Undefined instruction or illegal state 0x0000 0018
0x0000 001C -
- - - - Reserved
0x0000 0028
- 3 settable SVCall System service call via SWI instruction 0x0000 002C
- 4 settable Debug Monitor Debug Monitor 0x0000 0030
- - - - Reserved 0x0000 0034
- 5 settable PendSV Pendable request for system service 0x0000 0038
- 6 settable SysTick System tick timer 0x0000 003C
0 7 settable WWDG Window Watchdog interrupt 0x0000 0040

PVD/PVM1/PVM2/PVM3/PVM4 through EXTI

1 8 settable PVD_PVM 0x0000 0044
lines 16/35/36/37/38 interrupts
RTC_TAMP_STAMP RTC Tamper or TimeStamp /CSS on LSE
2 9 settable 0x0000 0048
/CSS_LSE through EXTI line 19 interrupts

RTC Wakeup timer through EXTI line 20

3 10 settable RTC_WKUP 0x0000 004C
interrupt
4 11 settable FLASH Flash global interrupt 0x0000 0050
5 12 settable RCC RCC global interrupt 0x0000 0054
6 13 settable EXTI0 EXTI Line0 interrupt 0x0000 0058
7 14 settable EXTI1 EXTI Line1 interrupt 0x0000 005C
8 15 settable EXTI2 EXTI Line2 interrupt 0x0000 0060
9 16 settable EXTI3 EXTI Line3 interrupt 0x0000 0064
10 17 settable EXTI4 EXTI Line4 interrupt 0x0000 0068
11 18 settable DMA1_CH1 DMA1 channel 1 interrupt 0x0000 006C

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Table 76. STM32L4Rxxx and STM32L4Sxxx vector table (continued)

Position

Priority
Type of
Acronym Description Address
priority

12 19 settable DMA1_CH2 DMA1 channel 2 interrupt 0x0000 0070

13 20 settable DMA1_CH3 DMA1 channel 3 interrupt 0x0000 0074
14 21 settable DMA1_CH4 DMA1 channel 4 interrupt 0x0000 0078
15 22 settable DMA1_CH5 DMA1 channel 5 interrupt 0x0000 007C
16 23 settable DMA1_CH6 DMA1 channel 6 interrupt 0x0000 0080
17 24 settable DMA1_CH7 DMA1 channel 7 interrupt 0x0000 0084
18 25 settable ADC1 ADC1 global interrupt 0x0000 0088
19 26 settable CAN1_TX CAN1_TX interrupts 0x0000 008C
20 27 settable CAN1_RX0 CAN1_RX0 interrupts 0x0000 0090
21 28 settable CAN1_RX1 CAN1_RX1 interrupt 0x0000 0094
22 29 settable CAN1_SCE CAN1_SCE interrupt 0x0000 0098
23 30 settable EXTI9_5 EXTI Line[9:5] interrupts 0x0000 009C
24 31 settable TIM1_BRK/TIM15 TIM1 Break/TIM15 global interrupts 0x0000 00A0
25 32 settable TIM1_UP/TIM16 TIM1 Update/TIM16 global interrupts 0x0000 00A4
TIM1_TRG_COM TIM1 trigger and commutation/TIM17
26 33 settable 0x0000 00A8
/TIM17 interrupts
27 34 settable TIM1_CC TIM1 capture compare interrupt 0x0000 00AC
28 35 settable TIM2 TIM2 global interrupt 0x0000 00B0
29 36 settable TIM3 TIM3 global interrupt 0x0000 00B4
30 37 settable TIM4 TIM4 global interrupt 0x0000 00B8
31 38 settable I2C1_EV I2C1 event interrupt 0x0000 00BC
32 39 settable I2C1_ER I2C1 error interrupt 0x0000 00C0
33 40 settable I2C2_EV I2C2 event interrupt 0x0000 00C4
34 41 settable I2C2_ER I2C2 error interrupt 0x0000 00C8
35 42 settable SPI1 SPI1 global interrupt 0x0000 00CC
36 43 settable SPI2 SPI2 global interrupt 0x0000 00D0
37 44 settable USART1 USART1 global interrupt 0x0000 00D4
38 45 settable USART2 USART2 global interrupt 0x0000 00D8
39 46 settable USART3 USART3 global interrupt 0x0000 00DC
40 47 settable EXTI15_10 EXTI Line[15:10] interrupts 0x0000 00E0
41 48 settable RTC_ALARM RTC alarms through EXTI line 18 interrupts 0x0000 00E4
42 49 settable DFSDM1_FLT3 DFSDM1_FLT3 global interrupt 0x0000 00E8
43 50 settable TIM8_BRK TIM8 Break interrupt 0x0000 00EC

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RM0432 Nested vectored interrupt controller (NVIC)

Table 76. STM32L4Rxxx and STM32L4Sxxx vector table (continued)

Position

Priority
Type of
Acronym Description Address
priority

44 51 settable TIM8_UP TIM8 Update interrupt 0x0000 00F0

45 52 settable TIM8_TRG_COM TIM8 trigger and commutation interrupt 0x0000 00F4
46 53 settable TIM8_CC TIM8 capture compare interrupt 0x0000 00F8
47 54 settable Reserved Reserved 0x0000 00FC
48 55 settable FMC FMC global interrupt 0x0000 0100
49 56 settable SDMMC1 SDMMC1 global interrupt 0x0000 0104
50 57 settable TIM5 TIM5 global interrupt 0x0000 0108
51 58 settable SPI3 SPI3 global interrupt 0x0000 010C
52 59 settable UART4 UART4 global interrupt 0x0000 0110
53 60 settable UART5 UART5 global interrupt 0x0000 0114
54 61 settable TIM6_DACUNDER TIM6 global and DAC1 underrun interrupts 0x0000 0118
55 62 settable TIM7 TIM7 global interrupt 0x0000 011C
56 63 settable DMA2_CH1 DMA2 channel 1 interrupt 0x0000 0120
57 64 settable DMA2_CH2 DMA2 channel 2 interrupt 0x0000 0124
58 65 settable DMA2_CH3 DMA2 channel 3 interrupt 0x0000 0128
59 66 settable DMA2_CH4 DMA2 channel 4 interrupt 0x0000 012C
60 67 settable DMA2_CH5 DMA2 channel 5 interrupt 0x0000 0130
61 68 settable DFSDM1_FLT0 DFSDM1_FLT0 global interrupt 0x0000 0134
62 69 settable DFSDM1_FLT1 DFSDM1_FLT1 global interrupt 0x0000 0138
63 70 settable DFSDM1_FLT2 DFSDM1_FLT2 global interrupt 0x0000 013C
COMP1/COMP2 through EXTI lines 21/22
64 71 settable COMP 0x0000 0140
interrupts
65 72 settable LPTIM1 LPTIM1 global interrupt 0x0000 0144
66 73 settable LPTIM2 LPTIM2 global interrupt 0x0000 0148
67 74 settable OTG_FS OTG_FS global interrupt 0x0000 014C
68 75 settable DMA2_CH6 DMA2 channel 6 interrupt 0x0000 0150
69 76 settable DMA2_CH7 DMA2 channel 7 interrupt 0x0000 0154
70 77 settable LPUART1 LPUART1 global interrupt 0x0000 0158
71 78 settable OCTOSPI1 OCTOSPI1 global interrupt 0x0000 015C
72 79 settable I2C3_EV I2C3 event interrupt 0x0000 0160
73 80 settable I2C3_ER I2C3 error interrupt 0x0000 0164
74 81 settable SAI1 SAI1 global interrupt 0x0000 0168
75 82 settable SAI2 SAI2 global interrupt 0x0000 016C

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Table 76. STM32L4Rxxx and STM32L4Sxxx vector table (continued)

Position

Priority
Type of
Acronym Description Address
priority

76 83 settable OCTOSPI2 OCTOSPI2 global interrupt 0x0000 0170

77 84 settable TSC TSC global interrupt 0x0000 0174
78 85 settable DSIHSOT DSI global interrupt 0x0000 0178
79 86 settable AES AES global interrupt 0x0000 017C
80 87 settable RNG RNG global interrupt 0x0000 0180
81 88 settable FPU Floating point interrupt 0x0000 0184
82 89 settable HASH and CRS HASH and CRS interrupt 0x0000 0188
83 90 settable I2C4_ER I2C4 error interrupt 0x0000 018C
84 91 settable I2C4_EV I2C4 event interrupt 0x0000 0190
85 92 settable DCMI DCMI global interrupt 0x0000 0194
86 93 settable Reserved Reserved 0x0000 0198
87 94 settable Reserved Reserved 0x0000 019C
88 95 settable Reserved Reserved 0x0000 01A0
89 96 settable Reserved Reserved 0x0000 01A4
90 97 settable DMA2D DMA2D global interrupt 0x0000 01A8
91 98 settable LCD-TFT LTDC global interrupt 0x0000 019C
92 99 settable LCD-TFT_ER LTDC global error interrupt 0x0000 01A0
93 100 settable GFXMMU GFXMMU global error interrupt 0x0000 01A4
94 101 settable DMAMUX1_OVR DMAMUX Overrun interrupt 0x0000 01A8

Table 77. STM32L4P5xx and STM32Q5xx vector table

Position

Priority

Type of
Acronym Description Address
priority

- - - - Reserved 0x0000 0000

- -3 fixed Reset Reset 0x0000 0004
Non maskable interrupt. The RCC Clock
- -2 fixed NMI Security System (CSS) is linked to the NMI 0x0000 0008
vector.

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RM0432 Nested vectored interrupt controller (NVIC)

Table 77. STM32L4P5xx and STM32Q5xx vector table (continued)

Position

Priority

Type of
Acronym Description Address
priority

- -1 fixed HardFault All classes of fault 0x0000 000C

- 0 settable MemManage Memory management 0x0000 0010
- 1 settable BusFault Pre-fetch fault, memory access fault 0x0000 0014
- 2 settable UsageFault Undefined instruction or illegal state 0x0000 0018
0x0000 001C -
- - - - Reserved
0x0000 0028
- 3 settable SVCall System service call via SWI instruction 0x0000 002C
- 4 settable Debug Monitor Debug Monitor 0x0000 0030
- - - - Reserved 0x0000 0034
- 5 settable PendSV Pendable request for system service 0x0000 0038
- 6 settable SysTick System tick timer 0x0000 003C
0 7 settable WWDG Window Watchdog interrupt 0x0000 0040
PVD/PVM1/PVM2/PVM3/PVM4 through
1 8 settable PVD_PVM EXTI 0x0000 0044
lines 16/35/36/37/38 interrupts
RTC_TAMP_STAMP RTC Tamper or TimeStamp /CSS on LSE
2 9 settable 0x0000 0048
/CSS_LSE through EXTI line 19 interrupts
RTC Wakeup timer through EXTI line 20
3 10 settable RTC_WKUP 0x0000 004C
interrupt
4 11 settable FLASH Flash global interrupt 0x0000 0050
5 12 settable RCC RCC global interrupt 0x0000 0054
6 13 settable EXTI0 EXTI Line0 interrupt 0x0000 0058
7 14 settable EXTI1 EXTI Line1 interrupt 0x0000 005C
8 15 settable EXTI2 EXTI Line2 interrupt 0x0000 0060
9 16 settable EXTI3 EXTI Line3 interrupt 0x0000 0064
10 17 settable EXTI4 EXTI Line4 interrupt 0x0000 0068
11 18 settable DMA1_CH1 DMA1 channel 1 interrupt 0x0000 006C
12 19 settable DMA1_CH2 DMA1 channel 2 interrupt 0x0000 0070
13 20 settable DMA1_CH3 DMA1 channel 3 interrupt 0x0000 0074
14 21 settable DMA1_CH4 DMA1 channel 4 interrupt 0x0000 0078
15 22 settable DMA1_CH5 DMA1 channel 5 interrupt 0x0000 007C
16 23 settable DMA1_CH6 DMA1 channel 6 interrupt 0x0000 0080

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Nested vectored interrupt controller (NVIC) RM0432

Table 77. STM32L4P5xx and STM32Q5xx vector table (continued)

Position

Priority

Type of
Acronym Description Address
priority

17 24 settable DMA1_CH7 DMA1 channel 7 interrupt 0x0000 0084

18 25 settable ADC1_2 ADC1 and ADC2 global interrupt 0x0000 0088
19 26 settable CAN1_TX CAN1_TX interrupts 0x0000 008C
20 27 settable CAN1_RX0 CAN1_RX0 interrupts 0x0000 0090
21 28 settable CAN1_RX1 CAN1_RX1 interrupt 0x0000 0094
22 29 settable CAN1_SCE CAN1_SCE interrupt 0x0000 0098
23 30 settable EXTI9_5 EXTI Line[9:5] interrupts 0x0000 009C
24 31 settable TIM1_BRK/TIM15 TIM1 Break/TIM15 global interrupts 0x0000 00A0
25 32 settable TIM1_UP/TIM16 TIM1 Update/TIM16 global interrupts 0x0000 00A4
TIM1_TRG_COM/TIM TIM1 trigger and commutation/TIM17
26 33 settable 0x0000 00A8
17 interrupts
27 34 settable TIM1_CC TIM1 capture compare interrupt 0x0000 00AC
28 35 settable TIM2 TIM2 global interrupt 0x0000 00B0
29 36 settable TIM3 TIM3 global interrupt 0x0000 00B4
30 37 settable TIM4 TIM4 global interrupt 0x0000 00B8
31 38 settable I2C1_EV I2C1 event interrupt 0x0000 00BC
32 39 settable I2C1_ER I2C1 error interrupt 0x0000 00C0
33 40 settable I2C2_EV I2C2 event interrupt 0x0000 00C4
34 41 settable I2C2_ER I2C2 error interrupt 0x0000 00C8
35 42 settable SPI1 SPI1 global interrupt 0x0000 00CC
36 43 settable SPI2 SPI2 global interrupt 0x0000 00D0
37 44 settable USART1 USART1 global interrupt 0x0000 00D4
38 45 settable USART2 USART2 global interrupt 0x0000 00D8
39 46 settable USART3 USART3 global interrupt 0x0000 00DC
40 47 settable EXTI15_10 EXTI Line[15:10] interrupts 0x0000 00E0
RTC alarms or SSRU through EXTI line 18
41 48 settable RTC_ALARM_SSRU 0x0000 00E4
interrupts
42 49 settable Reserved Reserved 0x0000 00E8
43 50 settable TIM8_BRK TIM8 Break interrupt 0x0000 00EC
44 51 settable TIM8_UP TIM8 Update interrupt 0x0000 00F0
45 52 settable TIM8_TRG_COM TIM8 trigger and commutation interrupt 0x0000 00F4

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RM0432 Nested vectored interrupt controller (NVIC)

Table 77. STM32L4P5xx and STM32Q5xx vector table (continued)

Position

Priority

Type of
Acronym Description Address
priority

46 53 settable TIM8_CC TIM8 capture compare interrupt 0x0000 00F8

47 54 settable SDMMC2 SDMMC2 global interrupt 0x0000 00FC
48 55 settable FMC FMC global interrupt 0x0000 0100
49 56 settable SDMMC1 SDMMC1 global interrupt 0x0000 0104
50 57 settable TIM5 TIM5 global interrupt 0x0000 0108
51 58 settable SPI3 SPI3 global interrupt 0x0000 010C
52 59 settable UART4 UART4 global interrupt 0x0000 0110
53 60 settable UART5 UART5 global interrupt 0x0000 0114
54 61 settable TIM6_DACUNDER TIM6 global and DAC12 underrun interrupts 0x0000 0118
55 62 settable TIM7 TIM7 global interrupt 0x0000 011C
56 63 settable DMA2_CH1 DMA2 channel 1 interrupt 0x0000 0120
57 64 settable DMA2_CH2 DMA2 channel 2 interrupt 0x0000 0124
58 65 settable DMA2_CH3 DMA2 channel 3 interrupt 0x0000 0128
59 66 settable DMA2_CH4 DMA2 channel 4 interrupt 0x0000 012C
60 67 settable DMA2_CH5 DMA2 channel 5 interrupt 0x0000 0130
61 68 settable DFSDM1_FLT0 DFSDM1 Filter 0 global interrupt 0x0000 0134
62 69 settable DFSDM1_FLT1 DFSDM1 Filter 1 global interrupt 0x0000 0138
63 70 settable Reserved Reserved 0x0000 013C
COMP1/COMP2 through EXTI lines 21/22
64 71 settable COMP 0x0000 0140
interrupts
65 72 settable LPTIM1 LPTIM1 global interrupt 0x0000 0144
66 73 settable LPTIM2 LPTIM2 global interrupt 0x0000 0148
67 74 settable OTG_FS OTG_FS global interrupt 0x0000 014C
68 75 settable DMA2_CH6 DMA2 channel 6 interrupt 0x0000 0150
69 76 settable DMA2_CH7 DMA2 channel 7 interrupt 0x0000 0154
70 77 settable LPUART1 LPUART1 global interrupt 0x0000 0158
71 78 settable OCTOSPI1 OCTOSPI1 global interrupt 0x0000 015C
72 79 settable I2C3_EV I2C3 event interrupt 0x0000 0160
73 80 settable I2C3_ER I2C3 error interrupt 0x0000 0164
74 81 settable SAI1 SAI1 global interrupt 0x0000 0168

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Table 77. STM32L4P5xx and STM32Q5xx vector table (continued)

Position

Priority

Type of
Acronym Description Address
priority

75 82 settable SAI2 SAI2 global interrupt 0x0000 016C

76 83 settable OCTOSPI2 OCTOSPI2 global interrupt 0x0000 0170
77 84 settable TSC TSC global interrupt 0x0000 0174
78 85 settable Reserved Reserved 0x0000 0178
79 86 settable AES AES global interrupt 0x0000 017C
80 87 settable RNG RNG global interrupt 0x0000 0180
81 88 settable FPU Floating point interrupt 0x0000 0184
82 89 settable HASH_CRS HASH and CRS interrupt 0x0000 0188
83 90 settable I2C4_ER I2C4 error interrupt 0x0000 018C
84 91 settable I2C4_EV I2C4 event interrupt 0x0000 0190
85 92 settable DCMI_PSSI DCMI_PSSI global interrupt 0x0000 0194
86 93 settable PKA PKA global interrupt 0x0000 0198
87 94 settable Reserved Reserved 0x0000 019C
88 95 settable Reserved Reserved 0x0000 01A0
89 96 settable Reserved Reserved 0x0000 01A4
90 97 settable DMA2D DMA2D global interrupt 0x0000 0198
91 98 settable LCD-TFT LTDC global interrupt 0x0000 019C
92 99 settable LCD-TFT LTDC global error interrupt 0x0000 01A0
93 100 settable Reserved Reserved 0x0000 01A4
94 101 settable DMAMUX_OVR DMAMUX Overrun interrupt 0x0000 01A8

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RM0432 Extended interrupts and events controller (EXTI)

16 Extended interrupts and events controller (EXTI)

16.1 Introduction
The EXTI main features are as follows:
• Generation of up to 39 event/interrupt requests
– 26 configurable lines
– 13 direct lines
• Independent mask on each event/interrupt line
• Configurable rising or falling edge (configurable lines only)
• Dedicated status bit (configurable lines only)
• Emulation of event/interrupt requests (configurable lines only)

16.2 EXTI main features

The extended interrupts and events controller (EXTI) manages the external and internal
asynchronous events/interrupts and generates the event request to the CPU/Interrupt
Controller and a wake-up request to the Power Controller.
The EXTI allows the management of up to 39 event lines which can wake up from the Stop
0 and Stop 1 modes. Not all events can wake up from the Stop 2 mode (refer to Table 78:
EXTI lines connections).
The lines are either configurable or direct:
• The lines are configurable: the active edge can be chosen independently, and a status
flag indicates the source of the interrupt. The configurable lines are used by the I/Os
external interrupts, and by few peripherals.
• The lines are direct: they are used by some peripherals to generate a wakeup from
Stop event or interrupt. The status flag is provided by the peripheral.
Each line can be masked independently for an interrupt or an event generation.
This controller also allows to emulate events or interrupts by software, multiplexed with the
corresponding hardware event line, by writing to a dedicated register.

16.3 EXTI functional description

For the configurable interrupt lines, the interrupt line should be configured and enabled in
order to generate an interrupt. This is done by programming the two trigger registers with
the desired edge detection and by enabling the interrupt request by writing a ‘1’ to the
corresponding bit in the interrupt mask register. When the selected edge occurs on the
interrupt line, an interrupt request is generated. The pending bit corresponding to the
interrupt line is also set. This request is cleared by writing a ‘1’ in the pending register.
For the direct interrupt lines, the interrupt is enabled by default in the interrupt mask register
and there is no corresponding pending bit in the pending register.
To generate an event, the event line should be configured and enabled. This is done by
programming the two trigger registers with the desired edge detection and by enabling the
event request by writing a ‘1’ to the corresponding bit in the event mask register. When the

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Extended interrupts and events controller (EXTI) RM0432

selected edge occurs on the event line, an event pulse is generated. The pending bit
corresponding to the event line is not set.
For the configurable lines, an interrupt/event request can also be generated by software by
writing a ‘1’ in the software interrupt/event register.
Note: The interrupts or events associated to the direct lines are triggered only when the system is
in Stop mode. If the system is still running, no interrupt/event is generated by the EXTI.

16.3.1 EXTI block diagram

The extended interrupt/event block diagram is shown on Figure 43.

Figure 43. Configurable interrupt/event block diagram

APB bus

PCLK Peripheral interface

Falling Rising Software

Event Interrupt Pending
trigger trigger interrupt
mask mask request
selection selection event
register register register
register register register

Interrupts
Configurable Edge detect
events circuit
Events
Stop mode Rising
Direct events edge
detect

Wakeup

MS33393V1

16.3.2 Wakeup event management

The STM32L4+ Series devices are able to handle external or internal events in order to
wake up the core (WFE). The wakeup event can be generated either by:
• enabling an interrupt in the peripheral control register but not in the NVIC, and enabling
the SEVONPEND bit in the CortexTM-M4 System Control register. When the MCU
resumes from WFE, the EXTI peripheral interrupt pending bit and the peripheral NVIC
IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be
cleared
• or by configuring an EXTI line in event mode. When the CPU resumes from WFE, it is
not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel
pending bit as the pending bit corresponding to the event line is not set.

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RM0432 Extended interrupts and events controller (EXTI)

16.3.3 Peripherals asynchronous Interrupts

Some peripherals are able to generate events when the system is in run mode and also
when the system is in Stop mode, allowing to wake up the system from Stop mode.
To accomplish this, the peripheral generates both a synchronized (to the system clock, e.g.
APB clock) and an asynchronous version of the event. This asynchronous event is
connected to an EXTI direct line.
Note: Few peripherals with wakeup from Stop capability are connected to an EXTI configurable
line. In this case, the EXTI configuration is necessary to allow the wakeup from Stop mode.

16.3.4 Hardware interrupt selection

To configure a line as an interrupt source, use the following procedure:
1. Configure the corresponding mask bit in the EXTI_IMR register.
2. Configure the Trigger Selection bits of the Interrupt line (EXTI_RTSR and EXTI_FTSR).
3. Configure the enable and mask bits that control the NVIC IRQ channel mapped to the
EXTI so that an interrupt coming from one of the EXTI lines can be correctly
acknowledged.
Note: The direct lines do not require any EXTI configuration.

16.3.5 Hardware event selection

To configure a line as an event source, use the following procedure:
1. Configure the corresponding mask bit in the EXTI_EMR register.
2. Configure the Trigger Selection bits of the Event line (EXTI_RTSR and EXTI_FTSR).

16.3.6 Software interrupt/event selection

Any of the configurable lines can be configured as a software interrupt/event line. The
procedure to generate a software interrupt is as follows:
1. Configure the corresponding mask bit (EXTI_IMR, EXTI_EMR).
2. Set the required bit of the software interrupt register (EXTI_SWIER).

16.4 EXTI interrupt/event line mapping

In the STM32L4+ Series, 39 interrupt/event lines are available. The GPIOs are connected to
16 configurable interrupt/event lines (see Figure 44).

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Figure 44. External interrupt/event GPIO mapping

EXTI0[3:0] bits in the SYSCFG_EXTICR1 register

PA0
PB0
PC0
PD0 EXTI0
PE0
PF0
PG0
PH0
PI0(1)

EXTI1[3:0] bits in the SYSCFG_EXTICR1 register

PA1
PB1
PC1
PD1 EXTI1
PE1
PF1
PG1
PH1
PI1(1)
...

EXTI15[3:0] bits in the SYSCFG_EXTICR4 register

PA15
PB15
PC15
PD15 EXTI15
PE15
PF15
PG15
PH15(1)

MS46947V1

1. The GPIOs PI12 to PI15 are not available.

The EXTI lines are connected as shown in Table 78: EXTI lines connections.

Table 78. EXTI lines connections

EXTI line Line source(1) Line type

0-15 GPIO configurable

16 PVD configurable
(2)
OTG FS wakeup event
17 direct
(OTG_FS_WKUP)
18 RTC alarms or SSRU(3) configurable

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RM0432 Extended interrupts and events controller (EXTI)

Table 78. EXTI lines connections (continued)

EXTI line Line source(1) Line type

RTC tamper or timestamp or

19 configurable
CSS_LSE
20 RTC wakeup timer configurable
21 COMP1 output configurable
22 COMP2 output configurable
23 I2C1 wakeup direct
(2)
24 I2C2 wakeup direct
25 I2C3 wakeup direct
26 USART1 wakeup(2) direct
(2)
27 USART2 wakeup direct
28 USART3 wakeup(2) direct
29 UART4 wakeup(2) direct
30 UART5 wakeup(2) direct
31 LPUART1 wakeup direct
32 LPTIM1 direct
33 LPTIM2 (4) direct
34 Reserved reserved
35 PVM1 wakeup configurable
36 PVM2 wakeup configurable
37 PVM3 wakeup configurable
38 PVM4 wakeup configurable
39 Reserved reserved
40 I2C4 wakeup direct
1. All the lines can wake up from the Stop 0 and Stop 1 modes. All the lines, except the ones
mentioned above, can wake up from the Stop 2 mode.
2. This line source cannot wake up from the Stop 2 mode.
3. SSRU is only available on STM32L4P5xx and STM32L4Q5xx devices.
4. LPTIM2 can wakeup from the Stop 2 mode only on STM32L4P5xx and STM32L4Q5xx devices.

RM0432 Rev 6 481/2301

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Extended interrupts and events controller (EXTI) RM0432

16.5 EXTI registers

Refer to Section 1.2 on page 84 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32-bit).

16.5.1 Interrupt mask register 1 (EXTI_IMR1)

Address offset: 0x00
Reset value: 0xFF82 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IM31 IM30 IM29 IM28 IM27 IM26 IM25 IM24 IM23 IM22 IM21 IM20 IM19 IM18 IM17 IM16
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IM15 IM14 IM13 IM12 IM11 IM10 IM9 IM8 IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 IMx: Interrupt Mask on line x (x = 31 to 0)

0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked

Note: The reset value for the direct lines (line 17, lines from 23 to 34, line 39) is set to ‘1’ in order
to enable the interrupt by default.

16.5.2 Event mask register 1 (EXTI_EMR1)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EM31 EM30 EM29 EM28 EM27 EM26 EM25 EM24 EM23 EM22 EM21 EM20 EM19 EM18 EM17 EM16
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EM15 EM14 EM13 EM12 EM11 EM10 EM9 EM8 EM7 EM6 EM5 EM4 EM3 EM2 EM1 EM0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 EMx: Event mask on line x (x = 31 to 0)

0: Event request from line x is masked
1: Event request from line x is not masked

16.5.3 Rising trigger selection register 1 (EXTI_RTSR1)

Address offset: 0x08
Reset value: 0x0000 0000

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RM0432 Extended interrupts and events controller (EXTI)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. RT22 RT21 RT20 RT19 RT18 Res. RT16
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RT0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:18 RTx: Rising trigger event configuration bit of line x (x = 22 to 18)
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line
Bit 17 Reserved, must be kept at reset value.
Bits 16:0 RTx: Rising trigger event configuration bit of line x (x = 16 to 0)
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line

Note: The configurable wakeup lines are edge-triggered. No glitch must be generated on these
lines. If a rising edge on a configurable interrupt line occurs during a write operation in the
EXTI_RTSR register, the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this case, both
generate a trigger condition.

16.5.4 Falling trigger selection register 1 (EXTI_FTSR1)

Address offset: 0x0C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. FT22 FT21 FT20 FT19 FT18 Res. FT16
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FT15 FT14 FT13 FT12 FT11 FT10 FT9 FT8 FT7 FT6 FT5 FT4 FT3 FT2 FT1 FT0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:18 FTx: Falling trigger event configuration bit of line x (x = 22 to 18)
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line
Bit 17 Reserved, must be kept at reset value.
Bits 16:0 FTx: Falling trigger event configuration bit of line x (x = 16 to 0)
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line

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Extended interrupts and events controller (EXTI) RM0432

Note: The configurable wakeup lines are edge-triggered. No glitch must be generated on these
lines. If a falling edge on a configurable interrupt line occurs during a write operation to the
EXTI_FTSR register, the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this case, both
generate a trigger condition.

16.5.5 Software interrupt event register 1 (EXTI_SWIER1)

Address offset: 0x10
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWI SWI SWI SWI SWI SWI
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
22 21 20 19 18 16
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWI SWI SWI SWI SWI SWI SWI SWI SWI SWI SWI SWI SWI SWI SWI SWI
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22: 18 SWIx: Software interrupt on line x (x = 22 o 18)
If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit
when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an
interrupt request generation.
This bit is cleared by clearing the corresponding bit in the EXTI_PR register (by
writing a ‘1’ into the bit).
Bit 17 Reserved, must be kept at reset value.
Bits 16:0 SWIx: Software interrupt on line x (x = 16 to 0)
If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit
when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an
interrupt request generation.
This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a ‘1’
into the bit).

484/2301 RM0432 Rev 6

RM0432 Extended interrupts and events controller (EXTI)

16.5.6 Pending register 1 (EXTI_PR1)

Address offset: 0x14
Reset value: undefined

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. PIF22 PIF21 PIF20 PIF19 PIF18 Res. PIF16
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PIF15 PIF14 PIF13 PIF12 PIF11 PIF10 PIF9 PIF8 PIF7 PIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:18 PIFx: Pending interrupt flag on line x (x = 22 to 18)
0: No trigger request occurred
1: Selected trigger request occurred
This bit is set when the selected edge event arrives on the interrupt line. This bit
is cleared by writing a ‘1’ to the bit.
Bit 17 Reserved, must be kept at reset value.
Bits 16:0 PIFx: Pending interrupt flag on line x (x = 16 to 0)
0: No trigger request occurred
1: Selected trigger request occurred
This bit is set when the selected edge event arrives on the interrupt line. This bit
is cleared by writing a ‘1’ to the bit.

16.5.7 Interrupt mask register 2 (EXTI_IMR2)

Address offset: 0x20
Reset value: 0x0000 0187

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. IM40 IM39 IM38 IM37 IM36 IM35 IM34 IM33 IM32

rw rw rw rw rw rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value

Bits 8:0 IMx: Interrupt mask on line x (x = 40 to 32)
0: Interrupt request from line x is masked
1: Interrupt request from line x is not masked

Note: The reset value for the direct lines (line 17, lines from 23 to 34, line 39, line 40) is set to ‘1’ in
order to enable the interrupt by default.

RM0432 Rev 6 485/2301

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Extended interrupts and events controller (EXTI) RM0432

16.5.8 Event mask register 2 (EXTI_EMR2)

Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. EM40 EM39 EM38 EM37 EM36 EM35 EM34 EM33 EM32

rw rw rw rw rw rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value

Bits 8:0 EMx: Event mask on line x (x = 40 to 32)
0: Event request from line x is masked
1: Event request from line x is not masked

16.5.9 Rising trigger selection register 2 (EXTI_RTSR2)

Address offset: 0x28
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. RT38 RT37 RT36 RT35 Res. Res. Res.
rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:3 RTx: Rising trigger event configuration bit of line x (x = 35 to 38)
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line
Bits 2:0 Reserved, must be kept at reset value.

Note: The configurable wakeup lines are edge-triggered. No glitch must be generated on these
lines. If a rising edge on a configurable interrupt line occurs during a write operation to the
EXTI_RTSR register, the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this case, both
generate a trigger condition.

486/2301 RM0432 Rev 6

RM0432 Extended interrupts and events controller (EXTI)

16.5.10 Falling trigger selection register 2 (EXTI_FTSR2)

Address offset: 0x2C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. FT38 FT37 FT36 FT35 Res. Res. Res.

rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:3 FTx: Falling trigger event configuration bit of line x (x = 35 to 38)
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line
Bits 2:0 Reserved, must be kept at reset value.

Note: The configurable wakeup lines are edge-triggered. No glitch must be generated on these
lines. If a falling edge on a configurable interrupt line occurs during a write operation to the
EXTI_FTSR register, the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this case, both
generate a trigger condition.

16.5.11 Software interrupt event register 2 (EXTI_SWIER2)

Address offset: 0x30
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWI SWI SWI SWI
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
38 37 36 35
rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 SWIx: Software interrupt on line x (x = 35 to 38)
If the interrupt is enabled on this line in EXTI_IMR, writing a '1' to this bit when it
is at '0' sets the corresponding pending bit of EXTI_PR resulting in an interrupt
request generation.
This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a ‘1’
to the bit).
Bits 2:0 Reserved, must be kept at reset value.

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Extended interrupts and events controller (EXTI) RM0432

16.5.12 Pending register 2 (EXTI_PR2)

Address offset: 0x34
Reset value: undefined

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. PIF38 PIF37 PIF36 PIF35 Res. Res. Res.

rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 PIFx: Pending interrupt flag on line x (x = 35 to 38)
0: No trigger request occurred
1: Selected trigger request occurred
This bit is set when the selected edge event arrives on the interrupt line. This bit
is cleared by writing a ‘1’ into the bit.
Bits 2:0 Reserved, must be kept at reset value.

488/2301 RM0432 Rev 6

 0x34
0x30
0x28
0x24
0x20
0x14
0x10
0x08
0x04
0x00

0x2C
0x0C
Offset
RM0432

16.5.13

EXTI_PR2
EXTI_PR1
Register

EXTI_IMR2
EXTI_IMR1

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

EXTI_EMR2
EXTI_EMR1

EXTI_FTSR2
EXTI_FTSR1

EXTI_RTSR2
EXTI_RTSR1

EXTI_SWIER2
EXTI_SWIER1
0
1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EM31 IM31 31

0
1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EM30 IM30 30

0
1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EM29 IM29 29

0
1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EM28 IM28 28

0
1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EM27 IM27 27

0
1
EXTI register map

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EM26 IM26 26

0
1

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EM25 IM25 25
0
1

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 EM24 IM24 24
1

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EM23 IM23 23
0
0

0
0
0
0
Res. Res. Res. Res. Res. Res. PIF22 SWI22 FT22 RT22 EM22 IM22 22
0
0

0
0
0
0
Res. Res. Res. Res. Res. Res. PIF21 SWI21 FT21 RT21 EM21 IM21 21
0
0

0
0
0
Res. Res. Res. Res. Res. Res. PIF20 SWI20 FT20 0 RT20 EM20 IM20 20
0
0

0
0
0
0
Res. Res. Res. Res. Res. Res. PIF19 SWI19 FT19 RT19 EM19 IM19 19
0
0

0
0
0
0

Res. Res. Res. Res. Res. Res. PIF18 SWI18 FT18 RT18 EM18 IM18 18

RM0432 Rev 6
0
1

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EM17 IM17 17
0
0

0
0
0
0

Res. Res. Res. Res. Res. Res. PIF16 SWI16 FT16 RT16 EM16 IM16 16
0
0

0
0
0
0

Res. Res. Res. Res. Res. Res. PIF15 SWI15 FT15 RT15 EM15 IM15 15
0
0

0
0
0
0

Res. Res. Res. Res. Res. Res. PIF14 SWI14 FT14 RT14 EM14 IM14 14
0
0

0
0
0
0

Res. Res. Res. Res. Res. Res. PIF13 SWI13 FT13 RT13 EM13 IM13 13
Table 79 gives the EXTI register map and the reset values.

0
0

0
0
0
0

Res. Res. Res. Res. Res. Res. PIF12 SWI12 FT12 RT12 EM12 IM12 12
0
0

0
0
0
0

Res. Res. Res. Res. Res. Res. PIF11 SWI11 FT11 RT11 EM11 IM11 11
0
0

0
0
0
0

Res. Res. Res. Res. Res. Res. PIF10 SWI10 FT10 RT10 EM10 IM10 10
0
0

0
0
0
0

Res. Res. Res. Res. Res. Res. PIF9 SWI9 FT9 RT9 EM9 IM9 9

Refer to Section 2.2 on page 91 for the register boundary addresses.

0
0

0
0
0
0

0
1
Res. Res. Res. Res. EM40 IM40 PIF8 SWI8 FT8 RT8 EM8 IM8 8
0
0

0
0
0
0

0
1
Res. Res. Res. Res. EM39 IM39 PIF7 SWI7 FT7 RT7 EM7 IM7 7
0
0

0
0
0
0

0
0
0
0
0
0
PIF38 SWI38 FT38 RT38 EM38 IM38 PIF6 SWI6 FT6 RT6 EM6 IM6 6
0
0

0
0
0
0

0
0
0
0
0
PIF37 SWI37 FT37 RT37 EM37 0 IM37 PIF5 SWI5 FT5 RT5 EM5 IM5 5
Table 79. Extended interrupt/event controller register map and reset values

0
0

0
0
0
0

0
0
0
0
0
0
PIF36 SWI36 FT36 RT36 EM36 IM36 PIF4 SWI4 FT4 RT4 EM4 IM4 4
0
0

0
0
0
0

0
0
0
0
0
0

PIF35 SWI35 FT35 RT35 EM35 IM35 PIF3 SWI3 FT3 RT3 EM3 IM3 3
0
0

0
0
0
0

0
1

Res. Res. Res. Res. EM34 IM34 PIF2 SWI2 FT2 RT2 EM2 IM2 2
0
0

0
0
0
0

0
1

Res. Res. Res. Res. EM33 IM33 PIF1 SWI1 FT1 RT1 EM1 IM1 1
0
0

0
0
0
0

0
1

Res. Res. Res. Res. EM32 IM32 0

489/2301
Extended interrupts and events controller (EXTI)

PIF0 SWI0 FT0 RT0 EM0 IM0

489
Cyclic redundancy check calculation unit (CRC) RM0432

17 Cyclic redundancy check calculation unit (CRC)

17.1 Introduction
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16-
or 32-bit data word and a generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the functional safety standards, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link
time and stored at a given memory location.

17.2 CRC main features

• Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+ X +1
• Alternatively, uses fully programmable polynomial with programmable size (7, 8, 16, 32
bits)
• Handles 8-,16-, 32-bit data size
• Programmable CRC initial value
• Single input/output 32-bit data register
• Input buffer to avoid bus stall during calculation
• CRC computation done in 4 AHB clock cycles (HCLK) for the 32-bit data size
• General-purpose 8-bit register (can be used for temporary storage)
• Reversibility option on I/O data

490/2301 RM0432 Rev 6

RM0432 Cyclic redundancy check calculation unit (CRC)

17.3 CRC functional description

17.3.1 CRC block diagram

Figure 45. CRC calculation unit block diagram

32-bit AHB bus

32-bit (read access)

Data register (output)
crc_hclk

CRC computation

32-bit (write access)

Data register (input)

MS19882V2

17.3.2 CRC internal signals

Table 80. CRC internal input/output signals

Signal name Signal type Description

crc_hclk Digital input AHB clock

17.3.3 CRC operation

The CRC calculation unit has a single 32-bit read/write data register (CRC_DR). It is used to
input new data (write access), and holds the result of the previous CRC calculation (read
access).
Each write operation to the data register creates a combination of the previous CRC value
(stored in CRC_DR) and the new one. CRC computation is done on the whole 32-bit data
word or byte by byte depending on the format of the data being written.
The CRC_DR register can be accessed by word, right-aligned half-word and right-aligned
byte. For the other registers only 32-bit access is allowed.
The duration of the computation depends on data width:
• 4 AHB clock cycles for 32-bit
• 2 AHB clock cycles for 16-bit
• 1 AHB clock cycles for 8-bit
An input buffer allows a second data to be immediately written without waiting for any wait
states due to the previous CRC calculation.
The data size can be dynamically adjusted to minimize the number of write accesses for a
given number of bytes. For instance, a CRC for 5 bytes can be computed with a word write
followed by a byte write.

RM0432 Rev 6 491/2301

495
Cyclic redundancy check calculation unit (CRC) RM0432

The input data can be reversed, to manage the various endianness schemes. The reversing
operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits
in the CRC_CR register.
For example: input data 0x1A2B3C4D is used for CRC calculation as:
• 0x58D43CB2 with bit-reversal done by byte
• 0xD458B23C with bit-reversal done by half-word
• 0xB23CD458 with bit-reversal done on the full word
The output data can also be reversed by setting the REV_OUT bit in the CRC_CR register.
The operation is done at bit level: for example, output data 0x11223344 is converted into
0x22CC4488.
The CRC calculator can be initialized to a programmable value using the RESET control bit
in the CRC_CR register (the default value is 0xFFFFFFFF).
The initial CRC value can be programmed with the CRC_INIT register. The CRC_DR
register is automatically initialized upon CRC_INIT register write access.
The CRC_IDR register can be used to hold a temporary value related to CRC calculation. It
is not affected by the RESET bit in the CRC_CR register.

Polynomial programmability
The polynomial coefficients are fully programmable through the CRC_POL register, and the
polynomial size can be configured to be 7, 8, 16 or 32 bits by programming the
POLYSIZE[1:0] bits in the CRC_CR register. Even polynomials are not supported.
If the CRC data is less than 32-bit, its value can be read from the least significant bits of the
CRC_DR register.
To obtain a reliable CRC calculation, the change on-fly of the polynomial value or size can
not be performed during a CRC calculation. As a result, if a CRC calculation is ongoing, the
application must either reset it or perform a CRC_DR read before changing the polynomial.
The default polynomial value is the CRC-32 (Ethernet) polynomial: 0x4C11DB7.

492/2301 RM0432 Rev 6

RM0432 Cyclic redundancy check calculation unit (CRC)

17.4 CRC registers

17.4.1 CRC data register (CRC_DR)

Address offset: 0x00
Reset value: 0xFFFF FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DR[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DR[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 DR[31:0]: Data register bits

This register is used to write new data to the CRC calculator.
It holds the previous CRC calculation result when it is read.
If the data size is less than 32 bits, the least significant bits are used to write/read the
correct value.

17.4.2 CRC independent data register (CRC_IDR)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. IDR[7:0]

rw

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 IDR[7:0]: General-purpose 8-bit data register bits
These bits can be used as a temporary storage location for one byte.
This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register

RM0432 Rev 6 493/2301

495
Cyclic redundancy check calculation unit (CRC) RM0432

17.4.3 CRC control register (CRC_CR)

Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_
Res. Res. Res. Res. Res. Res. Res. Res. REV_IN[1:0] POLYSIZE[1:0] Res. Res. RESET
OUT
rw rw rw rw rw rs

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 REV_OUT: Reverse output data
This bit controls the reversal of the bit order of the output data.
0: Bit order not affected
1: Bit-reversed output format
Bits 6:5 REV_IN[1:0]: Reverse input data
These bits control the reversal of the bit order of the input data
00: Bit order not affected
01: Bit reversal done by byte
10: Bit reversal done by half-word
11: Bit reversal done by word
Bits 4:3 POLYSIZE[1:0]: Polynomial size
These bits control the size of the polynomial.
00: 32 bit polynomial
01: 16 bit polynomial
10: 8 bit polynomial
11: 7 bit polynomial
Bits 2:1 Reserved, must be kept at reset value.
Bit 0 RESET: RESET bit
This bit is set by software to reset the CRC calculation unit and set the data register to the value
stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware

17.4.4 CRC initial value (CRC_INIT)

Address offset: 0x10
Reset value: 0xFFFF FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CRC_INIT[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CRC_INIT[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:0 CRC_INIT[31:0]: Programmable initial CRC value

This register is used to write the CRC initial value.

17.4.5 CRC polynomial (CRC_POL)

Address offset: 0x14
Reset value: 0x04C1 1DB7

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

POL[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

POL[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 POL[31:0]: Programmable polynomial

This register is used to write the coefficients of the polynomial to be used for CRC calculation.
If the polynomial size is less than 32 bits, the least significant bits have to be used to program the
correct value.

17.4.6 CRC register map

Table 81. CRC register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name

CRC_DR DR[31:0]
0x00
Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

CRC_IDR IDR[7:0]
0x04
Reset value 0 0 0 0 0 0 0 0
POLYSIZE[1:0]
REV_IN[1:0]
REV_OUT

RESET
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

CRC_CR
0x08

Reset value 0 0 0 0 0 0

CRC_INIT CRC_INIT[31:0]
0x10
Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CRC_POL POL[31:0]
0x14
Reset value 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 0 0 0 1 1 1 0 1 1 0 1 1 0 1 1 1

Refer to Section 2.2 on page 91 for the register boundary addresses.

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18 Flexible static memory controller (FSMC)

18.1 Introduction
The flexible static memory controller (FSMC) includes two memory controllers:
• The NOR/PSRAM memory controller
• The NAND memory controller
This memory controller is also named flexible memory controller (FMC).

18.2 FMC main features

The FMC functional block makes the interface with: synchronous and asynchronous static
memories, and NAND Flash memory. Its main purposes are:
• to translate AHB transactions into the appropriate external device protocol
• to meet the access time requirements of the external memory devices
All external memories share the addresses, data and control signals with the controller.
Each external device is accessed by means of a unique chip select. The FMC performs only
one access at a time to an external device.
The main features of the FMC controller are the following:
• Interface with static-memory mapped devices including:
– Static random access memory (SRAM)
– NOR Flash memory/OneNAND Flash memory
– PSRAM (4 memory banks)
– Ferroelectric RAM (FRAM)
– NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
• Interface with parallel LCD modules, supporting Intel 8080 and Motorola 6800 modes.
• Burst mode support for faster access to synchronous devices such as NOR Flash
memory, PSRAM)
• Programmable continuous clock output for asynchronous and synchronous accesses
• 8-,16-bit wide data bus
• Independent chip select control for each memory bank
• Independent configuration for each memory bank
• Write enable and byte lane select outputs for use with PSRAM, SRAM devices
• External asynchronous wait control
• Write FIFO with 16 x32-bit depth
The Write FIFO is common to all memory controllers and consists of:
• a Write Data FIFO which stores the AHB data to be written to the memory (up to 32
bits) plus one bit for the AHB transfer (burst or not sequential mode)
• a Write Address FIFO which stores the AHB address (up to 28 bits) plus the AHB data
size (up to 2 bits). When operating in burst mode, only the start address is stored
except when crossing a page boundary (for PSRAM). In this case, the AHB burst is
broken into two FIFO entries.

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The Write FIFO can be disabled by setting the WFDIS bit in the FMC_BCR1 register.
At startup the FMC pins must be configured by the user application. The FMC I/O pins which
are not used by the application can be used for other purposes.
The FMC registers that define the external device type and associated characteristics are
usually set at boot time and do not change until the next reset or power-up. However, the
settings can be changed at any time.

18.3 FMC implementation

Table 82. FMC implementation
STM32L4R7xx/STM32L4R9xx and STM32L4P5xx and
References
STM32L4S7xx/STM32L4S9xx STM32L4Q5xx

PSRAM chip select counter - X

18.4 FMC block diagram

The FMC consists of the following main blocks:
• The AHB interface (including the FMC configuration registers)
• The NOR Flash/PSRAM/SRAM controller
• The external device interface
• The NAND Flash controller
The block diagram is shown in the figure below.

Figure 46. FMC block diagram

FSMC interrupts to NVIC

NOR/PSRAM
FSMC_NL (or NADV)
signals
FSMC_CLK
From clock NOR/PSRAM
controller NOR / PSRAM / SRAM
memory FSMC_NBL[1:0]
HCLK shared signals
controller
FSMC_A[25:0]
Shared signals
FSMC_D[15:0]

FSMC_NE[4:1]
Configuration
FSMC_NOE NOR / PSRAM / SRAM
registers
NAND FSMC_NWE shared signals
memory FSMC_NWAIT
controller
FSMC_NCE
NAND signals
FSMC_INT

MSv39280V1

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18.5 AHB interface

The AHB slave interface allows internal CPUs and other bus master peripherals to access
the external memories.
AHB transactions are translated into the external device protocol. In particular, if the
selected external memory is 16- or 8-bit wide, 32-bit wide transactions on the AHB are split
into consecutive 16- or 8-bit accesses. The FMC chip select (FMC_NEx) does not toggle
between the consecutive accesses except in case of Access mode D when the Extended
mode is enabled.
The FMC generates an AHB error in the following conditions:
• When reading or writing to an FMC bank (Bank 1 to 4) which is not enabled.
• When reading or writing to the NOR Flash bank while the FACCEN bit is reset in the
FMC_BCRx register.
The effect of an AHB error depends on the AHB master which has attempted the R/W
access:
• If the access has been attempted by the Cortex®-M4 CPU, a hard fault interrupt is
generated.
• If the access has been performed by a DMA controller, a DMA transfer error is
generated and the corresponding DMA channel is automatically disabled.
The AHB clock (HCLK) is the reference clock for the FMC.

18.5.1 Supported memories and transactions

General transaction rules
The requested AHB transaction data size can be 8-, 16- or 32-bit wide whereas the
accessed external device has a fixed data width. This may lead to inconsistent transfers.
Therefore, some simple transaction rules must be followed:
• AHB transaction size and memory data size are equal
There is no issue in this case.
• AHB transaction size is greater than the memory size:
In this case, the FMC splits the AHB transaction into smaller consecutive memory
accesses to meet the external data width. The FMC chip select (FMC_NEx) does not
toggle between the consecutive accesses. If the bus turnaround timings is configured

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to any other value than 0, the FMC chip select (FMC_NEx) toggles between the
consecutive accesses. This feature is required when interfacing with FRAM memory.
• AHB transaction size is smaller than the memory size:
The transfer may or not be consistent depending on the type of external device:
– Accesses to devices that have the byte select feature (SRAM, ROM, PSRAM)
In this case, the FMC allows read/write transactions and accesses the right data
through its byte lanes NBL[1:0].
Bytes to be written are addressed by NBL[1:0].
All memory bytes are read (NBL[1:0] are driven low during read transaction) and
the useless ones are discarded.
– Accesses to devices that do not have the byte select feature (NOR and NAND
Flash memories)
This situation occurs when a byte access is requested to a 16-bit wide Flash
memory. Since the device cannot be accessed in Byte mode (only 16-bit words
can be read/written from/to the Flash memory), Write transactions and Read
transactions are allowed (the controller reads the entire 16-bit memory word and
uses only the required byte).

Wrap support for NOR Flash/PSRAM

Wrap burst mode for synchronous memories is not supported. The memories must be
configured in Linear burst mode of undefined length.

Configuration registers
The FMC can be configured through a set of registers. Refer to Section 18.7.6, for a
detailed description of the NOR Flash/PSRAM controller registers. Refer to Section 18.8.7,
for a detailed description of the NAND Flash registers.

18.6 External device address mapping

From the FMC point of view, the external memory is divided into fixed-size banks of
256 Mbytes each (see Figure 47):
• Bank 1 used to address up to 4 NOR Flash memory or PSRAM devices. This bank is
split into 4 NOR/PSRAM subbanks with 4 dedicated chip selects, as follows:
– Bank 1 - NOR/PSRAM 1
– Bank 1 - NOR/PSRAM 2
– Bank 1 - NOR/PSRAM 3
– Bank 1 - NOR/PSRAM 4
• Bank 3 used to address NAND Flash memory devices.The MPU memory attribute for
this space must be reconfigured by software to Device.
For each bank the type of memory to be used can be configured by the user application
through the Configuration register.

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Figure 47. FMC memory banks

Address Bank Supported memory type

0x6000 0000
Bank 1 NOR/PSRAM/SRAM
4 x 64 Mbyte

0x6FFF FFFF
0x7000 0000

Not used

0x7FFF FFFF
0x8000 0000

Bank 3
NAND Flash memory
4 x 64 Mbyte

0x8FFF FFFF
0x9000 0000

Not used

0x9FFF FFFF
MSv34475V2

18.6.1 NOR/PSRAM address mapping

HADDR[27:26] bits are used to select one of the four memory banks as shown in Table 83.

Table 83. NOR/PSRAM bank selection

HADDR[27:26](1) Selected bank

00 Bank 1 - NOR/PSRAM 1
01 Bank 1 - NOR/PSRAM 2
10 Bank 1 - NOR/PSRAM 3
11 Bank 1 - NOR/PSRAM 4
1. HADDR are internal AHB address lines that are translated to external memory.

The HADDR[25:0] bits contain the external memory address. Since HADDR is a byte
address whereas the memory is addressed at word level, the address actually issued to the
memory varies according to the memory data width, as shown in the following table.

Table 84. NOR/PSRAM External memory address

Memory width(1) Data address issued to the memory Maximum memory capacity (bits)

8-bit HADDR[25:0] 64 Mbytes x 8 = 512 Mbit

16-bit HADDR[25:1] >> 1 64 Mbytes/2 x 16 = 512 Mbit

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1. In case of a 16-bit external memory width, the FMC internally uses HADDR[25:1] to generate the address
for external memory FMC_A[24:0].
Whatever the external memory width, FMC_A[0] should be connected to external memory address A[0].

18.6.2 NAND Flash memory address mapping

The NAND bank is divided into memory areas as indicated in Table 85.

Table 85. NAND memory mapping and timing registers

Start address End address FMC bank Memory space Timing register

0x8800 0000 0x8BFF FFFF Attribute FMC_PATT (0x8C)

Bank 3 - NAND Flash
0x8000 0000 0x83FF FFFF Common FMC_PMEM (0x88)

For NAND Flash memory, the common and attribute memory spaces are subdivided into
three sections (see in Table 86 below) located in the lower 256 Kbytes:
• Data section (first 64 Kbytes in the common/attribute memory space)
• Command section (second 64 Kbytes in the common / attribute memory space)
• Address section (next 128 Kbytes in the common / attribute memory space)

Table 86. NAND bank selection

Section name HADDR[17:16] Address range

Address section 1X 0x020000-0x03FFFF

Command section 01 0x010000-0x01FFFF
Data section 00 0x000000-0x0FFFF

The application software uses the 3 sections to access the NAND Flash memory:
• To sending a command to NAND Flash memory, the software must write the
command value to any memory location in the command section.
• To specify the NAND Flash address that must be read or written, the software
must write the address value to any memory location in the address section. Since an
address can be 4 or 5 bytes long (depending on the actual memory size), several
consecutive write operations to the address section are required to specify the full
address.
• To read or write data, the software reads or writes the data from/to any memory
location in the data section.
Since the NAND Flash memory automatically increments addresses, there is no need to
increment the address of the data section to access consecutive memory locations.

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18.7 NOR Flash/PSRAM controller

The FMC generates the appropriate signal timings to drive the following types of memories:
• Asynchronous SRAM, FRAM and ROM
– 8 bits
– 16 bits
• PSRAM (CellularRAM™)
– Asynchronous mode
– Burst mode for synchronous accesses
– Multiplexed or non-multiplexed
• NOR Flash memory
– Asynchronous mode
– Burst mode for synchronous accesses
– Multiplexed or non-multiplexed
The FMC outputs a unique chip select signal, NE[4:1], per bank. All the other signals
(addresses, data and control) are shared.
The FMC supports a wide range of devices through a programmable timings among which:
• Programmable wait states (up to 15)
• Programmable bus turnaround cycles (up to 15)
• Programmable output enable and write enable delays (up to 15)
• Independent read and write timings and protocol to support the widest variety of
memories and timings
• Programmable continuous clock (FMC_CLK) output.
The FMC Clock (FMC_CLK) is a submultiple of the HCLK clock. It can be delivered to the
selected external device either during synchronous accesses only or during asynchronous
and synchronous accesses depending on the CCKEN bit configuration in the FMC_BCR1
register:
• If the CCLKEN bit is reset, the FMC generates the clock (CLK) only during
synchronous accesses (Read/write transactions).
• If the CCLKEN bit is set, the FMC generates a continuous clock during asynchronous
and synchronous accesses. To generate the FMC_CLK continuous clock, Bank 1 must
be configured in Synchronous mode (see Section 18.7.6: NOR/PSRAM controller
registers). Since the same clock is used for all synchronous memories, when a
continuous output clock is generated and synchronous accesses are performed, the
AHB data size has to be the same as the memory data width (MWID) otherwise the
FMC_CLK frequency is changed depending on AHB data transaction (refer to
Section 18.7.5: Synchronous transactions for FMC_CLK divider ratio formula).
The size of each bank is fixed and equal to 64 Mbytes. Each bank is configured through
dedicated registers (see Section 18.7.6: NOR/PSRAM controller registers).
The programmable memory parameters include access times (see Table 87) and support
for wait management (for PSRAM and NOR Flash accessed in Burst mode).

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Table 87. Programmable NOR/PSRAM access parameters

Parameter Function Access mode Unit Min. Max.

Address Duration of the address AHB clock cycle

Asynchronous 0 15
setup setup phase (HCLK)
Duration of the address hold Asynchronous, AHB clock cycle
Address hold 1 15
phase muxed I/Os (HCLK)
Duration of the byte lanes AHB clock cycle
NBL setup Asynchronous 0 3
setup phase (HCLK)
Duration of the data setup AHB clock cycle
Data setup Asynchronous 1 256
phase (HCLK)
Duration of the data hold AHB clock cycle
Data hold Asynchronous 0 3
phase (HCLK)
Asynchronous and
Duration of the bus AHB clock cycle
Bust turn synchronous read 0 15
turnaround phase (HCLK)
/ write
Number of AHB clock cycles
Clock divide AHB clock cycle
(HCLK) to build one memory Synchronous 2 16
ratio (HCLK)
clock cycle (CLK)
Number of clock cycles to
Memory clock
Data latency issue to the memory before Synchronous 2 17
cycle (CLK)
the first data of the burst

18.7.1 External memory interface signals

Table 88, Table 89 and Table 90 list the signals that are typically used to interface with NOR
Flash memory, SRAM and PSRAM.
Note: The prefix “N” identifies the signals that are active low.

NOR Flash memory, non-multiplexed I/Os

Table 88. Non-multiplexed I/O NOR Flash memory

FMC signal name I/O Function

CLK O Clock (for synchronous access)

A[25:0] O Address bus
D[15:0] I/O Bidirectional data bus
NE[x] O Chip select, x = 1..4
NOE O Output enable
NWE O Write enable
Latch enable (this signal is called address
NL(=NADV) O
valid, NADV, by some NOR Flash devices)
NWAIT I NOR Flash wait input signal to the FMC

The maximum capacity is 512 Mbits (26 address lines).

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NOR Flash memory, 16-bit multiplexed I/Os

Table 89. 16-bit multiplexed I/O NOR Flash memory

FMC signal name I/O Function

CLK O Clock (for synchronous access)

A[25:16] O Address bus
16-bit multiplexed, bidirectional address/data bus (the 16-bit address
AD[15:0] I/O
A[15:0] and data D[15:0] are multiplexed on the databus)
NE[x] O Chip select, x = 1..4
NOE O Output enable
NWE O Write enable
Latch enable (this signal is called address valid, NADV, by some NOR
NL(=NADV) O
Flash devices)
NWAIT I NOR Flash wait input signal to the FMC

The maximum capacity is 512 Mbits.

PSRAM/FRAM/SRAM, non-multiplexed I/Os

Table 90. Non-multiplexed I/Os PSRAM/SRAM

FMC signal name I/O Function

CLK O Clock (only for PSRAM synchronous access)

A[25:0] O Address bus
D[15:0] I/O Data bidirectional bus
NE[x] O Chip select, x = 1..4 (called NCE by PSRAM (CellularRAM™ i.e. CRAM))
NOE O Output enable
NWE O Write enable
NL(= NADV) O Address valid only for PSRAM input (memory signal name: NADV)
NWAIT I PSRAM wait input signal to the FMC
NBL[1:0] O Byte lane output. Byte 0 and Byte 1 control (upper and lower byte enable)

The maximum capacity is 512 Mbits.

PSRAM, 16-bit multiplexed I/Os

Table 91. 16-Bit multiplexed I/O PSRAM

FMC signal name I/O Function

CLK O Clock (for synchronous access)

A[25:16] O Address bus
16-bit multiplexed, bidirectional address/data bus (the 16-bit address
AD[15:0] I/O
A[15:0] and data D[15:0] are multiplexed on the databus)

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Table 91. 16-Bit multiplexed I/O PSRAM (continued)

FMC signal name I/O Function

NE[x] O Chip select, x = 1..4 (called NCE by PSRAM (CellularRAM™ i.e. CRAM))
NOE O Output enable
NWE O Write enable
NL(= NADV) O Address valid PSRAM input (memory signal name: NADV)
NWAIT I PSRAM wait input signal to the FMC
NBL[1:0] O Byte lane output. Byte 0 and Byte 1 control (upper and lower byte enable)

The maximum capacity is 512 Mbits (26 address lines).

18.7.2 Supported memories and transactions

Table 92 below shows an example of the supported devices, access modes and
transactions when the memory data bus is 16-bit wide for NOR Flash memory, PSRAM and
SRAM. The transactions not allowed (or not supported) by the FMC are shown in gray in
this example.

Table 92. NOR Flash/PSRAM: example of supported memories

and transactions
AHB Allowed/
Memory
Device Mode R/W data not Comments
data size
size allowed

Asynchronous R 8 16 Y -
Asynchronous W 8 16 N -
Asynchronous R 16 16 Y -
Asynchronous W 16 16 Y -
NOR Flash Asynchronous R 32 16 Y Split into 2 FMC accesses
(muxed I/Os
and nonmuxed Asynchronous W 32 16 Y Split into 2 FMC accesses
I/Os) Asynchronous
R - 16 N Mode is not supported
page
Synchronous R 8 16 N -
Synchronous R 16 16 Y -
Synchronous R 32 16 Y -

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Table 92. NOR Flash/PSRAM: example of supported memories

and transactions (continued)
AHB Allowed/
Memory
Device Mode R/W data not Comments
data size
size allowed

Asynchronous R 8 16 Y -
Asynchronous W 8 16 Y Use of byte lanes NBL[1:0]
Asynchronous R 16 16 Y -
Asynchronous W 16 16 Y -
Asynchronous R 32 16 Y Split into 2 FMC accesses
PSRAM
(multiplexed Asynchronous W 32 16 Y Split into 2 FMC accesses
I/Os and non- Asynchronous
multiplexed R - 16 N Mode is not supported
page
I/Os)
Synchronous R 8 16 N -
Synchronous R 16 16 Y -
Synchronous R 32 16 Y -
Synchronous W 8 16 Y Use of byte lanes NBL[1:0]
Synchronous W 16/32 16 Y -
Asynchronous R 8 / 16 16 Y -
Asynchronous W 8 / 16 16 Y Use of byte lanes NBL[1:0]
SRAM and
ROM Asynchronous R 32 16 Y Split into 2 FMC accesses
Split into 2 FMC accesses
Asynchronous W 32 16 Y
Use of byte lanes NBL[1:0]

18.7.3 General timing rules

Signals synchronization
• All controller output signals change on the rising edge of the internal clock (HCLK)
• In Synchronous mode (read or write), all output signals change on the rising edge of
HCLK. Whatever the CLKDIV value, all outputs change as follows:
– NOEL/NWEL/ NEL/NADVL/ NADVH /NBLL/ Address valid outputs change on the
falling edge of FMC_CLK clock.
– NOEH/ NWEH / NEH/ NOEH/NBLH/ Address invalid outputs change on the rising
edge of FMC_CLK clock.

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18.7.4 NOR Flash/PSRAM controller asynchronous transactions

Asynchronous static memories (NOR Flash, PSRAM, SRAM, FRAM)
• Signals are synchronized by the internal clock HCLK. This clock is not issued to the
memory
• The FMC always samples the data before de-asserting the NOE signal. This
guarantees that the memory data hold timing constraint is met (minimum Chip Enable
high to data transition is usually 0 ns)
• If the Extended mode is enabled (EXTMOD bit is set in the FMC_BCRx register), up to
four extended modes (A, B, C and D) are available. It is possible to mix A, B, C and D
modes for read and write operations. For example, read operation can be performed in
mode A and write in mode B.
• If the Extended mode is disabled (EXTMOD bit is reset in the FMC_BCRx register), the
FMC can operate in mode 1 or mode 2 as follows:
– Mode 1 is the default mode when SRAM/PSRAM memory type is selected (MTYP
= 0x0 or 0x01 in the FMC_BCRx register)
– Mode 2 is the default mode when NOR memory type is selected (MTYP = 0x10 in
the FMC_BCRx register).

Mode 1 - SRAM/FRAM/PSRAM (CRAM)

The next figures show the read and write transactions for the supported modes followed by
the required configuration of FMC_BCRx, and FMC_BTRx/FMC_BWTRx registers.

Figure 48. Mode 1 read access waveforms

Memory transaction

A[25:0]

NBL[x:0]

NEx

NOE

NWE High

Data bus Data driven by memory

NBLSET ADDSET HCLK cycles DATAST HCLK cycles DATAHLD

HCLK HCLK cycles
cycles
MSv41664V1

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Figure 49. Mode 1 write access waveforms

Memory transaction

A[25:0]

NBL[x:0]

NEx

NOE

NWE

Data bus Data driven by controller

NBLSET ADDSET HCLK cycles DATAST HCLK cycles DATAHLD +1

HCLK HCLK cycles
cycles
MSv41665V1

The DATAHLD time at the end of the read and write transactions guarantee the address and
data hold time after the NOE/NWE rising edge. The DATAST value must be greater than
zero (DATAST > 0).

Table 93. FMC_BCRx bitfields (mode 1)

Bit number Bit name Value to set

31:24 Reserved 0x000

23:22 NBLSET[1:0] As needed
21 WFDIS As needed
20 CCLKEN As needed
19 CBURSTRW 0x0 (no effect in Asynchronous mode)
18:16 CPSIZE 0x0 (no effect in Asynchronous mode)
15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
14 EXTMOD 0x0
13 WAITEN 0x0 (no effect in Asynchronous mode)
12 WREN As needed
11 Reserved 0x0
10 Reserved 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 Reserved 0x1

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Table 93. FMC_BCRx bitfields (mode 1) (continued)

Bit number Bit name Value to set

6 FACCEN Don’t care

5:4 MWID As needed
3:2 MTYP As needed, exclude 0x2 (NOR Flash memory)
1 MUXE 0x0
0 MBKEN 0x1

Table 94. FMC_BTRx bitfields (mode 1)

Bit number Bit name Value to set

Duration of the data hold phase (DATAHLD HCLK cycles for read
31:30 DATAHLD
accesses, DATAHLD+1 HCLK cycles for write accesses).
29:28 ACCMOD Don’t care
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15:8 DATAST Duration of the second access phase (DATAST HCLK cycles).
7:4 ADDHLD Don’t care
Duration of the first access phase (ADDSET HCLK cycles).
3:0 ADDSET
Minimum value for ADDSET is 0.

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Mode A - SRAM/FRAM/PSRAM (CRAM) OE toggling

Figure 50. Mode A read access waveforms

Memory transaction

A[25:0]

NBL[x:0]

NEx

NOE

NWE High

Data bus Data driven by memory

NBLSET ADDSET HCLK cycles DATAST HCLK cycles DATAHLD

HCLK HCLK cycles
cycles
MSv41681V1

1. NBL[1:0] are driven low during the read access

Figure 51. Mode A write access waveforms

Memory transaction

A[25:0]

NBL[x:0]

NEx

NOE

NWE

Data bus Data driven by controller

NBLSET ADDSET HCLK cycles DATAST HCLK cycles DATAHLD +1

HCLK HCLK cycles
cycles
MSv41665V1

The differences compared with Mode 1 are the toggling of NOE and the independent read
and write timings.

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Table 95. FMC_BCRx bitfields (mode A)

Bit number Bit name Value to set

31:24 Reserved 0x000

23:22 NBLSET[1:0] As needed
21 WFDIS As needed
20 CCLKEN As needed
19 CBURSTRW 0x0 (no effect in Asynchronous mode)
18:16 CPSIZE 0x0 (no effect in Asynchronous mode)
15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
14 EXTMOD 0x1
13 WAITEN 0x0 (no effect in Asynchronous mode)
12 WREN As needed
11 WAITCFG Don’t care
10 Reserved 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 Reserved 0x1
6 FACCEN Don’t care
5:4 MWID As needed
3:2 MTYP As needed, exclude 0x2 (NOR Flash memory)
1 MUXEN 0x0
0 MBKEN 0x1

Table 96. FMC_BTRx bitfields (mode A)

Bit number Bit name Value to set

Duration of the data hold phase (DATAHLD HCLK cycles for read
31:30 DATAHLD
accesses).
29:28 ACCMOD 0x0
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the second access phase (DATAST HCLK cycles) for read
15:8 DATAST
accesses.
7:4 ADDHLD Don’t care
Duration of the first access phase (ADDSET HCLK cycles) for read
3:0 ADDSET accesses.
Minimum value for ADDSET is 0.

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Table 97. FMC_BWTRx bitfields (mode A)

Bit number Bit name Value to set

Duration of the data hold phase (DATAHLD+1 HCLK cycles for write
31:30 DATAHLD
accesses).
29:28 ACCMOD 0x0
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the second access phase (DATAST HCLK cycles) for write
15:8 DATAST
accesses.
7:4 ADDHLD Don’t care
Duration of the first access phase (ADDSET HCLK cycles) for write
3:0 ADDSET accesses.
Minimum value for ADDSET is 0.

Mode 2/B - NOR Flash

Figure 52. Mode 2 and mode B read access waveforms

Memory transaction

A[25:0]

NADV

NEx

NOE

NWE High

D[15:0] Data driven by memory

ADDSET HCLK cycles DATAST HCLK cycles DATAHLD

HCLK cycles

MSv41678V1

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Figure 53. Mode 2 write access waveforms

Memory transaction

A[25:0]

NADV

NEx

NOE

NWE

Data bus Data driven by controller

ADDSET HCLK cycles DATAST HCLK cycles DATAHLD +1

HCLK cycles

MSv41679V1

Figure 54. Mode B write access waveforms

Memory transaction

A[25:0]

NADV

NEx

NOE

NWE

Data bus Data driven by controller

ADDSET HCLK cycles DATAST HCLK cycles DATAHLD +1

HCLK cycles

MSv41680V1

The differences with mode 1 are the toggling of NWE and the independent read and write
timings when extended mode is set (mode B).

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Table 98. FMC_BCRx bitfields (mode 2/B)

Bit number Bit name Value to set

31:24 Reserved 0x000

23:22 NBLSET[1:0] Don’t care
21 WFDIS As needed
20 CCLKEN As needed
19 CBURSTRW 0x0 (no effect in Asynchronous mode)
18:16 CPSIZE 0x0 (no effect in Asynchronous mode)
15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
14 EXTMOD 0x1 for mode B, 0x0 for mode 2
13 WAITEN 0x0 (no effect in Asynchronous mode)
12 WREN As needed
11 WAITCFG Don’t care
10 Reserved 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 Reserved 0x1
6 FACCEN 0x1
5:4 MWID As needed
3:2 MTYP 0x2 (NOR Flash memory)
1 MUXEN 0x0
0 MBKEN 0x1

Table 99. FMC_BTRx bitfields (mode 2/B)

Bit number Bit name Value to set

Duration of the data hold phase (DATAHLD HCLK cycles for read
31:30 DATAHLD accesses and DATAHLD+1 HCLK cycles for write accesses when
Extended mode is disabled).
29:28 ACCMOD 0x1 if Extended mode is set
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the access second phase (DATAST HCLK cycles) for
15:8 DATAST
read accesses.
7:4 ADDHLD Don’t care
Duration of the access first phase (ADDSET HCLK cycles) for read
3:0 ADDSET
accesses. Minimum value for ADDSET is 0.

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Table 100. FMC_BWTRx bitfields (mode 2/B)

Bit number Bit name Value to set

Duration of the data hold phase (DATAHLD+1 HCLK cycles for write
31:30 DATAHLD
accesses).
29:28 ACCMOD 0x1 if Extended mode is set
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the access second phase (DATAST HCLK cycles) for
15:8 DATAST
write accesses.
7:4 ADDHLD Don’t care
Duration of the access first phase (ADDSET HCLK cycles) for write
3:0 ADDSET
accesses. Minimum value for ADDSET is 0.

Note: The FMC_BWTRx register is valid only if the Extended mode is set (mode B), otherwise its
content is don’t care.

Mode C - NOR Flash - OE toggling

Figure 55. Mode C read access waveforms

Memory transaction

A[25:0]

NADV

NEx

NOE

NWE High

D[15:0] Data driven by memory

ADDSET HCLK cycles DATAST HCLK cycles DATAHLD

HCLK cycles

MSv41682V1

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Figure 56. Mode C write access waveforms

Memory transaction

A[25:0]

NADV

NEx

NOE

NWE

Data bus Data driven by controller

ADDSET HCLK cycles DATAST HCLK cycles DATAHLD +1

HCLK cycles

MSv41679V1

The differences compared with mode 1 are the toggling of NOE and the independent read
and write timings.

Table 101. FMC_BCRx bitfields (mode C)

Bit number Bit name Value to set

31:24 Reserved 0x000

23:22 NBLSET[1:0] Don’t care
21 WFDIS As needed
20 CCLKEN As needed
19 CBURSTRW 0x0 (no effect in Asynchronous mode)
18:16 CPSIZE 0x0 (no effect in Asynchronous mode)
15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
14 EXTMOD 0x1
13 WAITEN 0x0 (no effect in Asynchronous mode)
12 WREN As needed
11 WAITCFG Don’t care
10 Reserved 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 Reserved 0x1
6 FACCEN 0x1

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Table 101. FMC_BCRx bitfields (mode C) (continued)

Bit number Bit name Value to set

5:4 MWID As needed

3:2 MTYP 0x02 (NOR Flash memory)
1 MUXEN 0x0
0 MBKEN 0x1

Table 102. FMC_BTRx bitfields (mode C)

Bit number Bit name Value to set

Duration of the data hold phase (DATAHLD HCLK cycles for read
31:30 DATAHLD
accesses).
29:28 ACCMOD 0x2
27:24 DATLAT 0x0
23:20 CLKDIV 0x0
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the second access phase (DATAST HCLK cycles) for
15:8 DATAST
read accesses.
7:4 ADDHLD Don’t care
Duration of the first access phase (ADDSET HCLK cycles) for read
3:0 ADDSET
accesses. Minimum value for ADDSET is 0.

Table 103. FMC_BWTRx bitfields (mode C)

Bit number Bit name Value to set

Duration of the data hold phase (DATAHLD+1 HCLK cycles for write
31:30 DATAHLD
accesses).
29:28 ACCMOD 0x2
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the second access phase (DATAST HCLK cycles) for
15:8 DATAST
write accesses.
7:4 ADDHLD Don’t care
Duration of the first access phase (ADDSET HCLK cycles) for write
3:0 ADDSET
accesses. Minimum value for ADDSET is 0.

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Mode D - asynchronous access with extended address

Figure 57. Mode D read access waveforms

Memory transaction

A[25:0]

NADV

NBL[x:0]

NEx

NOE

NWE High

Data bus Data driven by memory

NBLSET ADDSET HCLK cycles ADDHLD DATAST HCLK cycles DATAHLD

HCLK HCLK HCLK cycles
cycles cycles
MSv41683V1

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Figure 58. Mode D write access waveforms

Memory transaction

A[25:0]

NADV

NBL[x:0]

NEx

NOE

NWE

Data bus Data driven by controller

NBLSET ADDSET HCLK cycles ADDHLD DATAST HCLK cycles DATAHLD +1

HCLK HCLK cycles HCLK cycles
cycles
MSv41684V1

The differences with mode 1 are the toggling of NOE that goes on toggling after NADV
changes and the independent read and write timings.

Table 104. FMC_BCRx bitfields (mode D)

Bit number Bit name Value to set

31:24 Reserved 0x000

23:22 NBLSET[1:0] As needed
21 WFDIS As needed
20 CCLKEN As needed
19 CBURSTRW 0x0 (no effect in Asynchronous mode)
18:16 CPSIZE 0x0 (no effect in Asynchronous mode)
15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
14 EXTMOD 0x1
13 WAITEN 0x0 (no effect in Asynchronous mode)
12 WREN As needed
11 WAITCFG Don’t care
10 Reserved 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0

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Table 104. FMC_BCRx bitfields (mode D) (continued)

Bit number Bit name Value to set

7 Reserved 0x1
6 FACCEN Set according to memory support
5:4 MWID As needed
3:2 MTYP As needed
1 MUXEN 0x0
0 MBKEN 0x1

Table 105. FMC_BTRx bitfields (mode D)

Bit number Bit name Value to set

Duration of the data hold phase (DATAHLD HCLK cycles for read
31:30 DATAHLD
accesses).
29:28 ACCMOD 0x3
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the second access phase (DATAST HCLK cycles) for read
15:8 DATAST
accesses.
Duration of the middle phase of the read access (ADDHLD HCLK
7:4 ADDHLD
cycles)
Duration of the first access phase (ADDSET HCLK cycles) for read
3:0 ADDSET
accesses. Minimum value for ADDSET is 1.

Table 106. FMC_BWTRx bitfields (mode D)

Bit number Bit name Value to set

Duration of the data hold phase (DATAHLD+1 HCLK cycles for write
31:30 DATAHLD
accesses).
29:28 ACCMOD 0x3
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15:8 DATAST Duration of the second access phase (DATAST HCLK cycles).
Duration of the middle phase of the write access (ADDHLD HCLK
7:4 ADDHLD
cycles)
Duration of the first access phase (ADDSET HCLK cycles) for write
3:0 ADDSET
accesses. Minimum value for ADDSET is 1.

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Muxed mode - multiplexed asynchronous access to NOR Flash memory

Figure 59. Muxed read access waveforms

Memory transaction

A[25:16]

NADV

NBL[x:0]

NEx

NOE

NWE High

AD[15:0] Lower address Data driven by memory

NBLSET ADDSET HCLK cycles ADDHLD DATAST HCLK cycles DATAHLD

HCLK HCLK HCLK cycles
cycles cycles
MSv41685V1

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Figure 60. Muxed write access waveforms

Memory transaction

A[25:16]

NADV

NBL[x:0]

NEx

NOE

NWE

AD[15:0] Lower address Data driven by controller

NBLSET ADDSET HCLK cycles ADDHLD DATAST HCLK cycles DATAHLD +1

HCLK HCLK cycles HCLK cycles
cycles
MSv41686V1

The difference with mode D is the drive of the lower address byte(s) on the data bus.

Table 107. FMC_BCRx bitfields (Muxed mode)

Bit number Bit name Value to set

31:24 Reserved 0x000

23:22 NBLSET[1:0] As needed
21 WFDIS As needed
20 CCLKEN As needed
19 CBURSTRW 0x0 (no effect in Asynchronous mode)
18:16 CPSIZE 0x0 (no effect in Asynchronous mode)
15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
14 EXTMOD 0x0
13 WAITEN 0x0 (no effect in Asynchronous mode)
12 WREN As needed
11 WAITCFG Don’t care
10 Reserved 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 Reserved 0x1

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Table 107. FMC_BCRx bitfields (Muxed mode) (continued)

Bit number Bit name Value to set

6 FACCEN 0x1
5:4 MWID As needed
3:2 MTYP 0x2 (NOR Flash memory) or 0x1(PSRAM)
1 MUXEN 0x1
0 MBKEN 0x1

Table 108. FMC_BTRx bitfields (Muxed mode)

Bit number Bit name Value to set

Duration of the data hold phase (DATAHLD HCLK cycles for read
31:30 DATAHLD
accesses, DATAHLD+1 HCLK cycles for write accesses).
29:28 ACCMOD 0x0
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15:8 DATAST Duration of the second access phase (DATAST HCLK cycles).
7:4 ADDHLD Duration of the middle phase of the access (ADDHLD HCLK cycles).
Duration of the first access phase (ADDSET HCLK cycles). Minimum
3:0 ADDSET
value for ADDSET is 1.

WAIT management in asynchronous accesses

If the asynchronous memory asserts the WAIT signal to indicate that it is not yet ready to
accept or to provide data, the ASYNCWAIT bit has to be set in FMC_BCRx register.
If the WAIT signal is active (high or low depending on the WAITPOL bit), the second access
phase (Data setup phase), programmed by the DATAST bits, is extended until WAIT
becomes inactive. Unlike the data setup phase, the first access phases (Address setup and
Address hold phases), programmed by the ADDSET and ADDHLD bits, are not WAIT
sensitive and so they are not prolonged.
The data setup phase must be programmed so that WAIT can be detected 4 HCLK cycles
before the end of the memory transaction. The following cases must be considered:

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1. The memory asserts the WAIT signal aligned to NOE/NWE which toggles:
DATAST ≥ ( 4 × HCLK ) + max_wait_assertion_time

2. The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):
if
max_wait_assertion_time > address_phase + hold_phase

then:

DATAST ≥ ( 4 × HCLK ) + ( max_wait_assertion_time – address_phase – hold_phase )

otherwise
DATAST ≥ 4 × HCLK

where max_wait_assertion_time is the maximum time taken by the memory to assert

the WAIT signal once NEx/NOE/NWE is low.
Figure 61 and Figure 62 show the number of HCLK clock cycles that are added to the
memory access phase after WAIT is released by the asynchronous memory (independently
of the above cases).

Figure 61. Asynchronous wait during a read access waveforms

Memory transaction

A[25:0]

address phase data setup phase

NEx

NWAIT don’t care don’t care

NOE

D[15:0] data driven by memory

4HCLK

MS30463V2

1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register.

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Figure 62. Asynchronous wait during a write access waveforms

Memory transaction

A[25:0]

address phase data setup phase

NEx

NWAIT don’t care don’t care

1HCLK

NWE

D[15:0] data driven by FMC

3HCLK

MSv40168V1

1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register.

CellularRAM™ (PSRAM) refresh management

The CellularRAM™ does not allow maintaining the chip select signal (NE) low for longer
than the tCEM timing specified for the memory device. This timing can be programmed in the
FMC_PCSCNTR register. It defines the maximum duration of the NE low pulse in HCLK
cycles for asynchronous accesses and FMC_CLK cycles for synchronous accesses

18.7.5 Synchronous transactions

The memory clock, FMC_CLK, is a submultiple of HCLK. It depends on the value of
CLKDIV and the MWID/ AHB data size, following the formula given below:

FMC_CLK divider ratio = max (CLKDIV + 1,MWID ( AHB data size ))

Whatever MWID size: 16 or 8-bit, the FMC_CLK divider ratio is always defined by the
programmed CLKDIV value.
Example:
• If CLKDIV=1, MWID = 16 bits, AHB data size=8 bits, FMC_CLK=HCLK/2.
NOR Flash memories specify a minimum time from NADV assertion to CLK high. To meet
this constraint, the FMC does not issue the clock to the memory during the first internal
clock cycle of the synchronous access (before NADV assertion). This guarantees that the
rising edge of the memory clock occurs in the middle of the NADV low pulse.

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Data latency versus NOR memory latency

The data latency is the number of cycles to wait before sampling the data. The DATLAT
value must be consistent with the latency value specified in the NOR Flash configuration
register. The FMC does not include the clock cycle when NADV is low in the data latency
count.
Caution: Some NOR Flash memories include the NADV Low cycle in the data latency count, so that
the exact relation between the NOR Flash latency and the FMC DATLAT parameter can be
either:
• NOR Flash latency = (DATLAT + 2) CLK clock cycles
• or NOR Flash latency = (DATLAT + 3) CLK clock cycles
Some recent memories assert NWAIT during the latency phase. In such cases DATLAT can
be set to its minimum value. As a result, the FMC samples the data and waits long enough
to evaluate if the data are valid. Thus the FMC detects when the memory exits latency and
real data are processed.
Other memories do not assert NWAIT during latency. In this case the latency must be set
correctly for both the FMC and the memory, otherwise invalid data are mistaken for good
data, or valid data are lost in the initial phase of the memory access.

Single-burst transfer
When the selected bank is configured in Burst mode for synchronous accesses, if for
example an AHB single-burst transaction is requested on 16-bit memories, the FMC
performs a burst transaction of length 1 (if the AHB transfer is 16 bits), or length 2 (if the
AHB transfer is 32 bits) and de-assert the chip select signal when the last data is strobed.
Such transfers are not the most efficient in terms of cycles compared to asynchronous read
operations. Nevertheless, a random asynchronous access would first require to re-program
the memory access mode, which would altogether last longer.

Cross boundary page for CellularRAM™ 1.5

CellularRAM™ 1.5 does not allow burst access to cross the page boundary. The FMC
controller allows to split automatically the burst access when the memory page size is
reached by configuring the CPSIZE bits in the FMC_BCR1 register following the memory
page size.

Wait management
For synchronous NOR Flash memories, NWAIT is evaluated after the programmed latency
period, which corresponds to (DATLAT+2) CLK clock cycles.
If NWAIT is active (low level when WAITPOL = 0, high level when WAITPOL = 1), wait
states are inserted until NWAIT is inactive (high level when WAITPOL = 0, low level when
WAITPOL = 1).
When NWAIT is inactive, the data is considered valid either immediately (bit WAITCFG = 1)
or on the next clock edge (bit WAITCFG = 0).
During wait-state insertion via the NWAIT signal, the controller continues to send clock
pulses to the memory, keeping the chip select and output enable signals valid. It does not
consider the data as valid.

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In Burst mode, there are two timing configurations for the NOR Flash NWAIT signal:
• The Flash memory asserts the NWAIT signal one data cycle before the wait state
(default after reset).
• The Flash memory asserts the NWAIT signal during the wait state
The FMC supports both NOR Flash wait state configurations, for each chip select, thanks to
the WAITCFG bit in the FMC_BCRx registers (x = 0..3).

Figure 63. Wait configuration waveforms

Memory transaction = burst of 4 half words

HCLK

CLK

A[25:16] addr[25:16]

NADV

NWAIT
(WAITCFG = 0)

NWAIT
(WAITCFG = 1)
inserted wait state

A/D[15:0] addr[15:0] data data data

ai15798c

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Figure 64. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM)

Memory transaction = burst of 4 half words

HCLK

CLK

A[25:16] addr[25:16]

NEx

NOE

High
NWE

NADV

NWAIT
(WAITCFG=
0)
(DATLAT + 2) inserted wait state
CLK cycles
A/D[15:0] Addr[15:0] data data data data

1 clock 1 clock
cycle cycle
Data strobes Data strobes
ai17723f

1. Byte lane outputs (NBL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM)
access, they are held low.

Table 109. FMC_BCRx bitfields (Synchronous multiplexed read mode)

Bit number Bit name Value to set

31:24 Reserved 0x000

23:22 NBLSET[1:0] Don’t care
21 WFDIS As needed
20 CCLKEN As needed
19 CBURSTRW No effect on synchronous read
18:16 CPSIZE 0x0 (no effect in Asynchronous mode)
15 ASYNCWAIT 0x0
14 EXTMOD 0x0
To be set to 1 if the memory supports this feature, to be kept at 0
13 WAITEN
otherwise
12 WREN No effect on synchronous read
11 WAITCFG To be set according to memory

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Table 109. FMC_BCRx bitfields (Synchronous multiplexed read mode) (continued)

Bit number Bit name Value to set

10 Reserved 0x0
9 WAITPOL To be set according to memory
8 BURSTEN 0x1
7 Reserved 0x1
6 FACCEN Set according to memory support (NOR Flash memory)
5-4 MWID As needed
3-2 MTYP 0x1 or 0x2
1 MUXEN As needed
0 MBKEN 0x1

Table 110. FMC_BTRx bitfields (Synchronous multiplexed read mode)

Bit number Bit name Value to set

31:30 DATAHLD Don’t care

29:28 ACCMOD 0x0
27-24 DATLAT Data latency
27-24 DATLAT Data latency
0x0 to get CLK = HCLK
23-20 CLKDIV 0x1 to get CLK = 2 × HCLK
..
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15-8 DATAST Don’t care
7-4 ADDHLD Don’t care
3-0 ADDSET Don’t care

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Figure 65. Synchronous multiplexed write mode waveforms - PSRAM (CRAM)

Memory transaction = burst of 2 half words

HCLK

CLK

A[25:16] addr[25:16]

NEx

Hi-Z
NOE

NWE

NADV

NWAIT
(WAITCFG = 0)

(DATLAT + 2) inserted wait state

CLK cycles
A/D[15:0] Addr[15:0] data data

1 clock 1 clock ai14731f

1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0.
2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active.

Table 111. FMC_BCRx bitfields (Synchronous multiplexed write mode)

Bit number Bit name Value to set

31:24 Reserved 0x000

23:22 NBLSET[1:0] Don’t care
21 WFDIS As needed
20 CCLKEN As needed
19 CBURSTRW 0x1
18:16 CPSIZE As needed (0x1 for CRAM 1.5)
15 ASYNCWAIT 0x0
14 EXTMOD 0x0

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Table 111. FMC_BCRx bitfields (Synchronous multiplexed write mode) (continued)

Bit number Bit name Value to set

To be set to 1 if the memory supports this feature, to be kept at 0

13 WAITEN
otherwise.
12 WREN 0x1
11 WAITCFG 0x0
10 Reserved 0x0
9 WAITPOL to be set according to memory
8 BURSTEN no effect on synchronous write
7 Reserved 0x1
6 FACCEN Set according to memory support
5-4 MWID As needed
3-2 MTYP 0x1
1 MUXEN As needed
0 MBKEN 0x1

Table 112. FMC_BTRx bitfields (Synchronous multiplexed write mode)

Bit number Bit name Value to set

31-30 DATAHLD Don’t care

29:28 ACCMOD 0x0
27-24 DATLAT Data latency
0x0 to get CLK = HCLK
23-20 CLKDIV
0x1 to get CLK = 2 × HCLK
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15-8 DATAST Don’t care
7-4 ADDHLD Don’t care
3-0 ADDSET Don’t care

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18.7.6 NOR/PSRAM controller registers

SRAM/NOR-Flash chip-select control register for bank x
(FMC_BCRx) (x = 1 to 4)
Address offset: 8 * (x – 1), (x = 1 to 4)
Reset value: Bank 1: 0x0000 30DB
Reset value: Bank 2: 0x0000 30D2
Reset value: Bank 3: 0x0000 30D2
Reset value: Bank 4: 0x0000 30D2
This register contains the control information of each memory bank, used for SRAMs,
PSRAM, FRAM and NOR Flash memories.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCLK CBURST
Res. Res. Res. Res. Res. Res. Res. Res. NBLSET[1:0] WFDIS CPSIZE[2:0]
EN RW

rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNC EXT WAIT WAIT WAIT BURST FACC MUX MBK
WREN Res. Res. MWID[1:0] MTYP[1:0]
WAIT MOD EN CFG POL EN EN EN EN

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:22 NBLSET[1:0]: Byte lane (NBL) setup
These bits configure the NBL setup timing from NBLx low to chip select NEx low.
00: NBL setup time is 0 AHB clock cycle
01: NBL setup time is 1 AHB clock cycle
10: NBL setup time is 2 AHB clock cycles
11: NBL setup time is 3 AHB clock cycles
Bit 21 WFDIS: Write FIFO disable
This bit disables the Write FIFO used by the FMC controller.
0: Write FIFO enabled (Default after reset)
1: Write FIFO disabled
Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the
FMC_BCR1 register.

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Bit 20 CCLKEN: Continuous clock enable

This bit enables the FMC_CLK clock output to external memory devices.
0: The FMC_CLK is only generated during the synchronous memory access (read/write
transaction). The FMC_CLK clock ratio is specified by the programmed CLKDIV value in the
FMC_BCRx register (default after reset).
1: The FMC_CLK is generated continuously during asynchronous and synchronous access. The
FMC_CLK clock is activated when the CCLKEN is set.
Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the
FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the
FMC_CLK continuous clock.
Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1
register. CLKDIV in FMC_BWTR1 is don’t care.
Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories
connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the
FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.)
Bit 19 CBURSTRW: Write burst enable
For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write
operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx
register.
0: Write operations are always performed in Asynchronous mode.
1: Write operations are performed in Synchronous mode.
Bits 18:16 CPSIZE[2:0]: CRAM page size
These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address
boundaries between pages. When these bits are configured, the FMC controller splits automatically
the burst access when the memory page size is reached (refer to memory datasheet for page size).
000: No burst split when crossing page boundary (default after reset)
001: 128 bytes
010: 256 bytes
011: 512 bytes
100: 1024 bytes
Others: reserved
Bit 15 ASYNCWAIT: Wait signal during asynchronous transfers
This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol.
0: NWAIT signal is not taken in to account when running an asynchronous protocol (default after
reset).
1: NWAIT signal is taken in to account when running an asynchronous protocol.
Bit 14 EXTMOD: Extended mode enable
This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses
inside the FMC_BWTR register, thus resulting in different timings for read and write operations.
0: values inside FMC_BWTR register are not taken into account (default after reset)
1: values inside FMC_BWTR register are taken into account
Note: When the Extended mode is disabled, the FMC can operate in mode 1 or mode 2 as follows:
– Mode 1 is the default mode when the SRAM/PSRAM memory type is selected
(MTYP = 0x0 or 0x01)
– Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).

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Bit 13 WAITEN: Wait enable bit

This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in
Synchronous mode.
0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after the
programmed Flash latency period).
1: NWAIT signal is enabled (its level is taken into account after the programmed latency period to
insert wait states if asserted) (default after reset).
Bit 12 WREN: Write enable bit
This bit indicates whether write operations are enabled/disabled in the bank by the FMC.
0: Write operations are disabled in the bank by the FMC, an AHB error is reported.
1: Write operations are enabled for the bank by the FMC (default after reset).
Bit 11 WAITCFG: Wait timing configuration
The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be
inserted when accessing the memory in Synchronous mode. This configuration bit determines if
NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:
0: NWAIT signal is active one data cycle before wait state (default after reset).
1: NWAIT signal is active during wait state (not used for PSRAM).
Bit 10 Reserved, must be kept at reset value.
Bit 9 WAITPOL: Wait signal polarity bit
Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous
mode.
0: NWAIT active low (default after reset)
1: NWAIT active high
Bit 8 BURSTEN: Burst enable bit
This bit enables/disables synchronous accesses during read operations. It is valid only for
synchronous memories operating in Burst mode.
0: Burst mode disabled (default after reset). Read accesses are performed in Asynchronous mode.
1: Burst mode enable. Read accesses are performed in Synchronous mode.
Bit 7 Reserved, must be kept at reset value.
Bit 6 FACCEN: Flash access enable
Enables NOR Flash memory access operations.
0: Corresponding NOR Flash memory access is disabled.
1: Corresponding NOR Flash memory access is enabled (default after reset).
Bits 5:4 MWID[1:0]: Memory data bus width
Defines the external memory device width, valid for all type of memories.
00: 8 bits
01: 16 bits (default after reset)
10: reserved
11: reserved

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Bits 3:2 MTYP[1:0]: Memory type

Defines the type of external memory attached to the corresponding memory bank.
00: SRAM/FRAM (default after reset for Bank 2...4)
01: PSRAM (CRAM) / FRAM
10: NOR Flash/OneNAND Flash (default after reset for Bank 1)
11: reserved
Bit 1 MUXEN: Address/data multiplexing enable bit
When this bit is set, the address and data values are multiplexed on the data bus, valid only with
NOR and PSRAM memories:
0: Address/data non multiplexed
1: Address/data multiplexed on databus (default after reset)
Bit 0 MBKEN: Memory bank enable bit
Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a
disabled bank causes an ERROR on AHB bus.
0: Corresponding memory bank is disabled.
1: Corresponding memory bank is enabled.

SRAM/NOR-Flash chip-select timing register for bank x (FMC_BTRx)

Address offset: 0x04 + 8 * (x – 1), (x = 1 to 4)
Reset value: 0x0FFF FFFF
This register contains the control information of each memory bank, used for SRAMs,
PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then
this register is partitioned for write and read access, that is, 2 registers are available: one to
configure read accesses (this register) and one to configure write accesses (FMC_BWTRx
registers).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD[1:0] ACCMOD[1:0] DATLAT[3:0] CLKDIV[3:0] BUSTURN[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30 DATAHLD[1:0]: Data hold phase duration

These bits are written by software to define the duration of the data hold phase in HCLK
cycles (refer to Figure 48 to Figure 60), used in asynchronous accesses:
For read accesses
00: DATAHLD phase duration = 0 × HCLK clock cycle (default)
01: DATAHLD phase duration = 1 × HCLK clock cycle
10: DATAHLD phase duration = 2 × HCLK clock cycle
11: DATAHLD phase duration = 3 × HCLK clock cycle
For write accesses
00: DATAHLD phase duration = 1 × HCLK clock cycle (default)
01: DATAHLD phase duration = 2 × HCLK clock cycle
10: DATAHLD phase duration = 3 × HCLK clock cycle
11: DATAHLD phase duration = 4 × HCLK clock cycle

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Bits 29:28 ACCMOD[1:0]: Access mode

Specifies the asynchronous access modes as shown in the timing diagrams. These bits are
taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.
00: Access mode A
01: Access mode B
10: Access mode C
11: Access mode D
Bits 27:24 DATLAT[3:0]: (see note below bit descriptions): Data latency for synchronous memory
For synchronous access with read/write Burst mode enabled (BURSTEN / CBURSTRW bits
set), defines the number of memory clock cycles (+2) to issue to the memory before
reading/writing the first data:
This timing parameter is not expressed in HCLK periods, but in FMC_CLK periods.
For asynchronous access, this value is don't care.
0000: Data latency of 2 CLK clock cycles for first burst access
1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)
Bits 23:20 CLKDIV[3:0]: Clock divide ratio (for FMC_CLK signal)
Defines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles:
0000: FMC_CLK period= 1x HCLK period
0001: FMC_CLK period = 2 × HCLK periods
0010: FMC_CLK period = 3 × HCLK periods
1111: FMC_CLK period = 16 × HCLK periods (default value after reset)
In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is don’t care.
Note: Refer to Section 18.7.5: Synchronous transactions for FMC_CLK divider ratio formula)
Bits 19:16 BUSTURN[3:0]: Bus turnaround phase duration
These bits are written by software to add a delay at the end of current read or write
transaction to next transaction on the same bank.
This delay allows to match the minimum time between consecutive transactions (tEHEL from
NEx high to NEx low) and the maximum time needed by the memory to free the data bus
after a read access (tEHQZ, chip enable high to output Hi-Z). This delay is recommended for
mode D and muxed mode. For non-muxed memory, the bus turnaround delay can be set to
minimum value.
(BUSTURN + 1)HCLK period ≥ max(tEHEL min, tEHQZ max)
For FRAM memories, the bus turnaround delay should be configured to match the minimum
tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive
transactions on the same bank (read/read, write/write, read/write and write/read) to match the
tPC memory timing. The chip select is toggling between any consecutive accesses.
(BUSTURN + 1)HCLK period ≥ tPC min

0000: BUSTURN phase duration = 1 HCLK clock cycle added

...
1111: BUSTURN phase duration = 16 x HCLK clock cycles added (default value after reset)

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Bits 15:8 DATAST[7:0]: Data-phase duration

These bits are written by software to define the duration of the data phase (refer to Figure 48
to Figure 60), used in asynchronous accesses:
0000 0000: Reserved
0000 0001: DATAST phase duration = 1 × HCLK clock cycles
0000 0010: DATAST phase duration = 2 × HCLK clock cycles
...
1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
For each memory type and access mode data-phase duration, refer to the respective figure
(Figure 48 to Figure 60).
Example: Mode 1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK
clock cycles.
Note: In synchronous accesses, this value is don’t care.
Bits 7:4 ADDHLD[3:0]: Address-hold phase duration
These bits are written by software to define the duration of the address hold phase (refer to
Figure 48 to Figure 60), used in mode D or multiplexed accesses:
0000: Reserved
0001: ADDHLD phase duration =1 × HCLK clock cycle
0010: ADDHLD phase duration = 2 × HCLK clock cycle
...
1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
For each access mode address-hold phase duration, refer to the respective figure (Figure 48
to Figure 60).
Note: In synchronous accesses, this value is not used, the address hold phase is always 1
memory clock period duration.
Bits 3:0 ADDSET[3:0]: Address setup phase duration
These bits are written by software to define the duration of the address setup phase (refer to
Figure 48 to Figure 60), used in SRAMs, ROMs, asynchronous NOR Flash and PSRAM:
0000: ADDSET phase duration = 0 × HCLK clock cycle
...
1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
For each access mode address setup phase duration, refer to the respective figure
(Figure 48 to Figure 60).
Note: In synchronous accesses, this value is don’t care.
In Muxed mode or mode D, the minimum value for ADDSET is 1.
In mode 1 and PSRAM memory, the minimum value for ADDSET is 1.

Note: PSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these
memories issue the NWAIT signal during the whole latency phase to prolong the latency as
needed.
With PSRAMs (CRAMs) the filled DATLAT must be set to 0, so that the FMC exits its latency
phase soon and starts sampling NWAIT from memory, then starts to read or write when the
memory is ready.
This method can be used also with the latest generation of synchronous Flash memories
that issue the NWAIT signal, unlike older Flash memories (check the datasheet of the
specific Flash memory being used).

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SRAM/NOR-Flash write timing registers x (FMC_BWTRx)

Address offset: 0x104 + 8 * (x – 1), (x = 1 to 4)
Reset value: 0x0FFF FFFF
This register contains the control information of each memory bank. It is used for SRAMs,
PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx
register, then this register is active for write access.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD[1:0] ACCMOD[1:0] Res. Res. Res. Res. Res. Res. Res. Res. BUSTURN[3:0]

rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30 DATAHLD[1:0]: Data hold phase duration

These bits are written by software to define the duration of the data hold phase in HCLK cycles
(refer to Figure 48 to Figure 60), used in asynchronous write accesses:
00: DATAHLD phase duration = 1 × HCLK clock cycle (default)
01: DATAHLD phase duration = 2 × HCLK clock cycle
10: DATAHLD phase duration = 3 × HCLK clock cycle
11: DATAHLD phase duration = 4 × HCLK clock cycle
Bits 29:28 ACCMOD[1:0]: Access mode.
Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are
taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.
00: Access mode A
01: Access mode B
10: Access mode C
11: Access mode D
Bits 27:20 Reserved, must be kept at reset value.
Bits 19:16 BUSTURN[3:0]: Bus turnaround phase duration
These bits are written by software to add a delay at the end of current write transaction to next
transaction on the same bank.
For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC
(precharge time) timings. The bus turnaround delay is inserted between any consecutive
transactions on the same bank (read/read, write/write, read/write and write/read). The chip select is
toggling between any consecutive accesses.
(BUSTURN + 1)HCLK period ≥ tPC min

0000: BUSTURN phase duration = 1 HCLK clock cycle added

...
1111: BUSTURN phase duration = 16 x HCLK clock cycles added (default value after reset)

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Bits 15:8 DATAST[7:0]: Data-phase duration.

These bits are written by software to define the duration of the data phase (refer to Figure 48 to
Figure 60), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:
0000 0000: Reserved
0000 0001: DATAST phase duration = 1 × HCLK clock cycles
0000 0010: DATAST phase duration = 2 × HCLK clock cycles
...
1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
Bits 7:4 ADDHLD[3:0]: Address-hold phase duration.
These bits are written by software to define the duration of the address hold phase (refer to
Figure 57 to Figure 60), used in asynchronous multiplexed accesses:
0000: Reserved
0001: ADDHLD phase duration = 1 × HCLK clock cycle
0010: ADDHLD phase duration = 2 × HCLK clock cycle
...
1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always
1 Flash clock period duration.
Bits 3:0 ADDSET[3:0]: Address setup phase duration.
These bits are written by software to define the duration of the address setup phase in HCLK cycles
(refer to Figure 48 to Figure 60), used in asynchronous accesses:
0000: ADDSET phase duration = 0 × HCLK clock cycle
...
1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash
clock period duration. In muxed mode, the minimum ADDSET value is 1.

PSRAM chip select counter register (FMC_PCSCNTR)

Address offset: 0x20
Reset value: 0x0000 0000
This register contains the PSRAM chip select counter value for Synchronous and
Asynchronous modes. The chip select counter is common to all banks and can be enabled
separately on each bank. During PSRAM read or write accesses, this value is loaded into a
timer which is decremented while the NE signal is held low. When the timer reaches 0, the
PSRAM controller splits the current access, toggles NE to allow PSRAM device refresh, and
restarts a new access. The programmed counter value guarantees a maximum NE pulse
width (tCEM) as specified for PSRAM devices. The counter is reloaded and starts
decrementing each time a new access is started by a transition of NE from high to low.
h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNTB4EN

CNTB3EN

CNTB2EN

CNTB1EN

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSCOUNT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:20 Reserved, must be kept at reset value.

Bit 19 CNTB4EN: Counter Bank 4 enable
This bit enables the chip select counter for PSRAM/NOR Bank 4.
0: Counter disabled for Bank 4
1: Counter enabled for Bank 4
Bit 18 CNTB3EN: Counter Bank 3 enable
This bit enables the chip select counter for PSRAM/NOR Bank 3.
0: Counter disabled for Bank 3.
1: Counter enabled for Bank 3
Bit 17 CNTB2EN: Counter Bank 2 enable
This bit enables the chip select counter for PSRAM/NOR Bank 2.
0: Counter disabled for Bank 2
1: Counter enabled for Bank 2
Bit 16 CNTB1EN: Counter Bank 1 enable
This bit enables the chip select counter for PSRAM/NOR Bank 1.
0: Counter disabled for Bank 1
1: Counter enabled for Bank 1
Bits 15:0 CSCOUNT[15:0]: Chip select counter.
These bits are written by software to define the maximum chip select low pulse duration. It is
expressed in FMC_CLK cycles for synchronous accesses and in HCLK cycles for asynchronous
accesses.
The counter is disabled if the programmed value is 0.

18.8 NAND Flash controller

The FMC generates the appropriate signal timings to drive the following types of device:
• 8- and 16-bit NAND Flash memories
The NAND bank is configured through dedicated registers (Section 18.8.7). The
programmable memory parameters include access timings (shown in Table 113) and ECC
configuration.

Table 113. Programmable NAND Flash access parameters

Parameter Function Access mode Unit Min. Max.

Number of clock cycles (HCLK)

Memory setup AHB clock cycle
required to set up the address Read/Write 1 255
time (HCLK)
before the command assertion
Minimum duration (in HCLK clock AHB clock cycle
Memory wait Read/Write 2 255
cycles) of the command assertion (HCLK)

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Table 113. Programmable NAND Flash access parameters (continued)

Parameter Function Access mode Unit Min. Max.

Number of clock cycles (HCLK)

during which the address must be
AHB clock cycle
Memory hold held (as well as the data if a write Read/Write 1 254
(HCLK)
access is performed) after the
command de-assertion
Number of clock cycles (HCLK)
Memory during which the data bus is kept AHB clock cycle
Write 1 255
databus high-Z in high-Z state after a write (HCLK)
access has started

18.8.1 External memory interface signals

The following tables list the signals that are typically used to interface NAND Flash memory.
Note: The prefix “N” identifies the signals which are active low.

8-bit NAND Flash memory

Table 114. 8-bit NAND Flash

FMC signal name I/O Function

A[17] O NAND Flash address latch enable (ALE) signal

A[16] O NAND Flash command latch enable (CLE) signal
D[7:0] I/O 8-bit multiplexed, bidirectional address/data bus
NCE O Chip select
NOE(= NRE) O Output enable (memory signal name: read enable, NRE)
NWE O Write enable
NWAIT/INT I NAND Flash ready/busy input signal to the FMC

Theoretically, there is no capacity limitation as the FMC can manage as many address
cycles as needed.

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16-bit NAND Flash memory

Table 115. 16-bit NAND Flash

FMC signal name I/O Function

A[17] O NAND Flash address latch enable (ALE) signal

A[16] O NAND Flash command latch enable (CLE) signal
D[15:0] I/O 16-bit multiplexed, bidirectional address/data bus
NCE O Chip select
NOE(= NRE) O Output enable (memory signal name: read enable, NRE)
NWE O Write enable
NWAIT/INT I NAND Flash ready/busy input signal to the FMC

Theoretically, there is no capacity limitation as the FMC can manage as many address
cycles as needed.

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18.8.2 NAND Flash supported memories and transactions

Table 116 shows the supported devices, access modes and transactions. Transactions not
allowed (or not supported) by the NAND Flash controller are shown in gray.

Table 116. Supported memories and transactions

AHB Memory Allowed/
Device Mode R/W Comments
data size data size not allowed

Asynchronous R 8 8 Y -
Asynchronous W 8 8 Y -
Asynchronous R 16 8 Y Split into 2 FMC accesses
NAND 8-bit
Asynchronous W 16 8 Y Split into 2 FMC accesses
Asynchronous R 32 8 Y Split into 4 FMC accesses
Asynchronous W 32 8 Y Split into 4 FMC accesses
Asynchronous R 8 16 Y -
Asynchronous W 8 16 N -
Asynchronous R 16 16 Y -
NAND 16-bit
Asynchronous W 16 16 Y -
Asynchronous R 32 16 Y Split into 2 FMC accesses
Asynchronous W 32 16 Y Split into 2 FMC accesses

18.8.3 Timing diagrams for NAND Flash memory

The NAND Flash memory bank is managed through a set of registers:
• Control register: FMC_PCR
• Interrupt status register: FMC_SR
• ECC register: FMC_ECCR
• Timing register for Common memory space: FMC_PMEM
• Timing register for Attribute memory space: FMC_PATT
Each timing configuration register contains three parameters used to define number of
HCLK cycles for the three phases of any NAND Flash access, plus one parameter that
defines the timing for starting driving the data bus when a write access is performed.
Figure 66 shows the timing parameter definitions for common memory accesses, knowing
that Attribute memory space access timings are similar.

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Figure 66. NAND Flash controller waveforms for common memory access

HCLK

A[25:0]

NCEx

NREG, High
NIOW,
NIOR MEMxSET
+1 MEMxWAIT + 1 MEMxHOLD
NWE,
NOE (1)
MEMxHIZ + 1
write_data

read_data Valid

MS33733V3

1. NOE remains high (inactive) during write accesses. NWE remains high (inactive) during read accesses.
2. For write access, the hold phase delay is (MEMHOLD) HCLK cycles and for read access is
(MEMHOLD + 2) HCLK cycles.

18.8.4 NAND Flash operations

The command latch enable (CLE) and address latch enable (ALE) signals of the NAND
Flash memory device are driven by address signals from the FMC controller. This means
that to send a command or an address to the NAND Flash memory, the CPU has to perform
a write to a specific address in its memory space.
A typical page read operation from the NAND Flash device requires the following steps:
1. Program and enable the corresponding memory bank by configuring the FMC_PCR
and FMC_PMEM (and for some devices, FMC_PATT, see Section 18.8.5: NAND Flash
prewait functionality) registers according to the characteristics of the NAND Flash
memory (PWID bits for the data bus width of the NAND Flash, PTYP = 1, PWAITEN =
0 or 1 as needed, see Section 18.6.2: NAND Flash memory address mapping for
timing configuration).
2. The CPU performs a byte write to the common memory space, with data byte equal to
one Flash command byte (for example 0x00 for Samsung NAND Flash devices). The
LE input of the NAND Flash memory is active during the write strobe (low pulse on
NWE), thus the written byte is interpreted as a command by the NAND Flash memory.
Once the command is latched by the memory device, it does not need to be written
again for the following page read operations.
3. The CPU can send the start address (STARTAD) for a read operation by writing four
bytes (or three for smaller capacity devices), STARTAD[7:0], STARTAD[16:9],
STARTAD[24:17] and finally STARTAD[25] (for 64 Mb x 8 bit NAND Flash memories) in
the common memory or attribute space. The ALE input of the NAND Flash device is
active during the write strobe (low pulse on NWE), thus the written bytes are
interpreted as the start address for read operations. Using the attribute memory space
makes it possible to use a different timing configuration of the FMC, which can be used

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to implement the prewait functionality needed by some NAND Flash memories (see
details in Section 18.8.5: NAND Flash prewait functionality).
4. The controller waits for the NAND Flash memory to be ready (R/NB signal high), before
starting a new access to the same or another memory bank. While waiting, the
controller holds the NCE signal active (low).
5. The CPU can then perform byte read operations from the common memory space to
read the NAND Flash page (data field + Spare field) byte by byte.
6. The next NAND Flash page can be read without any CPU command or address write
operation. This can be done in three different ways:
– by simply performing the operation described in step 5
– a new random address can be accessed by restarting the operation at step 3
– a new command can be sent to the NAND Flash device by restarting at step 2

18.8.5 NAND Flash prewait functionality

Some NAND Flash devices require that, after writing the last part of the address, the
controller waits for the R/NB signal to go low. (see Figure 67).

Figure 67. Access to non ‘CE don’t care’ NAND-Flash

1. CPU wrote byte 0x00 at address 0x7001 0000.

2. CPU wrote byte A7~A0 at address 0x7002 0000.
3. CPU wrote byte A16~A9 at address 0x7002 0000.
4. CPU wrote byte A24~A17 at address 0x7002 0000.
5. CPU wrote byte A25 at address 0x7802 0000: FMC performs a write access using FMC_PATT timing
definition, where ATTHOLD ≥ 7 (providing that (7+1) × HCLK = 112 ns > tWB max). This guarantees that
NCE remains low until R/NB goes low and high again (only requested for NAND Flash memories where
NCE is not don’t care).

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When this functionality is required, it can be ensured by programming the MEMHOLD value
to meet the tWB timing. However any CPU read access to the NAND Flash memory has a
hold delay of (MEMHOLD + 2) HCLK cycles and CPU write access has a hold delay of
(MEMHOLD) HCLK cycles inserted between the rising edge of the NWE signal and the next
access.
To cope with this timing constraint, the attribute memory space can be used by
programming its timing register with an ATTHOLD value that meets the tWB timing, and by
keeping the MEMHOLD value at its minimum value. The CPU must then use the common
memory space for all NAND Flash read and write accesses, except when writing the last
address byte to the NAND Flash device, where the CPU must write to the attribute memory
space.

18.8.6 Computation of the error correction code (ECC)

in NAND Flash memory
The FMC NAND Card controller includes two error correction code computation hardware
blocks, one per memory bank. They reduce the host CPU workload when processing the
ECC by software.
These two ECC blocks are identical and associated with Bank 2 and Bank 3. As a
consequence, no hardware ECC computation is available for memories connected to
Bank 4.
The ECC algorithm implemented in the FMC can perform 1-bit error correction and 2-bit
error detection per 256, 512, 1 024, 2 048, 4 096 or 8 192 bytes read or written from/to the
NAND Flash memory. It is based on the Hamming coding algorithm and consists in
calculating the row and column parity.
The ECC modules monitor the NAND Flash data bus and read/write signals (NCE and
NWE) each time the NAND Flash memory bank is active.
The ECC operates as follows:
• When accessing NAND Flash memory bank 2 or bank 3, the data present on the
D[15:0] bus is latched and used for ECC computation.
• When accessing any other address in NAND Flash memory, the ECC logic is idle, and
does not perform any operation. As a result, write operations to define commands or
addresses to the NAND Flash memory are not taken into account for ECC
computation.
Once the desired number of bytes has been read/written from/to the NAND Flash memory
by the host CPU, the FMC_ECCR registers must be read to retrieve the computed value.
Once read, they should be cleared by resetting the ECCEN bit to ‘0’. To compute a new data
block, the ECCEN bit must be set to one in the FMC_PCR registers.

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RM0432 Flexible static memory controller (FSMC)

To perform an ECC computation:

1. Enable the ECCEN bit in the FMC_PCR register.
2. Write data to the NAND Flash memory page. While the NAND page is written, the ECC
block computes the ECC value.
3. Read the ECC value available in the FMC_ECCR register and store it in a variable.
4. Clear the ECCEN bit and then enable it in the FMC_PCR register before reading back
the written data from the NAND page. While the NAND page is read, the ECC block
computes the ECC value.
5. Read the new ECC value available in the FMC_ECCR register.
6. If the two ECC values are the same, no correction is required, otherwise there is an
ECC error and the software correction routine returns information on whether the error
can be corrected or not.

18.8.7 NAND Flash controller registers

NAND Flash control registers (FMC_PCR)
Address offset: 0x80
Reset value: 0x0000 0018

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ECCPS[2:0] TAR3

rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAR[2:0] TCLR[3:0] Res. Res. ECCEN PWID[1:0] PTYP PBKEN PWAITEN Res.

rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:17 ECCPS[2:0]: ECC page size
Defines the page size for the extended ECC:
000: 256 bytes
001: 512 bytes
010: 1024 bytes
011: 2048 bytes
100: 4096 bytes
101: 8192 bytes
Bits 16:13 TAR[3:0]: ALE to RE delay
Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).
Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period
0000: 1 HCLK cycle (default)
1111: 16 HCLK cycles
Note: SET is MEMSET or ATTSET according to the addressed space.

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Bits 12:9 TCLR[3:0]: CLE to RE delay

Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).
Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period
0000: 1 HCLK cycle (default)
1111: 16 HCLK cycles
Note: SET is MEMSET or ATTSET according to the addressed space.
Bits 8:7 Reserved, must be kept at reset value.
Bit 6 ECCEN: ECC computation logic enable bit
0: ECC logic is disabled and reset (default after reset),
1: ECC logic is enabled.
Bits 5:4 PWID[1:0]: Data bus width
Defines the external memory device width.
00: 8 bits
01: 16 bits (default after reset).
10: reserved.
11: reserved.
Bit 3 PTYP: Memory type
Defines the type of device attached to the corresponding memory bank:
0: Reserved, must be kept at reset value
1: NAND Flash (default after reset)
Bit 2 PBKEN: NAND Flash memory bank enable bit
Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB
bus
0: Corresponding memory bank is disabled (default after reset)
1: Corresponding memory bank is enabled
Bit 1 PWAITEN: Wait feature enable bit
Enables the Wait feature for the NAND Flash memory bank:
0: disabled
1: enabled
Bit 0 Reserved, must be kept at reset value.

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RM0432 Flexible static memory controller (FSMC)

FIFO status and interrupt register (FMC_SR)

Address offset: 0x84
Reset value: 0x0000 0040
This register contains information about the FIFO status and interrupt. The FMC features a
FIFO that is used when writing to memories to transfer up to 16 words of data from the AHB.
This is used to quickly write to the FIFO and free the AHB for transactions to peripherals
other than the FMC, while the FMC is draining its FIFO into the memory. One of these
register bits indicates the status of the FIFO, for ECC purposes.
The ECC is calculated while the data are written to the memory. To read the correct ECC,
the software must consequently wait until the FIFO is empty.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. FEMPT IFEN ILEN IREN IFS ILS IRS

r rw rw rw rw rw rw

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 FEMPT: FIFO empty
Read-only bit that provides the status of the FIFO
0: FIFO not empty
1: FIFO empty
Bit 5 IFEN: Interrupt falling edge detection enable bit
0: Interrupt falling edge detection request disabled
1: Interrupt falling edge detection request enabled
Bit 4 ILEN: Interrupt high-level detection enable bit
0: Interrupt high-level detection request disabled
1: Interrupt high-level detection request enabled
Bit 3 IREN: Interrupt rising edge detection enable bit
0: Interrupt rising edge detection request disabled
1: Interrupt rising edge detection request enabled
Bit 2 IFS: Interrupt falling edge status
The flag is set by hardware and reset by software.
0: No interrupt falling edge occurred
1: Interrupt falling edge occurred
Note: If this bit is written by software to 1 it is set.
Bit 1 ILS: Interrupt high-level status
The flag is set by hardware and reset by software.
0: No Interrupt high-level occurred
1: Interrupt high-level occurred

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Bit 0 IRS: Interrupt rising edge status

The flag is set by hardware and reset by software.
0: No interrupt rising edge occurred
1: Interrupt rising edge occurred
Note: If this bit is written by software to 1 it is set.

Common memory space timing register (FMC_PMEM)

Address offset: Address: 0x88
Reset value: 0xFCFC FCFC
The FMC_PMEM read/write register contains the timing information for NAND Flash
memory bank. This information is used to access either the common memory space of the
NAND Flash for command, address write access and data read/write access.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MEMHIZ[7:0] MEMHOLD[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEMWAIT[7:0] MEMSET[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 MEMHIZ[7:0]: Common memory x data bus Hi-Z time

Defines the number of HCLK clock cycles during which the data bus is kept Hi-Z after the
start of a NAND Flash write access to common memory space on socket. This is only valid
for write transactions:
0000 0000: 1 HCLK cycle
1111 1110: 255 HCLK cycles
1111 1111: reserved.
Bits 23:16 MEMHOLD[7:0]: Common memory hold time
Defines the number of HCLK clock cycles for write access and HCLK (+2) clock cycles for
read access during which the address is held (and data for write accesses) after the
command is deasserted (NWE, NOE), for NAND Flash read or write access to common
memory space on socket x:
0000 0000: reserved.
0000 0001: 1 HCLK cycle for write access / 3 HCLK cycles for read access
1111 1110: 254 HCLK cycles for write access / 256 HCLK cycles for read access
1111 1111: reserved.
Bits 15:8 MEMWAIT[7:0]: Common memory wait time
Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
NOE), for NAND Flash read or write access to common memory space on socket. The
duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the
end of the programmed value of HCLK:
0000 0000: reserved
0000 0001: 2HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
1111 1110: 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
1111 1111: reserved.

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RM0432 Flexible static memory controller (FSMC)

Bits 7:0 MEMSET[7:0]: Common memory x setup time

Defines the number of HCLK (+1) clock cycles to set up the address before the command
assertion (NWE, NOE), for NAND Flash read or write access to common memory space on
socket x:
0000 0000: 1 HCLK cycle
1111 1110: 255 HCLK cycles
1111 1111: reserved

Attribute memory space timing register (FMC_PATT)

Address offset: 0x8C
Reset value: 0xFCFC FCFC
The FMC_PATT read/write register contains the timing information for NAND Flash memory
bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the
last address write access if the timing must differ from that of previous accesses (for
Ready/Busy management, refer to Section 18.8.5: NAND Flash prewait functionality).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZ[7:0] ATTHOLD[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAIT[7:0] ATTSET[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 ATTHIZ[7:0]: Attribute memory data bus Hi-Z time

Defines the number of HCLK clock cycles during which the data bus is kept in Hi-Z after the
start of a NAND Flash write access to attribute memory space on socket. Only valid for writ
transaction:
0000 0000: 0 HCLK cycle
1111 1110: 255 HCLK cycles
1111 1111: reserved.
Bits 23:16 ATTHOLD[7:0]: Attribute memory hold time
Defines the number of HCLK clock cycles for write access and HCLK (+2) clock cycles for
read access during which the address is held (and data for write access) after the command
deassertion (NWE, NOE), for NAND Flash read or write access to attribute memory space
on socket:
0000 0000: reserved
0000 0001: 1 HCLK cycle for write access / 3 HCLK cycles for read access
1111 1110: 254 HCLK cycles for write access / 256 HCLK cycles for read access
1111 1111: reserved.
Bits 15:8 ATTWAIT[7:0]: Attribute memory wait time
Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
NOE), for NAND Flash read or write access to attribute memory space on socket x. The
duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the
end of the programmed value of HCLK:
0000 0000: reserved
0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)
1111 1110: 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
1111 1111: reserved.

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Bits 7:0 ATTSET[7:0]: Attribute memory setup time

Defines the number of HCLK (+1) clock cycles to set up address before the command
assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space on
socket:
0000 0000: 1 HCLK cycle
1111 1110: 255 HCLK cycles
1111 1111: reserved.

ECC result registers (FMC_ECCR)

Address offset: 0x94
Reset value: 0x0000 0000
This register contain the current error correction code value computed by the ECC
computation modules of the FMC NAND controller. When the CPU reads the data from a
NAND Flash memory page at the correct address (refer to Section 18.8.6: Computation of
the error correction code (ECC) in NAND Flash memory), the data read/written from/to the
NAND Flash memory are processed automatically by the ECC computation module. When
X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU
must read the computed ECC value from the FMC_ECC registers. It then verifies if these
computed parity data are the same as the parity value recorded in the spare area, to
determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register
should be cleared after being read by setting the ECCEN bit to 0. To compute a new data
block, the ECCEN bit must be set to 1.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECC[31:16]

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC[15:0]

r r r r r r r r r r r r r r r r

Bits 31:0 ECC[31:0]: ECC result

This field contains the value computed by the ECC computation logic. Table 117 describes
the contents of these bitfields.

Table 117. ECC result relevant bits

ECCPS[2:0] Page size in bytes ECC bits

000 256 ECC[21:0]

001 512 ECC[23:0]
010 1024 ECC[25:0]
011 2048 ECC[27:0]
100 4096 ECC[29:0]
101 8192 ECC[31:0]

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RM0432 Flexible static memory controller (FSMC)

18.8.8 FMC register map

Table 118. FMC register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
ASYNCWAIT
CBURSTRW

BURSTEN
WAITCFG

WAITPOL
EXTMOD
CCLKEN

FACCEN
NBL

WAITEN

MUXEN
MBKEN
WFDIS

WREN
CPSIZE MWID MTYP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
FMC_BCR1 SET
0x00 [2:0] [1:0] [1:0]
[1:0]

Reset value 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 1 0 1 1

ASYNCWAIT
CBURSTRW

BURSTEN
WAITCFG

WAITPOL
EXTMOD

FACCEN
NBL

WAITEN

MUXEN
MBKEN
WREN
CPSIZE MWID MTYP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

Res.

Res.
FMC_BCR2 SET
0x08 [2:0] [1:0] [1:0]
[1:0]

Reset value 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0

ASYNCWAIT
CBURSTRW

BURSTEN
WAITCFG

WAITPOL
EXTMOD

FACCEN
NBL

WAITEN

MUXEN
MBKEN
WREN
CPSIZE MWID MTYP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

Res.

Res.
FMC_BCR3 SET
0x10 [2:0] [1:0] [1:0]
[1:0]

Reset value 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0

ASYNCWAIT
CBURSTRW

BURSTEN
WAITCFG

WAITPOL
EXTMOD

FACCEN
NBL

WAITEN

MUXEN
MBKEN
WREN
CPSIZE MWID MTYP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

Res.

Res.
FMC_BCR4 SET
0x18 [2:0] [1:0] [1:0]
[1:0]

Reset value 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0
DATAHLD [1:0]]

ACCMOD[1:0]

BUSTURN
FMC_BTR1 DATLAT[3:0] CLKDIV[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
0x04 [3:0]

Reset value 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DATAHLD [1:0]]

ACCMOD[1:0]

BUSTURN
FMC_BTR2 DATLAT[3:0] CLKDIV[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
0x0C [3:0]

Reset value 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DATAHLD [1:0]]

ACCMOD[1:0]

BUSTURN
FMC_BTR3 DATLAT[3:0] CLKDIV[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
0x14 [3:0]

Reset value 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DATAHLD [1:0]]

ACCMOD[1:0]

BUSTURN
FMC_BTR4 DATLAT[3:0] CLKDIV[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
0x1C [3:0]

Reset value 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CNTB4EN
CNTB3EN
CNTB2EN
CNTB1EN

FMC_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

CSCOUNT[15:0]
0x20 PCSCNTR

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Table 118. FMC register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
DATAHLD [1:0]]

ACCMOD[1:0]
BUSTURN

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FMC_BWTR1 DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
0x104 [3:0]

Reset value 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DATAHLD [1:0]]

ACCMOD[1:0]

BUSTURN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FMC_BWTR2 DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
0x10C [3:0]

Reset value 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DATAHLD [1:0]]

ACCMOD[1:0]

BUSTURN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FMC_BWTR3 Res. DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
0x114 [3:0]

Reset value 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DATAHLD [1:0]]

ACCMOD[1:0]

BUSTURN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

FMC_BWTR4 DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]

0x11C [3:0]

Reset value 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

PWAITEN
ECCEN

PBKEN
ECCPS PWID

PTYP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

Res.
FMC_PCR TAR[3:0] TCLR[3:0]
0x80 [2:0] [1:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0

FEMPT

IREN
IFEN
ILEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

IRS
FMC_SR

IFS
ILS
0x84
Reset value 1 0 0 0 0 0 0
FMC_PMEM MEMHIZx[7:0] MEMHOLDx[7:0] MEMWAITx[7:0] MEMSETx[7:0]
0x88
Reset value 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0
FMC_PATT ATTHIZ[7:0] ATTHOLD[7:0] ATTWAIT[7:0] ATTSET[7:0]
0x8C
Reset value 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0
FMC_ECCR ECCx[31:0]
0x94
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 91 for the register boundary addresses.

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RM0432 Octo-SPI interface (OCTOSPI)

19 Octo-SPI interface (OCTOSPI)

19.1 Introduction
The OCTOSPI supports two frame formats used by most external serial memories such as
serial PSRAMs, serial NAND and serial NOR Flash memories, HyperRAM™ and
HyperFlash™ memories:
• Indirect mode: all the operations are performed using the OCTOSPI registers.
• Status polling-mode: the external memory status register is periodically read and an
interrupt can be generated in case of flag setting.
• Memory-mapped mode: the external memory is memory mapped and it is seen by the
system as if it was an internal memory supporting both read and write operations.
The OCTOSPI supports two frame formats:
• the classical frame format with the command, address, alternate byte, dummy cycles
and data phase
• the HyperBus™ frame format

19.2 OCTOSPI main features

• Three functional modes: Indirect, Status polling, and Memory-mapped
• Read and write support in Memory-mapped mode
• Supports for single, dual, quad and octal communication
• Dual-quad mode, where 8 bits can be sent/received simultaneously by accessing two
quad memories in parallel
• SDR (single-data rate) and DTR (double-transfer rate) support
• Data strobe support
• Fully programmable opcode
• Fully programmable frame format
• HyperBus support
• Integrated FIFO for reception and transmission
• 8, 16, and 32-bit data accesses allowed
• DMA channel for indirect mode operations
• Interrupt generation on FIFO threshold, timeout, operation complete, and access error.

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19.3 OCTOSPI implementation

The table below describes the OCTOSPI implementation on STM32L4+ Series devices. The
full list of features is implemented in STM32L4P5xx and STM32L4Q5xx devices, while
STM32L4Rxxx and STM32L4Sxxx devices support a reduced set of features
.

Table 119. OCTOSPI implementation on STM32L4+ Series

STM32L4P5xx and STM32L4Rxxx and
OCTOSPI feature
STM32L4Q5xx STM32L4Sxxx

Hyperbus standard compliant X X

Xcella standard compliant X X
XSPI (JEDEC251ES) standard compliant X X
AMBA® AHB compliant interface X X
Supported functional modes: Indirect, Status polling,
X X
and Memory-mapped
Read and write support in Memory-mapped mode X X
Dual-quad mode support X X
SDR (single-data rate) and DTR (double-transfer
X X
rate) support
Data strobe (DS,DQS) support X X
Fully programmable opcode X X
Fully programmable frame format X X
Integrated FIFO for reception and transmission X X
8, 16, and 32-bit data accesses X X
Interrupt on FIFO threshold, timeout, operation
X X
complete, and access error
Compliant with dual-OCTOSPI arbiter
X -
(communication regulation feature)
Extended CSHT high time minimum duration X -
Refresh counter X -
HyperBus differential clock mode X -
Micron memory type (MTYP = 000) support X -

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RM0432 Octo-SPI interface (OCTOSPI)

19.4 OCTOSPI functional description

19.4.1 OCTOSPI block diagram

Figure 68. OCTOSPI block diagram for octal communication

Registers/ Clock
AHB/ control management Octo-SPI memory
AXI
OCTOSPI_CLK CLK
OCTOSPI_IO0 IO0
FIFO OCTOSPI_IO1 IO1
OCTOSPI_IO2 IO2
OCTOSPI_IO3 IO3
Shift OCTOSPI_IO4 IO4
register OCTOSPI_IO5 IO5
OCTOSPI_IO6 IO6
OCTOSPI_IO7 IO7
OCTOSPI_NCS NCS
OCTOSPI_DQS DQS
MSv43485V2

Figure 69. OCTOSPI block diagram in Quad mode

Registers/ Clock
AHB/ control management Quad-SPI memory
AXI
OCTOSPI_CLK CLK
OCTOSPI_IO0 Q0/SI
FIFO OCTOSPI_IO1 Q1/SO
Shift OCTOSPI_IO2 Q2/WP
register OCTOSPI_IO3 Q3/HOLD
OCTOSPI_nCS CS

MSv43486V2

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Figure 70. OCTOSPI block diagram when dual-Flash is enabled

Registers/ Clock
AHB/ control management Quad-SPI memory 1
AXI
OCTOSPI_CLK CLK
OCTOSPI_IO0 Q0/SI
FIFO OCTOSPI_IO1 Q1/SO
OCTOSPI_IO2 Q2/WP
OCTOSPI_IO3 Q3/HOLD
OCTOSPI_nCS CS

Shift
register Quad-SPI memory 2

CLK
OCTOSPI_IO4 Q0/SI
OCTOSPI_IO5 Q1/SO
OCTOSPI_IO6 Q2/WP
OCTOSPI_IO7 Q3/HOLD
CS

MSv43487V2

19.4.2 OCTOSPI interface to memory modes

The OCTOSPI can operate in two different operating modes:
• Regular-command mode
• HyperBus mode
In any of these two modes, the OCTOSPI uses from 6 to 12 signals to interface with a
memory, depending on the functional mode:
• nCS: chip-select used in all modes
• CLK: communication clock used in all modes
• DQS: data strobe used mainly in Octal mode
• IO[3:0]: data bus LSB used in all modes
• IO[7:4]: data bus MSB used in Dual-quad and Octal modes

19.4.3 OCTOSPI Regular-command mode

When in Regular-command mode, the OCTOSPI communicates with the external device
using commands. Each command can include five phases:
• Instruction phase
• Address phase
• Alternate-byte phase
• Dummy phase
• Data phase
Any of these phases can be configured to be skipped, but at least one of the instruction,
address, alternate byte, or data phases must be present.

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RM0432 Octo-SPI interface (OCTOSPI)

The nCS falls before the start of each command and rises again after each command
finishes.
In Memory-mapped mode, both read and write operation are supported, as a consequence,
some of the configuration registers are duplicated to specify write operations (read
operations are configured using regular registers).

Figure 71. SDR read command in Octal mode example

CS#

≈ ≈
CLK
Pre-drive

≈
IO[7:0] ECh 13h A[31:24] A[23:16] A[15:8] A[7:0] D0 D1 D2 D3

Address Dummy

MSv43488V1

The specific Regular-command mode features are configured through the registers in the
0x0100-0x01FC offset range.

Instruction phase
During this phase, a 1- to 4-byte instruction is sent to the external device specifying the type
of operation to be performed. The size of the instruction to be sent is configured in the
ISIZE[1:0] field of the OCTOSPI_CCR register and the instruction is programmed in the
INSTRUCTION[31:0] field of the OCTOSPI_IR register.
Most of the devices can receive instructions only 1 bit at a time from the IO0/SO signal
(Single-SPI mode), the instruction phase can optionally send 2 bits at a time (over IO0/IO1
in Dual-SPI mode), 4 bits at a time (over IO0 to IO3 in Quad-SPI mode) or 8-bits at a time
(over IO0 to IO7 in Octal SPI mode). This can be configured using the IMODE[2:0] field of
the OCTOSPI_CCR register.
The instruction can be sent in DTR (double-transfer rate) mode on each rising and falling
edge of the clock, by setting the IDTR bit in OCTOSPI_CCR.
When IMODE[2:0] = 000 in OCTOSPI_CCR, the instruction phase is skipped, and the
command sequence starts with the address phase, if present.
When in Memory-mapped mode, the instruction used for the write operation is specified in
the OCTOSPI_WIR register and the instruction format is specified in the OCTOSPI_WCCR
register. The instruction used for the read operation and the instruction format are specified
in the regular registers OCTOSPI_IR and OCTOSPI_CCR.

Address phase
In the address phase, 1 to 4 bytes are sent to the external device, to indicate the address of
the operation. The number of address bytes to be sent is configured in the ADSIZE[1:0] field
of the OCTOSPI_CCR register.
In Indirect and Automatic-polling modes, the address bytes to be sent are specified in the
ADDRESS[31:0] field of the OCTOSPI_AR register. In Memory-mapped mode, the address
is given directly via the AHB (from the Cortex-M core or from a DMA).
The address phase can send 1 it at a time (over SO in Single-SPI mode), 2 bits at a time
(over IO0/IO1 in Dual-SPI mode), 4 bits at a time (over IO0 to IO3 in Quad-SPI mode) or

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8 bits at a time (over IO0 to IO7 in Octal SPI mode). This can be configured using the
ADMODE[2:0] field of the OCTOSPI_CCR register.
The address can be sent in DTR mode (on each rising and falling edge of the clock) setting
the ADDTR bit in OCTOSPI_CCR.
When ADMODE[2:0] = 000, the address phase is skipped and the command sequence
proceeds directly to the next phase, if any.
In Memory-mapped mode, the address format for the write operation is specified in the
OCTOSPI_WCCR register. The address format for the read operation is specified in the
regular register OCTOSPI_CCR.

Alternate-bytes phase
In the alternate-bytes phase, 1 to 4 bytes are sent to the external device, generally to control
the mode of operation. The number of alternate bytes to be sent is configured in the
ABSIZE[1:0] field of the OCTOSPI_CCR register. The bytes to be sent are specified in the
OCTOSPI_ABR register.
The alternate-bytes phase can send 1 bit at a time (over SO in Single-SPI mode), 2 bits at a
time (over IO0 and IO1 in Dual-SPI mode), 4 bits at a time (over IO0 to IO3 in Quad-SPI
mode) or 8 bits at a time (over IO0 to IO7 in Octal SPI mode). This can be configured using
the ABMODE[2:0] field of the OCTOSPI_CCR register.
The alternate bytes can be sent in DTR mode (on each rising and falling edge of the clock)
setting the ABDTR bit of OCTOSPI_CCR.
When ABMODE[2:0] = 000, the alternate-bytes phase is skipped and the command
sequence proceeds directly to the next phase, if any.
There may be times when only a single nibble needs to be sent during the alternate-byte
phase rather than a full byte, such as when the Dual-SPI mode is used and only two cycles
are used for the alternate bytes.
In this case, the firmware can use the Quad-SPI mode (ABMODE[2:0] = 011) and send a
byte with bits 7 and 3 of ALTERNATE[31:0] set to 1 (keeping the IO3 line high), and bits 6
and 2 set to 0 (keeping the IO2 line low), in the OCSTOSPI_IR register.
The upper two bits of the nibble to be sent are then placed in bits 4:3 of ALTERNATE[31:0]
while the lower two bits are placed in bits 1 and 0. For example, if the nibble 2 (0010) is to be
sent over IO0/IO1, then ALTERNATE[31:0] must be set to 0x8A (1000_1010).
In Memory-mapped mode, the alternate bytes used for the write operation are specified in
the OCTOSPI_WABR register and the alternate byte format is specified in the
OCTOSPI_WCCR register. The alternate bytes used for read operation and the alternate
byte format are specified in the regular registers OCTOSPI_ABR and OCTOSPI_CCR.

Dummy-cycles phase
In the dummy-cycles phase, 1 to 31 cycles are given without any data being sent or
received, in order to give the external device, the time to prepare for the data phase when
the higher clock frequencies are used. The number of cycles given during this phase is
specified in the DCYC[4:0] field of the OCTOSPI_TCR register. In both SDR and DTR
modes, the duration is specified as a number of full CLK cycles.
When DCYC[4:0] = 00000, the dummy-cycles phase is skipped, and the command
sequence proceeds directly to the data phase, if present.

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RM0432 Octo-SPI interface (OCTOSPI)

In order to assure enough “turn-around” time for changing the data signals from the output
mode to the input mode, there must be at least one dummy cycle when using the Dual-SPI,
the Quad-SPI or the Octal-SPI mode, to receive data from the external device.
It is recommended to have at least five dummy cycles when using memories with DQS
activated.
In Memory-mapped mode, the dummy cycles for the write operations are specified in the
OCTOSPI_WTCR register. The dummy cycles for the read operation are specified in the
regular register (OCTOSPI_TCR)

Data phase
During the data phase, any number of bytes can be sent to or received from the external
device.
In Indirect mode, the number of bytes to be sent/received is specified in the OCTOSPI_DLR
register. In this mode, the data to be sent to the external device must be written to the
OCTOSPI_DR register, while in Indirect-read mode the data received from the external
device is obtained by reading from the OCTOSPI_DR register.
In Automatic-polling mode, the number of bytes to be received is specified in the
OCTOSPI_DLR register and the data received from the external device can be obtained by
reading from the OCTOSPI_DR register.
In Memory-mapped mode, the data read or written, is sent or received directly over the AHB
to the Cortex core or to a DMA.
The data phase can send/receive 1 bit at a time (over SO/SI in Single-SPI mode), 2 bits at a
time (over IO0/IO1 in Dual-SPI mode), 4 bits at a time (over IO0 to IO3 in Quad-SPI mode)
or 8 bits at a time (over IO0 to IO7 in Octal SPI mode). This can be configured using the
DMODE[2:0] field of the OCTOSPI_CCR register.
The data can be sent or received in DTR mode (on each rising and falling edge of the clock)
setting the DDTR bit of OCTOSPI_CCR.
When DMODE[2:0] = 000, the data phase is skipped, and the command sequence finishes
immediately by raising the nCS. This configuration must be used only in Indirect-write mode.
In Memory-mapped mode, the data format for the write operation is specified in the
OCTOSPI_WCCR register. The data format for the read operation is specified in the regular
register OCTOSPI_CCR.

DQS usage
The DQS signal can be used for data strobing during the read transactions when the device
toggles the DQS aligned with the data.
The DQS management can be enabled by setting the DQS enable (DQSE) bit of
OCTOSPI_CCR.

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Figure 72. DTR read in Octal mode with DQS (Macronix mode) example
CS#

≈
CLK

≈
≈
DQS

≈
IO[7:0] EEh 11h A[31:24] A[23:16] A[15:8] A[7:0] D1 D0 D3 D2

Word Word
Address Dummy unit unit

MSv43489V1

19.4.4 OCTOSPI Regular-command mode signal interface

Single-SPI mode
The legacy SPI mode allows just a single bit to be sent/received serially. In this mode, the
data is sent to the external device over the SO signal (whose I/O are shared with IO0). The
data received from the external device arrives via SI (whose I/O are shared with IO1).
The different phases can each be configured separately to use this Single-bit mode by
setting to 001 the IMODE/ADMODE/ABMODE/DMODE fields (in OCTOSPI_CCR and
OCTOSPI_WCCR).
In each phase configured in Single-SPI mode:
• IO0 (SO) is in output mode.
• IO1 (SI) is in input mode (high impedance).
• IO2 is in output mode and forced to 0 (to deactivate the “write protect” function).
• IO3 is in output mode and forced to 1 (to deactivate the “hold” function).
• IO4/IO5/IO6/IO7 are in output mode and forced to 0.
This is the case even for the dummy phase if DMODE[2:0] = 001.

Dual-SPI mode
In Dual-SPI mode, two bits are sent/received simultaneously over the IO0/IO1 signals.
The different phases can each be configured separately to use Dual-SPI mode by setting
to 010 the IMODE/ADMODE/ABMODE/DMODE fields (in OCTOSPI_CCR and
OCTOSPI_WCCR).
In each phase configured in Dual-SPI mode:
• IO0/IO1 are at high-impedance (input) during the data phase for the read operations,
and outputs in all other cases.
• IO2 is in output mode and forced to 0.
• IO3 is in output mode and forced to 1.
• IO4/IO5/IO6/IO7 are in output mode and forced to 0.
In the dummy phase when DMODE[2:0] = 010, IO0/IO1 are always high-impedance.

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RM0432 Octo-SPI interface (OCTOSPI)

Quad-SPI mode
In Quad-SPI mode, four bits are sent/received simultaneously over the IO0/IO1/IO2/IO3
signals.
The different phases can each be configured separately to use the Quad-SPI mode by
setting to 011 the IMODE/ADMODE/ABMODE/DMODE fields (in OCTOSPI_CCR and
OCTOSPI_WCCR).
In each phase configured in Quad-SPI mode:
• IO0/IO1/IO2/IO3 are all are at high-impedance (input) during the data phase for the
read operations, and outputs in all other cases.
• IO4/IO5/IO6/IO7 are in output mode and forced to 0.
In the dummy phase when DMODE[2:0] = 011, IO0/IO1/IO2/IO3 are all high-impedance.
IO2 and IO3 are used only in Quad-SPI mode. If none of the phases are configured to use
the Quad-SPI mode, then the pins corresponding to IO2 and IO3 can be used for other
functions even while the OCTOSPI is active.

Octo-SPI mode
In regular Octo-SPI mode, the eight bits are sent/received simultaneously over the IO[0:7]
signals.
The different phases can each be configured separately to use the Octo-SPI mode by
setting to 100 the IMODE/ADMODE/ABMODE/DMODE fields (in OCTOSPI_CCR and
OCTOSPI_WCCR).
In each phase that is configured in Octal mode, IO[0:7] are all at high-impedance (input)
during the data phase for read operations, and outputs in all other cases.
In the dummy phase when DMODE[2:0] = 100, IO[0:7] are all high-impedance.
IO[4:7] are used only in Octo-SPI mode. If none of the phases are configured to use
Octo-SPI mode, then the pins corresponding to IO[4:7] can be used for other functions even
while the OCTOSPI is active.

Single-data rate (SDR) mode

By default, all the phases operate in Single-data rate (SDR) mode.
In SDR mode, when the OCTOSPI is driving the IO0/SO, IO1, IO2, IO3, IO4, IO5, IO6 and
IO7 signals, these signals transition only with the falling edge of CLK.
When receiving data in SDR mode, the OCTOSPI assumes that the external devices also
send the data using CLK falling edge. By default (when SSHIFT = 0 in OCTOSPI_TCR), the
signals are sampled using the following (rising) edge of CLK.

Figure 73. SDR write command in Octo-SPI mode example.

CS#
≈

CLK
≈
≈≈

IO[7:0] 02h FDh A[31:24] A[23:16] A[15:8] A[7:0] D0 D1 D254 D255

MSv43490V1

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Double-transfer rate (DTR) mode

Each of the instruction/address/alternate/data phase can be configured to operate in
Double-transfer rate (DTR) mode setting IDTR/ADDTR/ABDTR/DDTR bit in the
OCTOSPI_CCR register.
In Memory-mapped mode, the DTR mode for each phases of the write operations is
specified in the OCTOSPI_WCCR register. The DTR mode for each phases of the read
operations is specified in the regular register (OCTOSPI_CCR).
In DTR mode, when the OCTOSPI drives the IO0/SO, IO1, IO2, IO3, IO4, IO5, IO6 and IO7
signals in the instruction/address/alternate-byte/data phases, a bit is sent or received on
each of the falling and rising edges of CLK.
When receiving data in DTR mode, the OCTOSPI assumes that the external device also
send the data using both CLK rising and falling edges. When DDTR = 1 in OCTOSPI_CCR,
the software must clear SSHIFT in OCTOSPI_TCR. Thus, the signals are sampled one half
of a CLK cycle later (on the following, opposite edge).
In DTR mode, it is recommended to set the delay hold quarter cycle (DHQC) bit of
OCTOSPI_TCR, to shift the outputs by a quarter of cycle and avoid to hold issues on the
memory side.
Note: DHQC must not be set when the prescaler value is 1, as this action leads to unpredictable
behavior.

Figure 74. DTR write in Octal mode (Macronix mode) example

CS#

CLK ≈
≈ ≈ ≈

IO[7:0] 02h FDh A[31:24] A[23:16] A[15:8] A[7:0] D1 D0 D255 D254

Word Unit Word Unit

MSv43491V1

Dual-quad mode
When the DQM = 1 in OCTOSPI_CR, the OCTOSPI is in Dual-quad mode: two external
Quad-SPI devices (device A and device B) are used in order to send/receive 8 bits (or
16 bits in DTR mode) every cycle, effectively doubling the throughput as well as the
capacity.
Each device (A or B) uses the same CLK and nCS signals, but each has separate IO0, IO1,
IO2, and IO3 signals.
The Dual-quad mode can be used in conjunction with the Single-bit, Dual-bit, and Quad-bit
modes, as well as with either the SDR or the DTR mode.
The device size, as specified in DEVSIZE[4:0] of OCTOSPI_DCR1, must reflect the total
external device capacity, that is the double of the size of one individual component.
If address X is even, then the byte that the OCTOSPI gives for address X is the byte at the
address X/2 of device A, and the byte that the OCTOSPI gives for address X + 1 is the byte
at the address X/2 of device B. In other words, the bytes at even addresses are all stored in
device A and the bytes at odd addresses are all stored in device B.

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RM0432 Octo-SPI interface (OCTOSPI)

When reading the status registers of the devices in Dual-quad mode, twice as many bytes
must be read compared to the same read in Regular mode: if each device gives eight valid
bits after the instruction for fetching the status register, then the OCTOSPI must be
configured with a data length of 2 bytes (16 bits), and the OCTOSPI receives one byte from
each device.
If each device gives a status of 16 bits, then the OCTOSPI must be configured to read
4 bytes to get all the status bits of both devices in Dual-quad mode. The least-significant
byte of the result (in the data register) is the least-significant byte of device A status register.
The next byte is the least-significant byte of device B status register. Then, the third byte of
the data register is the device A second byte. The forth byte is the device B second byte (if
devices have 16-bit status registers).
An even number of bytes must always be accessed in Dual-quad mode. For this reason,
bit 0 of the DL[31:0] field in OCTOSPI_DLR is stuck at 1 when DQM = 1.
In Dual-quad mode, the behavior of device A interface signals is basically the same as in
Normal mode. Device B interface signals have exactly the same waveforms as Device A
ones during the instruction, address, alternate-byte, and dummy-cycles phases. In other
words, each device always receives the same instruction and the same address.
Then, during the data phase, the AIOx and the BIOx buses both transfer data in parallel, but
the data that is sent to (or received from) device A is distinct than the one from device B.

19.4.5 HyperBus mode

In HyperBus mode, the OCTOSPI can communicate with the external device using the
HyperBus protocol.
The HyperBus uses 11 to 12 pins depending on the operating voltage:
• IO[7:0] as bidirectional data bus
• RWDS for read and write data strobe and latency insertion (mapped on DQS pin)
• nCS
• CLK
The HyperBus does not require any command specification nor any alternate bytes. As a
consequence, a separate register set is used to define the timing of the transaction.
The HyperBus frame is composed of two phases:
• Command/address phase
• Data phase
The nCS falls before the start of a transaction and rises again after each transaction
finishes.

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Octo-SPI interface (OCTOSPI) RM0432

Figure 75. Example of HyperBus read operation

CS#

t RWR =Read Write Recovery t ACC = Initial Access

CK

High = 2x Latency Count

RWDS Low = 1x Latency Count

RWDS and Data

Latency Count
are edge aligned
47:40 39:32 31:24 23:16 15:8 7:0 Dn Dn Dn+1 Dn+1
DQ[7:0] A B A B

Command-Address
Memory drives DQ[7:0]
and RWDS
Host drives DQ[7:0] and Memory drives RWDS
MSv43492V1

The specific HyperBus features are configured through the registers in the 0x0200-0x02FC
offset range.

Command/address phase
During this initial phase, the OCTOSPI sends 48 bits over IO[7:0] to specify the operations
to be performed with the external device.

Table 120. Command/address phase description

CA bit Bit name Description

47 R/W# Identifies the transaction as a read or a write

Indicates if the transaction accesses the memory or the register
46 Address space
space
45 Burst type Indicates if the burst is linear or wrapped
Row and upper
44-16 Selects the row and the upper column addresses
column address
15-3 Reserved -
Lower column
2-0 Select the starting 16-bit word within the half page
address

The address space is configured through the memory type MTYP[2:0] field of the
OCTOSPI_DCR1 register.
The total size of the device is configured in the device size DEVSIZE[4:0] field of the
OCTOSPI_DCR1 register. In case of multi-chip product (MCP), the device size is the sum of
all the sizes of all the dies of the MCP.

Read and write operation with initial latency

The HyperBus read and write operations need to respect two timings:
• tRWR: minimal read/write recovery time for the device (defined in TRWR[7:0] of
OCTOSPI_HLCR)
• tACC: access time for the device (defined in TAC[7:0] of OCTOSPI_HLCR)

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RM0432 Octo-SPI interface (OCTOSPI)

During the read operation, the RWDS is used by the device, in two ways:
• during the command/address phase, to request an additional latency
• during the data phase, for data strobing

Figure 76. HyperBus read operation with initial latency

CS#

t RWR =Read Write Recovery t ACC = Initial Access

CK

High = 2x Latency Count

RWDS Low = 1x Latency Count

RWDS and Data

Latency Count
are edge aligned
47:40 39:32 31:24 23:16 15:8 7:0 Dn Dn Dn+1 Dn+1
DQ[7:0] A B A B

Command-Address
Memory drives DQ[7:0]
and RWDS
Host drives DQ[7:0] and Memory drives RWDS
MSv43492V1

During the write operation the RWDS is used:

• By the device, during the command/address phase, to request an additional latency
• By the OCTOSPI, during the data phase, for write data masking

Figure 77. HyperBus write operation with initial latency

CS#

t RWR =Read Write Recovery tACC= Access

CK

High = 2x Latency Count

Low = 1x Latency Count
RWDS

Latency CK and Data

Count are center aligned
Dn Dn Dn+1 Dn+1
DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0 A B A B

Command-Address Host drives DQ[7:0]

and RWDS
Host drives DQ[7:0] and Memory drives RWDS
MSv43494V1

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Read and write operation with additional latency

If the device needs an additional latency (during refresh period of a SDRAM for example),
RWDS must be tied to one during one of the RWDS signals, during the command/address
phase.
An additional tACC duration is added by the OCTOSPI to meet the device request.

Figure 78. HyperBus read operation with additional latency

CS#
tRWR=Read Write Recovery Additional Latency tACC = Access

CK
Latency Count 1 Latency Count 2

RWDS High = 2x Latency Count

Low = 1x Latency Count
RWDS and Data
are edge aligned

DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0 Dn

A
Dn
B
Dn+1
A
Dn+1
B

Command-Address Memory drives DQ[7:0]

and RWDS
Host drives DQ[7:0] and Memory drives RWDS

MSv43495V1

Figure 79. HyperBus write operation with additional latency

CS#

Additional Latency
tRWR= Read Write Recovery
t ACC = Initial Access

CK

RWDS High = 2x Latency Count

Low = 1x Latency Count
CK and Data
Latency Count 1 Latency Count 2
are center aligned
Dn Dn Dn+1 Dn+1
DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0
A B A B

Host drives DQ[7:0]

Command-Address and RWDS
Host drives DQ[7:0] and Memory drives RWDS
MSv43496V1

Fixed latency mode

Some devices or some applications may not want to operate with a variable latency time as
described above.
The latency can be forced to 2 x tACC by setting the Latency mode (LM) bit of
OCTOSPI_HLCR.
In this Fixed latency mode, the state of the RWDS signal is not taken into account by the
OCTOSPI and an additional latency is always added leading to a fixed 2 x tACC latency time.

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RM0432 Octo-SPI interface (OCTOSPI)

Write operation with no latency

Some devices can also require a zero latency for the write operations.
This zero write latency can be forced by setting the write zero latency (WZL) bit of
OCTOSPI_HLCR).

Figure 80. HyperBus write operation with no latency

CS#

CK

RWDS Memory drives RWDS but master ignores

DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0 15:8 7:0

Command-Address Data

MSv43497V1

Latency on page-crossing during the read operations

An additional latency can be needed by some devices for the read operation when crossing
pages.
The initial latency must be respected for any page access, as a consequence, when the first
access is close to the page boundary, a latency is automatically added at the page crossing
to respect the tACC time.

Figure 81. HyperBus read operation page crossing with latency

12 Clock 9 Words
Initial Latency Data
CS#

CK
3 Clock Initial Page
Crossing Latency
RDS
DQ[7:0] A0 02 46 8A 80 07 dd dd dd dd dd dd dd dd dd dd dd dd dd dd

Read from Address = 123457h Address Address Address Address Address Address Address
123457 123458 12345D 12345E 12345F 123460 123461

MSv43498V1

19.4.6 Common functionality between the Regular-command and

HyperBus modes
The OCTOSPI supports some specific features common to both the Regular-command and
the HyperBus modes, such as:
• CS boundary and regulation

CS boundary and refresh

Two processes can be activated to regulate the OCTOSPI transactions:
• CS boundary
• Refresh

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The CS boundary feature limits a transaction to a boundary of aligned addresses. The size
of the address to be aligned with, is configured in the CS boundary CSBOUND[4:0] field of
OCTOSPI_DCR3 and it is equal to 2CSBOUND.
As an example, if CSBOUND(4:0] = 0x4, the boundary is set to 24 = 16 bytes. As a
consequence, the nCS is released each time that the LSB address is equal to 0xF and each
time that a new transaction is issued to address the next data.
If CSBOUND[4:0] = 0, the feature is disabled and a minimum value of 3 is recommended.
The CS boundary feature cannot be used for Flash memory devices in write mode since a
command is necessary to program another page of the Flash memory.
The refresh feature limits the duration of the transactions to the value programmed in the
REFRESH[31:0] field of OCTOSPI_DCR4. The duration is expressed in number of cycles.
This allows an external RAM to perform its internal refresh operation regularly.
The refresh value must be greater than the minimal transaction size in terms of number of
cycles including the command/address/alternate/dummy phases.
If CS boundary and refresh are enabled at the same time, the nCS is released on the first
condition met.

Communication regulation feature

Note: This section is relevant only when communication regulation feature is supported. Refer to
Section 19.3: OCTOSPI implementation.
The communication regulation feature limits the maximum length of a transaction to the
value programmed in the maximum transfer MAXTRAN[7:0] field of OCTOSPI_DCR3.
If the number of clock cycles reach the MAXTRAN + 1 value, and if the second OCTOSPI
requests an access, the nCS is released and a new transaction is issued to address the
next data. If the second OCTOSPI does not request an access, the transaction is not
stopped and the nCS is not released.
If MAXTRAN[7:0] = 0, no limitation occurs.
The MAXTRAN[7:0] value must be greater than the minimal transaction size in terms of
number of cycles including the command/address/alternate/dummy phases.
The communication regulation feature cannot be used for Flash memory devices in write
mode, since a command is necessary to program another page of the Flash memory.If CS
boundary, refresh and communication regulation are enabled at the same time, the nCS is
released on the first condition met.

19.4.7 OCTOSPI operating modes introduction

The OCTOSPI has three operating modes regardless of the low-level protocol used (either
regular or HyperBus):
• Indirect mode (read or write)
• Status polling mode
• Memory-mapped mode

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19.4.8 OCTOSPI Indirect mode

In Indirect mode, the commands are started by writing to the OCTOSPI registers and the
data is transferred by writing or reading the data register, in a similar way to other
communication peripherals.
When FMODE[1:0] = 0 in OCTOSPI_CR, the OCTOSPI is in Indirect-write mode: bytes are
sent to the external device during the data phase. Data is provided by writing to
OCTOSPI_DR.
When FMODE[1:0] = 01, the OCTOSPI is in Indirect-read mode: bytes are received from
the external device during the data phase. Data is recovered by reading OCTOSPI_DR.
In Indirect mode, when the OCTOSPI is configured in DTR mode over eight lanes, the given
starting address must be even.
The number of bytes to be read/written is specified in OCTOSPI_DLR:
• If DL[31:0] = 0xFFFF FFFF, the data length is considered undefined and the OCTOSPI
simply continues to transfer data until it reaches the end of the external device (as
defined by DEVSIZE). If no bytes are to be transferred, DMODE[2:0] must be set to 0 in
OCTOSPI_CCR.
• If DL[31:0] = 0xFFFF FFFFF and DEVSIZE[4:0] = 0x1F (its maximum value indicating
at 4-Gbyte device), the transfers continue indefinitely, stopping only after an abort
request or after the OCTOSPI is disabled. After the last memory address is read (at
address 0xFFFF_FFFF), reading continues with address = 0x0000_0000.
When the programmed number of bytes to be transmitted or received is reached, TCF bit is
set in OCTOSPI_SR and an interrupt is generated if TCIE = 1 in OCTOSPI_CR. In the case
of an undefined number of data, TCF is set when the limit of the external SPI memory is
reached, according to the device size defined in OCTOSPI_DCR1.

Triggering the start of a transfer in Regular-command mode

Depending on the OCTOSPI configuration, there are three different ways to trigger the start
of a transfer in Indirect mode when using Regular mode. In general, the start of transfer is
triggered as soon as the software gives the last information that is necessary for the
command. More specifically in Indirect mode, a transfer starts when one of the following
sequence of events occurs:
• if no address is necessary (ADMODE[2:0] = 000) and if no data needs to be provided
by the software (FMODE[1:0] = 01 or DMODE[2:0] = 000), and at the moment when a
write is performed to INSTRUCTION[31:0] in OCTOSPI_IR
• if an address is necessary (when ADMODE[2:0] ≠ 000) and if no data needs to be
provided by the software (when FMODE[1:0] = 01 or DMODE[2:0] = 000), and at the
moment when a write is performed to ADDRESS[31:0] in OCTOSPI_AR
• if an address is necessary (when ADMODE[2:0] ≠ 000) and if data needs to be
provided by the software (when FMODE[1:0] = 00 and DMODE[2:0] ≠ 000), and at the
moment when a write is performed to DATA[31:0] in OCTOSPI_DR
A write to the alternate byte register OCTOSPI_ABR never triggers the communication start.
If alternate bytes are required, they must have been programmed before.
As soon as a command is started, the BUSY bit is automatically set in OCTOSPI_SR.

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Triggering the start of a transfer in HyperBus mode

Depending on the OCTOSPI configuration, there are three different ways to trigger the start
of a command in Indirect mode. In general, it is triggered as soon as the firmware gives the
last information that is necessary for the command, and more specifically, a communication
in Indirect mode starts at the moment when:
• A write is performed to ADDRESS[31:0] (OCTOSPI_AR) in Indirect-read mode (when
FMODE=01)
• A write is performed to DATA[31:0] (OCTOSPI_DR) in Indirect-write mode (when
FMODE=00)
As soon as a transfer is started, the BUSY bit (OCTOSPI_SR[5]) is automatically set.

FIFO and data management

Data in Indirect mode passes through a 32-byte FIFO that is internal to the OCTOSPI.
FLEVEL[5:0] in OCTOSPI_SR indicates how many bytes are currently being held in the
FIFO.
In Indirect-write mode (FMODE[1:0] = 00), the software adds data to the FIFO when it writes
in the OCTOSPI_DR. A word write adds 4 bytes to the FIFO, an half-word write adds
2 bytes, and a byte write adds only 1 byte. If the software adds too many bytes to the FIFO
(more than indicated in DL[31:0]), the extra bytes are flushed from the FIFO at the end of
the write operation (when TCF is set).
The byte/half-word accesses to the OCTOSPI_DR must be done only to the least significant
byte/halfword of the 32-bit register.
FTHRES[4:0] is used to define a FIFO threshold after which point the FIFO threshold flag,
FTF, gets set. In Indirect-read mode, FTF is set when the number of valid bytes to be read
from the FIFO is above the threshold. FTF is also set if there is any data left in the FIFO
after the last byte is read from the external device, regardless of the FTHRES[4:0] setting. In
Indirect-write mode, the FTF is set when the number of empty bytes in the FIFO is above
the threshold.
If FTIE = 1, there is an interrupt when the FTF is set. If DMAEN = 1, a DMA transfer is
initiated when the FTF is set. The FTF is cleared by hardware as soon as the threshold
condition is no longer true (after enough data has been transferred by the CPU or DMA).
In Indirect-read mode, when the FIFO becomes full, the OCTOSPI temporarily stops
reading bytes from the external device to avoid an overrun. Note that the reading of the
external device does not restart until 4 bytes become vacant in the FIFO (when
FLEVEL[5:0] ≤ 0x28). Thus, when FTHRES[4:0] ≥ 0x29, the application must be sure to
read enough bytes to assure that the OCTOSPI starts retrieving data from the external
device again. Otherwise, the FTF flag stays at 0 as long as FLEVEL[5:0] < FTHRES[4:0].
The last data read in RX FIFO remains valid as long as there is no request for the next line.
This means that, when the application reads several times in a row at the same location, the
data is provided from the RX FIFO and not read again from the distant memory.

19.4.9 OCTOSPI Status-flag polling mode

In Automatic-polling mode, the OCTOSPI periodically starts a command to read a defined
number of status bytes (up to 4). The received bytes can be masked to isolate some status
bits and an interrupt can be generated when the selected bits have a defined value.

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The access to the device begins in the same manner as in Indirect-read mode. The BUSY
bit in OCTOSPI_SR goes high at this point and stays high even between the periodic
accesses.
The content of MASK[31:0] in OCTOSPI_PSMAR is used to mask the data from the
external device in Automatic-polling mode:
• If the MASK[n] = 0, then bit n of the result is masked and not considered.
• If MASK[n] = 1, and the content of bit[n] is the same as MATCH[n] in
OCTOSPI_PSMAR, /°then there is a match for bit n.
If the polling match mode PMM bit in OCTOSPI_CR is 0, the AND-match mode is activated:
the status match flag (SMF) is set in OCTOSPI_SR only when there is a match on all of the
unmasked bits.
If PMM = 1 in OCTOSPI_CR, the OR-match mode is activated: SMF gets set if there is a
match on any of the unmasked bits.
An interrupt is called when SMF = 1 if SMIE = 1.
If the Automatic-polling mode stop APMS bit is set in OCTOSPI_CR, the operation stops
and BUSY goes to 0 as soon as a match is detected. Otherwise, BUSY stays at 1 and the
periodic accesses continue until there is an abort or until the OCTOSPI is disabled (EN = 0).
The OCTOSPI_DR register contains the latest received status bytes (FIFO deactivated).
The content of this register is not affected by the masking used in the matching logic. The
FTF status bit in OCTOSPI_SR is set as soon as a new reading of the status is complete.
FTF is cleared as soon as the data is read.
In Automatic-polling mode, variable latency is not supported. As a consequence, the
memory must be configured in Fixed latency.

19.4.10 OCTOSPI Memory-mapped mode

When configured in Memory-mapped mode, the external SPI device is seen as an internal
memory.
Note: More than 256 Mbytes can be addressed even if the external device capacity is larger.
If an access is made to an address outside of the range defined by DEVSIZE[4:0] but still
within the 256 Mbytes range, then an AHB error is given. The effect of this error depends on
the AHB master that attempted the access:
• If it is the Cortex CPU, a hard-fault interrupt is generated.
• If it is a DMA, a DMA transfer error is generated and the corresponding DMA channel is
automatically disabled.
Byte, half-word, and word access types are all supported.
A support for execute in place (XIP) operation is implemented, where the OCTOSPI
continues to load the bytes to the addresses following the most recent access. If
subsequent accesses are continuous to the bytes that follow, then these operations ends up
quickly since their results were pre-fetched.
By default, the OCTOSPI never stops its prefetch operation, it either keeps the previous
read operation active with the nCS maintained low or it relaunches a new transfer, even if no
access to the external device occurs for a long time.
Since external devices tend to consume more when the nCS is held low, the application
may want to activate the timeout counter (TCEN = 1 in OCTOSPI_CR): the nCS is released

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after a period defined by TIMEOUT[15:0] in OCTOSPI_LPTR, when x cycles have elapsed

without an access since the clock is inactive.
BUSY goes high as soon as the first memory-mapped access occurs. Because of the
prefetch operations, BUSY does not fall until there is an abort, or the peripheral is disabled.

19.4.11 OCTOSPI configuration introduction

The OCTOSPI configuration is done in three steps:
1. OCTOSPI system configuration
2. OCTOSPI device configuration
3. OCTOSPI mode configuration

19.4.12 OCTOSPI system configuration

The OCTOSPI is configured using the OCTOSPI_CR. The user must program:
• Functional mode with FMODE[1:0]
• Polling mode behavior if needed with PMM and APMS bits
• FIFO level with FTHRES[4:0]
• DMA usage with DMAEN
• Timeout counter usage with TCEN
• Dual-quad mode, if needed, with DQM (only for Quad-SPI configuration)
In case of an interrupt usage, the respective enable bit can also be set during this phase.
If the timeout counter is used, the timeout value is programmed in OCTOSPI_LPTR.
The DMA channel must not be enabled during the OCTOSPI configuration: it must be
enabled only when the operation is fully configured, to avoid any unexpected request
generation.
The DMA and OCTOSPI must be configured in a coherent manner regarding data length:
the FTHRES[4:0] value in OCTOSPI must reflect the DMA burst size.

19.4.13 OCTOSPI device configuration

The parameters related to the external device targeted are configured through
OCTOSPI_DCR1 and OCTOSPI_DCR2.The user must program:
• Device size with DEVSIZE[4:0]
• Chip-select minimum high time with CSHT[5:0]
• Clock mode with FRCK and CKMODE
• Device frequency with PRESCALER[7:0]
MTYP[2:0] defines the memory type to be used for 8-line modes:
• Micron mode with D0/D1 ordering in 8-data-bit mode (DMODE[2:0] = 100)
• Macronix mode with D1/D0 ordering in 8-data-bit mode (DMODE[2:0] = 100)
• HyperBus memory mode: the protocol follows the HyperBus specification, and an 8-
data-bit DDR mode must be selected.
• HyperBus register mode, addressing register space: the memory-mapped accesses in
this mode must be non-cacheable, or the indirect read/write modes must be used.

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DEVSIZE[4:0] defines the size of external memory using the following formula:
Number of bytes in the device = 2[DEVSIZE+1]
where DEVSIZE+1 is the number of address bits required to address the external device.
The external device capacity can go up to 4 Gbytes (addressed using 32 bits) in Indirect
mode, but the addressable space in Memory-mapped mode is limited to 256 Mbytes.
If DQM = 1, DEVSIZE[4:0] indicates the total capacity of the two devices together.
When the OCTOSPI executes two commands, one immediately after the other, it raises the
chip-select signal (nCS) high between the two commands for only one CLK cycle by default.
If the external device requires more time between commands, the chip-select high time
CSHT[5:0] field can be used to specify the minimum number of CLK cycles (up to 64) for
which the nCS must remain high.
Note: The CLK cycles are up to 64 when extended CSHT timeout feature is supported and up to 8
when it is not supported. Refer to Section 19.3: OCTOSPI implementation.
The clock mode CKMODE bit indicates the level that the CLK takes between commands
(when nCS=1).
In HyperBus mode, the device timing (tACC and tRWR) and the Latency mode must be
configured in OCTOSPI_HLCR.

19.4.14 OCTOSPI Regular-command mode configuration

Indirect mode configuration
When FMODE[1:0] = 00, the Indirect-write mode is selected and data can be sent to the
external device. When FMODE[1:0] = 01, the Indirect-read mode is selected and data can
be read from the external device.
When the OCTOSPI is used in Indirect mode, the frames are constructed in the following
way:
1. Specify a number of data bytes to read or write in OCTOSPI_DLR.
2. Specify the frame timing in OCTOSPI_TCR.
3. Specify the frame format in OCTOSPI_CCR.
4. Specify the instruction in OCTOSPI_IR.
5. Specify the optional alternate byte to be sent right after the address phase in
OCTOSPI_ABR.
6. Specify the targeted address in OCTOSPI_AR.
7. Enable the DMA channel if needed.
8. Read/write the data from/to the FIFO through OCTOSPI_DR (if no DMA usage).
If neither the address register (OCTOSPI_AR) nor the data register (OCTOSPI_DR) need to
be updated for a particular command, then the command sequence starts as soon as
OCTOSPI_IR is written. This is the case when both ADMODE[2:0] and DMODE[2:0] equal
000, or if just ADMODE[2:0] = 000 when in Indirect-read mode (FMODE[1:0] = 01).
When an address is required (ADMODE[2:0] ≠ 000) and the data register does not need to
be written (FMODE[1:0] = 01 or DMODE[2:0] = 000), the command sequence starts as
soon as the address is updated with a write to OCTOSPI_AR.
In case of data transmission (FMODE[1:0] = 00 and DMODE[2:0] ≠ 000), the
communication start is triggered by a write in the FIFO through OCTOSPI_DR.

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Status-flag polling mode configuration

The Status-flag polling mode is enabled by setting FMODE[1:0] = 10. In this mode, the
programmed frame is sent and the data is retrieved periodically.
The maximum amount of data read in each frame is 4 bytes. If more data is requested in
OCTOSPI_DLR, it is ignored and only 4 bytes are read.The periodicity is specified in
OCTOSPI_PIR.
Once the status data has been retrieved, the following can be processed:
• Set SMF (an interrupt is generated if enabled).
• Stop automatically the periodic retrieving of the status bytes.
The received value can be masked with the value stored in OCTOSPI_PSMKR, and can be
ORed or ANDed with the value stored in OCTOSPI_PSMAR.
In case of a match, SMF is set and an interrupt is generated if enabled; The OCTOSPI can
be automatically stopped if AMPS is set. In any case, the latest retrieved value is available
in OCTOSPI_DR.
When the OCTOSPI is used in Auto-polling mode, the frames are constructed in the
following way:
1. Specify the input mask in OCTOSPI_PSMKR.
2. Specify the comparison value in OCTOSPI_PSMAR.
3. Specify the read period in OCTOSPI_PIR.
4. Specify a number of data bytes to read in OCTOSPI_DLR.
5. Specify the frame timing in OCTOSPI_TCR.
6. Specify the frame format in OCTOSPI_CCR.
7. Specify the instruction in OCTOSPI_IR.
8. Specify the optional alternate byte to be sent right after the address phase in
OCTOSPI_ABR.
9. Specify the optional targeted address in OCTOSPI_AR.
If the address register (OCTOSPI_AR) does not need to be updated for a particular
command, then the command sequence starts as soon as OCTOSPI_CCR is written. This
is the case when ADMODE[2:0] = 000.
When an address is required (ADMODE[2:0] ≠ 000), the command sequence starts as soon
as the address is updated with a write to OCTOSPI_AR.

Memory-mapped mode configuration

In Memory-mapped mode, the external device is seen as an internal memory but with some
latency during accesses. Read and write operations are allowed to the external device in
this mode.
It is not recommended to program the Flash memory using memory-mapped writes, as the
internal flags for erase or programming status have to be polled.
Memory-mapped mode is entered by setting FMODE[1:0] = 11 in OCTOSPI_CR.
The programmed instruction and frame are sent when an AHB master is accessing the
memory mapped space.
The FIFO is used as a prefetch buffer to anticipate any linear reads. Any access to
OCTOSPI_DR in this mode returns zero.

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The data length register (OCTOSPI_DLR) has no meaning in Memory-mapped mode.

When the OCTOSPI is used in Memory-mapped mode, the frames are constructed in the
following way:
1. Specify the frame timing in OCTOSPI_TCR for read operation.
2. Specify the frame format in OCTOSPI_CCR for read operation.
3. Specify the instruction in OCTOSPI_IR.
4. Specify the optional alternate byte to be sent right after the address phase in
OCTOSPI_ABR for read operation.
5. Specify the frame timing in OCTOSPI_WTCR for write operation.
6. Specify the frame format in OCTOSPI_WCCR for write operation.
7. Specify the instruction in OCTOSPI_WIR.
8. Specify the optional alternate byte to be sent right after the address phase in
OCTOSPI_WABR for read operation.
All the configuration operations must be completed before the first access to the memory
area. On the first access, the OCTOSPI becomes busy, and no further configuration is
allowed.

OCTOSPI delayed data sampling when no DQS is used

By default, when no DQS is used, the OCTOSPI samples the data driven by the external
device one half of a CLK cycle after the external device drives the signal.
In case of any external signal delays, it may be useful to sample the data later. Using the
SSHIFT bit in OCTOSPI_TCR, the sampling of the data can be shifted by half of a CLK
cycle.
The firmware must clear SSHIFT when the data phase is configured in DTR mode
(DDTR = 1).

OCTOSPI delayed data sampling when DQS is used

When external DQS is used as a sampling clock, it can be shifted in time to compensate the
data propagation delay. This shift is performed by an external delay block located outside
the OCTOSPI. The control of this feature depends on the device implementation (see the
product reference manual for more details).
In certain configuration cases, this external delay block is implemented but is not useful, so
it can be bypassed by setting DLYBYP bit in OCTOSPI_DCR1.

Sending the instruction only once (SIOO)

A Flash memory can provide a mode where an instruction must be sent only with the first
command sequence, while subsequent commands start directly with the address. The user
can take advantage of this type of features using the SIOO bit in OCTOSPI_CCR.
The SIOO is valid for Memory-mapped mode only. If this bit is set, the instruction is sent only
for the first command following a write to OCTOSPI_CCR.
Subsequent command sequences skip the instruction phase, until there is a write to
OCTOSPI_CCR. The SIOO has no effect when IMODE[1:0] = 00 (no instruction).
SIOO mode is not supported when any of the communication regulation, CS boundary or
refresh features are used.

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19.4.15 OCTOSPI HyperBus mode configuration

Indirect mode configuration
When FMODE[1:0] = 00, the Indirect-write mode is selected and data can be sent to the
external device. When FMODE[1:0] = 01, the Indirect-read mode is selected where data can
be read from the external device.
When the OCTOSPI is used in Indirect mode, the frames are constructed in the following
way:
1. Specify a number of data bytes to read or write in OCTOSPI_DLR.
2. Specify the targeted address in OCTOSPI_AR.
3. Enable the DMA channel if needed.
4. Read/write the data from/to the FIFO through OCTOSPI_DR (if no DMA usage).
In Indirect-read mode, the command sequence starts as soon as the address is updated
with a write to OCTOSPI_AR.
In Indirect-write mode, the communication start is triggered by a write in the FIFO through
OCTOSPI_DR.

Status-flag polling mode configuration

The Status-flag polling mode is enabled setting FMODE[1:0] = 10. In this mode, the
programmed frame is sent and the data is retrieved periodically.
The maximum amount of data read in each frame is 4 bytes. If more data is requested in
OCTOSPI_DLR, it is ignored and only 4 bytes are read. The periodicity is specified in
OCTOSPI_PIR.
Once the status data has been retrieved, it can be internally processed to:
• Set SMF (an interrupt is generated if enabled).
• Stop automatically the periodic retrieving of the status bytes.
The received value can be masked with the value stored in OCTOSPI_PSMKR and can be
ORed or ANDed with the value stored in OCTOSPI_PSMAR.
In case of a match, SMF is set and an interrupt is generated if enabled. The OCTOSPI can
be automatically stopped if AMPS is set.
In any case, the latest retrieved value is available in OCTOSPI_DR.
When the OCTOSPI is used in Auto-polling mode, the frames are constructed in the
following way:
1. Specify the input mask in OCTOSPI_PSMKR.
2. Specify the comparison value in OCTOSPI_PSMAR.
3. Specify the read period in OCTOSPI_PIR.
4. Specify a number of data bytes to read in OCTOSPI_DLR.
5. Specify the targeted address in OCTOSPI_AR.
The command sequence starts as soon as the address is updated with a write to
OCTOSPI_AR.

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Memory-mapped mode configuration

In Memory-mapped mode, the external device is seen as an internal memory but with some
latency during the accesses. Read and write operations are allowed to the external device in
this mode.
The Memory-mapped mode is entered by setting FMODE[1:0] = 11. The programmed
instruction and frame is sent when an AHB master is accessing the memory mapped space.
The FIFO is used as a prefetch buffer to anticipate any linear reads. Any access to
OCTOSPI_DR in this mode returns zero.
The data length register (OCTOSPI_DLR) has no meaning in Memory-mapped mode.
All the configuration operation must be completed prior to the first access to the memory
area. On the first access, the OCTOSPI becomes busy, and no configuration is allowed.

19.4.16 OCTOSPI error management

A error can be generated in the following cases:
• In Indirect mode or Status-flag polling mode, when a wrong address has been
programmed in OCTOSPI_AR (according to the device size defined by DEVSIZE[4:0]).
This sets TEF and an interrupt is generated if enabled.
• In Indirect mode, if the address plus the data length exceed the device size. TEF is set
as soon as the access is triggered.
• In Memory-mapped mode when an out-of-range access is done by an AHB master, it
generates an AHB error as a response to the faulty AHB request.
• An access to the memory-mapped area when the Memory-mapped mode is disabled,
generates an AHB error as a response to the faulty AHB request.
The OCTOSPI1 generates an AHB slave error in the following situations:
• Memory mapped mode is disabled and an AHB read request occurs.
• Read or write address exceeds the size of the external memory.
• Abort is received while a read or write burst is ongoing.
• OCTOSIPI is disabled while a read or write burst is ongoing.
• Write request received while the DQSE bit in the WCCR register is 0, which means that
the DQS output is disabled.
• Write request received while DMODE[2:0] = 000 (no data phase), except when
MTYP[2:0] is HyperBus.

19.4.17 OCTOSPI busy bit and abort functionality

Once the OCTOSPI starts an operation with the external device, BUSY is automatically set
in OCTOSPI_SR.
In Indirect mode, BUSY is reset once the OCTOSPI has completed the requested command
sequence and the FIFO is empty.
In Automatic-polling mode, BUSY goes low only after the last periodic access is complete,
due to a match when APMS = 1 or due to an abort.
After the first access in Memory-mapped mode, BUSY goes low only on an abort.
Any operation can be aborted by setting the ABORT bit in OCTOSPI_CR. Once the abort is
completed, BUSY and ABORT are automatically reset, and the FIFO is flushed.

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Before setting ABORT, the software must ensure that all the current transactions are
finished using the synchronization barriers.
Note: Some devices may misbehave if a write operation to a status register is aborted.

19.4.18 OCTOSPI reconfiguration or deactivation

Prior to any OCTOSPI reconfiguration, the software must ensure that all the transactions
are completed:
• After a Memory-mapped write, the software must perform a dummy read followed by a
synchronization barrier, then an abort.
• After a Memory-mapped read, the software must perform a synchronization barrier
then an abort.

19.4.19 nCS behavior

By default, the nCS is high, deselecting the external device. The nCS falls before an
operation begins and rises as soon as it finishes.
When CKMODE = 0 (Mode 0: CLK stays low when no operation is in progress), the nCS
falls one CLK cycle before an operation first rising CLK edge, and the nCS rises one CLK
cycle after the operation final rising CLK edge (see the figure below).

Figure 82. nCS when CKMODE=0 (T = CLK period)

T T

nCS

SCLK

MSv44100V1

When CKMODE = 1 (Mode 3: CLK goes high when no operation is in progress) and when in
SDR mode, nCS falls one CLK cycle before an operation first rising CLK edge, and the nCS
rises one CLK cycle after the operation final rising CLK edge (see the figure below).

Figure 83. CS when CKMODE=1 in SDR mode (T = CLK period)

T T

nCS

SCLK

MSv44101V1

When the CKMODE = 1 (Mode 3) and DDTR = 1 (data DTR mode), the nCS falls one CLK
cycle before an operation first rising CLK edge, and the nCS rises one CLK cycle after the
operation final active rising CLK edge (see the figure below). Because the DDR operations

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must finish with a falling edge, the CLK is low when the nCS rises, and the CLK rises back
up one half of a CLK cycle afterwards.

Figure 84. nCS when CKMODE=1 in DDTR mode (T = CLK period)

T/2
T
T

nCS

SCLK

MSv44102V1

When the FIFO stays full during a read operation, or if the FIFO stays empty during a write
operation, the operation stalls and the CLK stays low until the software services the FIFO. If
an abort occurs when an operation is stalled, the nCS rises just after the abort is requested
and then the CLK rises one half of a CLK cycle later (see the figure below).

Figure 85. nCS when CKMODE=1 with an abort (T = CLK period)

T/2
Clock stalled
T

nCS

SCLK

Abort

MSv44103V1

When not in Dual-quad mode (DQM = 0), only device A is accessed and thus the BnCS
stays high. In Dual-quad mode, the BnCS behaves exactly the same as the AnCS. Thus, if
there is a device B and if the application always stays in Dual-quad mode, then the device B
may use the AnCS and the pin outputting BnCS can be used for other functions.

19.5 OCTOSPI interrupts

An interrupt can be produced on the following events:
• Timeout
• Status match
• FIFO threshold
• Transfer complete
• Transfer error
Separate interrupt enable bits are available to provide more flexibility.

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Table 121. OCTOSPI interrupt requests

Interrupt event Event flag Enable control bit

Timeout TOF TOIE

Status match SMF SMIE
FIFO threshold FTF FTIE
Transfer complete TCF TCIE
Transfer error TEF TEIE

19.6 OCTOSPI registers

19.6.1 OCTOSPI control register (OCTOSPI_CR)

Address offset: 0x0000
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. FMODE[1:0] Res. Res. Res. Res. PMM APMS Res. TOIE SMIE FTIE TCIE TEIE

rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. FTHRES[4:0] FSEL DQM Res. Res. TCEN DMAEN ABORT EN

rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 FMODE[1:0]: Functional mode
This field defines the OCTOSPI functional mode of operation.
00: Indirect-write mode
01: Indirect-read mode
10: Automatic-polling mode
11: Memory-mapped mode
If DMAEN = 1 already, then the DMA controller for the corresponding channel must be
disabled before changing the FMODE[1:0] value.
This field can be written only when BUSY = 0. In such case, the request from OCTOSPI to
DMA becomes inactive.
Bits 27:24 Reserved, must be kept at reset value.
Bit 23 PMM: Polling match mode
This bit indicates which method must be used to determine a match during the Automatic-
polling mode.
0: AND-match mode, SMF is set if all the unmasked bits received from the device match the
corresponding bits in the match register.
1: OR-match mode, SMF is set if any of the unmasked bits received from the device matches
its corresponding bit in the match register.
This bit can be modified only when BUSY = 0.

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Bit 22 APMS: Automatic-poll mode stop

This bit determines if the automatic polling is stopped after a match.
0: Automatic-polling mode is stopped only by abort or by disabling the OCTOSPI.
1: Automatic-polling mode stops as soon as there is a match.
This bit can be modified only when BUSY=0
Bit 21 Reserved, must be kept at reset value.
Bit 20 TOIE: Timeout interrupt enable
This bit enables the timeout interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bit 19 SMIE: Status match interrupt enable
This bit enables the status match interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bit 18 FTIE: FIFO threshold interrupt enable
This bit enables the FIFO threshold interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bit 17 TCIE: Transfer complete interrupt enable
This bit enables the transfer complete interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bit 16 TEIE: Transfer error interrupt enable
This bit enables the transfer error interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bits 15:13 Reserved, must be kept at reset value.
Bits 12:8 FTHRES[4:0]: FIFO threshold level
This field defines, in Indirect mode, the threshold number of bytes in the FIFO that causes
the FIFO threshold flag FTF in OCTOSPI_SR, to be set.
0: FTF is set if there are 1 or more free bytes available to be written to in the FIFO in Indirect-
write mode, or if there are 1 or more valid bytes can be read from the FIFO in Indirect-read
mode.
1: FTF is set if there are 2 or more free bytes available to be written to in the FIFO in Indirect-
write mode, or if there are 2 or more valid bytes can be read from the FIFO in Indirect-read
mode.
...
31: FTF is set if there are 32 free bytes available to be written to in the FIFO in Indirect-write
mode, or if there are 32 valid bytes can be read from the FIFO in Indirect-read mode.

If DMAEN = 1, the DMA controller for the corresponding channel must be disabled before
changing the FTHRES[4:0] value.

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Bit 7 FSEL: Flash select

This bit selects the Flash memory to be addressed in Single/Dual/Quad mode in Single-Flash
mode (when DQM = 0).
0: FLASH 1 selected (data exchanged over IO[3:0])
1: FLASH 2 selected (data exchanged over IO[7:4])
This bit is ignored when DQM = 1 or when Octal mode is selected.
This bit can be modified only when BUSY = 0.
Bit 6 DQM: Dual-quad mode
This bit activates the Dual-quad mode, where two external devices are used simultaneously
to double the throughput and the capacity
0: Dual-quad mode disabled
1: Dual-quad mode enabled
This bit can be modified only when BUSY = 0.
Bits 5:4 Reserved, must be kept at reset value.
Bit 3 TCEN: Timeout counter enable
This bit is valid only when the Memory-mapped mode (FMODE[1:0] = 11) is selected. This bit
enables the timeout counter.
0: Timeout counter is disabled, and thus the chip-select (nCS) remains active indefinitely
after an access in Memory-mapped mode.
1: Timeout counter is enabled, and thus the chip-select is released in the Memory-mapped
mode after TIMEOUT[15:0] cycles of external device inactivity.
This bit can be modified only when BUSY = 0.
Bit 2 DMAEN: DMA enable
In Indirect mode, the DMA can be used to input or output data via OCTOSPI_DR. DMA
transfers are initiated when FTF is set.
0: DMA disabled for Indirect mode
1: DMA enabled for Indirect mode
Note: Resetting the DMAEN bit while a DMA transfer is ongoing, breaks the handshake with
the DMA. Do not write this bit during DMA operation.
Bit 1 ABORT: Abort request
This bit aborts the on-going command sequence. It is automatically reset once the abort is
completed. This bit stops the current transfer.
0: No abort requested
1: Abort requested
Note: This bit is always read as 0.
Bit 0 EN: Enable
This bit enables the OCTOSPI.
0: OCTOSPI disabled
1: OCTOSPI enabled
Note: The DMA request may be aborted without having received the ACK. In this case, the EN
bit is cleared during the operation.

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19.6.2 OCTOSPI device configuration register 1 (OCTOSPI_DCR1)

Address offset: 0x0008
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. MTYP[2:0] Res. Res. Res. DEVSIZE[4:0]

rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYBY CKMO
Res. Res. CSHT[5:0] Res. Res. Res. Res. Res. FRCK
P DE
rw rw rw rw rw rw rw rw rw

Bits 31:27 Reserved, must be kept at reset value.

Bits 26:24 MTYP[2:0]: Memory type
This bit indicates the type of memory to be supported.
000: Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular SPI protocol in
Octal/Quad/Dual/Single modes
Note: In this mode, DQS signal polarity is inverted with respect to the memory clock signal.
This is the default value and care must be taken to change MTYP[2:0] for memories different
from Micron.
001: Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular SPI protocol in
Octal/Quad/Dual/Single modes
010: Standard mode
011: Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular SPI protocol in
Octal/Quad/Dual/Single modes with dedicated address mapping.
100: HyperBus memory mode, the protocol follows the HyperBus specification. 8-data-bit
DTR mode must be selected.
101: HyperBus register mode, addressing register space. The memory-mapped accesses in
this mode must be non-cacheable, or Indirect read/write modes must be used.
110-111: Reserved
Bits 23:21 Reserved, must be kept at reset value.
Bits 20:16 DEVSIZE[4:0]: Device size
This field defines the size of the external device using the following formula:
Number of bytes in device = 2[DEVSIZE+1].
DEVSIZE+1 is effectively the number of address bits required to address the external device.
The device capacity can be up to 4 Gbytes (addressed using 32-bits) in Indirect mode, but
the addressable space in Memory-mapped mode is limited to 256 Mbytes.
In Regular-command mode, if DQM = 1, DEVSIZE[4:0] indicates the total capacity of the two
devices together.
Bits 15:14 Reserved, must be kept at reset value.

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Bits 13:8 CSHT[5:0]: Chip-select high time

CSHT + 1 defines the minimum number of CLK cycles where the chip-select (nCS) must
remain high between commands issued to the external device.
0: nCS stays high for at least 1 cycle between external device commands.
1: nCS stays high for at least 2 cycles between external device commands.
...
63: nCS stays high for at least 64 cycles between external device commands.
Note: When the extended CSHT timeout feature is not supported, CSHT[5:3] are reserved
and the number of cycles is limited to 8. Refer to Section 19.3: OCTOSPI
implementation.
Bits 7:4 Reserved, must be kept at reset value.
Bit 3 DLYBYP: Delay block bypass
0: The internal sampling clock (called feedback clock) or the DQS data strobe external signal
is delayed by the delay block (for more details on this block, refer to the dedicated section of
the reference manual as it is not part of the OCTOSPI peripheral).
1: The delay block is bypassed, so the internal sampling clock or the DQS data strobe
external signal is not affected by the delay block. The delay is shorter than when the delay
block is not bypassed, even with the delay value set to minimum value in delay block.
Bit 2 Reserved, must be kept at reset value.
Bit 1 FRCK: Free running clock
This bit configures the free running clock.
0: CLK is not free running.
1: CLK is free running (always provided).
Bit 0 CKMODE: Mode 0/Mode 3
This bit indicates the level taken by the CLK between commands (when nCS = 1).
0: CLK must stay low while nCS is high (chip-select released). This is referred to as Mode 0.
1: CLK must stay high while nCS is high (chip-select released). This is referred to as Mode 3.

19.6.3 OCTOSPI device configuration register 2 (OCTOSPI_DCR2)

Address offset: 0x000C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. PRESCALER[7:0]

rw rw rw rw rw rw rw rw

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Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 PRESCALER[7:0]: Clock prescaler
This field defines the scaler factor for generating the CLK based on the kernel clock
(value + 1).
0: FCLK = FKERNEL, kernel clock used directly as OCTOSPI CLK (prescaler bypassed). In this
case, if the DDR mode is used, it is mandatory to provide to the OCTOSPI a kernel clock that
has 50% duty-cycle.
1: FCLK = FKERNEL/2
2: FCLK = FKERNEL/3
...
255: FCLK = FKERNEL/256
For odd clock division factors, the CLK duty cycle is not 50 %. The clock signal remains high
one cycle longer than it stays low.
This field can be modified only when BUSY = 0.

19.6.4 OCTOSPI device configuration register 3 (OCTOSPI_DCR3)

Address offset: 0x0010
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CSBOUND[4:0]

rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. MAXTRAN[7:0]

rw rw rw rw rw rw rw rw

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:16 CSBOUND[4:0]: CS boundary
This field enables the transaction boundary feature. When active, a minimum value of 3 is
recommended.
The nCS is released on each boundary of 2CSBOUND bytes.
0: CS boundary disabled
others: CS boundary set to 2CSBOUND bytes
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 MAXTRAN[7:0]: Maximum transfer
This field enables the communication regulation feature.
The nCS is released every MAXTRAN+1 clock cycles when the other OCTOSPI request the
access to the bus.
0: Maximum communication disabled
others: Maximum communication is set to MAXTRAN+1 bytes

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19.6.5 OCTOSPI device configuration register 4 (OCTOSPI_DCR4)

Address offset: 0x0014
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

REFRESH[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

REFRESH[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 REFRESH[31:0]: Refresh rate

This field enables the refresh rate feature.
The nCS is released every REFRESH+1 clock cycles for writes, and REFRESH+4 clock
cycles for reads.
Note: These two values can be extended with few clock cycles when refresh occurs during a
byte transmission in single, dual or quad mode, because the byte transmission must be
completed.
0: Refresh disabled
others: Maximum communication length is set to REFRESH+1 clock cycles.

19.6.6 OCTOSPI status register (OCTOSPI_SR)

Address offset: 0x0020
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. FLEVEL[5:0] Res. Res. BUSY TOF SMF FTF TCF TEF

r r r r r r r r r r r r

Bits 31:14 Reserved, must be kept at reset value.

Bits 13:8 FLEVEL[5:0]: FIFO level
This field gives the number of valid bytes that are being held in the FIFO. FLEVEL=0 when
the FIFO is empty, and 32 when it is full.
In Automatic-status polling mode, FLEVEL is zero.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 BUSY: Busy
This bit is set when an operation is ongoing. It is cleared automatically when the operation
with the external device is finished and the FIFO is empty.
Bit 4 TOF: Timeout flag
This bit is set when timeout occurs. It is cleared by writing 1 to CTOF.

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Bit 3 SMF: Status match flag

This bit is set in Automatic-polling mode when the unmasked received data matches the
corresponding bits in the match register (OCTOSPI_PSMAR).
It is cleared by writing 1 to CSMF.
Bit 2 FTF: FIFO threshold flag
In Indirect mode, this bit is set when the FIFO threshold has been reached, or if there is any
data left in the FIFO after the reads from the external device are complete.
It is cleared automatically as soon as the threshold condition is no longer true.
In Automatic-polling mode this bit is set every time the status register is read, and the bit is
cleared when the data register is read.
Bit 1 TCF: Transfer complete flag
This bit is set in Indirect mode when the programmed number of data has been transferred or
in any mode when the transfer has been aborted.It is cleared by writing 1 to CTCF.
Bit 0 TEF: Transfer error flag
This bit is set in Indirect mode when an invalid address is being accessed in Indirect mode.
It is cleared by writing 1 to CTEF.

19.6.7 OCTOSPI flag clear register (OCTOSPI_FCR)

Address offset: 0x0024
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CTOF CSMF Res. CTCF CTEF

w w w w

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 CTOF: Clear timeout flag
Writing 1 clears the TOF flag in the OCTOSPI_SR register.
Bit 3 CSMF: Clear status match flag
Writing 1 clears the SMF flag in the OCTOSPI_SR register.
Bit 2 Reserved, must be kept at reset value.
Bit 1 CTCF: Clear transfer complete flag
Writing 1 clears the TCF flag in the OCTOSPI_SR register.
Bit 0 CTEF: Clear transfer error flag
Writing 1 clears the TEF flag in the OCTOSPI_SR register.

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19.6.8 OCTOSPI data length register (OCTOSPI_DLR)

Address offset: 0x0040
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DL[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DL[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 DL[31: 0]: Data length

Number of data to be retrieved (value+1) in Indirect and Status-polling modes. A value not
greater than 3 (indicating 4 bytes) must be used for status polling-mode.
All 1s in Indirect mode means undefined length, where OCTOSPI continues until the end of
the memory, as defined by DEVSIZE.
0x0000_0000: 1 byte is to be transferred.
0x0000_0001: 2 bytes are to be transferred.
0x0000_0002: 3 bytes are to be transferred.
0x0000_0003: 4 bytes are to be transferred.
...
0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred.
0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred.
0xFFFF_FFFF: undefined length; all bytes, until the end of the external device, (as defined
by DEVSIZE) are to be transferred. Continue reading indefinitely if DEVSIZE = 0x1F.
DL[0] is stuck at 1 in Dual-quad mode (DQM = 1) even when 0 is written to this bit, thus
assuring that each access transfers an even number of bytes.
This field has no effect when in Memory-mapped mode (FMODE = 10).
This field can be written only when BUSY = 0.

19.6.9 OCTOSPI address register (OCTOSPI_AR)

Address offset: 0x0048
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADDRESS[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDRESS[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 ADDRESS[31:0]: Address

Address to be sent to the external device. In HyperFlash mode, this field must be even as
this protocol is 16-bit word oriented. Writes to this field are ignored when BUSY = 1 or when
FMODE = 11 (Memory-mapped mode).

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RM0432 Octo-SPI interface (OCTOSPI)

19.6.10 OCTOSPI data register (OCTOSPI_DR)

Address offset: 0x0050
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 DATA[31: 0]: Data

Data to be sent/received to/from the external SPI device
In Indirect-write mode, data written to this register is stored on the FIFO before it is sent to
the external device during the data phase. If the FIFO is too full, a write operation is stalled
until the FIFO has enough space to accept the amount of data being written.
In Indirect-read mode, reading this register gives (via the FIFO) the data that was received
from the external device. If the FIFO does not have as many bytes as requested by the read
operation and if BUSY = 1, the read operation is stalled until enough data is present or until
the transfer is complete, whichever happens first.
In Automatic-polling mode, this register contains the last data read from the external device
(without masking).
Word, half-word, and byte accesses to this register are supported. In Indirect-write mode, a
byte write adds 1 byte to the FIFO, a half-word write 2 bytes, and a word write 4 bytes.
Similarly, in Indirect-read mode, a byte read removes 1 byte from the FIFO, a halfword read
2 bytes, and a word read 4 bytes. Accesses in Indirect mode must be aligned to the bottom
of this register: A byte read must read DATA[7:0] and a half-word read must read DATA[15:0].

19.6.11 OCTOSPI polling status mask register (OCTOSPI _PSMKR)

Address offset: 0x0080
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MASK[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MASK[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MASK[31:0]: Status mask

Mask to be applied to the status bytes received in Polling mode
For bit n:
0: Bit n of the data received in Automatic-polling mode is masked and its value is not
considered in the matching logic.
1: Bit n of the data received in Automatic-polling mode is unmasked and its value is
considered in the matching logic.
This field can be written only when BUSY = 0.

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19.6.12 OCTOSPI polling status match register (OCTOSPI_PSMAR)

Address offset: 0x0088
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MATCH[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MATCH[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MATCH[31: 0]: Status match

Value to be compared with the masked status register to get a match
This field can be written only when BUSY = 0.

19.6.13 OCTOSPI polling interval register (OCTOSPI_PIR)

Address offset: 0x0090
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INTERVAL[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 INTERVAL[15: 0]: Polling interval
Number of CLK cycle between a read during the automatic polling phases
This field can be written only when BUSY = 0.

19.6.14 OCTOSPI communication configuration register (OCTOSPI_CCR)

Address offset: 0x0100
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SIOO Res. DQSE Res. DDTR DMODE[2:0] Res. Res. ABSIZE[1:0] ABDTR ABMODE[2:0]

rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDT
Res. Res. ADSIZE[1:0] ADMODE[2:0] Res. Res. ISIZE[1:0] IDTR IMODE[2:0]
R
rw rw rw rw rw rw rw rw rw rw rw rw

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Bit 31 SIOO: Send instruction only once mode

See Sending the instruction only once (SIOO). This bit has no effect when IMODE = 00.
0: Send instruction on every transaction
1: Send instruction only for the first command
This field can be written only when BUSY = 0.
Bit 30 Reserved, must be kept at reset value.
Bit 29 DQSE: DQS enable
This bit enables the data strobe management.
0: DQS disabled
1: DQS enabled
Bit 28 Reserved, must be kept at reset value.
Bit 27 DDTR: Data double transfer rate
This bit sets the DTR mode for the data phase.
0: DTR mode disabled for data phase
1: DTR mode enabled for data phase
This field can be written only when BUSY = 0.
Bits 26:24 DMODE[2:0]: Data mode
This field defines the data phase’s mode of operation.
000: No data
001: Data on a single line
010: Data on two lines
011: Data on four lines
100: Data on eight lines
101-111: Reserved
This field can be written only when BUSY = 0.
Bits 23:22 Reserved, must be kept at reset value.
Bits 21:20 ABSIZE[1:0]: Alternate bytes size
This bit defines alternate bytes size.
00: 8-bit alternate bytes
01: 16-bit alternate bytes
10: 24-bit alternate bytes
11: 32-bit alternate bytes
This field can be written only when BUSY = 0.
Bit 19 ABDTR: Alternate bytes double transfer rate
This bit sets the DTR mode for the alternate bytes phase.
0: DTR mode disabled for alternate bytes phase
1: DTR mode enabled for alternate bytes phase
This field can be written only when BUSY = 0.
Bits 18:16 ABMODE[2:0]: Alternate-byte mode
This field defines the Alternate byte phase’s mode of operation.
000: No alternate bytes
001: Alternate bytes on a single line
010: Alternate bytes on two lines
011: Alternate bytes on four lines
100: Alternate bytes on eight lines
101-111: Reserved
This field can be written only when BUSY = 0.

RM0432 Rev 6 593/2301

603
Octo-SPI interface (OCTOSPI) RM0432

Bits 15:14 Reserved, must be kept at reset value.

Bits 13:12 ADSIZE[1:0]: Address size
This field defines address size.
00: 8-bit address
01: 16-bit address
10: 24-bit address
11: 32-bit address
This field can be written only when BUSY = 0.
Bit 11 ADDTR: Address double transfer rate
This bit sets the DTR mode for the address phase.
0: DTR mode disabled for address phase
1: DTR mode enabled for address phase
This field can be written only when BUSY = 0.
Bits 10:8 ADMODE[2:0]: Address mode
This field defines the Address phase’s mode of operation.
000: No address
001: Address on a single line
010: Address on two lines
011: Address on four lines
100: Address on eight lines
101-111: Reserved
This field can be written only when BUSY = 0.
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 ISIZE[1:0]: Instruction size
This bit defines instruction size.
00: 8-bit instruction
01: 16-bit instruction
10: 24-bit instruction
11: 32-bit instruction
This field can be written only when BUSY = 0.
Bit 3 IDTR: Instruction double transfer rate
This bit sets the DTR mode for the instruction phase.
0: DTR mode disabled for instruction phase
1: DTR mode enabled for instruction phase
This field can be written only when BUSY = 0.
Bits 2:0 IMODE[2:0]: Instruction mode
This field defines the Instruction phase’s mode of operation.
000: No instruction
001: Instruction on a single line
010: Instruction on two lines
011: Instruction on four lines
100: Instruction on eight lines
101-111: Reserved
This field can be written only when BUSY = 0.

594/2301 RM0432 Rev 6

RM0432 Octo-SPI interface (OCTOSPI)

19.6.15 OCTOSPI timing configuration register (OCTOSPI_TCR)

Address offset: 0x0108
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSHIF
Res. Res. DHQC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
T
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DCYC[4:0]

rw rw rw rw rw

Bit 31 Reserved, must be kept at reset value.

Bit 30 SSHIFT: Sample shift
By default, the OCTOSPI samples data 1/2 of a CLK cycle after the data is driven by the
external device.
This bit allows the data to be sampled later in order to consider the external signal delays.
0: No shift
1: 1/2 cycle shift
The software must ensure that SSHIFT = 0 when the data phase is configured in DTR mode
(when DDTR = 1.)
This field can be modified only when BUSY = 0.
Bit 29 Reserved, must be kept at reset value.
Bit 28 DHQC: Delay hold quarter cycle
0: No delay hold
1: 1/4 cycle hold
Bits 27:5 Reserved, must be kept at reset value.
Bits 4:0 DCYC[4:0]: Number of dummy cycles
This field defines the duration of the dummy phase.
In both SDR and DTR modes, it specifies a number of CLK cycles (0-31).
It is recommended to have at least six dummy cycles when using memories with DQS
activated.
This field can be written only when BUSY = 0.

19.6.16 OCTOSPI instruction register (OCTOSPI_IR)

Address offset: 0x0110
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

INSTRUCTION[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INSTRUCTION[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RM0432 Rev 6 595/2301

603
Octo-SPI interface (OCTOSPI) RM0432

Bits 31:0 INSTRUCTION[31:0]: Instruction

Instruction to be sent to the external SPI device
This field can be written only when BUSY = 0.

19.6.17 OCTOSPI alternate bytes register (OCTOSPI_ABR)

Address offset: 0x0120
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ALTERNATE[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ALTERNATE[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 ALTERNATE[31: 0]: Alternate bytes

Optional data to be send to the external SPI device right after the address.
This field can be written only when BUSY = 0.

19.6.18 OCTOSPI low-power timeout register (OCTOSPI_LPTR)

Address offset: 0x00130
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TIMEOUT[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 TIMEOUT[15: 0]: Timeout period
After each access in Memory-mapped mode, the OCTOSPI prefetches the subsequent bytes
and hold them in the FIFO.
This field indicates how many CLK cycles the OCTOSPI waits after the clock becomes
inactive and until it raises the nCS, putting the external device in a lower-consumption state.
This field can be written only when BUSY = 0.

596/2301 RM0432 Rev 6

RM0432 Octo-SPI interface (OCTOSPI)

19.6.19 OCTOSPI write communication configuration register

(OCTOSPI_WCCR)
Address offset: 0x0180
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. DQSE Res. DDTR DMODE[2:0] Res. Res. ABSIZE[1:0] ABDTR ABMODE[2:0]

rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDT
Res. Res. ADSIZE[1:0] ADMODE[2:0] Res. Res. ISIZE[1:0] IDTR IMODE[2:0]
R
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 DQSE: DQS enable
This bit enables the data strobe management.
0: DQS disabled
1: DQS enabled
Bit 28 Reserved, must be kept at reset value.
Bit 27 DDTR: data double transfer rate
This bit sets the DTR mode for the data phase.
0: DTR mode disabled for data phase
1: DTR mode enabled for data phase
This field can be written only when BUSY = 0.
Bits 26:24 DMODE[2:0]: Data mode
This field defines the Data phase’s mode of operation.
000: No data
001: Data on a single line
010: Data on two lines
011: Data on four lines
100: Data on eight lines
101-111: Reserved
This field can be written only when BUSY = 0.
Bits 23:22 Reserved, must be kept at reset value.
Bits 21:20 ABSIZE[1:0]: Alternate bytes size
This field defines alternate bytes size:
00: 8-bit alternate bytes
01: 16-bit alternate bytes
10: 24-bit alternate bytes
11: 32-bit alternate bytes
This field can be written only when BUSY = 0.
Bit 19 ABDTR: Alternate bytes double transfer rate
This bit sets the DTR mode for the alternate bytes phase.
0: DTR mode disabled for alternate bytes phase
1: DTR mode enabled for alternate bytes phase
This field can be written only when BUSY = 0.

RM0432 Rev 6 597/2301

603
Octo-SPI interface (OCTOSPI) RM0432

Bits 18:16 ABMODE[2:0]: Alternate-byte mode

This field defines the Alternate byte phase’s mode of operation.
000: No alternate bytes
001: Alternate bytes on a single line
010: Alternate bytes on two lines
011: Alternate bytes on four lines
100: Alternate bytes on eight lines
101-111: Reserved
This field can be written only when BUSY = 0.
Bits 15:14 Reserved, must be kept at reset value.
Bits 13:12 ADSIZE[1:0]: Address size
This field defines address size.
00: 8-bit address
01: 16-bit address
10: 24-bit address
11: 32-bit address
This field can be written only when BUSY = 0.
Bit 11 ADDTR: Address double transfer rate
This bit sets the DTR mode for the address phase.
0: DTR mode disabled for address phase
1: DTR mode enabled for address phase
This field can be written only when BUSY = 0.
Bits 10:8 ADMODE[2:0]: Address mode
This field defines the Address phase’s mode of operation.
000: No address
001: Address on a single line
010: Address on two lines
011: Address on four lines
100: Address on eight lines
101-111: Reserved
This field can be written only when BUSY = 0.
Bits 7:6 Reserved, must be kept at reset value.

598/2301 RM0432 Rev 6

RM0432 Octo-SPI interface (OCTOSPI)

Bits 5:4 ISIZE[1:0]: Instruction size

This bit defines instruction size:
00: 8-bit instruction
01: 16-bit instruction
10: 24-bit instruction
11: 32-bit instruction
This field can be written only when BUSY = 0.
Bit 3 IDTR: Instruction double transfer rate
This bit sets the DTR mode for the instruction phase.
0: DTR mode disabled for instruction phase
1: DTR mode enabled for instruction phase
This field can be written only when BUSY = 0.
Bits 2:0 IMODE[2:0]: Instruction mode
This field defines the Instruction phase’s mode of operation.
000: No instruction
001: Instruction on a single line
010: Instruction on two lines
011: Instruction on four lines
100: Instruction on eight lines
101-111: Reserved
This field can be written only when BUSY = 0.

19.6.20 OCTOSPI write timing configuration register (OCTOSPI_WTCR)

Address offset: 0x0188
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DCYC[4:0]

rw rw rw rw rw

Bits 31:5 Reserved, must be kept at reset value.

Bits 4:0 DCYC[4:0]: Number of dummy cycles
This field defines the duration of the dummy phase.
In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended
to have at least 5 dummy cycles when using memories with DQS activated.
This field can be written only when BUSY = 0.

RM0432 Rev 6 599/2301

603
Octo-SPI interface (OCTOSPI) RM0432

19.6.21 OCTOSPI write instruction register (OCTOSPI_WIR)

Address offset: 0x0190
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

INSTRUCTION[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INSTRUCTION[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 INSTRUCTION[31:0]: Instruction

Instruction to be sent to the external SPI device
This field can be written only when BUSY = 0.

19.6.22 OCTOSPI write alternate bytes register (OCTOSPI_WABR)

Address offset: 0x01A0
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ALTERNATE[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ALTERNATE[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 ALTERNATE[31: 0]: Alternate bytes

Optional data to be sent to the external SPI device right after the address
This field can be written only when BUSY = 0.

19.6.23 OCTOSPI HyperBus latency configuration register

(OCTOSPI_HLCR)
Address offset: 0x0200
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. TRWR[7:0]

rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TACC[7:0] Res. Res. Res. Res. Res. Res. WZL LM

rw rw rw rw rw rw rw rw rw rw

600/2301 RM0432 Rev 6

RM0432 Octo-SPI interface (OCTOSPI)

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 TRWR[7:0]: Read write recovery time
Device read write recovery time expressed in number of communication clock cycles
Bits 15:8 TACC[7: 0]: Access time
Device access time expressed in number of communication clock cycles
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 WZL: Write zero latency
This bit enables zero latency on write operations.
0: Latency on write accesses
1: No latency on write accesses
Bit 0 LM: Latency mode
This bit selects the Latency mode.
0: Variable initial latency
1: Fixed latency

19.6.24 OCTOSPI register map

The following table summarizes the OCTOSPI registers. Refer to the register boundary
addresses table for the OCTOSPI register base address.

Table 122. OCTOSPI register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
FMDOE[1:0]

DMAEN
ABORT
APMS

TCEN
FSEL
SMIE
PMM

DQM
TOIE

TCIE
TEIE
FTIE
Res.
Res.

Res.
Res.
Res.
Res.

Res.

Res.
Res.
Res.

Res.
Res.

EN
OCTOSPI_CR FTHRES[4:0]
0x0000

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
MTYP[2:0] Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x0004 Reserved

CKMODE
DLYBYP

FRCK
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.

Res.
Res.

Res.
Res.
Res.
Res.

Res.
OCTOSPI_DCR1 DEVSIZE[4:0] CSHT[5:0]
0x0008

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

OCTOSPI_DCR2 PRESCALER[7:0]
0x000C
Reset value 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

OCTOSPI_DCR3 CSBOUND[4:0]. MAXTRAN[7:0]

0x0010
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0

OCTOSPI_DCR4 REFRESH[31:0]
0x0014
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0018
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

- Reserved
0x001C
SMF
BUS
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

TOF

TCF
TEF
FTF

OCTOSPI_SR FLEVEL[5:0]
0x0020
Reset value 0 0 0 0 0 0 0 0 0 0 0 0

RM0432 Rev 6 601/2301

603
 -
-
-

0x0104
0x0084
0x0044

0x0108
0x0100
0x0094
0x0090
0x0088
0x0080
0x0054
0x0050
0x0048
0x0040
0x0028
0x0024

0x010C
0x008C
0x004C

0x007C
0x003C

0x00FC
Offset

602/2301
PSMAR
PSMKR

Reserved

Reserved
Reserved
Reserved
Reserved
Reserved

Reserved
Reserved
Reserved

OCTOSPI_
OCTOSPI_
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

OCTOSPI_AR

OCTOSPI_DR

OCTOSPI_PIR
OCTOSPI_DLR

OCTOSPI_TCR
OCTOSPI_FCR

OCTOSPI_CCR

0
0
0
0
0
0
Res. Res. Res. SIOO Res. Res. Res. Res. Res. Res. Res. Res. Res. 31

0
0
0
0
0

0
Res. SSHIFT Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30

0
0
0
0
0
0
Res. Res. Res. DQSE Res. Res. Res. Res. Res. Res. Res. Res. Res. 29

0
0
0
0
0

0
Octo-SPI interface (OCTOSPI)

Res. DHQC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28

0
0
0
0
0
0
Res. Res. Res. DDTR Res. Res. Res. Res. Res. Res. Res. Res. Res. 27

0
0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. 26

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25

[2:0]
DMODE

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24

0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23

0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22

0
0
0
0
0
0

Res. Res. Res. ABSIZE Res. Res. Res. Res. Res. Res. Res. Res. Res. 21

0
0
0
0
0
0

Res. Res. Res. [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. 20

0
0
0
0
0
0

Res. Res. Res. ABDTR Res. Res. Res. Res. Res. Res. Res. Res. Res. 19

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 18

RM0432 Rev 6
ABMODE

0
0
0
0
0
0

Res. Res. Res. [2:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. 17

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 16

0
0
0
0
0

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15
DL[31:0]

DATA[31:0]

MASK[31:0]

0
0
0
0
0

0
MATCH[31:0]
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 14
ADDRESS[31:0]

0
0
0
0
0
0

0
Res. Res. Res. ADSIZE Res. Res. Res. Res. Res. Res. Res. Res. 13

0
0
0
0
0
0

0
Res. Res. Res. [1:0] Res. Res. Res. Res. Res. Res. Res. Res. 12

0
0
0
0
0
0

0
Res. Res. Res. ADDTR Res. Res. Res. Res. Res. Res. Res. Res. 11

0
0
0
0
0
0

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 10
ADMODE

0
0
0
0
0
0

0
Res. Res. Res. [2:0] Res. Res. Res. Res. Res. Res. Res. Res. 9

0
0
0
0
0
0

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 8

0
0
0
0
0

0
Table 122. OCTOSPI register map and reset values (continued)

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 7
0
0
0
0
0

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 6

INTERVAL[15:0]

0
0
0
0
0
0

0
Res. Res. Res.
ISIZE[1:0]
Res. Res. Res. Res. Res. Res. Res. Res. 5

0
0
0
0
0
0

0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. CTOF 4

0
0
0
0
0
0

0
0

Res. Res. IDTR Res. Res. Res. Res. Res. Res. Res. CSMF 3

0
0
0
0
0
0

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 2

0
0
0
0
0
0

0
0

IMODE[2:0]

DCYC[4:0]
Res. Res. Res. Res. Res. Res. Res. Res. Res. CTCF 1

0
0
0
0
0
0

0
0

0
RM0432

Res. Res. Res. Res. Res. Res. Res. Res. Res. CTEF
 -
-
-
-
0x0114
0x0110

0x0200
0x0194
0x0190
0x0188
0x0180
0x0200
0x0134
0x0130
0x0124
0x0120

0x01A4
0x01A0
0x018C

0x019C
0x012C

0x01FC
-0x011C
Offset
RM0432

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
OCTOSPI_IR

OCTOSPI_WIR
OCTOSPI_ABR

OCTOSPI_LPTR

OCTOSPI_HLCR
OCTOSPI_WABR
OCTOSPI_WTCR
OCTOSPI_WCCR

0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30

0
0
0
0
0

Res. Res. Res. Res. Res. DQSE Res. Res. Res. Res. 29

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28

0
0
0
0
0

Res. Res. Res. Res. Res. DDTR Res. Res. Res. Res. 27

0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. 26

DMODE

0
0
0
0
0

Res. Res. Res. Res. Res. [2:0] Res. Res. Res. Res. 25

0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. 24

0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. 23

0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. 22

0
0
0
0
0
0

Res. Res. Res. Res. ABSIZE Res. Res. Res. Res. 21

0
0
0
0
0
0

Res. Res. Res. Res. [1:0] Res. Res. Res. Res. 20

0
0
0
0
0
0

Res. Res. Res. Res. ABDTR Res. Res. Res. Res. 19

TRWR[7:0]

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 18

RM0432 Rev 6
ABMODE

0
0
0
0
0
0

Res. Res. Res. Res. [2:0] Res. Res. Res. Res. 17

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 16

0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 15

0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 14

ALTERNATE[31:0]
ALTERNATE[31:0]

0
0
0
0
0
0

0
INSTRUCTION[31:0]

INSTRUCTION[31:0]
Res. Res. Res. Res. ADSIZE Res. Res. Res. 13

0
0
0
0
0
0

Res. Res. Res. Res. [1:0] Res. Res. Res. 12

0
0
0
0
0
0

Res. Res. Res. Res. ADDTR Res. Res. Res. 11

TACC[7:0]

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 10

ADMODE

0
0
0
0
0
0

Res. Res. Res. Res. [2:0] Res. Res. Res. 9

Refer to Section 2.2 on page 91 for the register boundary addresses.

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 8

0
0
0
0

0
Table 122. OCTOSPI register map and reset values (continued)

Res. Res. Res. Res. Res. Res. Res. Res. Res. 7

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. 6

TIMEOUT[15:0]

0
0
0
0
0

Res. Res. Res. Res. Res. ISIZE Res. Res. Res. 5

0
0
0
0
0

Res. Res. Res. Res. [1:0] Res. Res. Res. 4

0
0
0
0
0

Res. Res. Res. Res. IDTR Res. Res. Res. 3

0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 2

0 IMODE
0
0
0
0

0
0

DCYC[4:0]

WZL Res. Res. Res. [2:0] Res. Res. Res. 1

0
0
0
0
0

0
0

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Octo-SPI interface (OCTOSPI)

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OCTOSPI I/O manager (OCTOSPIM) RM0432

20 OCTOSPI I/O manager (OCTOSPIM)

20.1 Introduction
The OCTOSPI I/O manager is a low-level interface that enables:
• An efficient OCTOSPI pin assignment with a full I/O Matrix (before alternate function
map)
• Multiplex of single/dual/quad/octal SPI interfaces over the same bus

20.2 OCTOSPIM main features

• Supports up to two single/dual/quad/octal SPI Interfaces
• Supports up to 2 ports for pin assignment
• Fully programmable I/O matrix for pin assignment by function (data/control/clock)

20.3 OCTOSPIM implementation

The table below describes the OCTOSPI implementation on STM32L4+ Series devices. The
full list of features is implemented in STM32L4P5xx and STM32L4Q5xx devices, while
STM32L4Rxxx and STM32L4Sxxx devices support a reduced set of features.

Table 123. OCTOSPI implementation on STM32L4+ Series

STM32L4P5xx and STM32L4Rxxx and
OCTOSPI feature
STM32L4Q5xx STM32L4Sxxx

Supports up to two single/dual/quad/octal SPI interfaces X X

Supports up to 3 ports for pin assignment X X
Fully programmable I/O matrix for pin assignment X X
Multiplexer for single/dual/quad/octal SPI interface X -

20.4 OCTOSPIM functional description

20.4.1 OCTOSPIM block diagram

The block diagram of the OCTOSPI I/O manager is shown in Figure 86.

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Figure 86. OCTOSPIM block diagram for SMT32L4P5xx and STM32L4Q5xx

OCTOSPI I/O manager

AHB PnCR
AHB interface
CR
P1CR

MUXEN OCTOSPIM_P1_CLK
OCTOSPI1
sig. OCTOSPIM_P1_NCLK

Port 1
OCTOSPIM_P1_DQS
OCTOSPI1 ACK1 OCTOSPIM_P1_NCS
OCTOSPIM_P1_IO[7:0]
REQ1
I/O Matrix
Muxer
OCTOSPIM_Pn_CLK

REQ2 OCTOSPIM_Pn_NCLK

Port n
OCTOSPIM_Pn_DQS
OCTOSPI2
ACK2 OCTOSPIM_Pn_NCS
OCTOSPIM_Pn_IO[7:0]
OCTOSPI2
sig.
MS42409V4

1. The number of ports (n) is 2.

Figure 87. OCTOSPIM block diagram for SMT32L4Rxxx and STM32L4Sxxx

OCTOSPI I/O manager

AHB PnCR
AHB interface P1CR

OCTOSPIM_P1_CLK
OCTOSPI1 OCTOSPIM_P1_NCLK
Port 1

OCTOSPI1 sig.
OCTOSPIM_P1_DQS
OCTOSPIM_P1_NCS
OCTOSPIM_P1_IO[7:0]
OCTOSPI
Kernel I/O Matrix
clock
OCTOSPIM_Pn_CLK
OCTOSPIM_Pn_NCLK
Port n

OCTOSPI2 OCTOSPIM_Pn_DQS
OCTOSPI2
OCTOSPIM_Pn_NCS
sig.
OCTOSPIM_Pn_IO[7:0]

MS42422V3

1. The number of ports (n) is 2.

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20.4.2 OCTOSPIM matrix

The OCTOSPI I/O manager matrix allows the user to set a fully programmable pre-mapping
of functions:
• Any OCTOSPIM_Pn_CLK / OCTOSPIM_Pn_NCLK pair can be mapped independently
to OCTOSPI1_CLK/OCTOSPI1_NCLK or OCTOSPI2_CLK/OCTOSPI2_NCLK
• Any OCTOSPIM_Pn_DQS can be mapped independently to OCTOSPI1_DQS or
OCTOSPI2_DQS
• Any OCTOSPIM_Pn_NCS can be mapped independently to OCTOSPI1_NCS or
OCTOSPI2_NCS
• Any OCTOSPIM_Pn_IO[3:0] and OCTOSPIM_Pn_IO[7:4] can be mapped
independently to OCTOSPI1_IO[3:0], OCTOSPI1_IO[7:4], OCTOSPI2_IO1[3:0] or
OCTOSPI2_IO[7:4]
For each OCTOSPI I/O manager port, individual signal enables and mapping are configured
through the corresponding OCTOSPI I/O manager Port n configuration register
(OCTOSPIM_PnCR).
When several I/O pins have the same configuration, and are enabled at the same time, the
result may not be predictable.
In the default Out of reset configuration, all the signals of the OCTOSPI1 and OCTOSPI2
are mapped, respectively, on Port 1and on Port 2.
The I/O matrix shall be configured when the OCTOSPIs are disabled, to avoid unexpected
transactions on the bus.

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20.4.3 OCTOSPIM multiplexer

When the Multiplexed mode is set, the two OCTOSPIs are multiplexed over the same bus.
Both OCTOSPIs get the ownership of the bus in turn through a request/acknowledge
protocol with REQ/ACK signals.
The multiplexing is enabled by setting the MUXEN bit of the OCTOSPI I/O manager
configuration register (OCTOSPIM_CR).
The fairness counter (MAXTRAN) of each OCTOSPI can be used to accurately manage the
maximum duration for which a given OCTOSPI is taking the bus: this feature ensures a
maximum bus access latency for the other OCTOSPIs. When the bus is released by one
OCTOSPI, an arbitration phase occurs, which is round-robin: if the other OCTOSPI requests
the bus, it gets it.
OCTOSPIn_nCS are not part of the multiplexing. Only the OCTOSPIn_IO[7:0], the
OCTOSPIn_DQS and OCTOSPIn_CLK / OCTOSPIn_NCLK are muxed.
When the Multiplexed mode is used, only clock mode 0 is supported on the OCTOSPIs.
Due to arbitration and bus sharing, the auto polling interval time of the OCTOSPI, when
used, may be increased.

Minimum switching duration

The minimum number of cycles needed to switch from an OCTOSPI to another can be
configured.
This internal timer guarantees a latency between the falling edge of the REQ signal of the
active OCTOSPI, and the rising edge of the ACK signal of the requesting OCTOSPI.
The duration is defined by the REQ2ACK_TIME fields of the OCTOSPI I/O manager
configuration register (OCTOSPIM_CR).

Pin mapping in Multiplexed mode

In Multiplexed mode, the mapping of the bus is done as described below:
• OCTOSPI1_nCS and OCTOSPI2_NCS work in the same way, then in
Non-multiplexed mode they have to be assigned to their respective
OCTOSPIM_Pn_NCS.
• All the other signals are seen by the I/O matrix as if they were seen from OCTOSPI1.
The Multiplexed mode shall be configured when the OCTOSPIs are disabled to avoid
unexpected transactions on the bus.

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20.5 OCTOSPI I/O manager registers

20.5.1 OCTOSPI I/O manager control register (OCTOSPIM_CR)

Address offset: 0x0000
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. REQ2ACK_TIME[7:0]

rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MUXEN

rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 REQ2ACK_TIME [7:0]: REQ to ACK time
In Multiplexed mode (MUXEN = 1), this field defines the time between two transactions.
The value is the number of OCTOSPI clock cycles - 1
Bits 15:1 Reserved, must be kept at reset value.
Bit 0 MUXEN: Multiplexed mode enable
This bit enables the multiplexing of the two OCTOSPIs.
0: No multiplexing
1: OCTOSPI1 and OCTOSPI2 are multiplexed over the same bus

20.5.2 OCTOSPI I/O manager Port n configuration register

(OCTOSPIM_PnCR) (n=1 to 2)
Address offset: 0x0000 + 0x04*n (n=1 to 2)
Reset value: Block 1: 0x03010111
Reset value: Block 2: 0x07050333

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. IOHSRC[1:0] IOHEN Res. Res. Res. Res. Res. IOLSRC[1:0] IOLEN

rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. NCSSRC NCSEN Res. Res. DQSSRC DQSEN Res. Res. CLKSRC CLKEN

rw rw rw rw rw rw

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Bits 31:27 Reserved, must be kept at reset value.

Bits 26:25 IOHSRC[1:0]: IO[7:4] Source for Port n
This bits select the source of Port n IO[7:4].
00: OCTOSPI1_IO[3:0] in non muxed mode / MUXED_IO[3:0] in muxed mode
01: OCTOSPI1_IO[7:4] in non muxed mode / MUXED_IO[7:4] in muxed mode
10: OCTOSPI2_IO[3:0] in non muxed mode / unused in muxed mode
11: OCTOSPI2_IO[7:4] in non muxed mode / unused in muxed mode
Bit 24 IOHEN: IO[7:4] Enable for Port n
This bit enables the Port n IO[7:4].
0: IO[7:4] for Port n is disabled
1: IO[7:4] for Port n is enabled
Bits 23:19 Reserved, must be kept at reset value.
Bits 18:17 IOLSRC[1:0]: IO[3:0] Source for Port n
This bits select the source of Port n IO[3:0].
00: OCTOSPI1_IO[3:0] in non muxed mode / MUXED_IO[3:0] in muxed mode
01: OCTOSPI1_IO[7:4] in non muxed mode / MUXED_IO[7:4] in muxed mode
10: OCTOSPI2_IO[3:0] in non muxed mode / unused in muxed mode
11: OCTOSPI2_IO[7:4] in non muxed mode / unused in muxed mode
Bit 16 IOLEN: IO[3:0] Enable for Port n
This bit enables the Port n IO[3:0].
0: IO[3:0] for Port n is disabled
1: IO[3:0] for Port n is enabled
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 NCSSRC: nCS Source for Port n
This bit selects the source of Port n nCS.
0: OCTOSPI1_nCS
1: OCTOSPI2_nCS
Bit 8 NCSEN: nCS Enable for Port n
This bit enables the Port n nCS.
0: nCS for Port n is disabled
1: nCS for Port n is enabled
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 DQSSRC: DQS Source for Port n
This bit selects the source of Port n DQS.
0: OCTOSPI1_DQS in non muxed mode / MUXED_DQS in muxed mode
1: OCTOSPI2_DQS in non muxed mode / unused port in muxed mode
Bit 4 DQSEN: DQS Enable for Port n
This bit enables the Port n DQS.
0: DQS for Port n is disabled
1: DQS for Port n is enabled

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Bits 3:2 Reserved, must be kept at reset value.

Bit 1 CLKSRC: CLK/CLKn Source for Port n
This bit selects the source of Port n CLK/CLKn.
0: OCTOSPI1_CLK/CLKn in non muxed mode / MUXED_CLK/CLKn in muxed mode
1: OCTOSPI2_CLK/CLKn in non muxed mode / unused port in muxed mode
Bit 0 CLKEN: CLK/CLKn Enable for Port n
This bit enables the Port n CLK/CLKn.
0: CLK/CLKn for Port n is disabled
1: CLK/CLKn for Port n is enabled

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20.5.3 OCTOSPIM register map

The following table summarizes the OCTOSPI I/O manager registers. Refer to the register
boundary addresses table for the OCTOSPI I/O manager register base address.

Table 124. OCTOSPIM register map and reset values

Offset Register name 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0 MUXEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OCTOSPIM _CR REQ2ACK_TIME[7:0]
0x0000

Reset value 0 0 0 0 0 0 0 0 0

DQSSRC
NCSSRC

CLKSRC
IOHSRC

IOLSRC

DQSEN
NCSEN

CLKEN
IOHEN

IOLEN
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

Res.
Res.
[1:0}

[1:0}
OCTOSPIM _P1CR
0x0004

Reset value 0 1 1 0 0 1 0 1 0 1 0 1

DQSSRC
NCSSRC

CLKSRC
IOHSRC

IOLSRC

DQSEN
NCSEN

CLKEN
IOHEN

IOLEN
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

Res.
Res.
[1:0}

[1:0}
OCTOSPIM _P2CR
0x0008

Reset value 1 1 1 1 0 1 1 1 1 1 1 1

Refer to Section 2.2 on page 91 for the register boundary addresses.

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21 Analog-to-digital converters (ADC)

21.1 Introduction
This section describes the implementation of up to 2 ADCs:
• ADC1 and ADC2 are tightly coupled and can operate in dual mode (ADC1 is master).
Each ADC consists of a 12-bit successive approximation analog-to-digital converter.
Each ADC has up to 19 multiplexed channels. A/D conversion of the various channels can
be performed in single, continuous, scan or discontinuous mode. The result of the ADC is
stored in a left-aligned or right-aligned 16-bit data register.
The ADCs are mapped on the AHB bus to allow fast data handling.
The analog watchdog features allow the application to detect if the input voltage goes
outside the user-defined high or low thresholds.
A built-in hardware oversampler allows to improve analog performances while off-loading
the related computational burden from the CPU.
An efficient low-power mode is implemented to allow very low consumption at low
frequency.

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21.2 ADC main features

• High-performance features
– Up to 2 ADCs which can operate in dual mode:
ADC1 is connected to 16 external channels + 3 internal channels
ADC2 is connected to 16 external channels + 2 internal channels
– 12, 10, 8 or 6-bit configurable resolution
– ADC conversion time is independent from the AHB bus clock frequency
– Faster conversion time by lowering resolution
– Manage single-ended or differential inputs
– AHB slave bus interface to allow fast data handling
– Self-calibration
– Channel-wise programmable sampling time
– Up to four injected channels (analog inputs assignment to regular or injected
channels is fully configurable)
– Hardware assistant to prepare the context of the injected channels to allow fast
context switching
– Data alignment with in-built data coherency
– Data can be managed by DMA for regular channel conversions
– Data can be routed to DFSDM for post processing
– 4 dedicated data registers for the injected channels
• Oversampler
– 16-bit data register
– Oversampling ratio adjustable from 2 to 256
– Programmable data shift up to 8-bit
• Low-power features
– Speed adaptive low-power mode to reduce ADC consumption when operating at
low frequency
– Allows slow bus frequency application while keeping optimum ADC performance
– Provides automatic control to avoid ADC overrun in low AHB bus clock frequency
application (auto-delayed mode)
• Number of external analog input channels per ADC
– Up to 5 fast channels from GPIO pads
– Up to 11 slow channels from GPIO pads
• In addition, there are several internal dedicated channels
– The internal reference voltage (VREFINT), connected to ADC1
– The internal temperature sensor (VTS), connected to ADC1
– The VBAT monitoring channel (VBAT/3), connected to ADC1
– DAC1 and DAC2 internal channels, connected to ADC2
• Start-of-conversion can be initiated:
– By software for both regular and injected conversions
– By hardware triggers with configurable polarity (internal timers events or GPIO
input events) for both regular and injected conversions

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• Conversion modes
– Each ADC can convert a single channel or can scan a sequence of channels
– Single mode converts selected inputs once per trigger
– Continuous mode converts selected inputs continuously
– Discontinuous mode
• Dual ADC mode for ADC1 and 2
• Interrupt generation at ADC ready, the end of sampling, the end of conversion (regular
or injected), end of sequence conversion (regular or injected), analog watchdog 1, 2 or
3 or overrun events
• 3 analog watchdogs per ADC
• ADC input range: VREF– ≤ VIN ≤ VREF+
Figure 88 shows the block diagram of one ADC.

21.3 ADC implementation

Table 125. Main ADC features
References ADC1 ADC2(1)

Dual mode X(1) X

DFSDM interface X X
SMPPLUS control(1) X X
1. Available only on STM32L4Q5xx and STM32L4P5xx.

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RM0432 Analog-to-digital converters (ADC)

21.4 ADC functional description

21.4.1 ADC block diagram

Figure 88 shows the ADC block diagram and Table 127 gives the ADC pin description.

Figure 88. ADC block diagram

VREF+
1.62 to 3.6 V

Cortex
AREADY
M4 with
EOSMP
ADC Interrupt FPU
EOC
EOS IRQ
OVR
JAUTO RDATA[11:0] JEOS master

AHB
JQOVF slave
AWDx

ADEN/ADDIS
ADC_JSQRx master
Analog Supply (VDDA) JDATA1[11:0]
ADC_SQRx 1.62V to 3.6 V JDATA2[11:0]
JDATA3[11:0] DMA
CONT JDATA4[11:0] AHB
single/cont interface DMA request
VTS
dac_out1 DFSDM
VREFINT Bias & Ref 16
VBAT/3 ADCAL
self calibration Oversampler DMACFG
dac_out2
VINP[18:0] Input DMAEN
ADC_INP[16:1] SAR ADC
VINN[18:0] selection & VIN
ADC_INN[16:1] scan control ROVSM
analog input CONVERTED
VREF- channels SMPx[2:0] DATA TROVS
sampling time start
Start & Stop OVSS[3:0]
Control
OVSR[2:0]
AUTDLY OVRMOD
auto delayed S/W trigger overrun mode JOVSE
ADSTP ALIGN
stop conv left/right ROVSE
RES[1:0] Oversampling
12, 10, 8 bits options
JOFFSETx[11:0]
EXT0 JOFFSETx_CH[11:0]
EXT1 h/w
EXT2 trigger
....... DISCEN
....... EXTEN[1:0] DISCNU[:0]
trigger enable Analog watchdog 1,2,3
EXT13 and edge selection Discontinuous
EXT14
mode TIMERs
EXT15
AWD1 AWD1_OUT
EXTi mapped AWD2 AWD2_OUT ETR
EXTSEL[3:0] AWD3 AWD3_OUT
at product level trigger selection

J
S/W trigger
AWD1EN
JEXT0 JAWD1EN
JEXT1 H/W AWD1SGL
JEXT2 trigger
JDISCEN AWDCH1[4:0]
.......
....... JEXTEN[1:0] JDISCNUM[2:0] LT1[11:0]
trigger enable
JEXT13 and edge selection HT1[11:0]
JQM
JEXT14 Injced Context AWDCH2[18:0]
JEXT15 Queue Mode LT2[7:0]
JEXTi mapped AWDCH3[18:0]
at product level HT2[7:0]
JEXTSEL[3:0]
trigger selection HT3[7:0]
LT3[7:0]

MSv43756V7

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21.4.2 ADC pins and internal signals

Table 126. ADC internal input/output signals

Signal
Internal signal name Description
type

Up to 16 external trigger inputs for the regular conversions (can

be connected to on-chip timers).
EXT[15:0] Inputs
These inputs are shared between the ADC master and the ADC
slave.
Up to 16 external trigger inputs for the injected conversions (can
be connected to on-chip timers).
JEXT[15:0] Inputs
These inputs are shared between the ADC master and the ADC
slave.
Internal analog watchdog output signal connected to on-chip
ADC_AWDx_OUT Output
timers. (x = Analog watchdog number 1,2,3)
VTS Input Output voltage from internal temperature sensor
dac_out1 Input DAC internal channel 1
VREFINT Input Output voltage from internal reference voltage
dac_out2 Input DAC internal channel 2
Input
VBAT External battery voltage supply
supply

Table 127. ADC input/output pins

Pin name Signal type Comments

Input, analog reference The higher/positive reference voltage for the ADC,
VREF+
positive 1.62 V ≤ VREF+ ≤ VDDA
Analog power supply equal VDDA:
VDDA Input, analog supply
1.62 V ≤ VDDA ≤ 3.6 V
Input, analog reference The lower/negative reference voltage for the ADC.
VREF−
negative VREF− is internally connected to VSSA
Ground for analog power supply. On device package
Input, analog supply
VSSA which do not have a dedicated VSSA pin, VSSA is
ground
internally connected to VSS.
Positive analog input Connected either to ADCx_INPi external channels or
VINPi
channels for each ADC to internal channels.
Negative analog input Connected either to VREF− or to external channels:
VINNi
channels for each ADC ADCx_INNi and ADCx_INP[i+1].
Up to 16 analog input channels (x = ADC number = 1
Negative external analog or 2)
ADCx_INNi
input signals Refer to Section 21.4.4: ADC1/2 connectivity for
details.
Up to 10 analog input channels (x = ADC number = 1
Positive external analog or 2)
ADCx_INPi
input signals Refer to Section 21.4.4: ADC1/2 connectivity for
details

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21.4.3 ADC clocks

Dual clock domain architecture
The dual clock-domain architecture means that the ADC clock is independent from the AHB
bus clock.
The input clock is the same for all ADCs and can be selected between two different clock
sources (see Figure 89: ADC clock scheme):
1. The ADC clock can be a specific clock source, derived from the following clock
sources:
– The system clock
– PLLSAI1 (single ADC implementation)
Refer to RCC Section for more information on how to generate ADC dedicated clock.
To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be reset.
2. The ADC clock can be derived from the AHB clock of the ADC bus interface, divided by
a programmable factor (1, 2 or 4). In this mode, a programmable divider factor can be
selected (/1, 2 or 4 according to bits CKMODE[1:0]).
To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be different
from “00”.
Note: For option 2), a prescaling factor of 1 (CKMODE[1:0]=01) can be used only if the AHB
prescaler is set to 1 (HPRE[3:0] = 0xxx in RCC_CFGR register).
Option 1) has the advantage of reaching the maximum ADC clock frequency whatever the
AHB clock scheme selected. The ADC clock can eventually be divided by the following ratio:
1, 2, 4, 6, 8, 12, 16, 32, 64, 128, 256; using the prescaler configured with bits PRESC[3:0] in
the ADCx_CCR register.
Option 2) has the advantage of bypassing the clock domain resynchronizations. This can be
useful when the ADC is triggered by a timer and if the application requires that the ADC is
precisely triggered without any uncertainty (otherwise, an uncertainty of the trigger instant is
added by the resynchronizations between the two clock domains).

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Figure 89. ADC clock scheme

RCC ADC1 and ADC2

(Reset and
clock HCLK
controller) AHB interface

Bits CKMODE[1:0]
of ADCx_CCR
Analog ADC1
(master)
/1 or /2 or /4 Others
Analog ADC2
/1, 2, 4, 6, 8, 10, (slave)
ADC12_CK 00
12, 16, 32, 64,
128, 256

Bits PREC[3:0] Bits CKMODE[1:0]

of ADCx_CCR of ADCx_CCR

MSv50635V1

Clock ratio constraint between ADC clock and AHB clock

There are generally no constraints to be respected for the ratio between the ADC clock and
the AHB clock except if some injected channels are programmed. In this case, it is
mandatory to respect the following ratio:
• FHCLK >= FADC / 4 if the resolution of all channels are 12-bit or 10-bit
• FHCLK >= FADC / 3 if there are some channels with resolutions equal to 8-bit (and none
with lower resolutions)
• FHCLK >= FADC / 2 if there are some channels with resolutions equal to 6-bit

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21.4.4 ADC1/2 connectivity

ADC1 and ADC2 are tightly coupled and share some external channels as described in the
below figures.

Figure 90. ADC1 connectivity

ADC1
Channel selection
VINP[0]
VREFINT
VINN[0] Fast channel
VREF−
VINP[1]
ADC12_INP1
VINN[1] Fast channel
ADC12_INN1 VINP[2]
ADC12_INP2 VINN[2] Fast channel
ADC12_INN2 VINP[3]
ADC12_INP3 VINN[3] Fast channel
ADC12_INN3 VINP[4]
ADC12_INP4 VINN[4] Fast channel
ADC12_INN4 VINP[5]
ADC12_INP5 VINN[5] Fast channel
ADC12_INN5 VINP[6]
ADC12_INP6 VINN[6] Slow channel
ADC12_INN6 VINP[7] VREF+
ADC12_INP7 VINN[7] Slow channel
ADC12_INN7 VINP[8] VINP
ADC12_INP8 VINN[8] Slow channel
SAR
ADC12_INN8 VINP[9]
ADC1
ADC12_INP9 VINN[9] Slow channel VINN
ADC12_INN9 VINP[10]
ADC12_INP10 VINN[10] Slow channel
ADC12_INN10 VINP[11] VREF−
ADC12_INP11 VINN[11] Slow channel
ADC12_INN11 VINP[12]
ADC12_INP12 VINN[12] Slow channel
ADC12_INN12 VINP[13]
ADC12_INP13 VINN[13] Slow channel
ADC12_INN13 VINP[14]
ADC12_INP14 VINN[14] Slow channel
ADC12_INN14 VINP[15]
ADC12_INP15 VINN[15] Slow channel
ADC12_INN15 VINP[16]
ADC12_INP16 VINN[16] Slow channel
VREF−
VINP[17]
VTS
VINN[17] Slow channel
VREF−
VINP[18]
VBAT/3
VINN[18] Slow channel
VREF−

MSv41967V5

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Figure 91. ADC2 connectivity

ADC2

ADC2
Channel selection
VINP[0]
VREF−
VINN[0] Fast channel
VREF−
VINP[1]
ADC12_INP1
VINN[1] Fast channel
ADC12_INN1 VINP[2]
ADC12_INP2 VINN[2] Fast channel
ADC12_INN2 VINP[3]
ADC12_INP3 VINN[3] Fast channel
ADC12_INN3 VINP[4]
ADC12_INP4 VINN[4] Fast channel
ADC12_INN4 VINP[5]
ADC12_INP5 VINN[5] Fast channel
ADC12_INN5 VINP[6]
ADC12_INP6 VINN[6] Slow channel
ADC12_INN6 VINP[7] VREF+
ADC12_INP7 VINN[7] Slow channel
ADC12_INN7 VINP[8] VINP
ADC12_INP8 VINN[8] Slow channel
SAR
ADC12_INN8 VINP[9]
ADC2
ADC12_INP9 VINN[9] Slow channel VINN
ADC12_INN9 VINP[10]
ADC12_INP10 VINN[10] Slow channel
ADC12_INN10 VINP[11] VREF−
ADC12_INP11 VINN[11] Slow channel
ADC12_INN11 VINP[12]
ADC12_INP12 VINN[12] Slow channel
ADC12_INN12 VINP[13]
ADC12_INP13 VINN[13] Slow channel
ADC12_INN13 VINP[14]
ADC12_INP14 VINN[14] Slow channel
ADC12_INN14 VINP[15]
ADC12_INP15 VINN[15] Slow channel
ADC12_INN15 VINP[16]
ADC12_INP16 VINN[16] Slow channel
VREF−
dac_out1 VINP[17]
VINN[17] Slow channel
VREF−
dac_out2 VINP[18]
VINN[18] Slow channel
VREF−

MSv50636V4

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RM0432 Analog-to-digital converters (ADC)

21.4.5 Slave AHB interface

The ADCs implement an AHB slave port for control/status register and data access. The
features of the AHB interface are listed below:
• Word (32-bit) accesses
• Single cycle response
• Response to all read/write accesses to the registers with zero wait states.
The AHB slave interface does not support split/retry requests, and never generates AHB
errors.

21.4.6 ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator

(ADVREGEN)
By default, the ADC is in Deep-power-down mode where its supply is internally switched off
to reduce the leakage currents (the reset state of bit DEEPPWD is 1 in the ADC_CR
register).
To start ADC operations, it is first needed to exit Deep-power-down mode by setting bit
DEEPPWD=0.
Then, it is mandatory to enable the ADC internal voltage regulator by setting the bit
ADVREGEN=1 into ADC_CR register. The software must wait for the startup time of the
ADC voltage regulator (TADCVREG_STUP) before launching a calibration or enabling the
ADC. This delay must be implemented by software.
For the startup time of the ADC voltage regulator, refer to device datasheet for
TADCVREG_STUP parameter.
After ADC operations are complete, the ADC can be disabled (ADEN=0). It is possible to
save power by also disabling the ADC voltage regulator. This is done by writing bit
ADVREGEN=0.
Then, to save more power by reducing the leakage currents, it is also possible to re-enter in
ADC Deep-power-down mode by setting bit DEEPPWD=1 into ADC_CR register. This is
particularly interesting before entering STOP mode.
Note: Writing DEEPPWD=1 automatically disables the ADC voltage regulator and bit ADVREGEN
is automatically cleared.
When the internal voltage regulator is disabled (ADVREGEN=0), the internal analog
calibration is kept.
In ADC Deep-power-down mode (DEEPPWD=1), the internal analog calibration is lost and
it is necessary to either relaunch a calibration or re-apply the calibration factor which was
previously saved (refer to Section 21.4.8: Calibration (ADCAL, ADCALDIF,
ADC_CALFACT)).

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21.4.7 Single-ended and differential input channels

Channels can be configured to be either single-ended input or differential input by
programming DIFSEL[i] bits in the ADC_DIFSEL register. This configuration must be written
while the ADC is disabled (ADEN=0). Note that the DIFSEL[i] bits corresponding to single-
ended channels are always programmed at 0.
In single-ended input mode, the analog voltage to be converted for channel “i” is the
difference between the external voltage VINP[i] (positive input) and VREF− (negative input).
In differential input mode, the analog voltage to be converted for channel “i” is the difference
between the external voltage VINP[i] (positive input) and VINN[i] (negative input).
When ADC is configured as differential mode, both inputs should be biased at (VREF+) / 2
voltage.
The input signals are supposed to be differential (common mode voltage should be fixed).
Internal channels (such as VTS and VREFINT) are used in single-ended mode only.
For a complete description of how the input channels are connected for each ADC, refer to
Section 21.4.4: ADC1/2 connectivity.
Caution: When configuring the channel “i” in differential input mode, its negative input voltage VINN[i]
is connected to another channel. As a consequence, this channel is no longer usable in
single-ended mode or in differential mode and must never be configured to be converted.
Some channels are shared between ADC1/ADC2: this can make the channel on the other
ADC unusable. Only exception is interleaved mode for ADC master and the slave.

21.4.8 Calibration (ADCAL, ADCALDIF, ADC_CALFACT)

Each ADC provides an automatic calibration procedure which drives all the calibration
sequence including the power-on/off sequence of the ADC. During the procedure, the ADC
calculates a calibration factor which is 7-bit wide and which is applied internally to the ADC
until the next ADC power-off. During the calibration procedure, the application must not use
the ADC and must wait until calibration is complete.
Calibration is preliminary to any ADC operation. It removes the offset error which may vary
from chip to chip due to process or bandgap variation.
The calibration factor to be applied for single-ended input conversions is different from the
factor to be applied for differential input conversions:
• Write ADCALDIF=0 before launching a calibration which will be applied for single-
ended input conversions.
• Write ADCALDIF=1 before launching a calibration which will be applied for differential
input conversions.
The calibration is then initiated by software by setting bit ADCAL=1. Calibration can only be
initiated when the ADC is disabled (when ADEN=0). ADCAL bit stays at 1 during all the
calibration sequence. It is then cleared by hardware as soon the calibration completes. At
this time, the associated calibration factor is stored internally in the analog ADC and also in
the bits CALFACT_S[6:0] or CALFACT_D[6:0] of ADC_CALFACT register (depending on
single-ended or differential input calibration)
The internal analog calibration is kept if the ADC is disabled (ADEN=0). However, if the ADC
is disabled for extended periods, then it is recommended that a new calibration cycle is run
before re-enabling the ADC.

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RM0432 Analog-to-digital converters (ADC)

The internal analog calibration is lost each time the power of the ADC is removed (example,
when the product enters in STANDBY or VBAT mode). In this case, to avoid spending time
recalibrating the ADC, it is possible to re-write the calibration factor into the ADC_CALFACT
register without recalibrating, supposing that the software has previously saved the
calibration factor delivered during the previous calibration.
The calibration factor can be written if the ADC is enabled but not converting (ADEN=1 and
ADSTART=0 and JADSTART=0). Then, at the next start of conversion, the calibration factor
will automatically be injected into the analog ADC. This loading is transparent and does not
add any cycle latency to the start of the conversion. It is recommended to recalibrate when
VREF+ voltage changed more than 10%.

Software procedure to calibrate the ADC

1. Ensure DEEPPWD=0, ADVREGEN=1 and that ADC voltage regulator startup time has
elapsed.
2. Ensure that ADEN=0.
3. Select the input mode for this calibration by setting ADCALDIF=0 (single-ended input)
or ADCALDIF=1 (differential input).
4. Set ADCAL=1.
5. Wait until ADCAL=0.
6. The calibration factor can be read from ADC_CALFACT register.

Figure 92. ADC calibration

ADCALDIF 0: Single-ended input 1: Differential input

tCAB
ADCAL

ADC State OFF Startup Calibrate OFF

CALFACT_x[6:0] 0x00 Calibration factor

by S/W by H/W Indicative timings

MSv30263V2

Software procedure to re-inject a calibration factor into the ADC

1. Ensure ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no
conversion is ongoing).
2. Write CALFACT_S and CALFACT_D with the new calibration factors.
3. When a conversion is launched, the calibration factor will be injected into the analog
ADC only if the internal analog calibration factor differs from the one stored in bits
CALFACT_S for single-ended input channel or bits CALFACT_D for differential input
channel.

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Figure 93. Updating the ADC calibration factor

ADC state Ready (not converting) Converting channel Ready Converting channel
(Single ended) (Single ended)
Updating calibration
Internal
calibration factor[6:0] F1 F2

Start conversion
(hardware or sofware)

WRITE ADC_CALFACT

CALFACT_S[6:0] F2

by s/w by h/w
MSv30529V2

Converting single-ended and differential analog inputs with a single ADC

If the ADC is supposed to convert both differential and single-ended inputs, two calibrations
must be performed, one with ADCALDIF=0 and one with ADCALDIF=1. The procedure is
the following:
1. Disable the ADC.
2. Calibrate the ADC in single-ended input mode (with ADCALDIF=0). This updates the
register CALFACT_S[6:0].
3. Calibrate the ADC in differential input modes (with ADCALDIF=1). This updates the
register CALFACT_D[6:0].
4. Enable the ADC, configure the channels and launch the conversions. Each time there
is a switch from a single-ended to a differential inputs channel (and vice-versa), the
calibration will automatically be injected into the analog ADC.

Figure 94. Mixing single-ended and differential channels

Trigger event

ADC state RDY CONV CH 1 RDY CONV CH2 RDY CONV CH3 RDY CONV CH4
Single ended (Differential (Differential (Single inputs
inputs channel) inputs channel) inputs channel) channel)

Internal
calibration factor[6:0] F2 F3 F2

CALFACT_S[6:0] F2

CALFACT_D[6:0] F3

MSv30530V2

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21.4.9 ADC on-off control (ADEN, ADDIS, ADRDY)

First of all, follow the procedure explained in Section 21.4.6: ADC Deep-power-down mode
(DEEPPWD) and ADC voltage regulator (ADVREGEN)).
Once DEEPPWD=0 and ADVREGEN=1, the ADC can be enabled and the ADC needs a
stabilization time of tSTAB before it starts converting accurately, as shown in Figure 95. Two
control bits enable or disable the ADC:
• ADEN=1 enables the ADC. The flag ADRDY will be set once the ADC is ready for
operation.
• ADDIS=1 disables the ADC. ADEN and ADDIS are then automatically cleared by
hardware as soon as the analog ADC is effectively disabled.
Regular conversion can then start either by setting ADSTART=1 (refer to Section 21.4.18:
Conversion on external trigger and trigger polarity (EXTSEL, EXTEN,JEXTSEL, JEXTEN))
or when an external trigger event occurs, if triggers are enabled.
Injected conversions start by setting JADSTART=1 or when an external injected trigger
event occurs, if injected triggers are enabled.

Software procedure to enable the ADC

1. Clear the ADRDY bit in the ADC_ISR register by writing ‘1’.
2. Set ADEN=1.
3. Wait until ADRDY=1 (ADRDY is set after the ADC startup time). This can be done
using the associated interrupt (setting ADRDYIE=1).
4. Clear the ADRDY bit in the ADC_ISR register by writing ‘1’ (optional).
Caution: ADEN bit cannot be set when ADCAL is set and during four ADC clock cycles after the
ADCAL bit is cleared by hardware (end of the calibration).

Software procedure to disable the ADC

1. Check that both ADSTART=0 and JADSTART=0 to ensure that no conversion is
ongoing. If required, stop any regular and injected conversion ongoing by setting
ADSTP=1 and JADSTP=1 and then wait until ADSTP=0 and JADSTP=0.
2. Set ADDIS=1.
3. If required by the application, wait until ADEN=0, until the analog ADC is effectively
disabled (ADDIS will automatically be reset once ADEN=0).

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Figure 95. Enabling / disabling the ADC

ADEN
tSTAB

ADRDY

ADDIS

ADC REQ
state OFF Startup RDY Converting CH RDY OFF
-OF

by S/W by H/W
MSv30264V2

21.4.10 Constraints when writing the ADC control bits

The software is allowed to write the RCC control bits to configure and enable the ADC clock
(refer to RCC Section), the DIFSEL[i] control bits in the ADC_DIFSEL register and the
control bits ADCAL and ADEN in the ADC_CR register, only if the ADC is disabled (ADEN
must be equal to 0).
The software is then allowed to write the control bits ADSTART, JADSTART and ADDIS of
the ADC_CR register only if the ADC is enabled and there is no pending request to disable
the ADC (ADEN must be equal to 1 and ADDIS to 0).
For all the other control bits of the ADC_CFGR, ADC_SMPRx, ADC_SQRy, ADC_JDRy,
ADC_OFRy, ADC_OFCHRy and ADC_IER registers:
• For control bits related to configuration of regular conversions, the software is allowed
to write them only if the ADC is enabled (ADEN=1) and if there is no regular conversion
ongoing (ADSTART must be equal to 0).
• For control bits related to configuration of injected conversions, the software is allowed
to write them only if the ADC is enabled (ADEN=1) and if there is no injected
conversion ongoing (JADSTART must be equal to 0).
The software is allowed to write the ADSTP or JADSTP control bits of the ADC_CR register
only if the ADC is enabled, possibly converting, and if there is no pending request to disable
the ADC (ADSTART or JADSTART must be equal to 1 and ADDIS to 0).
The software can write the register ADC_JSQR at any time, when the ADC is enabled
(ADEN=1). Refer to Section 21.6.16: ADC injected sequence register (ADC_JSQR) for
additional details.
Note: There is no hardware protection to prevent these forbidden write accesses and ADC
behavior may become in an unknown state. To recover from this situation, the ADC must be
disabled (clear ADEN=0 as well as all the bits of ADC_CR register).

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RM0432 Analog-to-digital converters (ADC)

21.4.11 Channel selection (SQRx, JSQRx)

There are up to 19 multiplexed channels per ADC:
• 5 fast analog inputs coming from GPIO pads (ADCx_INP/INN[1:5])
• Up to 11 slow analog inputs coming from GPIO pads (ADCx_INP/INN[6:16])
• The ADCs are connected to the following internal analog inputs:
– The internal reference voltage (VREFINT) is connected to ADC1_INP0.
– The internal temperature sensor (VTS) is connected to ADC1_INP17.
– The VBAT monitoring channel (VBAT/3) is connected to ADC1_INP18.
– The DAC1 internal channel 1 is connected to ADC2_INP17.
– The DAC1 internal channel 2 is connected to ADC2_INP18.
Note: To convert one of the internal analog channels, the corresponding analog sources must first
be enabled by programming bits VREFEN, CH17SEL or CH18SEL in the ADCx_CCR
registers.
It is possible to organize the conversions in two groups: regular and injected. A group
consists of a sequence of conversions that can be done on any channel and in any order.
For instance, it is possible to implement the conversion sequence in the following order:
ADCx_INP/INN3, ADCx_INP/INN8, ADCx_INP/INN2, ADCx_INN/INP2, ADCx_INP/INN0,
ADCx_INP/INN2, ADCx_INP/INN2, ADCx_INP/INN15.
• A regular group is composed of up to 16 conversions. The regular channels and their
order in the conversion sequence must be selected in the ADC_SQRy registers. The
total number of conversions in the regular group must be written in the L[3:0] bits in the
ADC_SQR1 register.
• An injected group is composed of up to 4 conversions. The injected channels and
their order in the conversion sequence must be selected in the ADC_JSQR register.
The total number of conversions in the injected group must be written in the L[1:0] bits
in the ADC_JSQR register.
ADC_SQRy registers must not be modified while regular conversions can occur. For this,
the ADC regular conversions must be first stopped by writing ADSTP=1 (refer to
Section 21.4.17: Stopping an ongoing conversion (ADSTP, JADSTP)).
The software is allowed to modify on-the-fly the ADC_JSQR register when JADSTART is set
to 1 (injected conversions ongoing) only when the context queue is enabled (JQDIS=0 in
ADC_CFGR register). Refer to Section 21.4.21: Queue of context for injected conversions

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21.4.12 Channel-wise programmable sampling time (SMPR1, SMPR2)

Before starting a conversion, the ADC must establish a direct connection between the
voltage source under measurement and the embedded sampling capacitor of the ADC. This
sampling time must be enough for the input voltage source to charge the embedded
capacitor to the input voltage level.
Each channel can be sampled with a different sampling time which is programmable using
the SMP[2:0] bits in the ADC_SMPR1 and ADC registers. It is therefore possible to select
among the following sampling time values:
• SMP = 000: 2.5 ADC clock cycles
• SMP = 001: 6.5 ADC clock cycles
• SMP = 010: 12.5 ADC clock cycles
• SMP = 011: 24.5 ADC clock cycles
• SMP = 100: 47.5 ADC clock cycles
• SMP = 101: 92.5 ADC clock cycles
• SMP = 110: 247.5 ADC clock cycles
• SMP = 111: 640.5 ADC clock cycles
The total conversion time is calculated as follows:
TCONV = Sampling time + 12.5 ADC clock cycles
Example:
With FADC_CLK = 30 MHz and a sampling time of 2.5 ADC clock cycles:
TCONV = (2.5 + 12.5) ADC clock cycles = 15 ADC clock cycles = 500 ns
The ADC notifies the end of the sampling phase by setting the status bit EOSMP (only for
regular conversion).

Constraints on the sampling time

For each channel, SMP[2:0] bits must be programmed to respect a minimum sampling time
as specified in the ADC characteristics section of the datasheets.

I/O analog switches voltage booster

The I/O analog switches resistance increases when the VDDA voltage is too low. This
requires to have the sampling time adapted accordingly (cf datasheet for electrical
characteristics). This resistance can be minimized at low VDDA by enabling an internal
voltage booster with BOOSTEN bit in the SYSCFG_CFGR1 register.

SMPPLUS control bit

When a sampling time of 2.5 ADC clock cycles is selected, the total conversion time
becomes 15 cycles in 12-bit mode. If the dual interleaved mode is used (see Section :
Interleaved mode with independent injected), the sampling interval cannot be equal to the
value specified since an even number of cycles is required for the conversion. The
SMPPLUS bit can be used to change the sampling time 2.5 ADC clock cycles into 3.5 ADC
clock cycles. In this way, the total conversion time becomes 16 clock cycles, thus making
possible to interleave every 8 cycles.

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RM0432 Analog-to-digital converters (ADC)

21.4.13 Single conversion mode (CONT=0)

In Single conversion mode, the ADC performs once all the conversions of the channels.
This mode is started with the CONT bit at 0 by either:
• Setting the ADSTART bit in the ADC_CR register (for a regular channel)
• Setting the JADSTART bit in the ADC_CR register (for an injected channel)
• External hardware trigger event (for a regular or injected channel)
Inside the regular sequence, after each conversion is complete:
• The converted data are stored into the 16-bit ADC_DR register
• The EOC (end of regular conversion) flag is set
• An interrupt is generated if the EOCIE bit is set
Inside the injected sequence, after each conversion is complete:
• The converted data are stored into one of the four 16-bit ADC_JDRy registers
• The JEOC (end of injected conversion) flag is set
• An interrupt is generated if the JEOCIE bit is set
After the regular sequence is complete:
• The EOS (end of regular sequence) flag is set
• An interrupt is generated if the EOSIE bit is set
After the injected sequence is complete:
• The JEOS (end of injected sequence) flag is set
• An interrupt is generated if the JEOSIE bit is set
Then the ADC stops until a new external regular or injected trigger occurs or until bit
ADSTART or JADSTART is set again.
Note: To convert a single channel, program a sequence with a length of 1.

21.4.14 Continuous conversion mode (CONT=1)

This mode applies to regular channels only.
In continuous conversion mode, when a software or hardware regular trigger event occurs,
the ADC performs once all the regular conversions of the channels and then automatically
restarts and continuously converts each conversions of the sequence. This mode is started
with the CONT bit at 1 either by external trigger or by setting the ADSTART bit in the
ADC_CR register.
Inside the regular sequence, after each conversion is complete:
• The converted data are stored into the 16-bit ADC_DR register
• The EOC (end of conversion) flag is set
• An interrupt is generated if the EOCIE bit is set
After the sequence of conversions is complete:
• The EOS (end of sequence) flag is set
• An interrupt is generated if the EOSIE bit is set
Then, a new sequence restarts immediately and the ADC continuously repeats the
conversion sequence.

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Note: To convert a single channel, program a sequence with a length of 1.

It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both DISCEN=1 and CONT=1.
Injected channels cannot be converted continuously. The only exception is when an injected
channel is configured to be converted automatically after regular channels in continuous
mode (using JAUTO bit), refer to Auto-injection mode section).

21.4.15 Starting conversions (ADSTART, JADSTART)

Software starts ADC regular conversions by setting ADSTART=1.
When ADSTART is set, the conversion starts:
• Immediately: if EXTEN[1:0] = 00 (software trigger)
• At the next active edge of the selected regular hardware trigger: if EXTEN[1:0] # 00
Software starts ADC injected conversions by setting JADSTART=1.
When JADSTART is set, the conversion starts:
• Immediately, if JEXTEN[1:0] = 00 (software trigger)
• At the next active edge of the selected injected hardware trigger: if JEXTEN[1:0] # 00
Note: In auto-injection mode (JAUTO=1), use ADSTART bit to start the regular conversions
followed by the auto-injected conversions (JADSTART must be kept cleared).
ADSTART and JADSTART also provide information on whether any ADC operation is
currently ongoing. It is possible to re-configure the ADC while ADSTART=0 and
JADSTART=0 are both true, indicating that the ADC is idle.
ADSTART is cleared by hardware:
• In single mode with software regular trigger (CONT=0, EXTSEL=0x0)
– At any end of regular conversion sequence (EOS assertion) or at any end of
subgroup processing if DISCEN = 1
• In all cases (CONT=x, EXTSEL=x)
– After execution of the ADSTP procedure asserted by the software.
Note: In continuous mode (CONT=1), ADSTART is not cleared by hardware with the assertion of
EOS because the sequence is automatically relaunched.
When a hardware trigger is selected in single mode (CONT=0 and EXTSEL /=0x00),
ADSTART is not cleared by hardware with the assertion of EOS to help the software which
does not need to reset ADSTART again for the next hardware trigger event. This ensures
that no further hardware triggers are missed.
JADSTART is cleared by hardware:
• In single mode with software injected trigger (JEXTSEL=0x0)
– At any end of injected conversion sequence (JEOS assertion) or at any end of
subgroup processing if JDISCEN = 1
• in all cases (JEXTSEL=x)
– After execution of the JADSTP procedure asserted by the software.
Note: When the software trigger is selected, ADSTART bit should not be set if the EOC flag is still
high.

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RM0432 Analog-to-digital converters (ADC)

21.4.16 ADC timing

The elapsed time between the start of a conversion and the end of conversion is the sum of
the configured sampling time plus the successive approximation time depending on data
resolution:

TCONV= TSMPL + TSAR = [2.5 |min + 12.5 |12bit ] x TADC_CLK

TCONV = TSMPL + TSAR = 83.33 ns |min + 416.67 ns |12bit = 500.0 ns (for FADC_CLK = 30 MHz)

Figure 96. Analog to digital conversion time

ADC state RDY Sampling Ch(N) Converting Ch(N) Sampling Ch(N+1)

Analog channel Ch(N) Ch(N+1)

Internal S/H Sample AIN(N) Hold AIN(N) Sample AIN(N+1)

tSMPL(1) tSAR(2)
Set
ADSTART by S/W
Set Cleared
EOSMP by H/W by S/W
Set Cleared
by H/W by S/W
EOC
ADC_DR Data N-1 Data N
Indicative timings

MS30532V1

1. TSMPL depends on SMP[2:0].

2. TSAR depends on RES[2:0].

21.4.17 Stopping an ongoing conversion (ADSTP, JADSTP)

The software can decide to stop regular conversions ongoing by setting ADSTP=1 and
injected conversions ongoing by setting JADSTP=1.
Stopping conversions will reset the ongoing ADC operation. Then the ADC can be
reconfigured (ex: changing the channel selection or the trigger) ready for a new operation.
Note that it is possible to stop injected conversions while regular conversions are still
operating and vice-versa. This allows, for instance, re-configuration of the injected
conversion sequence and triggers while regular conversions are still operating (and vice-
versa).
When the ADSTP bit is set by software, any ongoing regular conversion is aborted with
partial result discarded (ADC_DR register is not updated with the current conversion).
When the JADSTP bit is set by software, any ongoing injected conversion is aborted with
partial result discarded (ADC_JDRy register is not updated with the current conversion).
The scan sequence is also aborted and reset (meaning that relaunching the ADC would
restart a new sequence).
Once this procedure is complete, bits ADSTP/ADSTART (in case of regular conversion), or
JADSTP/JADSTART (in case of injected conversion) are cleared by hardware and the
software must poll ADSTART (or JADSTART) until the bit is reset before assuming the ADC
is completely stopped.

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Note: In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected
conversions (JADSTP must not be used).

Figure 97. Stopping ongoing regular conversions

Trigger Trigger

ADC state Sample Convert Sample

RDY Ch(N-1) RDY C RDY
Ch(N-1) Ch(N)

JADSTART

Cleared by Cleared by
ADSTART HW REGULAR CONVERSIONS ongoing HW
(software is not allowed to configure regular conversions selection and triggers)

Set by Cleared by
ADSTP SW HW

ADC_DR Data N-2 Data N-1

MSv30533V2

Figure 98. Stopping ongoing regular and injected conversions

Regular trigger Injected trigger Regular trigger

Sample Convert Sample

ADC state RDY RDY C RDY Sampl RDY
Ch(N-1) Ch(N-1) Ch(M)

Set Cleared
JADSTART by S/W INJECTED CONVERSIONS ongoing by H/W
(software is not allowed to configure injected conversions selection and triggers)

Set Cleared
JADSTP by S/W by H/W

ADC_JDR DATA M-1

Set Cleared
by S/W
by H/W
ADSTART
REGULAR CONVERSIONS ongoing
(software is not allowed to configure regular conversions selection and triggers)
Set Cleared
ADSTP by S/W by H/W

ADC_DR DATA N-2 DATA N-1

MS30534V1

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RM0432 Analog-to-digital converters (ADC)

21.4.18 Conversion on external trigger and trigger polarity

(EXTSEL, EXTEN,JEXTSEL, JEXTEN)
A conversion or a sequence of conversions can be triggered either by software or by an
external event (e.g. timer capture, input pins). If the EXTEN[1:0] control bits (for a regular
conversion) or JEXTEN[1:0] bits (for an injected conversion) are different from 0b00, then
external events are able to trigger a conversion with the selected polarity.
When the Injected Queue is enabled (bit JQDIS=0), injected software triggers are not
possible.
The regular trigger selection is effective once software has set bit ADSTART=1 and the
injected trigger selection is effective once software has set bit JADSTART=1.
Any hardware triggers which occur while a conversion is ongoing are ignored.
• If bit ADSTART=0, any regular hardware triggers which occur are ignored.
• If bit JADSTART=0, any injected hardware triggers which occur are ignored.
Table 128 provides the correspondence between the EXTEN[1:0] and JEXTEN[1:0] values
and the trigger polarity.

Table 128. Configuring the trigger polarity for regular external triggers
EXTEN[1:0] Source

00 Hardware Trigger detection disabled, software trigger detection enabled

01 Hardware Trigger with detection on the rising edge
10 Hardware Trigger with detection on the falling edge
11 Hardware Trigger with detection on both the rising and falling edges

Note: The polarity of the regular trigger cannot be changed on-the-fly.

Table 129. Configuring the trigger polarity for injected external triggers
JEXTEN[1:0] Source

– If JQDIS=1 (Queue disabled): Hardware trigger detection disabled, software

00 trigger detection enabled
– If JQDIS=0 (Queue enabled), Hardware and software trigger detection disabled
01 Hardware Trigger with detection on the rising edge
10 Hardware Trigger with detection on the falling edge
11 Hardware Trigger with detection on both the rising and falling edges

Note: The polarity of the injected trigger can be anticipated and changed on-the-fly when the
queue is enabled (JQDIS=0). Refer to Section 21.4.21: Queue of context for injected
conversions.
The EXTSEL and JEXTSEL control bits select which out of 16 possible events can trigger
conversion for the regular and injected groups.
A regular group conversion can be interrupted by an injected trigger.

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Note: The regular trigger selection cannot be changed on-the-fly.

The injected trigger selection can be anticipated and changed on-the-fly. Refer to
Section 21.4.21: Queue of context for injected conversions on page 638
Each ADC master shares the same input triggers with its ADC slave as described in
Figure 99.

Figure 99. Triggers sharing between ADC master and ADC slave

ADC MASTER

Regular EXT0
sequencer EXT1 External regular trigger
..............
triggers
EXT15

EXTSEL[3:0]

External injected trigger

JEXTSEL[3:0]

ADC SLAVE

External regular trigger

EXTSEL[3:0]
JEXT0
Injected JEXT1 External injected trigger
sequencer ..............
triggers
JEXT15
JEXTSEL[3:0]
MS35356V1

Table 130 to Table 131 give all the possible external triggers of the three ADCs for regular
and injected conversion.

Table 130. ADC1 - External triggers for regular channels

Name Source Type EXTSEL[3:0]

EXT0 TIM1_CH1 Internal signal from on-chip timers 0000

EXT1 TIM1_CH2 Internal signal from on-chip timers 0001
EXT2 TIM1_CH3 Internal signal from on-chip timers 0010
EXT3 TIM2_CH2 Internal signal from on-chip timers 0011
EXT4 TIM3_TRGO Internal signal from on-chip timers 0100
EXT5 TIM4_CH4 Internal signal from on-chip timers 0101
EXT6 EXTI line 11 External pin 0110
EXT7 TIM8_TRGO Internal signal from on-chip timers 0111
EXT8 TIM8_TRGO2 Internal signal from on-chip timers 1000
EXT9 TIM1_TRGO Internal signal from on-chip timers 1001

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RM0432 Analog-to-digital converters (ADC)

Table 130. ADC1 - External triggers for regular channels (continued)

Name Source Type EXTSEL[3:0]

EXT10 TIM1_TRGO2 Internal signal from on-chip timers 1010

EXT11 TIM2_TRGO Internal signal from on-chip timers 1011
EXT12 TIM4_TRGO Internal signal from on-chip timers 1100
EXT13 TIM6_TRGO Internal signal from on-chip timers 1101
EXT14 TIM15_TRGO Internal signal from on-chip timers 1110
EXT15 TIM3_CH4 Internal signal from on-chip timers 1111

Table 131. ADC1 - External trigger for injected channels

Name Source Type JEXTSEL[3:0]

JEXT0 TIM1_TRGO Internal signal from on-chip timers 0000

JEXT1 TIM1_CH4 Internal signal from on-chip timers 0001
JEXT2 TIM2_TRGO Internal signal from on-chip timers 0010
JEXT3 TIM2_CH1 Internal signal from on-chip timers 0011
JEXT4 TIM3_CH4 Internal signal from on-chip timers 0100
JEXT5 TIM4_TRGO Internal signal from on-chip timers 0101
JEXT6 EXTI line 15 External pin 0110
JEXT7 TIM8_CH4 Internal signal from on-chip timers 0111
JEXT8 TIM1_TRGO2 Internal signal from on-chip timers 1000
JEXT9 TIM8_TRGO Internal signal from on-chip timers 1001
JEXT10 TIM8_TRGO2 Internal signal from on-chip timers 1010
JEXT11 TIM3_CH3 Internal signal from on-chip timers 1011
JEXT12 TIM3_TRGO Internal signal from on-chip timers 1100
JEXT13 TIM3_CH1 Internal signal from on-chip timers 1101
JEXT14 TIM6_TRGO Internal signal from on-chip timers 1110
JEXT15 TIM15_TRGO Internal signal from on-chip timers 1111

21.4.19 Injected channel management

Triggered injection mode
To use triggered injection, the JAUTO bit in the ADC_CFGR register must be cleared.
1. Start the conversion of a group of regular channels either by an external trigger or by
setting the ADSTART bit in the ADC_CR register.
2. If an external injected trigger occurs, or if the JADSTART bit in the ADC_CR register is
set during the conversion of a regular group of channels, the current conversion is

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reset and the injected channel sequence switches are launched (all the injected
channels are converted once).
3. Then, the regular conversion of the regular group of channels is resumed from the last
interrupted regular conversion.
4. If a regular event occurs during an injected conversion, the injected conversion is not
interrupted but the regular sequence is executed at the end of the injected sequence.
Figure 100 shows the corresponding timing diagram.
Note: When using triggered injection, one must ensure that the interval between trigger events is
longer than the injection sequence. For instance, if the sequence length is 28 ADC clock
cycles (that is two conversions with a sampling time of 1.5 clock periods), the minimum
interval between triggers must be 29 ADC clock cycles.

Auto-injection mode
If the JAUTO bit in the ADC_CFGR register is set, then the channels in the injected group
are automatically converted after the regular group of channels. This can be used to convert
a sequence of up to 20 conversions programmed in the ADC_SQRy and ADC_JSQR
registers.
In this mode, the ADSTART bit in the ADC_CR register must be set to start regular
conversions, followed by injected conversions (JADSTART must be kept cleared). Setting
the ADSTP bit aborts both regular and injected conversions (JADSTP bit must not be used).
In this mode, external trigger on injected channels must be disabled.
If the CONT bit is also set in addition to the JAUTO bit, regular channels followed by injected
channels are continuously converted.
Note: It is not possible to use both the auto-injected and discontinuous modes simultaneously.
When the DMA is used for exporting regular sequencer’s data in JAUTO mode, it is
necessary to program it in circular mode (CIRC bit set in DMA_CCRx register). If the CIRC
bit is reset (single-shot mode), the JAUTO sequence will be stopped upon DMA Transfer
Complete event.

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RM0432 Analog-to-digital converters (ADC)

Figure 100. Injected conversion latency

ADCCLK

Injection event

Reset ADC

(1)
max. latency
SOC

ai16049b

1. The maximum latency value can be found in the electrical characteristics of the device datasheet.

21.4.20 Discontinuous mode (DISCEN, DISCNUM, JDISCEN)

Regular group mode
This mode is enabled by setting the DISCEN bit in the ADC_CFGR register.
It is used to convert a short sequence (subgroup) of n conversions (n ≤ 8) that is part of the
sequence of conversions selected in the ADC_SQRy registers. The value of n is specified
by writing to the DISCNUM[2:0] bits in the ADC_CFGR register.
When an external trigger occurs, it starts the next n conversions selected in the ADC_SQRy
registers until all the conversions in the sequence are done. The total sequence length is
defined by the L[3:0] bits in the ADC_SQR1 register.
Example:
• DISCEN=1, n=3, channels to be converted = 1, 2, 3, 6, 7, 8, 9, 10, 11
– 1st trigger: channels converted are 1, 2, 3 (an EOC event is generated at each
conversion).
– 2nd trigger: channels converted are 6, 7, 8 (an EOC event is generated at each
conversion).
– 3rd trigger: channels converted are 9, 10, 11 (an EOC event is generated at each
conversion) and an EOS event is generated after the conversion of channel 11.
– 4th trigger: channels converted are 1, 2, 3 (an EOC event is generated at each
conversion).
– ...
• DISCEN=0, channels to be converted = 1, 2, 3, 6, 7, 8, 9, 10,11
– 1st trigger: the complete sequence is converted: channel 1, then 2, 3, 6, 7, 8, 9, 10
and 11. Each conversion generates an EOC event and the last one also generates
an EOS event.
– All the next trigger events will relaunch the complete sequence.

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Note: The channel numbers referred to in the above example might not be available on all
microcontrollers.
When a regular group is converted in discontinuous mode, no rollover occurs (the last
subgroup of the sequence can have less than n conversions).
When all subgroups are converted, the next trigger starts the conversion of the first
subgroup. In the example above, the 4th trigger reconverts the channels 1, 2 and 3 in the
1st subgroup.
It is not possible to have both discontinuous mode and continuous mode enabled. In this
case (if DISCEN=1, CONT=1), the ADC behaves as if continuous mode was disabled.

Injected group mode

This mode is enabled by setting the JDISCEN bit in the ADC_CFGR register. It converts the
sequence selected in the ADC_JSQR register, channel by channel, after an external
injected trigger event. This is equivalent to discontinuous mode for regular channels where
‘n’ is fixed to 1.
When an external trigger occurs, it starts the next channel conversions selected in the
ADC_JSQR registers until all the conversions in the sequence are done. The total sequence
length is defined by the JL[1:0] bits in the ADC_JSQR register.
Example:
• JDISCEN=1, channels to be converted = 1, 2, 3
– 1st trigger: channel 1 converted (a JEOC event is generated)
– 2nd trigger: channel 2 converted (a JEOC event is generated)
– 3rd trigger: channel 3 converted and a JEOC event + a JEOS event are generated
– ...
Note: The channel numbers referred to in the above example might not be available on all
microcontrollers.
When all injected channels have been converted, the next trigger starts the conversion of
the first injected channel. In the example above, the 4th trigger reconverts the 1st injected
channel 1.
It is not possible to use both auto-injected mode and discontinuous mode simultaneously:
the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set.

21.4.21 Queue of context for injected conversions

A queue of context is implemented to anticipate up to 2 contexts for the next injected
sequence of conversions. JQDIS bit of ADC_CFGR register must be reset to enable this
feature. Only hardware-triggered conversions are possible when the context queue is
enabled.
This context consists of:
• Configuration of the injected triggers (bits JEXTEN[1:0] and JEXTSEL bits in
ADC_JSQR register)
• Definition of the injected sequence (bits JSQx[4:0] and JL[1:0] in ADC_JSQR register)

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RM0432 Analog-to-digital converters (ADC)

All the parameters of the context are defined into a single register ADC_JSQR and this
register implements a queue of 2 buffers, allowing the bufferization of up to 2 sets of
parameters:
• The JSQR register can be written at any moment even when injected conversions are
ongoing.
• Each data written into the JSQR register is stored into the Queue of context.
• At the beginning, the Queue is empty and the first write access into the JSQR register
immediately changes the context and the ADC is ready to receive injected triggers.
• Once an injected sequence is complete, the Queue is consumed and the context
changes according to the next JSQR parameters stored in the Queue. This new
context is applied for the next injected sequence of conversions.
• A Queue overflow occurs when writing into register JSQR while the Queue is full. This
overflow is signaled by the assertion of the flag JQOVF. When an overflow occurs, the
write access of JSQR register which has created the overflow is ignored and the queue
of context is unchanged. An interrupt can be generated if bit JQOVFIE is set.
• Two possible behaviors are possible when the Queue becomes empty, depending on
the value of the control bit JQM of register ADC_CFGR:
– If JQM=0, the Queue is empty just after enabling the ADC, but then it can never be
empty during run operations: the Queue always maintains the last active context
and any further valid start of injected sequence will be served according to the last
active context.
– If JQM=1, the Queue can be empty after the end of an injected sequence or if the
Queue is flushed. When this occurs, there is no more context in the queue and
hardware triggers are disabled. Therefore, any further hardware injected triggers
are ignored until the software re-writes a new injected context into JSQR register.
• Reading JSQR register returns the current JSQR context which is active at that
moment. When the JSQR context is empty, JSQR is read as 0x0000.
• The Queue is flushed when stopping injected conversions by setting JADSTP=1 or
when disabling the ADC by setting ADDIS=1:
– If JQM=0, the Queue is maintained with the last active context.
– If JQM=1, the Queue becomes empty and triggers are ignored.
Note: When configured in discontinuous mode (bit JDISCEN=1), only the last trigger of the
injected sequence changes the context and consumes the Queue.The 1st trigger only
consumes the queue but others are still valid triggers as shown by the discontinuous mode
example below (length = 3 for both contexts):
• 1st trigger, discontinuous. Sequence 1: context 1 consumed, 1st conversion carried out
• 2nd trigger, disc. Sequence 1: 2nd conversion.
• 3rd trigger, discontinuous. Sequence 1: 3rd conversion.
• 4th trigger, discontinuous. Sequence 2: context 2 consumed, 1st conversion carried out.
• 5th trigger, discontinuous. Sequence 2: 2nd conversion.
• 6th trigger, discontinuous. Sequence 2: 3rd conversion.

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Behavior when changing the trigger or sequence context

The Figure 101 and Figure 102 show the behavior of the context Queue when changing the
sequence or the triggers.

Figure 101. Example of JSQR queue of context (sequence change)

P1 P2 P3

Write JSQR

JSQR queue EMPTY P1 P1,P2 P2 P2,P3 P3

Trigger 1
ADC J context
EMPTY P1 P2 P3
(returned by reading
JQSR)
ADC state RDY Conversion1 Conversion2 Conversion3 RDY Conversion1 RDY

MS30536V2

1. Parameters:
P1: sequence of 3 conversions, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 4 conversions, hardware trigger 1

Figure 102. Example of JSQR queue of context (trigger change)

P1 P2 P3

Write JSQR

JSQR queue EMPTY P1 P1,P2 P2 P2,P3 P3

Ignored

Trigger 1

Ignored
Trigger 2
ADC J context
EMPTY P1 P2 P3
(returned by reading
JQSR)
ADC state RDY Conversion1 Conversion2 RDY Conversion1 RDY

MS30537V2

1. Parameters:
P1: sequence of 2 conversions, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 2
P3: sequence of 4 conversions, hardware trigger 1

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RM0432 Analog-to-digital converters (ADC)

Queue of context: Behavior when a queue overflow occurs

The Figure 103 and Figure 104 show the behavior of the context Queue if an overflow
occurs before or during a conversion.

Figure 103. Example of JSQR queue of context with overflow before conversion
P1 P2 P3 => Overflow, P4
ignored
Write JSQR

JSQR
EMPTY P1 P1, P2 P2 P2, P4
queue
Cleared by SW
JQOVF

Trigger 1

Trigger 2

ADC
J context
EMPTY P1 P2
(returned by
reading JQSR)

ADC state RDY Conversion1 Conversion2 RDY Conversion1

JEOS

MS30538V2

1. Parameters:
P1: sequence of 2 conversions, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 2
P3: sequence of 3 conversions, hardware trigger 1
P4: sequence of 4 conversions, hardware trigger 1

Figure 104. Example of JSQR queue of context with overflow during conversion

P1 P2 P3 => Overflow, P4
ignored
Write JSQR

JSQR
EMPTY P1 P1, P2 P2 P2, P4
queue
Cleared by SW
JQOVF

Trigger 1

Trigger 2
ADC
J context
(returned by EMPTY P1 P2
reading JQSR)

ADC state RDY Conversion1 Conversion2 RDY Conversion1

JEOS

MS30539V2

1. Parameters:
P1: sequence of 2 conversions, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 2
P3: sequence of 3 conversions, hardware trigger 1
P4: sequence of 4 conversions, hardware trigger 1

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It is recommended to manage the queue overflows as described below:

• After each P context write into JSQR register, flag JQOVF shows if the write has been
ignored or not (an interrupt can be generated).
• Avoid Queue overflows by writing the third context (P3) only once the flag JEOS of the
previous context P2 has been set. This ensures that the previous context has been
consumed and that the queue is not full.

Queue of context: Behavior when the queue becomes empty

Figure 105 and Figure 106 show the behavior of the context Queue when the Queue
becomes empty in both cases JQM=0 or 1.

Figure 105. Example of JSQR queue of context with empty queue (case JQM=0)

Queue not empty

The queue is not empty
(P3 maintained)
and maintains P2 because JQM=0
P1 P2 P3

Write JSQR

EMPTY P1 P1, P2 P2 P3
JSQR queue

Trigger 1

ADC J context
(returned by EMPTY P1 P2 P3
reading JQSR)

ADC state RDY Conversion1 RDY Conversion1 RDY Conversion1 RDY Conversion1 RDY Conv

MS30540V3

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1
Note: When writing P3, the context changes immediately. However, because of internal
resynchronization, there is a latency and if a trigger occurs just after or before writing P3, it
can happen that the conversion is launched considering the context P2. To avoid this
situation, the user must ensure that there is no ADC trigger happening when writing a new
context that applies immediately.

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RM0432 Analog-to-digital converters (ADC)

Figure 106. Example of JSQR queue of context with empty queue (case JQM=1)

Queue becomes empty

and triggers are ignored
P1 P2 because JQM=1 P3
Write JSQR

JSQR
EMPTY P1 P1,P2 P2 EMPTY P3 EMPTY
queue
Ignored Ignored
Trigger 1
ADC
J context EMPTY P1 P2 EMPTY (0x0000) P3 EMPTY
(returned by reading JQSR)
ADC state RDY Conversion1 RDY Conversion1 RDY Conversion1 RDY

MS30541V1

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

Flushing the queue of context

The figures below show the behavior of the context Queue in various situations when the
queue is flushed.

Figure 107. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).

Case when JADSTP occurs during an ongoing conversion.

Queue is flushed and maintains

P1 P2 the last active context P3
(P2 is lost)
Write JSQR

JSQR queue EMPTY P1 P1, P2 P1 P3

Set Reset
JADSTP by S/W by H/W
JADSTART Reset
by H/W Set
by S/W
Trigger 1

ADC J context EMPTY P1 P3

(returned by reading JSQR)

ADC state RDY STP RDY Conversion1 RDY

MS30544V2

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

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Figure 108. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).

Case when JADSTP occurs during an ongoing conversion and a new
trigger occurs.
Queue is flushed and maintains
P1 P2 the last active context P3
(P2 is lost)
Write JSQR
JSQR
queue EMPTY P1 P1, P2 P1 P1, P3 P3
Set Reset
JADSTP by S/W by H/W
JADSTART Reset
by H/W Set
by S/W
Trigger 1

ADC J
context EMPTY P1 P3
(returned by reading JSQR)

ADC state RDY Conv1 STP RDY Conversion1 RDY Conversion1 RDY
(Aborted)
MS30543V1

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

Figure 109. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).

Case when JADSTP occurs outside an ongoing conversion
P1 P2 the last active context P3
(P2 is lost)
Write JSQR

JSQR queue EMPTY P1 P1, P2 P1 P3

Set Reset
JADSTP by S/W by H/W
JADSTART Reset
by H/W Set
by S/W
Trigger 1

ADC J context EMPTY P1 P3

(returned byreading JSQR)

ADC state RDY STP RDY Conversion1 RDY

MS30544V1

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

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RM0432 Analog-to-digital converters (ADC)

Figure 110. Flushing JSQR queue of context by setting JADSTP=1 (JQM=1)

Queue is flushed and
becomes empty (P2 is lost)
P1 P2 P3
Write JSQR

JSQR queue EMPTY P1 P1, P2 EMPTY P3 EMPTY

Set Reset
by S/W by H/W
JADSTP
JADSTART
Reset Set
by H/W by S/W
Ignored
Trigger 1

ADC J context EMPTY P1 EMPTY (0x0000) P3 EMPTY

(returned by reading JSQR)

ADC state RDY Conv1 STP RDY Conversion1 RDY

(Aborted)
MS30545V1

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

Figure 111. Flushing JSQR queue of context by setting ADDIS=1 (JQM=0)

Queue is flushed and maintains

the last active context
(P2 which was not consumed is lost)

JSQR queue P1, P2 P1

Set Reset
ADDIS by S/W by H/W

ADC J context P1
(returned by reading JSQR)

ADC state RDY REQ-OFF OFF

MS30546V1

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

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Figure 112. Flushing JSQR queue of context by setting ADDIS=1 (JQM=1)

Queue is flushed and beomes empty

(JSQR is read as 0x0000)

JSQR queue P1, P2 EMPTY

Set Reset
ADDIS by S/W by H/W

ADC J context P1 EMPTY (0x0000)

(returned by reading JSQR)

ADC state RDY REQ-OFF OFF

MS30547V1

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

Queue of context: Starting the ADC with an empty queue

The following procedure must be followed to start ADC operation with an empty queue, in
case the first context is not known at the time the ADC is initialized. This procedure is only
applicable when JQM bit is reset:
5. Write a dummy JSQR with JEXTEN[1:0] not equal to 00 (otherwise triggering a
software conversion)
6. Set JADSTART
7. Set JADSTP
8. Wait until JADSTART is reset
9. Set JADSTART.

Disabling the queue

It is possible to disable the queue by setting bit JQDIS=1 into the ADC_CFGR register.

21.4.22 Programmable resolution (RES) - fast conversion mode

It is possible to perform faster conversion by reducing the ADC resolution.
The resolution can be configured to be either 12, 10, 8, or 6 bits by programming the control
bits RES[1:0]. Figure 117, Figure 118, Figure 119 and Figure 120 show the conversion
result format with respect to the resolution as well as to the data alignment.
Lower resolution allows faster conversion time for applications where high-data precision is
not required. It reduces the conversion time spent by the successive approximation steps
according to Table 132.

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RM0432 Analog-to-digital converters (ADC)

Table 132. TSAR timings depending on resolution

TCONV (ADC clock cycles)
RES TSAR TSAR (ns) at TCONV (ns) at
(bits) FADC= 30 MHz (with Sampling Time= FADC= 30 MHz
(ADC clock cycles)
2.5 ADC clock cycles)

12 12.5 ADC clock cycles 416.67 ns 15 ADC clock cycles 500.0 ns

10 10.5 ADC clock cycles 350.0 ns 13 ADC clock cycles 433.33 ns
8 8.5 ADC clock cycles 203.33 ns 11 ADC clock cycles 366.67 ns
6 6.5 ADC clock cycles 216.67 ns 9 ADC clock cycles 300.0 ns

21.4.23 End of conversion, end of sampling phase (EOC, JEOC, EOSMP)

The ADC notifies the application for each end of regular conversion (EOC) event and each
injected conversion (JEOC) event.
The ADC sets the EOC flag as soon as a new regular conversion data is available in the
ADC_DR register. An interrupt can be generated if bit EOCIE is set. EOC flag is cleared by
the software either by writing 1 to it or by reading ADC_DR.
The ADC sets the JEOC flag as soon as a new injected conversion data is available in one
of the ADC_JDRy register. An interrupt can be generated if bit JEOCIE is set. JEOC flag is
cleared by the software either by writing 1 to it or by reading the corresponding ADC_JDRy
register.
The ADC also notifies the end of Sampling phase by setting the status bit EOSMP (for
regular conversions only). EOSMP flag is cleared by software by writing 1 to it. An interrupt
can be generated if bit EOSMPIE is set.

21.4.24 End of conversion sequence (EOS, JEOS)

The ADC notifies the application for each end of regular sequence (EOS) and for each end
of injected sequence (JEOS) event.
The ADC sets the EOS flag as soon as the last data of the regular conversion sequence is
available in the ADC_DR register. An interrupt can be generated if bit EOSIE is set. EOS
flag is cleared by the software either by writing 1 to it.
The ADC sets the JEOS flag as soon as the last data of the injected conversion sequence is
complete. An interrupt can be generated if bit JEOSIE is set. JEOS flag is cleared by the
software either by writing 1 to it.

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21.4.25 Timing diagrams example (single/continuous modes,

hardware/software triggers)

Figure 113. Single conversions of a sequence, software trigger

ADSTART(1)

EOC

EOS

ADC state(2) RDY CH1 CH9 CH10 CH17 RDY CH1 CH9 CH10 CH17 RDY

D1 D9 D10 D17 D1 D9 D10 D17

ADC_DR

by s/w by h/w Indicative timings

MS30549V1

1. EXTEN[1:0]=00, CONT=0
2. Channels selected = 1,9, 10, 17; AUTDLY=0.

Figure 114. Continuous conversion of a sequence, software trigger

ADSTART(1)

EOC

EOS

ADSTP

ADC state(2) READY CH1 CH9 CH10 CH17 CH1 CH9 CH10 STP READY CH1 CH9

ADC_DR D1 D9 D10 D17 D1 D9 D1

by s/w by h/w Indicative timings

MS30550V1

1. EXTEN[1:0]=00, CONT=1
2. Channels selected = 1,9, 10, 17; AUTDLY=0.

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RM0432 Analog-to-digital converters (ADC)

Figure 115. Single conversions of a sequence, hardware trigger

ADSTART

EOC

EOS

TRGX(1)

ADC state(2) RDY CH1 CH2 CH3 CH4 READY CH1 CH2 CH3 CH4 RDY

ADC_DR D1 D2 D3 D4 D1 D2 D3 D4

by s/w by h/w triggered ignored Indicative timings

MS31013V2

1. TRGx (over-frequency) is selected as trigger source, EXTEN[1:0] = 01, CONT = 0

2. Channels selected = 1, 2, 3, 4; AUTDLY=0.

Figure 116. Continuous conversions of a sequence, hardware trigger

ADSTART

EOC

EOS

ADSTP

TRGx(1)

ADC(2) RDY CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4 CH1 STOP RDY

ADC_DR D1 D2 D3 D4 D1 D2 D3 D4

by s/w by h/w triggered ignored Not in scale timings

MS31014V2

1. TRGx is selected as trigger source, EXTEN[1:0] = 10, CONT = 1

2. Channels selected = 1, 2, 3, 4; AUTDLY=0.

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21.4.26 Data management

Data register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH,
ALIGN)

Data and alignment

At the end of each regular conversion channel (when EOC event occurs), the result of the
converted data is stored into the ADC_DR data register which is 16 bits wide.
At the end of each injected conversion channel (when JEOC event occurs), the result of the
converted data is stored into the corresponding ADC_JDRy data register which is 16 bits
wide.
The ALIGN bit in the ADC_CFGR register selects the alignment of the data stored after
conversion. Data can be right- or left-aligned as shown in Figure 117, Figure 118, Figure 119
and Figure 120.
Special case: when left-aligned, the data are aligned on a half-word basis except when the
resolution is set to 6-bit. In that case, the data are aligned on a byte basis as shown in
Figure 119 and Figure 120.
Note: Left-alignment is not supported in oversampling mode. When ROVSE and/or JOVSE bit is
set, the ALIGN bit value is ignored and the ADC only provides right-aligned data.

Offset
An offset y (y=1,2,3,4) can be applied to a channel by setting the bit OFFSETy_EN=1 into
ADC_OFRy register. The channel to which the offset will be applied is programmed into the
bits OFFSETy_CH[4:0] of ADC_OFRy register. In this case, the converted value is
decreased by the user-defined offset written in the bits OFFSETy[11:0]. The result may be a
negative value so the read data is signed and the SEXT bit represents the extended sign
value.
Note: Offset correction is not supported in oversampling mode. When ROVSE and/or JOVSE bit is
set, the value of the OFFSETy_EN bit in ADC_OFRy register is ignored (considered as
reset).
Table 135 describes how the comparison is performed for all the possible resolutions for
analog watchdog 1.

Table 133. Offset computation versus data resolution

Subtraction between raw
converted data and offset
Resolution
(bits Raw Result Comments
RES[1:0]) converted
Offset
Data, left
aligned

Signed
00: 12-bit DATA[11:0] OFFSET[11:0] -
12-bit data
Signed The user must configure OFFSET[1:0]
01: 10-bit DATA[11:2],00 OFFSET[11:0]
10-bit data to “00”

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RM0432 Analog-to-digital converters (ADC)

Table 133. Offset computation versus data resolution (continued)

Subtraction between raw
converted data and offset
Resolution
(bits Raw Result Comments
RES[1:0]) converted
Offset
Data, left
aligned

DATA[11:4],00 Signed The user must configure OFFSET[3:0]

10: 8-bit OFFSET[11:0]
00 8-bit data to “0000”
DATA[11:6],00 Signed The user must configure OFFSET[5:0]
11: 6-bit OFFSET[11:0]
0000 6-bit data to “000000”

When reading data from ADC_DR (regular channel) or from ADC_JDRy (injected channel,
y=1,2,3,4) corresponding to the channel “i”:
• If one of the offsets is enabled (bit OFFSETy_EN=1) for the corresponding channel, the
read data is signed.
• If none of the four offsets is enabled for this channel, the read data is not signed.
Figure 117, Figure 118, Figure 119 and Figure 120 show alignments for signed and
unsigned data.

Figure 117. Right alignment (offset disabled, unsigned value)

12-bit data
bit15 bit7 bit0
0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

10-bit data
bit15 bit7 bit0
0 0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

8-bit data
bit15 bit7 bit0
0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0

6-bit data
bit15 bit7 bit0
0 0 0 0 0 0 0 0 0 0 D5 D4 D3 D2 D1 D0

MS31015V1

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Figure 118. Right alignment (offset enabled, signed value)

12-bit data
bit15 bit7 bit0
SEXT SEXT SEXT SEXT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

10-bit data
bit15 bit7 bit0
SEXT SEXT SEXT SEXT SEXT SEXT D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

8-bit data
bit15 bit7 bit0
SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT D7 D6 D5 D4 D3 D2 D1 D0

6-bit data
bit15 bit7 bit0
SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT D5 D4 D3 D2 D1 D0

MS31016V1

Figure 119. Left alignment (offset disabled, unsigned value)

12-bit data
bit15 bit7 bit0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0

10-bit data
bit15 bit7 bit0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0

8-bit data
bit15 bit7 bit0
D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0

6-bit data
bit15 bit7 bit0
0 0 0 0 0 0 0 0 D5 D4 D3 D2 D1 D0 0 0

MS31017V1

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Figure 120. Left alignment (offset enabled, signed value)

12-bit data
bit15 bit7 bit0
SEXT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0

10-bit data
bit15 bit7 bit0
SEXT D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0

8-bit data
bit15 bit7 bit0
SEXT D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0

6-bit data
bit15 bit7 bit0
SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT D5 D4 D3 D2 D1 D0 0

MS31018V1

ADC overrun (OVR, OVRMOD)

The overrun flag (OSR) notifies of that a buffer overrun event occurred when the regular
converted data has not been read (by the CPU or the DMA) before new converted data
became available.
The OVR flag is set if the EOC flag is still 1 at the time when a new conversion completes.
An interrupt can be generated if bit OVRIE=1.
When an overrun condition occurs, the ADC is still operating and can continue converting
unless the software decides to stop and reset the sequence by setting bit ADSTP=1.
OVR flag is cleared by software by writing 1 to it.
It is possible to configure if data is preserved or overwritten when an overrun event occurs
by programming the control bit OVRMOD:
• OVRMOD=0: The overrun event preserves the data register from being overrun: the
old data is maintained and the new conversion is discarded and lost. If OVR remains at
1, any further conversions will occur but the result data will be also discarded.
• OVRMOD=1: The data register is overwritten with the last conversion result and the
previous unread data is lost. If OVR remains at 1, any further conversions will operate
normally and the ADC_DR register will always contain the latest converted data.

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Figure 121. Example of overrun (OVR)

ADSTART(1)

EOC

EOS

OVR

ADSTP

TRGx(1)

ADC state(2) RDY CH1 CH2 CH3 CH4 CH5 CH6 CH7 STOP RDY
Overun
ADC_DR read access

ADC_DR D1
(OVRMOD=0) D2 D3 D4

ADC_DR D1 D2 D3 D4 D5 D6
(OVRMOD=1)

by s/w by h/w triggered Indicative timings

MS31019V1

Note: There is no overrun detection on the injected channels since there is a dedicated data
register for each of the four injected channels.

Managing a sequence of conversions without using the DMA

If the conversions are slow enough, the conversion sequence can be handled by the
software. In this case the software must use the EOC flag and its associated interrupt to
handle each data. Each time a conversion is complete, EOC is set and the ADC_DR
register can be read. OVRMOD should be configured to 0 to manage overrun events as an
error.

Managing conversions without using the DMA and without overrun

It may be useful to let the ADC convert one or more channels without reading the data each
time (if there is an analog watchdog for instance). In this case, the OVRMOD bit must be
configured to 1 and OVR flag should be ignored by the software. An overrun event will not
prevent the ADC from continuing to convert and the ADC_DR register will always contain
the latest conversion.

Managing conversions using the DMA

Since converted channel values are stored into a unique data register, it is useful to use
DMA for conversion of more than one channel. This avoids the loss of the data already
stored in the ADC_DR register.
When the DMA mode is enabled (DMAEN bit set to 1 in the ADC_CFGR register in single
ADC mode or MDMA different from 0b00 in dual ADC mode), a DMA request is generated
after each conversion of a channel. This allows the transfer of the converted data from the
ADC_DR register to the destination location selected by the software.

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RM0432 Analog-to-digital converters (ADC)

Despite this, if an overrun occurs (OVR=1) because the DMA could not serve the DMA
transfer request in time, the ADC stops generating DMA requests and the data
corresponding to the new conversion is not transferred by the DMA. Which means that all
the data transferred to the RAM can be considered as valid.
Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten
(refer to Section : ADC overrun (OVR, OVRMOD)).
The DMA transfer requests are blocked until the software clears the OVR bit.
Two different DMA modes are proposed depending on the application use and are
configured with bit DMACFG of the ADC_CFGR register in single ADC mode, or with bit
DMACFG of the ADC_CCR register in dual ADC mode:
• DMA one shot mode (DMACFG=0).
This mode is suitable when the DMA is programmed to transfer a fixed number of data.
• DMA circular mode (DMACFG=1)
This mode is suitable when programming the DMA in circular mode.

DMA one shot mode (DMACFG=0)

In this mode, the ADC generates a DMA transfer request each time a new conversion data
is available and stops generating DMA requests once the DMA has reached the last DMA
transfer (when DMA_EOT interrupt occurs - refer to DMA paragraph) even if a conversion
has been started again.
When the DMA transfer is complete (all the transfers configured in the DMA controller have
been done):
• The content of the ADC data register is frozen.
• Any ongoing conversion is aborted with partial result discarded.
• No new DMA request is issued to the DMA controller. This avoids generating an
overrun error if there are still conversions which are started.
• Scan sequence is stopped and reset.
• The DMA is stopped.

DMA circular mode (DMACFG=1)

In this mode, the ADC generates a DMA transfer request each time a new conversion data
is available in the data register, even if the DMA has reached the last DMA transfer. This
allows configuring the DMA in circular mode to handle a continuous analog input data
stream.

21.4.27 Managing conversions using the DFSDM

The ADC conversion results can be transferred directly to the Digital filter for sigma delta
modulators (DFSDM).
In this case, the DFSDMCFG bit must be set to 1 and DMAEN bit must be cleared to 0.
The ADC transfers all the 16 bits of the regular data register to the DFSDM and resets the
EOC flag once the transfer is complete.

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The data format must be 16-bit signed:

ADC_DR[15:12] = sign extended
ADC_DR[11] = sign
ADC_DR[11:0] = data
To obtain 16-bit signed format in 12-bit ADC mode, the software needs to configure the
OFFSETy[11:0] to 0x800 after having set OFFSETy_EN to 1.
Only right aligned data format is available for the DFSDM interface (see Figure 118: Right
alignment (offset enabled, signed value)).

21.4.28 Dynamic low-power features

Auto-delayed conversion mode (AUTDLY)
The ADC implements an auto-delayed conversion mode controlled by the AUTDLY
configuration bit. Auto-delayed conversions are useful to simplify the software as well as to
optimize performance of an application clocked at low frequency where there would be risk
of encountering an ADC overrun.
When AUTDLY=1, a new conversion can start only if all the previous data of the same group
has been treated:
• For a regular conversion: once the ADC_DR register has been read or if the EOC bit
has been cleared (see Figure 122).
• For an injected conversion: when the JEOS bit has been cleared (see Figure 123).
This is a way to automatically adapt the speed of the ADC to the speed of the system which
will read the data.
The delay is inserted after each regular conversion (whatever DISCEN=0 or 1) and after
each sequence of injected conversions (whatever JDISCEN=0 or 1).
Note: There is no delay inserted between each conversions of the injected sequence, except after
the last one.
During a conversion, a hardware trigger event (for the same group of conversions) occurring
during this delay is ignored.
Note: This is not true for software triggers where it remains possible during this delay to set the
bits ADSTART or JADSTART to restart a conversion: it is up to the software to read the data
before launching a new conversion.
No delay is inserted between conversions of different groups (a regular conversion followed
by an injected conversion or conversely):
• If an injected trigger occurs during the automatic delay of a regular conversion, the
injected conversion starts immediately (see Figure 123).
• Once the injected sequence is complete, the ADC waits for the delay (if not ended) of
the previous regular conversion before launching a new regular conversion (see
Figure 125).
The behavior is slightly different in auto-injected mode (JAUTO=1) where a new regular
conversion can start only when the automatic delay of the previous injected sequence of
conversion has ended (when JEOS has been cleared). This is to ensure that the software
can read all the data of a given sequence before starting a new sequence (see Figure 126).

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RM0432 Analog-to-digital converters (ADC)

To stop a conversion in continuous auto-injection mode combined with autodelay mode

(JAUTO=1, CONT=1 and AUTDLY=1), follow the following procedure:
1. Wait until JEOS=1 (no more conversions are restarted)
2. Clear JEOS,
3. Set ADSTP=1
4. Read the regular data.
If this procedure is not respected, a new regular sequence can restart if JEOS is cleared
after ADSTP has been set.
In AUTDLY mode, a hardware regular trigger event is ignored if it occurs during an already
ongoing regular sequence or during the delay that follows the last regular conversion of the
sequence. It is however considered pending if it occurs after this delay, even if it occurs
during an injected sequence of the delay that follows it. The conversion then starts at the
end of the delay of the injected sequence.
In AUTDLY mode, a hardware injected trigger event is ignored if it occurs during an already
ongoing injected sequence or during the delay that follows the last injected conversion of
the sequence.

Figure 122. AUTODLY=1, regular conversion in continuous mode, software trigger

ADSTART(1)

EOC

EOS

ADSTP
ADC_DR read access

ADC state RDY CH1 DLY CH2 DLY CH3 DLY CH1 DLY STOP RDY

ADC_DR D1 D2 D3 D1

by s/w by h/w Indicative timings

MS31020V1

1. AUTDLY=1
2. Regular configuration: EXTEN[1:0]=00 (SW trigger), CONT=1, CHANNELS = 1,2,3
3. Injected configuration DISABLED

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Figure 123. AUTODLY=1, regular HW conversions interrupted by injected conversions

(DISCEN=0; JDISCEN=0)

Not ignored
Ignored (occurs during injected sequence)
Regular
trigger

ADC state RDY CH1 DLY CH2 DLY CH5 CH6 CH3 DLY CH1 DLY CH2
regular regular injected regular injected regular regular
DLY (CH1) DLY (CH2) DLY (CH3) DLY (CH1)

EOC

EOS
ADC_DR
read access

ADC_DR D1 D2 D3 D1
Ignored
Injected
trigger
DLY (inj)

JEOS

ADC_JDR1 D5

ADC_JDR2 D6

by s/w by h/w Indicative timings

MS31021V2

1. AUTDLY=1
2. Regular configuration: EXTEN[1:0]=01 (HW trigger), CONT=0, DISCEN=0, CHANNELS = 1, 2, 3
3. Injected configuration: JEXTEN[1:0]=01 (HW Trigger), JDISCEN=0, CHANNELS = 5,6

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RM0432 Analog-to-digital converters (ADC)

Figure 124. AUTODLY=1, regular HW conversions interrupted by injected conversions

(DISCEN=1, JDISCEN=1)
Not ignored
Ignored (occurs during injected sequence)
Regular
trigger
ADC RDY CH1 DLY RDY CH2 DLY RDY CH5 RDY CH6 CH3 DLY RDY CH1 DLY RDYCH2
state
regular regular injected injected regular regular regular
DLY (CH1) DLY (CH2) DLY (CH3) DLY (CH1)

EOC
EOS
ADC_DR read access

ADC_DR D1 D2 D3 D1
Ignored Ignored
Injected
trigger
DLY (inj)

JEOS
ADC_JDR1 D5

ADC_JDR2 D6

by s/w by h/w Indicative timings

MS31022V1

1. AUTDLY=1
2. Regular configuration: EXTEN[1:0]=01 (HW trigger), CONT=0, DISCEN=1, DISCNUM=1, CHANNELS = 1, 2, 3.
3. Injected configuration: JEXTEN[1:0]=01 (HW Trigger), JDISCEN=1, CHANNELS = 5,6

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Figure 125. AUTODLY=1, regular continuous conversions interrupted by injected conversions

ADSTART(1)

ADC
CH1 DLY CH2 DLY CH5 CH6 DLY CH3 DLY CH1
state RDY
regular regular injected injected regular regular
DLY (CH1) DLY (CH2) DLY (CH3)

EOC

EOS
ADC_DR read access

ADC_DR D1 D2 D3
Ignored
Injected
trigger
DLY (inj)

JEOS
ADC_JDR1 D5

ADC_JDR2 D6

by s/w by h/w Indicative timings

MS31023V3

1. AUTDLY=1
2. Regular configuration: EXTEN[1:0]=00 (SW trigger), CONT=1, DISCEN=0, CHANNELS = 1, 2, 3
3. Injected configuration: JEXTEN[1:0]=01 (HW Trigger), JDISCEN=0, CHANNELS = 5,6

Figure 126. AUTODLY=1 in auto- injected mode (JAUTO=1)

ADSTART(1) No delay

ADC state RDY CH1 DLY (CH1) CH2 CH5 CH6 DLY (inj) DLY(CH2) CH3 DLY CH1
regular regular injected injected regular regular
EOC

EOS

ADC_DR read access

ADC_DR D1 D2 D3

JEOS

ADC_JDR1 D5

ADC_JDR2 D6

by s/w by h/w
Indicative timings

MS31024V3

1. AUTDLY=1
2. Regular configuration: EXTEN[1:0]=00 (SW trigger), CONT=1, DISCEN=0, CHANNELS = 1, 2
3. Injected configuration: JAUTO=1, CHANNELS = 5,6

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RM0432 Analog-to-digital converters (ADC)

21.4.29 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL,

AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
The three AWD analog watchdogs monitor whether some channels remain within a
configured voltage range (window).

Figure 127. Analog watchdog guarded area

Analog voltage

Higher threshold HTR

Guarded area
Lower threshold LTR

ai16048

AWDx flag and interrupt

An interrupt can be enabled for each of the 3 analog watchdogs by setting AWDxIE in the
ADC_IER register (x=1,2,3).
AWDx (x=1,2,3) flag is cleared by software by writing 1 to it.
The ADC conversion result is compared to the lower and higher thresholds before
alignment.
Description of analog watchdog 1
The AWD analog watchdog 1 is enabled by setting the AWD1EN bit in the ADC_CFGR
register. This watchdog monitors whether either one selected channel or all enabled
channels(1) remain within a configured voltage range (window).
Table 134 shows how the ADC_CFGR registers should be configured to enable the analog
watchdog on one or more channels.

Table 134. Analog watchdog channel selection

Channels guarded by the analog
AWD1SGL bit AWD1EN bit JAWD1EN bit
watchdog

None x 0 0
All injected channels 0 0 1
All regular channels 0 1 0
All regular and injected channels 0 1 1
(1)
Single injected channel 1 0 1
Single(1) regular channel 1 1 0
(1)
Single regular or injected channel 1 1 1
1. Selected by the AWD1CH[4:0] bits. The channels must also be programmed to be converted in the
appropriate regular or injected sequence.

The AWD1 analog watchdog status bit is set if the analog voltage converted by the ADC is
below a lower threshold or above a higher threshold.

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These thresholds are programmed in bits HT1[11:0] and LT1[11:0] of the ADC_TR1 register
for the analog watchdog 1. When converting data with a resolution of less than 12 bits
(according to bits RES[1:0]), the LSB of the programmed thresholds must be kept cleared
because the internal comparison is always performed on the full 12-bit raw converted data
(left aligned).
Table 135 describes how the comparison is performed for all the possible resolutions for
analog watchdog 1.

Table 135. Analog watchdog 1 comparison

Analog watchdog comparison
Resolution( between:
bit Comments
RES[1:0]) Raw converted data,
Thresholds
left aligned

LT1[11:0] and
00: 12-bit DATA[11:0] -
HT1[11:0]
LT1[11:0] and User must configure LT1[1:0] and HT1[1:0]
01: 10-bit DATA[11:2],00
HT1[11:0] to 00
LT1[11:0] and User must configure LT1[3:0] and HT1[3:0]
10: 8-bit DATA[11:4],0000
HT1[11:0] to 0000
LT1[11:0] and User must configure LT1[5:0] and HT1[5:0]
11: 6-bit DATA[11:6],000000
HT1[11:0] to 000000

Description of analog watchdog 2 and 3

The second and third analog watchdogs are more flexible and can guard several selected
channels by programming the corresponding bits in AWDxCH[18:0] (x=2,3).
The corresponding watchdog is enabled when any bit of AWDxCH[18:0] (x=2,3) is set.
They are limited to a resolution of 8 bits and only the 8 MSBs of the thresholds can be
programmed into HTx[7:0] and LTx[7:0]. Table 136 describes how the comparison is
performed for all the possible resolutions.

Table 136. Analog watchdog 2 and 3 comparison

Analog watchdog comparison between:
Resolution
Comments
(bits RES[1:0]) Raw converted data,
Thresholds
left aligned

00: 12-bit DATA[11:4] LTx[7:0] and HTx[7:0] DATA[3:0] are not relevant for the comparison
01: 10-bit DATA[11:4] LTx[7:0] and HTx[7:0] DATA[3:2] are not relevant for the comparison
10: 8-bit DATA[11:4] LTx[7:0] and HTx[7:0] -
11: 6-bit DATA[11:6],00 LTx[7:0] and HTx[7:0] User must configure LTx[1:0] and HTx[1:0] to 00

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RM0432 Analog-to-digital converters (ADC)

ADCy_AWDx_OUT signal output generation

Each analog watchdog is associated to an internal hardware signal ADCy_AWDx_OUT
(y=ADC number, x=watchdog number) which is directly connected to the ETR input
(external trigger) of some on-chip timers. Refer to the on-chip timers section to understand
how to select the ADCy_AWDx_OUT signal as ETR.
ADCy_AWDx_OUT is activated when the associated analog watchdog is enabled:
• ADCy_AWDx_OUT is set when a guarded conversion is outside the programmed
thresholds.
• ADCy_AWDx_OUT is reset after the end of the next guarded conversion which is
inside the programmed thresholds (It remains at 1 if the next guarded conversions are
still outside the programmed thresholds).
• ADCy_AWDx_OUT is also reset when disabling the ADC (when setting ADDIS=1).
Note that stopping regular or injected conversions (setting ADSTP=1 or JADSTP=1)
has no influence on the generation of ADCy_AWDx_OUT.
Note: AWDx flag is set by hardware and reset by software: AWDx flag has no influence on the
generation of ADCy_AWDx_OUT (ex: ADCy_AWDx_OUT can toggle while AWDx flag
remains at 1 if the software did not clear the flag).

Figure 128. ADCy_AWDx_OUT signal generation (on all regular channels)

ADC
RDY Conversion1 Conversion2 Conversion3 Conversion4 Conversion5 Conversion6 Conversion7
STATE
inside outside inside outside outside outside inside
EOC FLAG

AWDx FLAG cleared cleared cleared cleared

by S/W by S/W by S/W by S/W

ADCy_AWDx_OUT

- Converting regular channels 1,2,3,4,5,6,7

- Regular channels 1,2,3,4,5,6,7 are all guarded

MS31025V1

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Figure 129. ADCy_AWDx_OUT signal generation (AWDx flag not cleared by software)

ADC
RDY Conversion1 Conversion2 Conversion3 Conversion4 Conversion5 Conversion6 Conversion7
STATE
inside outside inside outside outside outside inside
EOC FLAG

not cleared by S/W

AWDx FLAG

ADCy_AWDx_OUT

- Converting regular channels 1,2,3,4,5,6,7

- Regular channels 1,2,3,4,5,6,7 are all guarded

MS31026V1

Figure 130. ADCy_AWDx_OUT signal generation (on a single regular channel)

ADC
Conversion1 Conversion2 Conversion1 Conversion2 Conversion1 Conversion2 Conversion1 Conversion2
STATE
outside inside outside outside
EOC FLAG

EOS FLAG

AWDx FLAG cleared cleared

by S/W by S/W

ADCy_AWDx_OUT

- Converting regular channels 1 and 2

- Only channel 1 is guarded
MS31027V1

Figure 131. ADCy_AWDx_OUT signal generation (on all injected channels)

ADC
RDY Conversion1 Conversion2 Conversion3 Conversion4 Conversion Conversion Conversion
STATE
inside outside inside outside outside outside inside
JEOS FLAG

cleared cleared cleared cleared

AWDx FLAG by S/W by S/W by S/W by S/W

ADCy_AWDx_OUT

- Converting the injected channels 1, 2, 3, 4

- All injected channels 1, 2, 3, 4 are guarded

MS31028V1

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RM0432 Analog-to-digital converters (ADC)

21.4.30 Oversampler
The oversampling unit performs data pre-processing to offload the CPU. It is able to handle
multiple conversions and average them into a single data with increased data width, up to
16-bit.
It provides a result with the following form, where N and M can be adjusted:

n = N–1
1
Result = ----- ×
M  Conversion(t n)
n=0

It allows to perform by hardware the following functions: averaging, data rate reduction,
SNR improvement, basic filtering.
The oversampling ratio N is defined using the OVFS[2:0] bits in the ADC_CFGR2 register,
and can range from 2x to 256x. The division coefficient M consists of a right bit shift up to
8 bits, and is defined using the OVSS[3:0] bits in the ADC_CFGR2 register.
The summation unit can yield a result up to 20 bits (256x 12-bit results), which is first shifted
right. It is then truncated to the 16 least significant bits, rounded to the nearest value using
the least significant bits left apart by the shifting, before being finally transferred into the
ADC_DR data register.
Note: If the intermediary result after the shifting exceeds 16-bit, the result is truncated as is,
without saturation.

Figure 132. 20-bit to 16-bit result truncation

19 15 11 7 3 0
Raw 20-bit data

Shifting

15 0
Truncation and rounding
MS34453V1

Figure 133 gives a numerical example of the processing, from a raw 20-bit accumulated
data to the final 16-bit result.

Figure 133. Numerical example with 5-bit shift and rounding

19 15 11 7 3
Raw 20-bit data 3 B 7 D 7

15 0
Final result after 5-bit shift
1 D B F
and rounding to nearest
MS34454V1

Table 137 gives the data format for the various N and M combinations, for a raw conversion
data equal to 0xFFF.

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Table 137. Maximum output results versus N and M (gray cells indicate truncation)
No-shift 1-bit 2-bit 3-bit 4-bit 5-bit 6-bit 7-bit 8-bit
Over
Max shift shift shift shift shift shift shift shift
sampling
Raw data OVSS = OVSS = OVSS = OVSS = OVSS = OVSS = OVSS = OVSS = OVSS =
ratio
0000 0001 0010 0011 0100 0101 0110 0111 1000

2x 0x1FFE 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040 0x020
4x 0x3FFC 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040
8x 0x7FF8 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080
16x 0xFFF0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100
32x 0x1FFE0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200
64x 0x3FFC0 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400
128x 0x7FF80 0xFF80 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800
256x 0xFFF00 0xFF00 0xFF80 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF

There are no changes for conversion timings in oversampled mode: the sample time is
maintained equal during the whole oversampling sequence. A new data is provided every N
conversions, with an equivalent delay equal to N x TCONV = N x (tSMPL + tSAR). The flags are
set as follow:
• The end of the sampling phase (EOSMP) is set after each sampling phase
• The end of conversion (EOC) occurs once every N conversions, when the
oversampled result is available
• The end of sequence (EOS) occurs once the sequence of oversampled data is
completed (i.e. after N x sequence length conversions total)

ADC operating modes supported when oversampling (single ADC mode)

In oversampling mode, most of the ADC operating modes are maintained:
• Single or continuous mode conversions
• ADC conversions start either by software or with triggers
• ADC stop during a conversion (abort)
• Data read via CPU or DMA with overrun detection
• Low-power modes (AUTDLY)
• Programmable resolution: in this case, the reduced conversion values (as per RES[1:0]
bits in ADC_CFGR1 register) are accumulated, truncated, rounded and shifted in the
same way as 12-bit conversions are
Note: The alignment mode is not available when working with oversampled data. The ALIGN bit in
ADC_CFGR1 is ignored and the data are always provided right-aligned.
Offset correction is not supported in oversampling mode. When ROVSE and/or JOVSE bit is
set, the value of the OFFSETy_EN bit in ADC_OFRy register is ignored (considered as
reset).

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RM0432 Analog-to-digital converters (ADC)

Analog watchdog
The analog watchdog functionality is maintained (AWDSGL and AWDEN bits), with the
following difference:
– The RES[1:0] bits are ignored, comparison is always done on using the full 12-bit
values HT[11:0] and LT[11:0]
– the comparison is performed on the most significant 12-bit of the 16-bit
oversampled results ADC_DR[15:4]
Note: Care must be taken when using high shifting values, this will reduce the comparison range.
For instance, if the oversampled result is shifted by 4 bits, thus yielding a 12-bit data right-
aligned, the effective analog watchdog comparison can only be performed on 8 bits. The
comparison is done between ADC_DR[11:4] and HT[0:7] / LT[[0:7], and HT[11:8] / LT[11:8]
must be kept reset.

Triggered mode
The averager can also be used for basic filtering purpose. Although not a very powerful filter
(slow roll-off and limited stop band attenuation), it can be used as a notch filter to reject
constant parasitic frequencies (typically coming from the mains or from a switched mode
power supply). For this purpose, a specific discontinuous mode can be enabled with
TROVS bit in ADC_CFGR2, to be able to have an oversampling frequency defined by a
user and independent from the conversion time itself.
The Figure 134 below shows how conversions are started in response to triggers during
discontinuous mode.
If the TROVS bit is set, the content of the DISCEN bit is ignored and considered as 1.

Figure 134. Triggered regular oversampling mode (TROVS bit = 1)

Trigger Trigger
CONT=0
DISCEN = 1
TROVS = 0
Ch(N)0 Ch(N)1 Ch(N)2 Ch(N)3 Ch(N)0 Ch(N)1 Ch(N)2 Ch(N)3

EOC flag set

Trigger Trigger Trigger Trigger Trigger Trigger Trigger

CONT=0
DISCEN = 1
TROVS = 1
Ch(N)0 Ch(N)1 Ch(N)2 Ch(N)3 Ch(N)0 Ch(N)1 Ch(N)2

EOC flag set

MS34455V2

Injected and regular sequencer management when oversampling

In oversampling mode, it is possible to have differentiated behavior for injected and regular
sequencers. The oversampling can be enabled for both sequencers with some limitations if
they have to be used simultaneously (this is related to a unique accumulation unit).

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Oversampling regular channels only

The regular oversampling mode bit ROVSM defines how the regular oversampling
sequence is resumed if it is interrupted by injected conversion:
• In continued mode, the accumulation restarts from the last valid data (prior to the
conversion abort request due to the injected trigger). This ensures that oversampling
will be completed whatever the injection frequency (providing at least one regular
conversion can be completed between triggers);
• In resumed mode, the accumulation restarts from 0 (previous conversions results are
ignored). This mode allows to guarantee that all data used for oversampling were
converted back-to-back within a single timeslot. Care must be taken to have a injection
trigger period above the oversampling period length. If this condition is not respected,
the oversampling cannot be completed and the regular sequencer will be blocked.
The Figure 135 gives examples for a 4x oversampling ratio.

Figure 135. Regular oversampling modes (4x ratio)

Oversampling Oversampling
stopped continued

Regular channels Ch(N)0 Ch(N)1 Ch(N)2 Ch(N)3 Ch(M)0 Ch(M)1 Ch(M)1 Ch(M)2 Ch(M)3 Ch(O)0
Abort
Trigger

Injected channels Ch(J) Ch(K)

JEOC

Continued mode: ROVSE = 1, JOVSE = 0, ROVSM = 0, TROVS = X

Oversampling Oversampling
aborted resumed

Regular channels Ch(N)0 Ch(N)1 Ch(N)2 Ch(N)3 Ch(M)0 Ch(M)1 Ch(M)0 Ch(M)1 Ch(M)2 Ch(M)3
Abort
Trigger

Injected channels Ch(J) Ch(K)

JEOC

Resumed mode: ROVSE = 1, JOVSE = 0, ROVSM = 1, TROVS = X

MS34456V1

Oversampling Injected channels only

The Injected oversampling mode bit JOVSE enables oversampling solely for conversions in
the injected sequencer.

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RM0432 Analog-to-digital converters (ADC)

Oversampling regular and Injected channels

It is possible to have both ROVSE and JOVSE bits set. In this case, the regular
oversampling mode is forced to resumed mode (ROVSM bit ignored), as represented on
Figure 136 below.

Figure 136. Regular and injected oversampling modes used simultaneously

Oversampling Oversampling
aborted resumed

Regular channels Ch(N)0 Ch(N)1 Ch(N)2 Ch(N)3 Ch(M)0 Ch(M)1 Ch(M)0 Ch(M)1
Abort
Trigger

Injected channels Ch(J)0 Ch(J)1 Ch(J)2 Ch(J)3

JEOC

ROVSE = 1, JOVSE = 1, ROVSM = X, TROVS = 0

MS34457V1

Triggered regular oversampling with injected conversions

It is possible to have triggered regular mode with injected conversions. In this case, the
injected mode oversampling mode must be disabled, and the ROVSM bit is ignored
(resumed mode is forced). The JOVSE bit must be reset. The behavior is represented on
Figure 137 below.

Figure 137. Triggered regular oversampling with injection

Oversampling
resumed

Trigger Trigger Trigger Trigger Trigger

Regular channels Ch(N)0 Ch(N)1 Ch(N)2 Ch(N)0

Abort
Trigger

Injected channels Ch(J) Ch(K)

ROVSE = 1, JOVSE = 0, ROVSM = X, TROVS = 1

MS34458V2

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Auto-injected mode
It is possible to oversample auto-injected sequences and have all conversions results stored
in registers to save a DMA resource. This mode is available only with both regular and
injected oversampling active: JAUTO = 1, ROVSE = 1 and JOVSE = 1, other combinations
are not supported. The ROVSM bit is ignored in auto-injected mode. The Figure 138 below
shows how the conversions are sequenced.

Figure 138. Oversampling in auto-injected mode

Regular channels N0 N1 N2 N3 N0 N1 N2 N3

Injected channels I0 I1 I2 I3 J0 J1 J2 J3 K0 K1 K2 K3 L0 L1 L2 L3

JAUTO =1, ROVSE = 1, JOVSE = 1, ROVSM = X, TROVS = 0

MS34459V1

It is possible to have also the triggered mode enabled, using the TROVS bit. In this case,
the ADC must be configured as following: JAUTO = 1, DISCEN = 0, JDISCEN = 0, ROVSE
= 1, JOVSE = 1 and TROVSE = 1.

Dual ADC modes supported when oversampling

It is possible to have oversampling enabled when working in dual ADC configuration, for the
injected simultaneous mode and regular simultaneous mode. In this case, the two ADCs
must be programmed with the very same settings (including oversampling).
All other dual ADC modes are not supported when either regular or injected oversampling is
enabled (ROVSE = 1 or JOVSE = 1).

Combined modes summary

The Table 138 below summarizes all combinations, including modes not supported.

Table 138. Oversampler operating modes summary

Oversampler
Regular Injected mode Triggered
Oversampling Oversampling ROVSM Regular mode Comment
ROVSE JOVSE 0 = continued TROVS
1 = resumed

1 0 0 0 Regular continued mode

1 0 0 1 Not supported
1 0 1 0 Regular resumed mode
Triggered regular resumed
1 0 1 1
mode
1 1 0 X Not supported
Injected and regular resumed
1 1 1 0
mode
1 1 1 1 Not supported
0 1 X X Injected oversampling

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RM0432 Analog-to-digital converters (ADC)

21.4.31 Dual ADC modes

Dual ADC modes can be used in devices with two ADCs or more (see Figure 139).
In dual ADC mode the start of conversion is triggered alternately or simultaneously by the
ADCx master to the ADC slave, depending on the mode selected by the bits DUAL[4:0] in
the ADCx_CCR register.
Four possible modes are implemented:
• Injected simultaneous mode
• Regular simultaneous mode
• Interleaved mode
• Alternate trigger mode
It is also possible to use these modes combined in the following ways:
• Injected simultaneous mode + Regular simultaneous mode
• Regular simultaneous mode + Alternate trigger mode
• Injected simultaneous mode + Interleaved mode
In dual ADC mode (when bits DUAL[4:0] in ADCx_CCR register are not equal to zero), the
bits CONT, AUTDLY, DISCEN, DISCNUM[2:0], JDISCEN, JQM, JAUTO of the ADC_CFGR
register are shared between the master and slave ADC: the bits in the slave ADC are
always equal to the corresponding bits of the master ADC.
To start a conversion in dual mode, the user must program the bits EXTEN[1:0], EXTSEL,
JEXTEN[1:0], JEXTSEL of the master ADC only, to configure a software or hardware
trigger, and a regular or injected trigger. (the bits EXTEN[1:0] and JEXTEN[1:0] of the slave
ADC are don’t care).
In regular simultaneous or interleaved modes: once the user sets bit ADSTART or bit
ADSTP of the master ADC, the corresponding bit of the slave ADC is also automatically
set. However, bit ADSTART or bit ADSTP of the slave ADC is not necessary cleared at the
same time as the master ADC bit.
In injected simultaneous or alternate trigger modes: once the user sets bit JADSTART or bit
JADSTP of the master ADC, the corresponding bit of the slave ADC is also automatically
set. However, bit JADSTART or bit JADSTP of the slave ADC is not necessary cleared at
the same time as the master ADC bit.
In dual ADC mode, the converted data of the master and slave ADC can be read in parallel,
by reading the ADC common data register (ADCx_CDR). The status bits can be also read in
parallel by reading the dual-mode status register (ADCx_CSR).

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Figure 139. Dual ADC block diagram(1)

Regular data register (16-

bits)

Injected data registers (4

Internal analog inputs x16-bits)
ADCx_INN1 Regular
ADCx_INP1

Address/data bus
channels
ADCx_INN2
ADCx_INP2 Injected
Slave ADC
channels

Internal triggers

Regular data register (16-

bits)
ADCx_INN16
ADCx_INP16 Injected data registers (4
x16-bits)
Internal analog inputs Regular
channels

Injected
channels

Dual mode
control

Start trigger mux.

(regular group)

Master ADC

Start trigger mux.

(injected group)

MSv36025V2

1. External triggers also exist on slave ADC but are not shown for the purposes of this diagram.
2. The ADC common data register (ADCx_CDR) contains both the master and slave ADC regular converted data.

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RM0432 Analog-to-digital converters (ADC)

Injected simultaneous mode

This mode is selected by programming bits DUAL[4:0]=00101
This mode converts an injected group of channels. The external trigger source comes from
the injected group multiplexer of the master ADC (selected by the JEXTSEL bits in the
ADC_JSQR register).
Note: Do not convert the same channel on the two ADCs (no overlapping sampling times for the
two ADCs when converting the same channel).
In simultaneous mode, one must convert sequences with the same length or ensure that the
interval between triggers is longer than the longer of the 2 sequences. Otherwise, the ADC
with the shortest sequence may restart while the ADC with the longest sequence is
completing the previous conversions.
Regular conversions can be performed on one or all ADCs. In that case, they are
independent of each other and are interrupted when an injected event occurs. They are
resumed at the end of the injected conversion group.
• At the end of injected sequence of conversion event (JEOS) on the master ADC, the
converted data is stored into the master ADC_JDRy registers and a JEOS interrupt is
generated (if enabled)
• At the end of injected sequence of conversion event (JEOS) on the slave ADC, the
converted data is stored into the slave ADC_JDRy registers and a JEOS interrupt is
generated (if enabled)
• If the duration of the master injected sequence is equal to the duration of the slave
injected one (like in Figure 140), it is possible for the software to enable only one of the
two JEOS interrupt (ex: master JEOS) and read both converted data (from master
ADC_JDRy and slave ADC_JDRy registers).

Figure 140. Injected simultaneous mode on 4 channels: dual ADC mode

MASTER ADC CH1 CH2 CH3 CH4

SLAVE ADC CH15 CH14 CH13 CH12

Trigger
End of injected sequence on
Sampling MASTER and SLAVE ADC

Conversion
MS31900V1

If JDISCEN=1, each simultaneous conversion of the injected sequence requires an injected

trigger event to occur.
This mode can be combined with AUTDLY mode:
• Once a simultaneous injected sequence of conversions has ended, a new injected
trigger event is accepted only if both JEOS bits of the master and the slave ADC have
been cleared (delay phase). Any new injected trigger events occurring during the
ongoing injected sequence and the associated delay phase are ignored.
• Once a regular sequence of conversions of the master ADC has ended, a new regular
trigger event of the master ADC is accepted only if the master data register (ADC_DR)
has been read. Any new regular trigger events occurring for the master ADC during the

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ongoing regular sequence and the associated delay phases are ignored.
There is the same behavior for regular sequences occurring on the slave ADC.

Regular simultaneous mode with independent injected

This mode is selected by programming bits DUAL[4:0] = 00110.
This mode is performed on a regular group of channels. The external trigger source comes
from the regular group multiplexer of the master ADC (selected by the EXTSEL bits in the
ADC_CFGR register). A simultaneous trigger is provided to the slave ADC.
In this mode, independent injected conversions are supported. An injection request (either
on master or on the slave) will abort the current simultaneous conversions, which are
restarted once the injected conversion is completed.
Note: Do not convert the same channel on the two ADCs (no overlapping sampling times for the
two ADCs when converting the same channel).
In regular simultaneous mode, one must convert sequences with the same length or ensure
that the interval between triggers is longer than the longer conversion time of the 2
sequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with
the longest sequence is completing the previous conversions.
Software is notified by interrupts when it can read the data:
• At the end of each conversion event (EOC) on the master ADC, a master EOC interrupt
is generated (if EOCIE is enabled) and software can read the ADC_DR of the master
ADC.
• At the end of each conversion event (EOC) on the slave ADC, a slave EOC interrupt is
generated (if EOCIE is enabled) and software can read the ADC_DR of the slave ADC.
• If the duration of the master regular sequence is equal to the duration of the slave one
(like in Figure 141), it is possible for the software to enable only one of the two EOC
interrupt (ex: master EOC) and read both converted data from the Common Data
register (ADCx_CDR).
It is also possible to read the regular data using the DMA. Two methods are possible:
• Using two DMA channels (one for the master and one for the slave). In this case bits
MDMA[1:0] must be kept cleared.
– Configure the DMA master ADC channel to read ADC_DR from the master. DMA
requests are generated at each EOC event of the master ADC.
– Configure the DMA slave ADC channel to read ADC_DR from the slave. DMA
requests are generated at each EOC event of the slave ADC.
• Using MDMA mode, which leaves one DMA channel free for other uses:
– Configure MDMA[1:0]=0b10 or 0b11 (depending on resolution).
– A single DMA channel is used (the one of the master). Configure the DMA master
ADC channel to read the common ADC register (ADCx_CDR)
– A single DMA request is generated each time both master and slave EOC events
have occurred. At that time, the slave ADC converted data is available in the
upper half-word of the ADCx_CDR 32-bit register and the master ADC converted
data is available in the lower half-word of ADCx_CCR register.
– Both EOC flags are cleared when the DMA reads the ADCx_CCR register.
Note: In MDMA mode (MDMA[1:0]=0b10 or 0b11), the user must program the same number of
conversions in the master’s sequence as in the slave’s sequence. Otherwise, the remaining
conversions will not generate a DMA request.

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RM0432 Analog-to-digital converters (ADC)

Figure 141. Regular simultaneous mode on 16 channels: dual ADC mode

MASTER ADC CH1 CH2 CH3 CH4 ... CH16

SLAVE ADC CH16 CH14 CH13 CH12 ... CH1

Trigger
End of regular sequence on
Sampling MASTER and SLAVE ADC

Conversion ai16054b

If DISCEN=1 then each “n” simultaneous conversions of the regular sequence require a
regular trigger event to occur (“n” is defined by DISCNUM).
This mode can be combined with AUTDLY mode:
• Once a simultaneous conversion of the sequence has ended, the next conversion in
the sequence is started only if the common data register, ADCx_CDR (or the regular
data register of the master ADC) has been read (delay phase).
• Once a simultaneous regular sequence of conversions has ended, a new regular
trigger event is accepted only if the common data register (ADCx_CDR) has been read
(delay phase). Any new regular trigger events occurring during the ongoing regular
sequence and the associated delay phases are ignored.
It is possible to use the DMA to handle data in regular simultaneous mode combined with
AUTDLY mode, assuming that multi-DMA mode is used: bits MDMA must be set to 0b10 or
0b11.
When regular simultaneous mode is combined with AUTDLY mode, it is mandatory for the
user to ensure that:
• The number of conversions in the master’s sequence is equal to the number of
conversions in the slave’s.
• For each simultaneous conversions of the sequence, the length of the conversion of
the slave ADC is inferior to the length of the conversion of the master ADC. Note that
the length of the sequence depends on the number of channels to convert and the
sampling time and the resolution of each channels.
Note: This combination of regular simultaneous mode and AUTDLY mode is restricted to the use
case when only regular channels are programmed: it is forbidden to program injected
channels in this combined mode.

Interleaved mode with independent injected

This mode is selected by programming bits DUAL[4:0] = 00111.
This mode can be started only on a regular group (usually one channel). The external
trigger source comes from the regular channel multiplexer of the master ADC.
After an external trigger occurs:
• The master ADC starts immediately.
• The slave ADC starts after a delay of several ADC clock cycles after the sampling
phase of the master ADC has complete.
The minimum delay which separates two conversions in interleaved mode is configured in
the DELAY bits in the ADCx_CCR register. This delay starts counting one half cycle after the
end of the sampling phase of the master conversion. This way, an ADC cannot start a

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conversion if the complementary ADC is still sampling its input (only one ADC can sample
the input signal at a given time).
• The minimum possible DELAY is 1 to ensure that there is at least one cycle time
between the opening of the analog switch of the master ADC sampling phase and the
closing of the analog switch of the slave ADC sampling phase.
• The maximum DELAY is equal to the number of cycles corresponding to the selected
resolution. However the user must properly calculate this delay to ensure that an ADC
does not start a conversion while the other ADC is still sampling its input.
If the CONT bit is set on both master and slave ADCs, the selected regular channels of both
ADCs are continuously converted.
The software is notified by interrupts when it can read the data at the end of each
conversion event (EOC) on the slave ADC. A slave and master EOC interrupts are
generated (if EOCIE is enabled) and the software can read the ADC_DR of the slave/master
ADC.
Note: It is possible to enable only the EOC interrupt of the slave and read the common data
register (ADCx_CDR). But in this case, the user must ensure that the duration of the
conversions are compatible to ensure that inside the sequence, a master conversion is
always followed by a slave conversion before a new master conversion restarts. It is
recommended to use the MDMA mode.
It is also possible to have the regular data transferred by DMA. In this case, individual DMA
requests on each ADC cannot be used and it is mandatory to use the MDMA mode, as
following:
• Configure MDMA[1:0]=0b10 or 0b11 (depending on resolution).
• A single DMA channel is used (the one of the master). Configure the DMA master ADC
channel to read the common ADC register (ADCx_CDR).
• A single DMA request is generated each time both master and slave EOC events have
occurred. At that time, the slave ADC converted data is available in the upper half-word
of the ADCx_CDR 32-bit register and the master ADC converted data is available in the
lower half-word of ADCx_CCR register.
• Both EOC flags are cleared when the DMA reads the ADCx_CCR register.

Figure 142. Interleaved mode on 1 channel in continuous conversion mode: dual ADC
mode

0.5 ADCCLK 0.5 ADCCLK

cycle cycle

MASTER ADC CH1 CH1

SLAVE ADC
CH1 CH1
Trigger

4 ADCCLK 4 ADCCLK End of conversion on master and

cycles cycles slave ADC
Sampling

Conversion
MSv31030V3

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Figure 143. Interleaved mode on 1 channel in single conversion mode: dual ADC
mode
0.5 ADCCLK 0.5 ADCCLK
cycle cycle

MASTER ADC CH1 CH1

SLAVE ADC CH1 CH1

Trigger

4 ADCCLK End of conversion on 4 ADCCLK End of conversion on

cycles master and slave ADC cycles master and slave ADC

Sampling

Conversion
MSv31031V3

If DISCEN=1, each “n” simultaneous conversions (“n” is defined by DISCNUM) of the

regular sequence require a regular trigger event to occur.
In this mode, injected conversions are supported. When injection is done (either on master
or on slave), both the master and the slave regular conversions are aborted and the
sequence is restarted from the master (see Figure 144 below).

Figure 144. Interleaved conversion with injection

Injected trigger Resume (always on master)

CH11

ADC1 (master) CH1 CH1 CH1 CH1 CH1 CH1

ADC2 (slave) CH2 CH2 CH2 CH2 CH2 CH0

read read conversions read read

Legend: CDR CDR aborted CDR CDR

Sampling Conversion
MS34460V1

Alternate trigger mode

This mode is selected by programming bits DUAL[4:0] = 01001.
This mode can be started only on an injected group. The source of external trigger comes
from the injected group multiplexer of the master ADC.
This mode is only possible when selecting hardware triggers: JEXTEN[1:0] must not be 00.
Injected discontinuous mode disabled (JDISCEN=0 for both ADC)

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1. When the 1st trigger occurs, all injected master ADC channels in the group are
converted.
2. When the 2nd trigger occurs, all injected slave ADC channels in the group are
converted.
3. And so on.
A JEOS interrupt, if enabled, is generated after all injected channels of the master ADC in
the group have been converted.
A JEOS interrupt, if enabled, is generated after all injected channels of the slave ADC in the
group have been converted.
JEOC interrupts, if enabled, can also be generated after each injected conversion.
If another external trigger occurs after all injected channels in the group have been
converted then the alternate trigger process restarts by converting the injected channels of
the master ADC in the group.

Figure 145. Alternate trigger: injected group of each ADC

JEOC on JEOC on JEOC,JEOS on

1st trigger master ADC master ADC master ADC

MASTER ADC

SLAVE ADC

2nd trigger JEOC on JEOC on JEOC, JEOS on

slave ADC slave ADC slave ADC

JEOC on JEOC on JEOC,JEOS on

3rd trigger master ADC master ADC master ADC

MASTER ADC

SLAVE ADC

4th trigger JEOC on JEOC on JEOC, JEOS on

slave ADC slave ADC slave ADC

Sampling
Conversion
ai16059-m

Note: Regular conversions can be enabled on one or all ADCs. In this case the regular
conversions are independent of each other. A regular conversion is interrupted when the
ADC has to perform an injected conversion. It is resumed when the injected conversion is
finished.
The time interval between 2 trigger events must be greater than or equal to 1 ADC clock
period. The minimum time interval between 2 trigger events that start conversions on the
same ADC is the same as in the single ADC mode.
Injected discontinuous mode enabled (JDISCEN=1 for both ADC)

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If the injected discontinuous mode is enabled for both master and slave ADCs:
• When the 1st trigger occurs, the first injected channel of the master ADC is converted.
• When the 2nd trigger occurs, the first injected channel of the slave ADC is converted.
• And so on.
A JEOS interrupt, if enabled, is generated after all injected channels of the master ADC in
the group have been converted.
A JEOS interrupt, if enabled, is generated after all injected channels of the slave ADC in the
group have been converted.
JEOC interrupts, if enabled, can also be generated after each injected conversions.
If another external trigger occurs after all injected channels in the group have been
converted then the alternate trigger process restarts.

Figure 146. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode
1st trigger 3rd trigger 5th trigger 7th trigger
JEOC on JEOC on JEOC, JEOS on
JEOC on master ADC
master ADC master ADC master ADC

MASTER ADC
SLAVE ADC

JEOC on JEOC on JEOC on

master ADC master ADC master ADC JEOC, JEOS on
master ADC
2nd trigger 4th trigger 6th trigger 8th trigger

Sampling

Conversion ai16060V2-m

Combined regular/injected simultaneous mode

This mode is selected by programming bits DUAL[4:0] = 00001.
It is possible to interrupt the simultaneous conversion of a regular group to start the
simultaneous conversion of an injected group.
Note: In combined regular/injected simultaneous mode, one must convert sequences with the
same length or ensure that the interval between triggers is longer than the long conversion
time of the 2 sequences. Otherwise, the ADC with the shortest sequence may restart while
the ADC with the longest sequence is completing the previous conversions.

Combined regular simultaneous + alternate trigger mode

This mode is selected by programming bits DUAL[4:0]=00010.
It is possible to interrupt the simultaneous conversion of a regular group to start the alternate
trigger conversion of an injected group. Figure 147 shows the behavior of an alternate
trigger interrupting a simultaneous regular conversion.
The injected alternate conversion is immediately started after the injected event. If a regular
conversion is already running, in order to ensure synchronization after the injected
conversion, the regular conversion of all (master/slave) ADCs is stopped and resumed
synchronously at the end of the injected conversion.

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Note: In combined regular simultaneous + alternate trigger mode, one must convert sequences
with the same length or ensure that the interval between triggers is longer than the long
conversion time of the 2 sequences. Otherwise, the ADC with the shortest sequence may
restart while the ADC with the longest sequence is completing the previous conversions.

Figure 147. Alternate + regular simultaneous

1st trigger

ADC MASTER reg CH1 CH2 CH3 CH3 CH4 CH4 CH5

ADC MASTER inj CH1

ADC SLAVE reg CH4 CH6 CH7 CH7 CH8 CH8 CH9

ADC SLAVE inj CH1

synchro not lost

2nd trigger ai16062V2-m

If a trigger occurs during an injected conversion that has interrupted a regular conversion,
the alternate trigger is served. Figure 148 shows the behavior in this case (note that the 6th
trigger is ignored because the associated alternate conversion is not complete).

Figure 148. Case of trigger occurring during injected conversion

1st trigger 3rd trigger 5th trigger

ADC MASTER reg CH1 CH2 CH3 CH3 CH4 CH4 CH5 CH5 CH6
ADC MASTER inj CH14 CH14 CH14

ADC SLAVE reg CH7 CH8 CH9 CH9 CH10 CH10 CH11 CH11 CH12
ADC SLAVE inj CH15 CH15
6th trigger
2nd trigger 4th trigger (ignored)
ai16063V2

Combined injected simultaneous plus interleaved

This mode is selected by programming bits DUAL[4:0]=00011
It is possible to interrupt an interleaved conversion with a simultaneous injected event.
In this case the interleaved conversion is interrupted immediately and the simultaneous
injected conversion starts. At the end of the injected sequence the interleaved conversion is
resumed. When the interleaved regular conversion resumes, the first regular conversion
which is performed is alway the master’s one. Figure 149, Figure 150 and Figure 151 show
the behavior using an example.
Caution: In this mode, it is mandatory to use the Common Data Register to read the regular data with
a single read access. On the contrary, master-slave data coherency is not guaranteed.

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Figure 149. Interleaved single channel CH0 with injected sequence CH11, CH12

ADC1 (master) CH0 CH0 CH0 Conversions CH0 CH0 CH0

aborted
ADC2 (slave) CH0 CH0 CH0 CH0 CH0 CH0

read read CH11 CH11 read read

CDR CDR CDR CDR
CH12 CH12

Legend:
Injected trigger Resume
(always restart with the master)
Sampling Conversion
MS34461V1

Figure 150. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 1: Master interrupted first

ADC1 (master) CH1 CH1 CH1 Conversions CH1 CH1 CH1

aborted
ADC2 (slave) CH2 CH2 CH2 CH2 CH2 CH2

read read CH11 CH11 read read

CDR CDR CDR CDR
CH12 CH12

Legend:
Injected trigger Resume
(always restart with the master)
Sampling Conversion
MS34462V1

Figure 151. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 2: Slave interrupted first

ADC1 (master) CH1 CH1 CH1 Conversions CH1 CH1 CH1

aborted
ADC2 (slave) CH2 CH2 CH2 CH2 CH2 CH2

read read CH11 CH11 read read

CDR CDR CDR CDR
CH12 CH12

Legend:
Injected trigger Resume
(always restart with the master)
Sampling Conversion
MS34463V2

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DMA requests in dual ADC mode

In all dual ADC modes, it is possible to use two DMA channels (one for the master, one for
the slave) to transfer the data, like in single mode (refer to Figure 152: DMA Requests in
regular simultaneous mode when MDMA=0b00).

Figure 152. DMA Requests in regular simultaneous mode when MDMA=0b00

Trigger Trigger

ADC Master regular CH1 CH1

ADC Master EOC

ADC Slave regular CH2 CH2

ADC Slave EOC

DMA request from ADC Master

DMA reads Master DMA reads Mater

ADC_DR ADC_DR

DMA request from ADC Slave

DMA reads Slave DMA reads Slave

ADC_DR ADC_DR
Configuration where each sequence contains only one conversion
MSv31032V2

In simultaneous regular and interleaved modes, it is also possible to save one DMA channel
and transfer both data using a single DMA channel. For this MDMA bits must be configured
in the ADCx_CCR register:
• MDMA=0b10: A single DMA request is generated each time both master and slave
EOC events have occurred. At that time, two data items are available and the 32-bit
register ADCx_CDR contains the two half-words representing two ADC-converted data
items. The slave ADC data take the upper half-word and the master ADC data take the
lower half-word.
This mode is used in interleaved mode and in regular simultaneous mode when
resolution is 10-bit or 12-bit.
Example:
Interleaved dual mode: a DMA request is generated each time 2 data items are
available:
1st DMA request: ADCx_CDR[31:0] = SLV_ADC_DR[15:0] | MST_ADC_DR[15:0]
2nd DMA request: ADCx_CDR[31:0] = SLV_ADC_DR[15:0] |
MST_ADC_DR[15:0]

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Figure 153. DMA requests in regular simultaneous mode when MDMA=0b10

Trigger Trigger Trigger Trigger

ADC Master regular CH1 CH1 CH1 CH1

ADC Slave EOC

CH2 CH2 CH2 CH2

ADC Slave regular

ADC Slave EOC

DMA request from

ADC Master
DMA request from
ADC Slave

Configuration where each sequence contains only one conversion

MSv31033V2

Figure 154. DMA requests in interleaved mode when MDMA=0b10

Trigger Trigger Trigger Trigger Trigger

CH1 CH1 CH1 CH1 CH1

ADC Master regular

ADC Master EOC Delay Delay Delay Delay Delay

ADC Slave regular

CH2 CH2 CH2 CH2 CH2
ADC Slave EOC

DMA request from

ADC Master
DMA request from
ADC Slave

Configuration where each sequence contains only one conversion

MSv31034V2

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Note: When using MDMA mode, the user must take care to configure properly the duration of the
master and slave conversions so that a DMA request is generated and served for reading
both data (master + slave) before a new conversion is available.
• MDMA=0b11: This mode is similar to the MDMA=0b10. The only differences are that
on each DMA request (two data items are available), two bytes representing two ADC
converted data items are transferred as a half-word.
This mode is used in interleaved and regular simultaneous mode when resolution is 6-
bit or when resolution is 8-bit and data is not signed (offsets must be disabled for all the
involved channels).
Example:
Interleaved dual mode: a DMA request is generated each time 2 data items are
available:
1st DMA request: ADCx_CDR[15:0] = SLV_ADC_DR[7:0] | MST_ADC_DR[7:0]
2nd DMA request: ADCx_CDR[15:0] = SLV_ADC_DR[7:0] | MST_ADC_DR[7:0]

Overrun detection
In dual ADC mode (when DUAL[4:0] is not equal to b00000), if an overrun is detected on
one of the ADCs, the DMA requests are no longer issued to ensure that all the data
transferred to the RAM are valid (this behavior occurs whatever the MDMA configuration). It
may happen that the EOC bit corresponding to one ADC remains set because the data
register of this ADC contains valid data.

DMA one shot mode/ DMA circular mode when MDMA mode is selected
When MDMA mode is selected (0b10 or 0b11), bit DMACFG of the ADCx_CCR register
must also be configured to select between DMA one shot mode and circular mode, as
explained in section Section : Managing conversions using the DMA (bits DMACFG of
master and slave ADC_CFGR are not relevant).

Stopping the conversions in dual ADC modes

The user must set the control bits ADSTP/JADSTP of the master ADC to stop the
conversions of both ADC in dual ADC mode. The other ADSTP control bit of the slave ADC
has no effect in dual ADC mode.
Once both ADC are effectively stopped, the bits ADSTART/JADSTART of the master and
slave ADCs are both cleared by hardware.

21.4.32 Temperature sensor

The temperature sensor can be used to measure the junction temperature (Tj) of the device.
The temperature sensor is internally connected to the ADC input channels which are used
to convert the sensor output voltage to a digital value. When not in use, the sensor can be
put in power down mode. It support the temperature range –40 to 125 °C.
Figure 155 shows the block diagram of connections between the temperature sensor and
the ADC.
The temperature sensor output voltage changes linearly with temperature. The offset of this
line varies from chip to chip due to process variation (up to 45 °C from one chip to another).

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The uncalibrated internal temperature sensor is more suited for applications that detect
temperature variations instead of absolute temperatures. To improve the accuracy of the
temperature sensor measurement, calibration values are stored in system memory for each
device by ST during production.
During the manufacturing process, the calibration data of the temperature sensor and the
internal voltage reference are stored in the system memory area. The user application can
then read them and use them to improve the accuracy of the temperature sensor or the
internal reference (refer to the datasheet for additional information).
The temperature sensor is internally connected to the ADC input channel which is used to
convert the sensor’s output voltage to a digital value. Refer to the electrical characteristics
section of the device datasheet for the sampling time value to be applied when converting
the internal temperature sensor.
When not in use, the sensor can be put in power-down mode.
Figure 155 shows the block diagram of the temperature sensor.

Figure 155. Temperature sensor channel block diagram

CH17SEL control bit

Converted

Address/data bus
data

ADCx

Temperature VTS
sensor ADC input

MSv37243V3

Reading the temperature

To use the sensor:
1. Select the ADC input channels that is connected to VTS.
2. Program with the appropriate sampling time (refer to electrical characteristics section of
the device datasheet).
3. Set the CH17SEL bit in the ADCx_CCR register to wake up the temperature sensor
from power-down mode.
4. Start the ADC conversion.
5. Read the resulting VTS data in the ADC data register.
6. Calculate the actual temperature using the following formula:

TS_CAL2_TEMP – TS_CAL1_TEMP
Temperature ( in °C ) = -------------------------------------------------------------------------------------------------- × ( TS_DATA – TS_CAL1 ) + 30 °C
TS_CAL2 – TS_CAL1

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Where:
• TS_CAL2 is the temperature sensor calibration value acquired at TS_CAL2_TEMP.
• TS_CAL1 is the temperature sensor calibration value acquired at TS_CAL1_TEMP.
• TS_DATA is the actual temperature sensor output value converted by ADC.
Refer to the device datasheet for more information about TS_CAL1 and TS_CAL2
calibration points.
Note: The sensor has a startup time after waking from power-down mode before it can output VTS
at the correct level. The ADC also has a startup time after power-on, so to minimize the
delay, the ADEN and CH17SEL bits should be set at the same time.
The above formula is given for TS_DATA measurement done with the same VREF+voltage
as TS_CAL1/TS_CAL2 values. If VREF+ is different, the formula must be adapted. For
example if VREF+ = 3.3 V and TS_CAL data are acquired at VREF+= 3.0 V, TS_DATA must
be replaced by TS_DATA x (3.3/3.0).

21.4.33 VBAT supply monitoring

The CH18SEL bit in the ADCx_CCR register is used to switch to the battery voltage. As the
VBAT voltage could be higher than VDDA, to ensure the correct operation of the ADC, the
VBAT pin is internally connected to a bridge divider by 3. This bridge is automatically enabled
when CH18SEL is set, to connect VBAT/3 to the ADC input channels. As a consequence, the
converted digital value is one third of the VBAT voltage. To prevent any unwanted
consumption on the battery, it is recommended to enable the bridge divider only when
needed, for ADC conversion.
Refer to the electrical characteristics of the device datasheet for the sampling time value to
be applied when converting the VBAT/3 voltage.
The figure below shows the block diagram of the VBAT sensing feature.

Figure 156. VBAT channel block diagram

VBAT

CH18SEL control bit

Address/data bus

ADCx

VBAT/3
ADC input

MSv37245V1

1. The CH18SEL bit must be set to enable the conversion of internal channel for VBAT/3.

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21.4.34 Monitoring the internal voltage reference

It is possible to monitor the internal voltage reference (VREFINT) to have a reference point for
evaluating the ADC VREF+ voltage level.
The internal voltage reference is internally connected to the input channel 0 of the ADC1
(ADC1_INP0).
Refer to the electrical characteristics section of the product datasheet for the sampling time
value to be applied when converting the internal voltage reference voltage.
Figure 157 shows the block diagram of the VREFINT sensing feature.

Figure 157. VREFINT channel block diagram

VREFEN control bit

ADCx

VREFINT
Internal ADC input
power block

MSv34467V5

1. The VREFEN bit into ADCx_CCR register must be set to enable the conversion of internal channels
(VREFINT).

Calculating the actual VDDA voltage using the internal reference voltage
The power supply voltage applied to the device may be subject to variations or not precisely
known. When VDDA is connected to VREF+, it is possible to compute the actual VDDA voltage
using the embedded internal reference voltage (VREFINT). VREFINT and its calibration data
acquired by the ADC during the manufacturing process at VDDA_Charac can be used to
evaluate the actual VDDA voltage level.
The following formula gives the actual VDDA voltage supplying the device:

V REF+ = V DDA_Charac × VREFINT_CAL ⁄ VREFINT_DATA

Where:
• VREFINT_CAL is the VREFINT calibration value
• VREFINT_DATA is the actual VREFINT output value converted by ADC

Converting a supply-relative ADC measurement to an absolute voltage value

The ADC is designed to deliver a digital value corresponding to the ratio between VREF+ and
the voltage applied on the converted channel.
For most applications VDDA value is unknown and ADC converted values are right-aligned.
In this case, it is necessary to convert this ratio into a voltage independent from VDDA:
V REF+
V CHANNELx = ------------------------------------- × ADC_DATA
FULL_SCALE

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By replacing VREF+ by the formula provided above, the absolute voltage value is given by
the following formula
V DDA_Charac × VREFINT_CAL × ADC_DATA
V CHANNELx = ---------------------------------------------------------------------------------------------------------------------
VREFINT_DATA × FULL_SCALE

For applications where VDDA is known and ADC converted values are right-aligned, the
absolute voltage value can be obtained by using the following formula:
V DDA
V CHANNELx = ------------------------------------- × ADC_DATA
FULL_SCALE

Where:
– VDDA_Charac is the value of VDDA voltage characterized at VREFINT during the
manufacturing process.
– VREFINT_CAL is the VREFINT calibration value
– ADC_DATA is the value measured by the ADC on channel x (right-aligned)
– VREFINT_DATA is the actual VREFINT output value converted by the ADC
– FULL_SCALE is the maximum digital value of the ADC output. For example with
12-bit resolution, it will be 212 - 1 = 4095 or with 8-bit resolution, 28 - 1 = 255.
Note: If ADC measurements are done using an output format other than 16-bit right-aligned, all
the parameters must first be converted to a compatible format before the calculation is
done.

21.5 ADC interrupts

For each ADC, an interrupt can be generated:
• After ADC power-up, when the ADC is ready (flag ADRDY)
• On the end of any conversion for regular groups (flag EOC)
• On the end of a sequence of conversion for regular groups (flag EOS)
• On the end of any conversion for injected groups (flag JEOC)
• On the end of a sequence of conversion for injected groups (flag JEOS)
• When an analog watchdog detection occurs (flag AWD1, AWD2 and AWD3)
• When the end of sampling phase occurs (flag EOSMP)
• When the data overrun occurs (flag OVR)
• When the injected sequence context queue overflows (flag JQOVF)
Separate interrupt enable bits are available for flexibility.

Table 139. ADC interrupts per each ADC

Interrupt event Event flag Enable control bit

ADC ready ADRDY ADRDYIE

End of conversion of a regular group EOC EOCIE
End of sequence of conversions of a regular group EOS EOSIE
End of conversion of a injected group JEOC JEOCIE

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Table 139. ADC interrupts per each ADC (continued)

Interrupt event Event flag Enable control bit

End of sequence of conversions of an injected group JEOS JEOSIE

Analog watchdog 1 status bit is set AWD1 AWD1IE
Analog watchdog 2 status bit is set AWD2 AWD2IE
Analog watchdog 3 status bit is set AWD3 AWD3IE
End of sampling phase EOSMP EOSMPIE
Overrun OVR OVRIE
Injected context queue overflows JQOVF JQOVFIE

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21.6 ADC registers (for each ADC)

Refer to Section 1.2 on page 84 for a list of abbreviations used in register descriptions.

21.6.1 ADC interrupt and status register (ADC_ISR)

Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. JQOVF AWD3 AWD2 AWD1 JEOS JEOC OVR EOS EOC EOSMP ADRDY

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 JQOVF: Injected context queue overflow
This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared
by software writing 1 to it. Refer to Section 21.4.21: Queue of context for injected conversions for
more information.
0: No injected context queue overflow occurred (or the flag event was already acknowledged and
cleared by software)
1: Injected context queue overflow has occurred
Bit 9 AWD3: Analog watchdog 3 flag
This bit is set by hardware when the converted voltage crosses the values programmed in the fields
LT3[7:0] and HT3[7:0] of ADC_TR3 register. It is cleared by software writing 1 to it.
0: No analog watchdog 3 event occurred (or the flag event was already acknowledged and cleared
by software)
1: Analog watchdog 3 event occurred
Bit 8 AWD2: Analog watchdog 2 flag
This bit is set by hardware when the converted voltage crosses the values programmed in the fields
LT2[7:0] and HT2[7:0] of ADC_TR2 register. It is cleared by software writing 1 to it.
0: No analog watchdog 2 event occurred (or the flag event was already acknowledged and cleared
by software)
1: Analog watchdog 2 event occurred
Bit 7 AWD1: Analog watchdog 1 flag
This bit is set by hardware when the converted voltage crosses the values programmed in the fields
LT1[11:0] and HT1[11:0] of ADC_TR1 register. It is cleared by software. writing 1 to it.
0: No analog watchdog 1 event occurred (or the flag event was already acknowledged and cleared
by software)
1: Analog watchdog 1 event occurred
Bit 6 JEOS: Injected channel end of sequence flag
This bit is set by hardware at the end of the conversions of all injected channels in the group. It is
cleared by software writing 1 to it.
0: Injected conversion sequence not complete (or the flag event was already acknowledged and
cleared by software)
1: Injected conversions complete

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Bit 5 JEOC: Injected channel end of conversion flag

This bit is set by hardware at the end of each injected conversion of a channel when a new data is
available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by
reading the corresponding ADC_JDRy register
0: Injected channel conversion not complete (or the flag event was already acknowledged and
cleared by software)
1: Injected channel conversion complete
Bit 4 OVR: ADC overrun
This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new
conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to
it.
0: No overrun occurred (or the flag event was already acknowledged and cleared by software)
1: Overrun has occurred
Bit 3 EOS: End of regular sequence flag
This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is
cleared by software writing 1 to it.
0: Regular Conversions sequence not complete (or the flag event was already acknowledged and
cleared by software)
1: Regular Conversions sequence complete
Bit 2 EOC: End of conversion flag
This bit is set by hardware at the end of each regular conversion of a channel when a new data is
available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR
register
0: Regular channel conversion not complete (or the flag event was already acknowledged and
cleared by software)
1: Regular channel conversion complete
Bit 1 EOSMP: End of sampling flag
This bit is set by hardware during the conversion of any channel (only for regular channels), at the
end of the sampling phase.
0: not at the end of the sampling phase (or the flag event was already acknowledged and cleared by
software)
1: End of sampling phase reached
Bit 0 ADRDY: ADC ready
This bit is set by hardware after the ADC has been enabled (bit ADEN=1) and when the ADC
reaches a state where it is ready to accept conversion requests.
It is cleared by software writing 1 to it.
0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared
by software)
1: ADC is ready to start conversion

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21.6.2 ADC interrupt enable register (ADC_IER)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF EOSMP ADRDY
Res. Res. Res. Res. Res. AWD3IE AWD2IE AWD1IE JEOSIE JEOCIE OVRIE EOSIE EOCIE
IE IE IE
rw rw rw rw rw rw rw rw rw rw rw

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 JQOVFIE: Injected context queue overflow interrupt enable
This bit is set and cleared by software to enable/disable the Injected Context Queue Overflow
interrupt.
0: Injected Context Queue Overflow interrupt disabled
1: Injected Context Queue Overflow interrupt enabled. An interrupt is generated when the JQOVF bit
is set.
Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no
injected conversion is ongoing).
Bit 9 AWD3IE: Analog watchdog 3 interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt.
0: Analog watchdog 3 interrupt disabled
1: Analog watchdog 3 interrupt enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bit 8 AWD2IE: Analog watchdog 2 interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt.
0: Analog watchdog 2 interrupt disabled
1: Analog watchdog 2 interrupt enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bit 7 AWD1IE: Analog watchdog 1 interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog 1 interrupt.
0: Analog watchdog 1 interrupt disabled
1: Analog watchdog 1 interrupt enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bit 6 JEOSIE: End of injected sequence of conversions interrupt enable
This bit is set and cleared by software to enable/disable the end of injected sequence of conversions
interrupt.
0: JEOS interrupt disabled
1: JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set.
Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no
injected conversion is ongoing).

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RM0432 Analog-to-digital converters (ADC)

Bit 5 JEOCIE: End of injected conversion interrupt enable

This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt.
0: JEOC interrupt disabled.
1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.
Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no
injected conversion is ongoing).
Bit 4 OVRIE: Overrun interrupt enable
This bit is set and cleared by software to enable/disable the Overrun interrupt of a regular
conversion.
0: Overrun interrupt disabled
1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
Bit 3 EOSIE: End of regular sequence of conversions interrupt enable
This bit is set and cleared by software to enable/disable the end of regular sequence of conversions
interrupt.
0: EOS interrupt disabled
1: EOS interrupt enabled. An interrupt is generated when the EOS bit is set.
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
Bit 2 EOCIE: End of regular conversion interrupt enable
This bit is set and cleared by software to enable/disable the end of a regular conversion interrupt.
0: EOC interrupt disabled.
1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
Bit 1 EOSMPIE: End of sampling flag interrupt enable for regular conversions
This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt for
regular conversions.
0: EOSMP interrupt disabled.
1: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
Bit 0 ADRDYIE: ADC ready interrupt enable
This bit is set and cleared by software to enable/disable the ADC Ready interrupt.
0: ADRDY interrupt disabled
1: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).

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21.6.3 ADC control register (ADC_CR)

Address offset: 0x08
Reset value: 0x2000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCA ADCA DEEP ADVREG
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
L LDIF PWD EN
rs rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JADST JADST ADSTA
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ADSTP ADDIS ADEN
P ART RT
rs rs rs rs rs rs

Bit 31 ADCAL: ADC calibration

This bit is set by software to start the calibration of the ADC. Program first the bit ADCALDIF
to determine if this calibration applies for single-ended or differential inputs mode.
It is cleared by hardware after calibration is complete.
0: Calibration complete
1: Write 1 to calibrate the ADC. Read at 1 means that a calibration in progress.
Note: The software is allowed to launch a calibration by setting ADCAL only when ADEN=0.
The software is allowed to update the calibration factor by writing ADC_CALFACT only
when ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is
ongoing)
Bit 30 ADCALDIF: Differential mode for calibration
This bit is set and cleared by software to configure the single-ended or differential inputs
mode for the calibration.
0: Writing ADCAL will launch a calibration in single-ended inputs mode.
1: Writing ADCAL will launch a calibration in differential inputs mode.
Note: The software is allowed to write this bit only when the ADC is disabled and is not
calibrating (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0
and ADEN=0).
Bit 29 DEEPPWD: Deep-power-down enable
This bit is set and cleared by software to put the ADC in Deep-power-down mode.
0: ADC not in Deep-power down
1: ADC in Deep-power-down (default reset state)
Note: The software is allowed to write this bit only when the ADC is disabled (ADCAL=0,
JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bit 28 ADVREGEN: ADC voltage regulator enable
This bits is set by software to enable the ADC voltage regulator.
Before performing any operation such as launching a calibration or enabling the ADC, the
ADC voltage regulator must first be enabled and the software must wait for the regulator
start-up time.
0: ADC Voltage regulator disabled
1: ADC Voltage regulator enabled.
For more details about the ADC voltage regulator enable and disable sequences, refer to
Section 21.4.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator
(ADVREGEN).
The software can program this bit field only when the ADC is disabled (ADCAL=0,
JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

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Bits 27:6 Reserved, must be kept at reset value.

Bit 5 JADSTP: ADC stop of injected conversion command
This bit is set by software to stop and discard an ongoing injected conversion (JADSTP
Command).
It is cleared by hardware when the conversion is effectively discarded and the ADC injected
sequence and triggers can be re-configured. The ADC is then ready to accept a new start of
injected conversions (JADSTART command).
0: No ADC stop injected conversion command ongoing
1: Write 1 to stop injected conversions ongoing. Read 1 means that an ADSTP command is
in progress.
Note: The software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 (ADC is
enabled and eventually converting an injected conversion and there is no pending
request to disable the ADC)
In Auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected
conversions (do not use JADSTP)
Bit 4 ADSTP: ADC stop of regular conversion command
This bit is set by software to stop and discard an ongoing regular conversion (ADSTP
Command).
It is cleared by hardware when the conversion is effectively discarded and the ADC regular
sequence and triggers can be re-configured. The ADC is then ready to accept a new start of
regular conversions (ADSTART command).
0: No ADC stop regular conversion command ongoing
1: Write 1 to stop regular conversions ongoing. Read 1 means that an ADSTP command is in
progress.
Note: The software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 (ADC is
enabled and eventually converting a regular conversion and there is no pending request
to disable the ADC).
In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected
conversions (do not use JADSTP).
Bit 3 JADSTART: ADC start of injected conversion
This bit is set by software to start ADC conversion of injected channels. Depending on the
configuration bits JEXTEN[1:0], a conversion will start immediately (software trigger
configuration) or once an injected hardware trigger event occurs (hardware trigger
configuration).
It is cleared by hardware:
– in single conversion mode when software trigger is selected (JEXTSEL=0x0): at the
assertion of the End of Injected Conversion Sequence (JEOS) flag.
– in all cases: after the execution of the JADSTP command, at the same time that JADSTP is
cleared by hardware.
0: No ADC injected conversion is ongoing.
1: Write 1 to start injected conversions. Read 1 means that the ADC is operating and
eventually converting an injected channel.
Note: The software is allowed to set JADSTART only when ADEN=1 and ADDIS=0 (ADC is
enabled and there is no pending request to disable the ADC).
In auto-injection mode (JAUTO=1), regular and auto-injected conversions are started by
setting bit ADSTART (JADSTART must be kept cleared)

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Bit 2 ADSTART: ADC start of regular conversion

This bit is set by software to start ADC conversion of regular channels. Depending on the
configuration bits EXTEN[1:0], a conversion will start immediately (software trigger
configuration) or once a regular hardware trigger event occurs (hardware trigger
configuration).
It is cleared by hardware:
– in single conversion mode when software trigger is selected (EXTSEL=0x0): at the assertion
of the End of Regular Conversion Sequence (EOS) flag.
– in all cases: after the execution of the ADSTP command, at the same time that ADSTP is
cleared by hardware.
0: No ADC regular conversion is ongoing.
1: Write 1 to start regular conversions. Read 1 means that the ADC is operating and
eventually converting a regular channel.
Note: The software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is
enabled and there is no pending request to disable the ADC)
In auto-injection mode (JAUTO=1), regular and auto-injected conversions are started by
setting bit ADSTART (JADSTART must be kept cleared)
Bit 1 ADDIS: ADC disable command
This bit is set by software to disable the ADC (ADDIS command) and put it into power-down
state (OFF state).
It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by
hardware at this time).
0: no ADDIS command ongoing
1: Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.
Note: The software is allowed to set ADDIS only when ADEN=1 and both ADSTART=0 and
JADSTART=0 (which ensures that no conversion is ongoing)
Bit 0 ADEN: ADC enable control
This bit is set by software to enable the ADC. The ADC will be effectively ready to operate
once the flag ADRDY has been set.
It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS
command.
0: ADC is disabled (OFF state)
1: Write 1 to enable the ADC.
Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0
(ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0) except for
bit ADVREGEN which must be 1 (and the software must have wait for the startup time of
the voltage regulator)

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RM0432 Analog-to-digital converters (ADC)

21.6.4 ADC configuration register (ADC_CFGR)

Address offset: 0x0C
Reset value: 0x8000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JAWD1 AWD1 AWD1S JDISC DISC
JQDIS AWD1CH[4:0] JAUTO JQM DISCNUM[2:0]
EN EN GL EN EN
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUT OVR EXTSE EXTSE EXTSE EXTSE DFSD DMA DMA
Res. CONT EXTEN[1:0] ALIGN RES[1:0]
DLY MOD L3 L2 L1 L0 MCFG CFG EN
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 JQDIS: Injected Queue disable

These bits are set and cleared by software to disable the Injected Queue mechanism :
0: Injected Queue enabled
1: Injected Queue disabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no regular nor injected conversion is ongoing).
A set or reset of JQDIS bit causes the injected queue to be flushed and the JSQR register is
cleared.
Bits 30:26 AWD1CH[4:0]: Analog watchdog 1 channel selection
These bits are set and cleared by software. They select the input channel to be guarded by the
analog watchdog.
00000: ADC analog input channel 0 monitored by AWD1 (available on ADC1 only)
00001: ADC analog input channel 1 monitored by AWD1
.....
10010: ADC analog input channel 18 monitored by AWD1
others: reserved, must not be used
Note: Some channels are not connected physically. Keep the corresponding AWD1CH[4:0] setting to
the reset value.
The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers.
The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bit 25 JAUTO: Automatic injected group conversion
This bit is set and cleared by software to enable/disable automatic injected group conversion after
regular group conversion.
0: Automatic injected group conversion disabled
1: Automatic injected group conversion enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no regular nor injected conversion is ongoing).
When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit
JAUTO of the slave ADC is no more writable and its content is equal to the bit JAUTO of the
master ADC.

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Bit 24 JAWD1EN: Analog watchdog 1 enable on injected channels

This bit is set and cleared by software
0: Analog watchdog 1 disabled on injected channels
1: Analog watchdog 1 enabled on injected channels
Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no
injected conversion is ongoing).
Bit 23 AWD1EN: Analog watchdog 1 enable on regular channels
This bit is set and cleared by software
0: Analog watchdog 1 disabled on regular channels
1: Analog watchdog 1 enabled on regular channels
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
Bit 22 AWD1SGL: Enable the watchdog 1 on a single channel or on all channels
This bit is set and cleared by software to enable the analog watchdog on the channel identified by
the AWD1CH[4:0] bits or on all the channels
0: Analog watchdog 1 enabled on all channels
1: Analog watchdog 1 enabled on a single channel
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bit 21 JQM: JSQR queue mode
This bit is set and cleared by software.
It defines how an empty Queue is managed.
0: JSQR mode 0: The Queue is never empty and maintains the last written configuration into JSQR.
1: JSQR mode 1: The Queue can be empty and when this occurs, the software and hardware
triggers of the injected sequence are both internally disabled just after the completion of the last valid
injected sequence.
Refer to Section 21.4.21: Queue of context for injected conversions for more information.
Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no
injected conversion is ongoing).
When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit
JQM of the slave ADC is no more writable and its content is equal to the bit JQM of the master
ADC.
Bit 20 JDISCEN: Discontinuous mode on injected channels
This bit is set and cleared by software to enable/disable discontinuous mode on the injected
channels of a group.
0: Discontinuous mode on injected channels disabled
1: Discontinuous mode on injected channels enabled
Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no
injected conversion is ongoing).
It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the
bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set.
When dual mode is enabled (bits DUAL of ADCx_CCR register are not equal to zero), the bit
JDISCEN of the slave ADC is no more writable and its content is equal to the bit JDISCEN of
the master ADC.

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RM0432 Analog-to-digital converters (ADC)

Bits 19:17 DISCNUM[2:0]: Discontinuous mode channel count

These bits are written by software to define the number of regular channels to be converted in
discontinuous mode, after receiving an external trigger.
000: 1 channel
001: 2 channels
...
111: 8 channels
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no
regular conversion is ongoing).
When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bits
DISCNUM[2:0] of the slave ADC are no more writable and their content is equal to the bits
DISCNUM[2:0] of the master ADC.
Bit 16 DISCEN: Discontinuous mode for regular channels
This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels.
0: Discontinuous mode for regular channels disabled
1: Discontinuous mode for regular channels enabled
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden
to set both DISCEN=1 and CONT=1.
It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the
bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set.
The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit
DISCEN of the slave ADC is no more writable and its content is equal to the bit DISCEN of the
master ADC.
Bit 15 Reserved, must be kept at reset value.
Bit 14 AUTDLY: Delayed conversion mode
This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode.
0: Auto-delayed conversion mode off
1: Auto-delayed conversion mode on
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit
AUTDLY of the slave ADC is no more writable and its content is equal to the bit AUTDLY of the
master ADC.
Bit 13 CONT: Single / continuous conversion mode for regular conversions
This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it
is cleared.
0: Single conversion mode
1: Continuous conversion mode
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden
to set both DISCEN=1 and CONT=1.
The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit
CONT of the slave ADC is no more writable and its content is equal to the bit CONT of the
master ADC.

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Bit 12 OVRMOD: Overrun mode

This bit is set and cleared by software and configure the way data overrun is managed.
0: ADC_DR register is preserved with the old data when an overrun is detected.
1: ADC_DR register is overwritten with the last conversion result when an overrun is detected.
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
Bits 11:10 EXTEN[1:0]: External trigger enable and polarity selection for regular channels
These bits are set and cleared by software to select the external trigger polarity and enable the
trigger of a regular group.
00: Hardware trigger detection disabled (conversions can be launched by software)
01: Hardware trigger detection on the rising edge
10: Hardware trigger detection on the falling edge
11: Hardware trigger detection on both the rising and falling edges
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no
regular conversion is ongoing).
Bits 9:6 EXTSEL[3:0]: External trigger selection for regular group
These bits select the external event used to trigger the start of conversion of a regular group:
0000: Event 0
0001: Event 1
0010: Event 2
0011: Event 3
0100: Event 4
0101: Event 5
0110: Event 6
0111: Event 7
...
1111: Event 15
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no
regular conversion is ongoing).
Bit 5 ALIGN: Data alignment
This bit is set and cleared by software to select right or left alignment. Refer to Section : Data
register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN)
0: Right alignment
1: Left alignment
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bits 4:3 RES[1:0]: Data resolution
These bits are written by software to select the resolution of the conversion.
00: 12-bit
01: 10-bit
10: 8-bit
11: 6-bit
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).

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RM0432 Analog-to-digital converters (ADC)

Bit 2 DFSDMCFG: DFSDM mode configuration

This bit is set and cleared by software to enable the DFSDM mode. It is effective only when
DMAEN=0.
0: DFSDM mode disabled
1: DFSDM mode enabled
Note: To make sure no conversion is ongoing, the software is allowed to write this bit only when
ADSTART= 0 and JADSTART= 0.
Bit 1 DMACFG: Direct memory access configuration
This bit is set and cleared by software to select between two DMA modes of operation and is
effective only when DMAEN=1.
0: DMA One Shot mode selected
1: DMA Circular mode selected
For more details, refer to Section : Managing conversions using the DMA
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
In dual-ADC modes, this bit is not relevant and replaced by control bit DMACFG of the
ADCx_CCR register.
Bit 0 DMAEN: Direct memory access enable
This bit is set and cleared by software to enable the generation of DMA requests. This allows to use
the DMA to manage automatically the converted data. For more details, refer to Section : Managing
conversions using the DMA.
0: DMA disabled
1: DMA enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
In dual-ADC modes, this bit is not relevant and replaced by control bits MDMA[1:0] of the
ADCx_CCR register.

21.6.5 ADC configuration register 2 (ADC_CFGR2)

Address offset: 0x10
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROV
Res. Res. Res. Res. Res. TROVS OVSS[3:0] OVSR[2:0] JOVSE ROVSE
SM
rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:17 Reserved, must be kept at reset value.
Bits 16:11 Reserved, must be kept at reset value.

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Bit 10 ROVSM: Regular Oversampling mode

This bit is set and cleared by software to select the regular oversampling mode.
0: Continued mode: When injected conversions are triggered, the oversampling is temporary
stopped and continued after the injection sequence (oversampling buffer is maintained during
injected sequence)
1: Resumed mode: When injected conversions are triggered, the current oversampling is aborted
and resumed from start after the injection sequence (oversampling buffer is zeroed by injected
sequence start)
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bit 9 TROVS: Triggered Regular Oversampling
This bit is set and cleared by software to enable triggered oversampling
0: All oversampled conversions for a channel are done consecutively following a trigger
1: Each oversampled conversion for a channel needs a new trigger
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bits 8:5 OVSS[3:0]: Oversampling shift
This bitfield is set and cleared by software to define the right shifting applied to the raw oversampling
result.
0000: No shift
0001: Shift 1-bit
0010: Shift 2-bits
0011: Shift 3-bits
0100: Shift 4-bits
0101: Shift 5-bits
0110: Shift 6-bits
0111: Shift 7-bits
1000: Shift 8-bits
Other codes reserved
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).

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RM0432 Analog-to-digital converters (ADC)

Bits 4:2 OVSR[2:0]: Oversampling ratio

This bitfield is set and cleared by software to define the oversampling ratio.
000: 2x
001: 4x
010: 8x
011: 16x
100: 32x
101: 64x
110: 128x
111: 256x
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bit 1 JOVSE: Injected Oversampling Enable
This bit is set and cleared by software to enable injected oversampling.
0: Injected Oversampling disabled
1: Injected Oversampling enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing)
Bit 0 ROVSE: Regular Oversampling Enable
This bit is set and cleared by software to enable regular oversampling.
0: Regular Oversampling disabled
1: Regular Oversampling enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing)

21.6.6 ADC sample time register 1 (ADC_SMPR1)

Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMPPL
Res. SMP9[2:0] SMP8[2:0] SMP7[2:0] SMP6[2:0] SMP5[2:1]
US
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP5[
SMP4[2:0] SMP3[2:0] SMP2[2:0] SMP1[2:0] SMP0[2:0]
0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bit 31 SMPPLUS: Addition of one clock cycle to the sampling time.

1: 2.5 ADC clock cycle sampling time becomes 3.5 ADC clock cycles for the ADC_SMPR1
and ADC_SMPR2 registers.
0: The sampling time remains set to 2.5 ADC clock cycles remains
To make sure no conversion is ongoing, the software is allowed to write this bit only when
ADSTART= 0 and JADSTART= 0.
Bit 30 Reserved, must be kept at reset value.
Bits 29:0 SMP[9:0][2:0]: Channel x sampling time selection
These bits are written by software to select the sampling time individually for each channel.
During sample cycles, the channel selection bits must remain unchanged.
000: 2.5 ADC clock cycles
001: 6.5 ADC clock cycles
010: 12.5 ADC clock cycles
011: 24.5 ADC clock cycles
100: 47.5 ADC clock cycles
101: 92.5 ADC clock cycles
110: 247.5 ADC clock cycles
111: 640.5 ADC clock cycles
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0
(which ensures that no conversion is ongoing).
Some channels are not connected physically. Keep the corresponding SMPx[2:0]
setting to the reset value.

21.6.7 ADC sample time register 2 (ADC_SMPR2)

Address offset: 0x18
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. SMP18[2:0] SMP17[2:0] SMP16[2:0] SMP15[2:1]
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP15[0] SMP14[2:0] SMP13[2:0] SMP12[2:0] SMP11[2:0] SMP10[2:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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RM0432 Analog-to-digital converters (ADC)

Bits 31:27 Reserved, must be kept at reset value.

Bits 26:0 SMP[18:10][2:0]: Channel x sampling time selection
These bits are written by software to select the sampling time individually for each channel.
During sampling cycles, the channel selection bits must remain unchanged.
000: 2.5 ADC clock cycles
001: 6.5 ADC clock cycles
010: 12.5 ADC clock cycles
011: 24.5 ADC clock cycles
100: 47.5 ADC clock cycles
101: 92.5 ADC clock cycles
110: 247.5 ADC clock cycles
111: 640.5 ADC clock cycles
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0
(which ensures that no conversion is ongoing).
Some channels are not connected physically. Keep the corresponding SMPx[2:0]
setting to the reset value.

21.6.8 ADC watchdog threshold register 1 (ADC_TR1)

Address offset: 0x20
Reset value: 0x0FFF 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. HT1[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. LT1[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 HT1[11:0]: Analog watchdog 1 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog 1.
Refer to Section 21.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 LT1[11:0]: Analog watchdog 1 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog 1.
Refer to Section 21.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).

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21.6.9 ADC watchdog threshold register 2 (ADC_TR2)

Address offset: 0x24
Reset value: 0x00FF 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. HT2[7:0]

rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. LT2[7:0]

rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 HT2[7:0]: Analog watchdog 2 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog 2.
Refer to Section 21.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 LT2[7:0]: Analog watchdog 2 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog 2.
Refer to Section 21.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).

21.6.10 ADC watchdog threshold register 3 (ADC_TR3)

Address offset: 0x28
Reset value: 0x00FF 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. HT3[7:0]

rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. LT3[7:0]

rw rw rw rw rw rw rw rw

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RM0432 Analog-to-digital converters (ADC)

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 HT3[7:0]: Analog watchdog 3 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog 3.
Refer to Section 21.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 LT3[7:0]: Analog watchdog 3 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog 3.
This watchdog compares the 8-bit of LT3 with the 8 MSB of the converted data.
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).

21.6.11 ADC regular sequence register 1 (ADC_SQR1)

Address offset: 0x30
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. SQ4[4:0] Res. SQ3[4:0] Res. SQ2[4]
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ2[3:0] Res. SQ1[4:0] Res. Res. L[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:24 SQ4[4:0]: 4th conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 4th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 23 Reserved, must be kept at reset value.
Bits 22:18 SQ3[4:0]: 3rd conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 3rd in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 17 Reserved, must be kept at reset value.
Bits 16:12 SQ2[4:0]: 2nd conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 2nd in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 11 Reserved, must be kept at reset value.

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Bits 10:6 SQ1[4:0]: 1st conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 1st in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bits 5:4 Reserved, must be kept at reset value.
Bits 3:0 L[3:0]: Regular channel sequence length
These bits are written by software to define the total number of conversions in the regular
channel conversion sequence.
0000: 1 conversion
0001: 2 conversions
...
1111: 16 conversions
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).

Note: Some channels are not connected physically and must not be selected for conversion.

21.6.12 ADC regular sequence register 2 (ADC_SQR2)

Address offset: 0x34
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. SQ9[4:0] Res. SQ8[4:0] Res. SQ7[4]
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ7[3:0] Res. SQ6[4:0] Res. SQ5[4:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:24 SQ9[4:0]: 9th conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 9th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 23 Reserved, must be kept at reset value.
Bits 22:18 SQ8[4:0]: 8th conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 8th in
the regular conversion sequence
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 17 Reserved, must be kept at reset value.
Bits 16:12 SQ7[4:0]: 7th conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 7th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).

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RM0432 Analog-to-digital converters (ADC)

Bit 11 Reserved, must be kept at reset value.

Bits 10:6 SQ6[4:0]: 6th conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 6th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 5 Reserved, must be kept at reset value.
Bits 4:0 SQ5[4:0]: 5th conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 5th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).

Note: Some channels are not connected physically and must not be selected for conversion.

21.6.13 ADC regular sequence register 3 (ADC_SQR3)

Address offset: 0x38
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. SQ14[4:0] Res. SQ13[4:0] Res. SQ12[4]
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ12[3:0] Res. SQ11[4:0] Res. SQ10[4:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:24 SQ14[4:0]: 14th conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 14th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 23 Reserved, must be kept at reset value.
Bits 22:18 SQ13[4:0]: 13th conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 13th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 17 Reserved, must be kept at reset value.
Bits 16:12 SQ12[4:0]: 12th conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 12th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 11 Reserved, must be kept at reset value.

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Bits 10:6 SQ11[4:0]: 11th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 11th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 5 Reserved, must be kept at reset value.
Bits 4:0 SQ10[4:0]: 10th conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 10th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).

Note: Some channels are not connected physically and must not be selected for conversion.

21.6.14 ADC regular sequence register 4 (ADC_SQR4)

Address offset: 0x3C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. SQ16[4:0] Res. SQ15[4:0]
rw rw rw rw rw rw rw rw rw rw

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:6 SQ16[4:0]: 16th conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 16th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 5 Reserved, must be kept at reset value.
Bits 4:0 SQ15[4:0]: 15th conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 15th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).

Note: Some channels are not connected physically and must not be selected for conversion.

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RM0432 Analog-to-digital converters (ADC)

21.6.15 ADC regular data register (ADC_DR)

Address offset: 0x40
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RDATA[15:0]

r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 RDATA[15:0]: Regular data converted
These bits are read-only. They contain the conversion result from the last converted regular channel.
The data are left- or right-aligned as described in Section 21.4.26: Data management.

21.6.16 ADC injected sequence register (ADC_JSQR)

Address offset: 0x4C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. JSQ4[4:0] Res. JSQ3[4:0] Res. JSQ2[4:2]
rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ2[1:0] Res. JSQ1[4:0] JEXTEN[1:0] JEXTSEL[3:0] JL[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:26 JSQ4[4:0]: 4th conversion in the injected sequence
These bits are written by software with the channel number (0 to 18) assigned as the 4th in
the injected conversion sequence.
Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that
no injected conversion is ongoing).
Bit 25 Reserved, must be kept at reset value.
Bits 24:20 JSQ3[4:0]: 3rd conversion in the injected sequence
These bits are written by software with the channel number (0 to 18) assigned as the 3rd in
the injected conversion sequence.
Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that
no injected conversion is ongoing).
Bit 19 Reserved, must be kept at reset value.

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Bits 18:14 JSQ2[4:0]: 2nd conversion in the injected sequence

These bits are written by software with the channel number (0 to 18) assigned as the 2nd in
the injected conversion sequence.
Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that
no injected conversion is ongoing).
Bit 13 Reserved, must be kept at reset value.
Bits 12:8 JSQ1[4:0]: 1st conversion in the injected sequence
These bits are written by software with the channel number (0 to 18) assigned as the 1st in
the injected conversion sequence.
Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that
no injected conversion is ongoing).
Bits 7:6 JEXTEN[1:0]: External Trigger Enable and Polarity Selection for injected channels
These bits are set and cleared by software to select the external trigger polarity and enable
the trigger of an injected group.
00: If JQDIS=0 (queue enabled), Hardware and software trigger detection disabled
00: If JQDIS=1 (queue disabled), Hardware trigger detection disabled (conversions can be
launched by software)
01: Hardware trigger detection on the rising edge
10: Hardware trigger detection on the falling edge
11: Hardware trigger detection on both the rising and falling edges
Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that
no injected conversion is ongoing).
If JQM=1 and if the Queue of Context becomes empty, the software and hardware
triggers of the injected sequence are both internally disabled (refer to Section 21.4.21:
Queue of context for injected conversions)
Bits 5:2 JEXTSEL[3:0]: External Trigger Selection for injected group
These bits select the external event used to trigger the start of conversion of an injected
group:
0000: Event 0
0001: Event 1
0010: Event 2
0011: Event 3
0100: Event 4
0101: Event 5
0110: Event 6
0111: Event 7
...
1111: Event 15
Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that
no injected conversion is ongoing).
Bits 1:0 JL[1:0]: Injected channel sequence length
These bits are written by software to define the total number of conversions in the injected
channel conversion sequence.
00: 1 conversion
01: 2 conversions
10: 3 conversions
11: 4 conversions
Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that
no injected conversion is ongoing).

Note: Some channels are not connected physically and must not be selected for conversion.

712/2301 RM0432 Rev 6

RM0432 Analog-to-digital converters (ADC)

21.6.17 ADC offset y register (ADC_OFRy)

Address offset: 0x60 + 0x04 * (y -1), (y= 1 to 4)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSETy
OFFSETy_CH[4:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
_EN
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. OFFSETy[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 OFFSETy_EN: Offset y enable

This bit is written by software to enable or disable the offset programmed into bits
OFFSETy[11:0].
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0
(which ensures that no conversion is ongoing).
Bits 30:26 OFFSETy_CH[4:0]: Channel selection for the data offset y
These bits are written by software to define the channel to which the offset programmed into
bits OFFSETy[11:0] will apply.
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0
(which ensures that no conversion is ongoing).
Some channels are not connected physically and must not be selected for the data
offset y.
Bits 25:12 Reserved, must be kept at reset value.
Bits 11:0 OFFSETy[11:0]: Data offset y for the channel programmed into bits OFFSETy_CH[4:0]
These bits are written by software to define the offset y to be subtracted from the raw
converted data when converting a channel (can be regular or injected). The channel to which
applies the data offset y must be programmed in the bits OFFSETy_CH[4:0]. The conversion
result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi
registers (injected conversion).
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0
(which ensures that no conversion is ongoing).
If several offset (OFFSETy) point to the same channel, only the offset with the lowest x
value is considered for the subtraction.
Ex: if OFFSET1_CH[4:0]=4 and OFFSET2_CH[4:0]=4, this is OFFSET1[11:0] which is
subtracted when converting channel 4.

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21.6.18 ADC injected channel y data register (ADC_JDRy)

Address offset: 0x80 + 0x04 * (y - 1), (y = 1 to 4)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA[15:0]
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 JDATA[15:0]: Injected data
These bits are read-only. They contain the conversion result from injected channel y. The
data are left -or right-aligned as described in Section 21.4.26: Data management.

21.6.19 ADC Analog Watchdog 2 Configuration Register (ADC_AWD2CR)

Address offset: 0xA0
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AWD2CH[18:16]

rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AWD2CH[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:0 AWD2CH[18:0]: Analog watchdog 2 channel selection
These bits are set and cleared by software. They enable and select the input channels to be guarded
by the analog watchdog 2.
AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2
AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2
When AWD2CH[18:0] = 000..0, the analog Watchdog 2 is disabled
Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers.
The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Some channels are not connected physically and must not be selected for the analog
watchdog.

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RM0432 Analog-to-digital converters (ADC)

21.6.20 ADC Analog Watchdog 3 Configuration Register (ADC_AWD3CR)

Address offset: 0xA4
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AWD3CH[18:16]

rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AWD3CH[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:0 AWD3CH[18:0]: Analog watchdog 3 channel selection
These bits are set and cleared by software. They enable and select the input channels to be guarded
by the analog watchdog 3.
AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3
AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3
When AWD3CH[18:0] = 000..0, the analog Watchdog 3 is disabled
Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers.
The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Some channels are not connected physically and must not be selected for the analog
watchdog.

21.6.21 ADC Differential mode Selection Register (ADC_DIFSEL)

Address offset: 0xB0
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DIFSEL[18:16]

rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DIFSEL[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw r

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:0 DIFSEL[18:0]: Differential mode for channels 18 to 0.
These bits are set and cleared by software. They allow to select if a channel is configured as single-
ended or differential mode.
DIFSEL[i] = 0: ADC analog input channel is configured in single ended mode
DIFSEL[i] = 1: ADC analog input channel i is configured in differential mode
Note: The DIFSEL bits corresponding to channels that are either connected to a single-ended I/O port
or to an internal channel must be kept their reset value (single-ended input mode).
The software is allowed to write these bits only when the ADC is disabled (ADCAL=0,
JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

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21.6.22 ADC Calibration Factors (ADC_CALFACT)

Address offset: 0xB4
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. CALFACT_D[6:0]

rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. CALFACT_S[6:0]

rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:16 CALFACT_D[6:0]: Calibration Factors in differential mode
These bits are written by hardware or by software.
Once a differential inputs calibration is complete, they are updated by hardware with the calibration
factors.
Software can write these bits with a new calibration factor. If the new calibration factor is different
from the current one stored into the analog ADC, it will then be applied once a new differential
calibration is launched.
Note: The software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0
(ADC is enabled and no calibration is ongoing and no conversion is ongoing).
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 CALFACT_S[6:0]: Calibration Factors In single-ended mode
These bits are written by hardware or by software.
Once a single-ended inputs calibration is complete, they are updated by hardware with the
calibration factors.
Software can write these bits with a new calibration factor. If the new calibration factor is different
from the current one stored into the analog ADC, it will then be applied once a new single-ended
calibration is launched.
Note: The software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0
(ADC is enabled and no calibration is ongoing and no conversion is ongoing).

21.7 ADC common registers

These registers define the control and status registers common to master and slave ADCs:

21.7.1 ADC common status register (ADC_CSR)

Address offset: 0x00 (this offset address is relative to the master ADC base address +
0x300)
Reset value: 0x0000 0000
This register provides an image of the status bits of the different ADCs. Nevertheless it is
read-only and does not allow to clear the different status bits. Instead each status bit must
be cleared by writing 0 to it in the corresponding ADC_ISR register.

716/2301 RM0432 Rev 6

RM0432 Analog-to-digital converters (ADC)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JQOVF_ AWD3_ AWD2_ AWD1_ JEOS_ JEOC_ OVR_ EOS_ EOC_ EOSMP_ ADRDY_
Res. Res. Res. Res. Res.
SLV SLV SLV SLV SLV SLV SLV SLV SLV SLV SLV
r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF_ AWD3_ AWD2_ AWD1_ JEOS_ JEOC_ OVR_ EOS_ EOC_ EOSMP_ ADRDY_
Res. Res. Res. Res. Res.
MST MST MST MST MST MST MST MST MST MST MST
r r r r r r r r r r r

Bits 31:27 Reserved, must be kept at reset value.

Bit 26 JQOVF_SLV: Injected Context Queue Overflow flag of the slave ADC
This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register.
Bit 25 AWD3_SLV: Analog watchdog 3 flag of the slave ADC
This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register.
Bit 24 AWD2_SLV: Analog watchdog 2 flag of the slave ADC
This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register.
Bit 23 AWD1_SLV: Analog watchdog 1 flag of the slave ADC
This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register.
Bit 22 JEOS_SLV: End of injected sequence flag of the slave ADC
This bit is a copy of the JEOS bit in the corresponding ADC_ISR register.
Bit 21 JEOC_SLV: End of injected conversion flag of the slave ADC
This bit is a copy of the JEOC bit in the corresponding ADC_ISR register.
Bit 20 OVR_SLV: Overrun flag of the slave ADC
This bit is a copy of the OVR bit in the corresponding ADC_ISR register.
Bit 19 EOS_SLV: End of regular sequence flag of the slave ADC. This bit is a copy of the EOS bit in
the corresponding ADC_ISR register.
Bit 18 EOC_SLV: End of regular conversion of the slave ADC
This bit is a copy of the EOC bit in the corresponding ADC_ISR register.
Bit 17 EOSMP_SLV: End of Sampling phase flag of the slave ADC
This bit is a copy of the EOSMP2 bit in the corresponding ADC_ISR register.
Bit 16 ADRDY_SLV: Slave ADC ready
This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register.
Bits 15:11 Reserved, must be kept at reset value.
Bit 10 JQOVF_MST: Injected Context Queue Overflow flag of the master ADC
This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register.
Bit 9 AWD3_MST: Analog watchdog 3 flag of the master ADC
This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register.
Bit 8 AWD2_MST: Analog watchdog 2 flag of the master ADC
This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register.
Bit 7 AWD1_MST: Analog watchdog 1 flag of the master ADC
This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register.
Bit 6 JEOS_MST: End of injected sequence flag of the master ADC
This bit is a copy of the JEOS bit in the corresponding ADC_ISR register.

RM0432 Rev 6 717/2301

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Analog-to-digital converters (ADC) RM0432

Bit 5 JEOC_MST: End of injected conversion flag of the master ADC

This bit is a copy of the JEOC bit in the corresponding ADC_ISR register.
Bit 4 OVR_MST: Overrun flag of the master ADC
This bit is a copy of the OVR bit in the corresponding ADC_ISR register.
Bit 3 EOS_MST: End of regular sequence flag of the master ADC
This bit is a copy of the EOS bit in the corresponding ADC_ISR register.
Bit 2 EOC_MST: End of regular conversion of the master ADC
This bit is a copy of the EOC bit in the corresponding ADC_ISR register.
Bit 1 EOSMP_MST: End of Sampling phase flag of the master ADC
This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register.
Bit 0 ADRDY_MST: Master ADC ready
This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register.

21.7.2 ADC common control register (ADC_CCR)

Address offset: 0x08 (this offset address is relative to the master ADC base address +
0x300)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH18S VREF
Res. Res. Res. Res. Res. Res. Res. CH17SEL PRESC[3:0] CKMODE[1:0]
EL EN
rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA
MDMA[1:0] Res. DELAY[3:0] Res. Res. Res. DUAL[4:0]
CFG
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 CH18SEL: CH18 selection
This bit is set and cleared by software to control channel 18.
0: VBAT channel disabled.
1: VBAT channel enabled
Bit 23 CH17SEL: CH17 selection
This bit is set and cleared by software to control channel 17.
0: Temperature sensor channel disabled
1: Temperature sensor channel enabled
Bit 22 VREFEN: VREFINT enable
This bit is set and cleared by software to enable/disable the VREFINT channel.
0: VREFINT channel disabled
1: VREFINT channel enabled

718/2301 RM0432 Rev 6

RM0432 Analog-to-digital converters (ADC)

Bits 21:18 PRESC[3:0]: ADC prescaler

These bits are set and cleared by software to select the frequency of the clock to the ADC.
The clock is common for all the ADCs.
0000: input ADC clock not divided
0001: input ADC clock divided by 2
0010: input ADC clock divided by 4
0011: input ADC clock divided by 6
0100: input ADC clock divided by 8
0101: input ADC clock divided by 10
0110: input ADC clock divided by 12
0111: input ADC clock divided by 16
1000: input ADC clock divided by 32
1001: input ADC clock divided by 64
1010: input ADC clock divided by 128
1011: input ADC clock divided by 256
other: reserved
Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL=0,
JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). The ADC prescaler
value is applied only when CKMODE[1:0] = 0b00.
Bits 17:16 CKMODE[1:0]: ADC clock mode
These bits are set and cleared by software to define the ADC clock scheme (which is
common to both master and slave ADCs):
00: CK_ADCx (x=123) (Asynchronous clock mode), generated at product level (refer to
Section 6: Reset and clock control (RCC))
01: HCLK/1 (Synchronous clock mode). This configuration must be enabled only if the AHB
clock prescaler is set to 1 (HPRE[3:0] = 0xxx in RCC_CFGR register) and if the system clock
has a 50% duty cycle.
10: HCLK/2 (Synchronous clock mode)
11: HCLK/4 (Synchronous clock mode)

In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start
of a conversion.
Note: The software is allowed to write these bits only when the ADCs are disabled
(ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bits 15:14 MDMA[1:0]: Direct memory access mode for dual ADC mode
This bitfield is set and cleared by software. Refer to the DMA controller section for more
details.
00: MDMA mode disabled
01: Enable dual interleaved mode to output to the master channel of DFSDM interface both
Master and the Slave result (16-bit data width)
10: MDMA mode enabled for 12 and 10-bit resolution
11: MDMA mode enabled for 8 and 6-bit resolution
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 13 DMACFG: DMA configuration (for dual ADC mode)
This bit is set and cleared by software to select between two DMA modes of operation and is
effective only when DMAEN=1.
0: DMA One Shot mode selected
1: DMA Circular mode selected
For more details, refer to Section : Managing conversions using the DMA
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).

RM0432 Rev 6 719/2301

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Analog-to-digital converters (ADC) RM0432

Bit 12 Reserved, must be kept at reset value.

Bits 11:8 DELAY: Delay between 2 sampling phases
These bits are set and cleared by software. These bits are used in dual interleaved modes.
Refer to Table 140 for the value of ADC resolution versus DELAY bits values.
Note: The software is allowed to write these bits only when the ADCs are disabled
(ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 DUAL[4:0]: Dual ADC mode selection
These bits are written by software to select the operating mode.
All the ADCs independent:
00000: Independent mode

00001 to 01001: Dual mode, master and slave ADCs working together
00001: Combined regular simultaneous + injected simultaneous mode
00010: Combined regular simultaneous + alternate trigger mode
00011: Combined Interleaved mode + injected simultaneous mode
00100: Reserved
00101: Injected simultaneous mode only
00110: Regular simultaneous mode only
00111: Interleaved mode only
01001: Alternate trigger mode only
All other combinations are reserved and must not be programmed

Note: The software is allowed to write these bits only when the ADCs are disabled
(ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

Table 140. DELAY bits versus ADC resolution

DELAY bits 12-bit resolution 10-bit resolution 8-bit resolution 6-bit resolution

0000 1 * TADC_CLK 1 * TADC_CLK 1 * TADC_CLK 1 * TADC_CLK

0001 2 * TADC_CLK 2 * TADC_CLK 2 * TADC_CLK 2 * TADC_CLK
0010 3 * TADC_CLK 3 * TADC_CLK 3 * TADC_CLK 3 * TADC_CLK
0011 4 * TADC_CLK 4 * TADC_CLK 4 * TADC_CLK 4 * TADC_CLK
0100 5 * TADC_CLK 5 * TADC_CLK 5 * TADC_CLK 5 * TADC_CLK
0101 6 * TADC_CLK 6 * TADC_CLK 6 * TADC_CLK 6 * TADC_CLK
0110 7 * TADC_CLK 7 * TADC_CLK 7 * TADC_CLK 6 * TADC_CLK
0111 8 * TADC_CLK 8 * TADC_CLK 8 * TADC_CLK 6 * TADC_CLK
1000 9 * TADC_CLK 9 * TADC_CLK 8 * TADC_CLK 6 * TADC_CLK
1001 10 * TADC_CLK 10 * TADC_CLK 8 * TADC_CLK 6 * TADC_CLK
1010 11 * TADC_CLK 10 * TADC_CLK 8 * TADC_CLK 6 * TADC_CLK
1011 12 * TADC_CLK 10 * TADC_CLK 8 * TADC_CLK 6 * TADC_CLK
others 12 * TADC_CLK 10 * TADC_CLK 8 * TADC_CLK 6 * TADC_CLK

720/2301 RM0432 Rev 6

RM0432 Analog-to-digital converters (ADC)

21.7.3 ADC common regular data register for dual mode (ADC_CDR)
Address offset: 0x0C (this offset address is relative to the master ADC base address +
0x300)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA_SLV[15:0]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA_MST[15:0]
r r r r r r r r r r r r r r r r

Bits 31:16 RDATA_SLV[15:0]: Regular data of the slave ADC

In dual mode, these bits contain the regular data of the slave ADC. Refer to Section 21.4.31:
Dual ADC modes.
The data alignment is applied as described in Section : Data register, data alignment and
offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN))
Bits 15:0 RDATA_MST[15:0]: Regular data of the master ADC.
In dual mode, these bits contain the regular data of the master ADC. Refer to
Section 21.4.31: Dual ADC modes.
The data alignment is applied as described in Section : Data register, data alignment and
offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN))
In MDMA=0b11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains
MST_ADC_DR[7:0].

21.8 ADC register map

The following table summarizes the ADC registers.

Table 141. ADC global register map(1)

Offset Register

0x000 - 0x0B4 Master ADC1

0x0B8 - 0x0FC Reserved
0x100 - 0x1B4 Slave ADC2
0x1B8 - 0x2FC Reserved
0x300 - 0x30C Master and slave ADCs common registers
1. Reserved area highlighted in gray.

RM0432 Rev 6 721/2301

724
Analog-to-digital converters (ADC) RM0432

Table 142. ADC register map and reset values for each ADC (offset=0x000
for master ADC, 0x100 for slave ADC)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
EOSMP
ADRDY
JQOVF
AWD3
AWD2
AWD1

JEOC
JEOS

OVR

EOC
EOS
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_ISR
0x00

Reset value 0 0 0 0 0 0 0 0 0 0 0

EOSMPIE
ADRDYIE
JQOVFIE
AWD3IE
AWD2IE
AWD1IE

JEOCIE
JEOSIE

OVRIE

EOCIE
EOSIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_IER
0x04

Reset value 0 0 0 0 0 0 0 0 0 0 0
ADVREGEN

JADSTART
DEEPPWD
ADCALDIF

ADSTART
JADSTP
ADCAL

ADSTP

ADDIS
ADEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_CR
0x08

Reset value 0 0 1 0 0 0 0 0 0 0

DFSDMCFG
EXTEN[1:0]
AWD1SGL
JAWD1EN

OVRMOD

EXTSEL3
EXTSEL2
EXTSEL1
EXTSEL0

DMACFG
JDISCEN
AWD1EN

AUTDLY
DISCEN

DMAEN
JAUTO
JQDIS.

ALIGN
CONT
DISCNUM RES
JQM

Res.
ADC_CFGR AWD1CH[4:0]
0x0C [2:0] [1:0]

Reset value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ROVSM

ROVSE
TROVS

JOVSE
OVSR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_CFGR2 OVSS[3:0]
0x0C [2:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0
SMPPLUS.

SMP9 SMP8 SMP7 SMP6 SMP5 SMP4 SMP3 SMP2 SMP1 SMP0
Res.

ADC_SMPR1 [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] [2:0]
0x14

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SMP18 SMP17 SMP16 SMP15 SMP14 SMP13 SMP12 SMP11 SMP10
Res.
Res.
Res.
Res.
Res.

ADC_SMPR2
0x18 [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] [2:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x1C Reserved Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.

ADC_TR1 HT1[11:0] LT1[11:0]

0x20
Reset value 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ADC_TR2 HT2[[7:0] LT2[7:0]

0x24
Reset value 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ADC_TR3 HT3[[7:0] LT3[7:0]

0x28
Reset value 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
0x2C Reserved Res.
Res.
Res.
Res.

Res.

Res.

Res.

Res.
Res.

ADC_SQR1 SQ4[4:0] SQ3[4:0] SQ2[4:0] SQ1[4:0] L[3:0]

0x30
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.

Res.

Res.

Res.

Res.

ADC_SQR2 SQ9[4:0] SQ8[4:0] SQ7[4:0] SQ6[4:0] SQ5[4:0]

0x34
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.

Res.

Res.

Res.

Res.

ADC_SQR3 SQ14[4:0] SQ13[4:0] SQ12[4:0] SQ11[4:0] SQ10[4:0]

0x38
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

ADC_SQR4 SQ16[4:0] SQ15[4:0]

0x3C
Reset value 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ADC_DR regular RDATA[15:0]

0x40
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

722/2301 RM0432 Rev 6

RM0432 Analog-to-digital converters (ADC)

Table 142. ADC register map and reset values for each ADC (offset=0x000
for master ADC, 0x100 for slave ADC) (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
0x44-
Reserved Res.
0x48

JEXTEN[1:0]
JEXTSEL
Res.

Res.

Res.

Res.
ADC_JSQR JSQ4[4:0] JSQ3[4:0] JSQ2[4:0] JSQ1[4:0] JL[1:0]
0x4C [3:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x50-
Reserved Res.
0x5C
OFFSET1_EN

OFFSET1_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_OFR1 OFFSET1[11:0]
0x60 CH[4:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OFFSET2_EN

OFFSET2_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_OFR2 OFFSET2[11:0]
0x64 CH[4:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OFFSET3_EN

OFFSET3_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_OFR3 CH[4:0] Res. OFFSET3[11:0]
0x68

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OFFSET4_EN

OFFSET4_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ADC_OFR4 OFFSET4[11:0]
0x6C CH[4:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x70-
Reserved Res.
0x7C
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ADC_JDR1 JDATA1[15:0]
0x80
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ADC_JDR2 JDATA2[15:0]
0x84
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ADC_JDR3 JDATA3[15:0]
0x88
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ADC_JDR4 JDATA4[15:0]
0x8C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x8C-
Reserved Res.
0x9C
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ADC_AWD2CR AWD2CH[18:0]
0xA0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ADC_AWD3CR AWD3CH[18:0]
0xA4
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

0xA8-
Reserved
0xAC

RM0432 Rev 6 723/2301

724
Analog-to-digital converters (ADC) RM0432

Table 142. ADC register map and reset values for each ADC (offset=0x000
for master ADC, 0x100 for slave ADC) (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_DIFSEL DIFSEL[18:0]
0xB0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_CALFACT CALFACT_D[6:0] CALFACT_S[6:0]
0xB4
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 143. ADC register map and reset values (master and slave ADC
common registers) offset = 0x300

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
EOSMP_MST
ADRDY_MST
JQOVF_MST
EOSMP_SLV
ADRDY_SLV
JQOVF_SLV

AWD3_MST
AWD2_MST
AWD1_MST

JEOC_MST
JEOS_MST
AWD3_SLV
AWD2_SLV
AWD1_SLV

JEOC_SLV
JEOS_SLV

OVR_MST

EOC_MST
EOS_MST
OVR_SLV

EOC_SLV
EOS_SLV
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
ADC_CSR
0x00

slave ADC2 master ADC1

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x04 Reserved Res.
CKMODE[1:0]

MDMA[1:0]
CH18SEL
CH17SEL

DMACFG
VREFEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
Res.
Res.
ADC_CCR PRESC[3:0] DELAY[3:0] DUAL[4:0]
0x08

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADC_CDR RDATA_SLV[15:0] RDATA_MST[15:0]
0x0C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 91 for the register boundary addresses.

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RM0432 Digital-to-analog converter (DAC)

22 Digital-to-analog converter (DAC)

22.1 Introduction
The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be
configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In
12-bit mode, the data could be left- or right-aligned. The DAC features two output channels,
each with its own converter. In dual DAC channel mode, conversions could be done
independently or simultaneously when both channels are grouped together for synchronous
update operations. An input reference pin, VREF+ (shared with others analog peripherals) is
available for better resolution. An internal reference can also be set on the same input.
Refer to voltage reference buffer (VREFBUF) section.
The DAC_OUTx pin can be used as general purpose input/output (GPIO) when the DAC
output is disconnected from output pad and connected to on chip peripheral. The DAC
output buffer can be optionally enabled to allow a high drive output current. An individual
calibration can be applied on each DAC output channel. The DAC output channels support
a low power mode, the Sample and hold mode.

22.2 DAC main features

The DAC main features are the following (see Figure 158: Dual-channel DAC block
diagram)
• One DAC interface, maximum two output channels
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave and Triangular-wave generation
• Dual DAC channel for independent or simultaneous conversions
• DMA capability for each channel including DMA underrun error detection
• External triggers for conversion
• DAC output channel buffered/unbuffered modes
• Buffer offset calibration
• Each DAC output can be disconnected from the DAC_OUTx output pin
• DAC output connection to on chip peripherals
• Sample and hold mode for low power operation in Stop mode
• Input voltage reference, VREF+
Figure 158 shows the block diagram of a DAC channel and Table 145 gives the pin
description.

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22.3 DAC implementation

Table 144. DAC implementation
DAC features DAC1

Dual channel X
Output buffer X
I/O connection DAC1_OUT1 on PA4, DAC1_OUT2 on PA5
Maximum sampling time 1MSPS
Autonomous mode -

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22.4 DAC functional description

22.4.1 DAC block diagram

Figure 158. Dual-channel DAC block diagram

VREF+ VDDA

Offset calibration
Sample & Hold Registers
Control registers OTRIM1[5:0]bits
& logic Channel1 TSAMPLE1

THOLD1
TSEL1[3:0]
bits DMA_Request TREFRESH1

DAC_OUT1
DAC Buffer 1
TRIG DAC_DOR1
converter 1
12-bit
1

MODE1 bits

dac_out1
LSI clock
DAC channel 1

Offset calibration
Sample & Hold Registers
Control registers OTRIM2[5:0]bits On-chip
& logic Channel2 TSAMPLE2
Peripherals
THOLD2
TSEL2[3:0]
bits DMA_Request TREFRESH2

DAC_OUT2
TRIG
DAC
DAC_DOR2 Buffer 2
converter 2
12-bit
1

MODE2 bits

dac_out2
DAC channel 2

APB1 Bus On-chip

Peripherals

VSSA
MSv40461V3

1. MODEx bits in the DAC_MCR control the output mode and allow switching between the Normal mode in
buffer/unbuffered configuration and the Sample and hold mode.
2. Refer to Section 22.3: DAC implementation for channel2 availability.

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The DAC includes:

• Up to two output channels
• The DAC_OUTx can be disconnected from the output pin and used as an ordinary
GPIO
• The DAC_OUTx can use an internal pin connection to on-chip peripherals such as
comparator, operational amplifier and ADC (if available).
• DAC output channel buffered or non buffered
• Sample and hold block and registers operational in Stop mode, using the LSI clock
source for static conversion.
The DAC includes up to two separate output channels. Each output channel can be
connected to on-chip peripherals such as comparator, operational amplifier and ADC (if
available). In this case, the DAC output channel can be disconnected from the DAC_OUTx
output pin and the corresponding GPIO can be used for another purpose.
The DAC output can be buffered or not. The Sample and hold block and its associated
registers can run in Stop mode using the LSI clock source.

Table 145. DAC input/output pins

Pin name Signal type Remarks

Input, analog reference The higher/positive reference voltage for the DAC,
VREF+
positive VREF+ ≤ VDDAmax (refer to datasheet)
VDDA Input, analog supply Analog power supply
VSSA Input, analog supply ground Ground for analog power supply
DAC_OUTx Analog output signal DAC channelx analog output

22.4.2 DAC channel enable

Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR
register. The DAC channel is then enabled after a tWAKEUP startup time.
Note: The ENx bit enables the analog DAC channelx only. The DAC channelx digital interface is
enabled even if the ENx bit is reset.

22.4.3 DAC data format

Depending on the selected configuration mode, the data have to be written into the specified
register as described below:
• Single DAC channel
There are three possibilities:
– 8-bit right alignment: the software has to load data into the DAC_DHR8Rx[7:0] bits
(stored into the DHRx[11:4] bits)
– 12-bit left alignment: the software has to load data into the DAC_DHR12Lx [15:4]
bits (stored into the DHRx[11:0] bits)
– 12-bit right alignment: the software has to load data into the DAC_DHR12Rx [11:0]
bits (stored into the DHRx[11:0] bits)
Depending on the loaded DAC_DHRyyyx register, the data written by the user is shifted and
stored into the corresponding DHRx (data holding registerx, which are internal non-memory-

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mapped registers). The DHRx register is then loaded into the DORx register either
automatically, by software trigger or by an external event trigger.

Figure 159. Data registers in single DAC channel mode

31 24 15 7 0
8-bit right aligned

12-bit left aligned

12-bit right aligned

ai14710b
• Dual DAC channels (when available)
There are three possibilities:
– 8-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR8RD
[7:0] bits (stored into the DHR1[11:4] bits) and data for DAC channel2 to be loaded
into the DAC_DHR8RD [15:8] bits (stored into the DHR2[11:4] bits)
– 12-bit left alignment: data for DAC channel1 to be loaded into the DAC_DHR12LD
[15:4] bits (stored into the DHR1[11:0] bits) and data for DAC channel2 to be
loaded into the DAC_DHR12LD [31:20] bits (stored into the DHR2[11:0] bits)
– 12-bit right alignment: data for DAC channel1 to be loaded into the
DAC_DHR12RD [11:0] bits (stored into the DHR1[11:0] bits) and data for DAC
channel2 to be loaded into the DAC_DHR12RD [27:16] bits (stored into the
DHR2[11:0] bits)
Depending on the loaded DAC_DHRyyyD register, the data written by the user is shifted
and stored into DHR1 and DHR2 (data holding registers, which are internal non-memory-
mapped registers). The DHR1 and DHR2 registers are then loaded into the DAC_DOR1
and DOR2 registers, respectively, either automatically, by software trigger or by an external
event trigger.

Figure 160. Data registers in dual DAC channel mode

31 24 15 7 0
8-bit right aligned

12-bit left aligned

12-bit right aligned

ai14709b

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22.4.4 DAC conversion

The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must
be performed by loading the DAC_DHRx register (write operation to DAC_DHR8Rx,
DAC_DHR12Lx, DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12RD or DAC_DHR12LD).
Data stored in the DAC_DHRx register are automatically transferred to the DAC_DORx
register after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR
register is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR
register is set) and a trigger occurs, the transfer is performed three APB1 clock cycles after
the trigger signal.
When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage
becomes available after a time tSETTLING that depends on the power supply voltage and the
analog output load.
HFSEL bit of DAC_CR must be set when APB1 clock speed is faster than 80 MHz. It adds
an extra delay of three APB1 clock cycles to the transfer from DAC_DHRx register to
DAC_DORx register (tSETTLING).
The DAC_DORx update rate is limited to 1/3 of APB1 clock frequency. When HFSEL bit is
set, this rate is limited to 1/8 of the APB1 clock frequency.
When HFSEL is set, it is not allowed to write the DHRx register during a period of eight clock
cycles after the ENx bit is set. During this period, making software/hardware triggering is not
allowed either.

Figure 161. Timing diagram for conversion with trigger disabled TEN = 0

APB1_CLK

DHR 0x1AC

Output voltage
DOR 0x1AC available on DAC_OUT pin
tSETTLING
ai14711c

22.4.5 DAC output voltage

Digital inputs are converted to output voltages on a linear conversion between 0 and VREF+.
The analog output voltages on each DAC channel pin are determined by the following
equation:
DOR
DACoutput = V REF × --------------
4096

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22.4.6 DAC trigger selection

If the TENx control bit is set, the conversion can then be triggered by an external event (timer
counter, external interrupt line). The TSELx[3:0] control bits determine which out of 16 pos-
sible events triggers the conversion as shown in TSELx[3:0] bits of the DAC_CR register.
These events can be either the software trigger or hardware triggers. Refer to Table 146:
DAC trigger selection.
Each time a DAC interface detects a rising edge on the selected trigger source (refer to the
table below), the last data stored into the DAC_DHRx register are transferred into the
DAC_DORx register. The DAC_DORx register is updated three APB1 cycles after the
trigger occurs.
If the software trigger is selected, the conversion starts once the SWTRIG bit is set.
SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the
DAC_DHRx register contents.
Note: TSELx[3:0] bit cannot be changed when the ENx bit is set.
When software trigger is selected, the transfer from the DAC_DHRx register to the
DAC_DORx register takes only one APB1 clock cycle.

Table 146. DAC trigger selection

Source Type TSELx[3:0]

SWTRIG Software control bit 0000

TIM1_TRGO Internal signal from on-chip timers 0001
TIM2_TRGO Internal signal from on-chip timers 0010
TIM4_TRGO Internal signal from on-chip timers 0011
TIM5_TRGO Internal signal from on-chip timers 0100
TIM6_TRGO Internal signal from on-chip timers 0101
TIM7_TRGO Internal signal from on-chip timers 0110
TIM8_TRGO Internal signal from on-chip timers 0111
TIM15_TRGO Internal signal from on-chip timers 1000
Reserved - 1001
Reserved - 1010
LPTIM1_OUT Internal signal from on-chip timers 1011
LPTIM2_OUT Internal signal from on-chip timers 1100
EXTI9 External pin 1101
Reserved - 1110
Reserved - 1111

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22.4.7 DMA requests

Each DAC channel has a DMA capability. Two DMA channels are used to service DAC
channel DMA requests.
When an external trigger (but not a software trigger) occurs while the DMAENx bit is set, the
value of the DAC_DHRx register is transferred into the DAC_DORx register when the
transfer is complete, and a DMA request is generated.
In dual mode, if both DMAENx bits are set, two DMA requests are generated. If only one
DMA request is needed, only the corresponding DMAENx bit must be set. In this way, the
application can manage both DAC channels in dual mode by using one DMA request and a
unique DMA channel.
As DAC_DHRx to DAC_DORx data transfer occurred before the DMA request, the very first
data has to be written to the DAC_DHRx before the first trigger event occurs.

DMA underrun
The DAC DMA request is not queued so that if a second external trigger arrives before the
acknowledgment for the first external trigger is received (first request), then no new request
is issued and the DMA channelx underrun flag DMAUDRx in the DAC_SR register is set,
reporting the error condition. The DAC channelx continues to convert old data.
The software must clear the DMAUDRx flag by writing 1, clear the DMAEN bit of the used
DMA stream and re-initialize both DMA and DAC channelx to restart the transfer correctly.
The software must modify the DAC trigger conversion frequency or lighten the DMA
workload to avoid a new DMA underrun. Finally, the DAC conversion could be resumed by
enabling both DMA data transfer and conversion trigger.
For each DAC channelx, an interrupt is also generated if its corresponding DMAUDRIEx bit
in the DAC_CR register is enabled.

22.4.8 DAC noise generation

In order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift
register) is available. DAC noise generation is selected by setting WAVEx[1:0] to 01. The
preloaded value in LFSR is 0xAAA. This register is updated three APB1 clock cycles after
each trigger event, following a specific calculation algorithm.

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Figure 162. DAC LFSR register calculation algorithm

XOR

X6 X4 X X0
X 12
11 10 9 8 7 6 5 4 3 2 1 0

12

NOR

ai14713c

The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in
the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this
value is then transferred into the DAC_DORx register.
If LFSR is 0x0000, a ‘1 is injected into it (antilock-up mechanism).
It is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits.

Figure 163. DAC conversion (SW trigger enabled) with LFSR wave generation

APB1_CLK

DHR 0x00

DOR 0xAAA 0xD55

SWTRIG

ai14714b

Note: The DAC trigger must be enabled for noise generation by setting the TENx bit in the
DAC_CR register.

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22.4.9 DAC triangle-wave generation

It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal.
DAC triangle-wave generation is selected by setting WAVEx[1:0] to 10”. The amplitude is
configured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter
is incremented three APB1 clock cycles after each trigger event. The value of this counter is
then added to the DAC_DHRx register without overflow and the sum is transferred into the
DAC_DORx register. The triangle counter is incremented as long as it is less than the
maximum amplitude defined by the MAMPx[3:0] bits. Once the configured amplitude is
reached, the counter is decremented down to 0, then incremented again and so on.
It is possible to reset triangle wave generation by resetting the WAVEx[1:0] bits.

Figure 164. DAC triangle wave generation

MAMPx[3:0] max amplitude

+ DAC_DHRx base value

De
n
tio

cr
ta

em
en

en
em

ta
cr

tio
In

n
DAC_DHRx base value
0

ai14715c

Figure 165. DAC conversion (SW trigger enabled) with triangle wave generation

APB1_CLK

DHR 0xABE

DOR 0xABE 0xABF 0xAC0

SWTRIG

ai14716b

Note: The DAC trigger must be enabled for triangle wave generation by setting the TENx bit in the
DAC_CR register.
The MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot
be changed.

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22.4.10 DAC channel modes

Each DAC channel can be configured in Normal mode or Sample and hold mode. The
output buffer can be enabled to allow a high drive capability. Before enabling output buffer,
the voltage offset needs to be calibrated. This calibration is performed at the factory (loaded
after reset) and can be adjusted by software during application operation.

Normal mode
In Normal mode, there are four combinations, by changing the buffer state and by changing
the DAC_OUTx pin interconnections.
To enable the output buffer, the MODEx[2:0] bits in DAC_MCR register must be:
• 000: DAC is connected to the external pin
• 001: DAC is connected to external pin and to on-chip peripherals
To disable the output buffer, the MODEx[2:0] bits in DAC_MCR register must be:
• 010: DAC is connected to the external pin
• 011: DAC is connected to on-chip peripherals

Sample and hold mode

In Sample and hold mode, the DAC core converts data on a triggered conversion, and then
holds the converted voltage on a capacitor. When not converting, the DAC cores and buffer
are completely turned off between samples and the DAC output is tri-stated, therefore
reducing the overall power consumption. A stabilization period, which value depends on the
buffer state, is required before each new conversion.
In this mode, the DAC core and all corresponding logic and registers are driven by the LSI
low-speed clock in addition to the APB1 clock, allowing to use the DAC channels in deep
low power modes such as Stop mode.
The LSI low-speed clock must not be stopped on-the-fly when the Sample and hold mode is
enabled.
The sample/hold mode operations can be divided into 3 phases:
1. Sample phase: the sample/hold element is charged to the desired voltage. The
charging time depends on capacitor value (internal or external, selected by the user).
The sampling time is configured with the TSAMPLEx[9:0] bits in DAC_SHSRx register.
During the write of the TSAMPLEx[9:0] bits, the BWSTx bit in DAC_SR register is set to
1 to synchronize between both clocks domains (APB and low speed clock) and
allowing the software to change the value of sample phase during the DAC channel
operation
2. Hold phase: the DAC output channel is tri-stated, the DAC core and the buffer are
turned off, to reduce the current consumption. The hold time is configured with the
THOLDx[9:0] bits in DAC_SHHR register
3. Refresh phase: the refresh time is configured with the TREFRESHx[7:0] bits in
DAC_SHRR register

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The timings for the three phases above are in units of LSI clock periods. As an example, to
configure a sample time of 350 µs, a hold time of 2 ms and a refresh time of 100 µs
assuming LSI ~32 KHz is selected:
12 cycles are required for sample phase: TSAMPLEx[9:0] = 11,
62 cycles are required for hold phase: THOLDx[9:0] = 62,
and 4 cycles are required for refresh period: TREFRESHx[7:0] = 4.
In this example, the power consumption is reduced by almost a factor of 15 versus Normal
modes.
The formulas to compute the right sample and refresh timings are described in the table
below, the Hold time depends on the leakage current.

Table 147. Sample and refresh timings

Buffer
State
tSAMP(1)(2) tREFRESH(2)(3)

Enable 7 μs + (10*RBON*CSH) 7 μs + (RBON*CSH)*ln(2*NLSB)

Disable 3 μs + (10*RBOFF*CSH) 3 μs + (RBOFF*CSH)*ln(2*NLSB)
1. In the above formula the settling to the desired code value with ½ LSB or accuracy requires 10 constant
time for 12 bits resolution. For 8 bits resolution, the settling time is 7 constant time.
2. CSH is the capacitor in Sample and hold mode.
3. The tolerated voltage drop during the hold phase “Vd” is represented by the number of LSBs after the
capacitor discharging with the output leakage current. The settling back to the desired value with ½ LSB
error accuracy requires ln(2*Nlsb) constant time of the DAC.

Example of the sample and refresh time calculation with output buffer on
The values used in the example below are provided as indication only. Please refer to the
product datasheet for product data.
CSH = 100 nF
VDDA= 3.0 V
Sampling phase:
tSAMP = 7 μs + (10 * 2000 * 100 * 10-9) = 2.007 ms
(where RBON = 2 kΩ)
Refresh phase:
tREFRESH = 7 μs + (2000 * 100 * 10-9) * ln(2*10) = 606.1 μs
(where NLSB = 10 (10 LSB drop during the hold phase)
Hold phase:
Dv = ileak * thold / CSH = 0.0073 V (10 LSB of 12bit at 3 V)
ileak = 150 nA (worst case on the IO leakage on all the temperature range)
thold = 0.0073 * 100 * 10-9 / (150 * 10-9) = 4.867 ms

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RM0432 Digital-to-analog converter (DAC)

Figure 166. DAC Sample and hold mode phase diagram

V1
Vd
V2

t
Sampling phase Hold phase Refresh Sampling phase
LSI phase

t
DAC

ON ON ON
MSv40462V2

Like in Normal mode, the Sample and hold mode has different configurations.
To enable the output buffer, MODEx[2:0] bits in DAC_MCR register must be set to:
• 100: DAC is connected to the external pin
• 101: DAC is connected to external pin and to on chip peripherals
To disabled the output buffer, MODEx[2:0] bits in DAC_MCR register must be set to:
• 110: DAC is connected to external pin and to on chip peripherals
• 111: DAC is connected to on chip peripherals
When MODEx[2:0] bits are equal to 111, an internal capacitor, CLint, holds the voltage
output of the DAC core and then drive it to on-chip peripherals.
All Sample and hold phases are interruptible, and any change in DAC_DHRx immediately
triggers a new sample phase.

Table 148. Channel output modes summary

MODEx[2:0] Mode Buffer Output connections

0 0 0 Connected to external pin

Enabled Connected to external pin and to on chip-peripherals (such as
0 0 1
Normal mode comparators)
0 1 0 Connected to external pin
Disabled
0 1 1 Connected to on chip peripherals (such as comparators)

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Table 148. Channel output modes summary (continued)

MODEx[2:0] Mode Buffer Output connections

1 0 0 Connected to external pin

Enabled Connected to external pin and to on chip peripherals (such as
1 0 1
Sample and comparators)
hold mode Connected to external pin and to on chip peripherals (such as
1 1 0
Disabled comparators)
1 1 1 Connected to on chip peripherals (such as comparators)

22.4.11 DAC channel buffer calibration

The transfer function for an N-bit digital-to-analog converter (DAC) is:

V = ( ( D ⁄ 2N – 1 ) × G × V )+V
out ref OS
Where VOUT is the analog output, D is the digital input, G is the gain, Vref is the nominal full-
scale voltage, and Vos is the offset voltage. For an ideal DAC channel, G = 1 and Vos = 0.
Due to output buffer characteristics, the voltage offset may differ from part-to-part and
introduce an absolute offset error on the analog output. To compensate the Vos, a calibration
is required by a trimming technique.
The calibration is only valid when the DAC channelx is operating with buffer enabled
(MODEx[2:0] = 000b or 001b or 100b or 101b). if applied in other modes when the buffer is
off, it has no effect. During the calibration:
• The buffer output is disconnected from the pin internal/external connections and put in
tristate mode (HiZ).
• The buffer acts as a comparator to sense the middle-code value 0x800 and compare it
to VREF+/2 signal through an internal bridge, then toggle its output signal to 0 or 1
depending on the comparison result (CAL_FLAGx bit).
Two calibration techniques are provided:
• Factory trimming (default setting)
The DAC buffer offset is factory trimmed. The default value of OTRIMx[4:0] bits in
DAC_CCR register is the factory trimming value and it is loaded once DAC digital
interface is reset.
• User trimming
The user trimming can be done when the operating conditions differs from nominal
factory trimming conditions and in particular when VDDA voltage, temperature, VREF+
values change and can be done at any point during application by software.
Note: Refer to the datasheet for more details of the Nominal factory trimming conditions
In addition, when VDD is removed (example the device enters in STANDBY or VBAT modes)
the calibration is required.
The steps to perform a user trimming calibration are as below:

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1. If the DAC channel is active, write 0 to ENx bit in DAC_CR to disable the channel.
2. Select a mode where the buffer is enabled, by writing to DAC_MCR register,
MODEx[2:0] = 000b or 001b or 100b or 101b.
3. Start the DAC channelx calibration, by setting the CENx bit in DAC_CR register to 1.
4. Apply a trimming algorithm:
a) Write a code into OTRIMx[4:0] bits, starting by 00000b.
b) Wait for tTRIM delay.
c) Check if CAL_FLAGx bit in DAC_SR is set to 1.
d) If CAL_FLAGx is set to 1, the OTRIMx[4:0] trimming code is found and can be
used during device operation to compensate the output value, else increment
OTRIMx[4:0] and repeat sub-steps from (a) to (d) again.
The software algorithm may use either a successive approximation or dichotomy techniques
to compute and set the content of OTRIMx[4:0] bits in a faster way.
The commutation/toggle of CAL_FLAGx bit indicates that the offset is correctly
compensated and the corresponding trim code must be kept in the OTRIMx[4:0] bits in
DAC_CCR register.
Note: A tTRIM delay must be respected between the write to the OTRIMx[4:0] bits and the read of
the CAL_FLAGx bit in DAC_SR register in order to get a correct value.This parameter is
specified into datasheet electrical characteristics section.
If VDDA, VREF+ and temperature conditions do not change during device operation while it
enters more often in standby and VBAT mode, the software may store the OTRIMx[4:0] bits
found in the first user calibration in the flash or in back-up registers. then to load/write them
directly when the device power is back again thus avoiding to wait for a new calibration time.
When CENx bit is set, it is not allowed to set ENx bit.

22.4.12 Dual DAC channel conversion modes (if dual channels are
available)
To efficiently use the bus bandwidth in applications that require the two DAC channels at the
same time, three dual registers are implemented: DHR8RD, DHR12RD and DHR12LD. A
unique register access is then required to drive both DAC channels at the same time. For
the wave generation, no accesses to DHRxxxD registers are required. As a result, two
output channels can be used either independently or simultaneously.
11 conversion modes are possible using the two DAC channels and these dual registers. All
the conversion modes can nevertheless be obtained using separate DHRx registers if
needed.
All modes are described in the paragraphs below.

Independent trigger without wave generation

To configure the DAC in this conversion mode, the following sequence is required:
1. Set the two DAC channel trigger enable bits TEN1 and TEN2.
2. Configure different trigger sources by setting different values in the TSEL1 and TSEL2
bitfields.
3. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).

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When a DAC channel1 trigger arrives, the DHR1 register is transferred into DAC_DOR1
(three APB1 clock cycles later).
When a DAC channel2 trigger arrives, the DHR2 register is transferred into DAC_DOR2
(three APB1 clock cycles later).

Independent trigger with single LFSR generation

To configure the DAC in this conversion mode, the following sequence is required:
1. Set the two DAC channel trigger enable bits TEN1 and TEN2.
2. Configure different trigger sources by setting different values in the TSEL1 and TSEL2
bitfields.
3. Configure the two DAC channel WAVEx[1:0] bits as 01 and the same LFSR mask value
in the MAMPx[3:0] bits.
4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a DAC channel1 trigger arrives, the LFSR1 counter, with the same mask, is added to
the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles
later). Then the LFSR1 counter is updated.
When a DAC channel2 trigger arrives, the LFSR2 counter, with the same mask, is added to
the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles
later). Then the LFSR2 counter is updated.

Independent trigger with different LFSR generation

To configure the DAC in this conversion mode, the following sequence is required:
1. Set the two DAC channel trigger enable bits TEN1 and TEN2.
2. Configure different trigger sources by setting different values in the TSEL1 and TSEL2
bitfields.
3. Configure the two DAC channel WAVEx[1:0] bits as 01 and set different LFSR masks
values in the MAMP1[3:0] and MAMP2[3:0] bits.
4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a DAC channel1 trigger arrives, the LFSR1 counter, with the mask configured by
MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1
(three APB1 clock cycles later). Then the LFSR1 counter is updated.
When a DAC channel2 trigger arrives, the LFSR2 counter, with the mask configured by
MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2
(three APB1 clock cycles later). Then the LFSR2 counter is updated.

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Independent trigger with single triangle generation

To configure the DAC in this conversion mode, the following sequence is required:
1. Set the two DAC channel trigger enable bits TEN1 and TEN2.
2. Configure different trigger sources by setting different values in the TSEL1 and TSEL2
bitfields.
3. Configure the two DAC channel WAVEx[1:0] bits as 1x and the same maximum
amplitude value in the MAMPx[3:0] bits.
4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with the same
triangle amplitude, is added to the DHR1 register and the sum is transferred into
DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then
updated.
When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with the same
triangle amplitude, is added to the DHR2 register and the sum is transferred into
DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then
updated.

Independent trigger with different triangle generation

To configure the DAC in this conversion mode, the following sequence is required:
1. Set the two DAC channel trigger enable bits TEN1 and TEN2.
2. Configure different trigger sources by setting different values in the TSEL1 and TSEL2
bits.
3. Configure the two DAC channel WAVEx[1:0] bits as 1x and set different maximum
amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits.
4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with a triangle
amplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is
transferred into DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle
counter is then updated.
When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with a triangle
amplitude configured by MAMP2[3:0], is added to the DHR2 register and the sum is
transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle
counter is then updated.

Simultaneous software start

To configure the DAC in this conversion mode, the following sequence is required:
• Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
In this configuration, one APB1 clock cycle later, the DHR1 and DHR2 registers are
transferred into DAC_DOR1 and DAC_DOR2, respectively.

Simultaneous trigger without wave generation

To configure the DAC in this conversion mode, the following sequence is required:

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1. Set the two DAC channel trigger enable bits TEN1 and TEN2.
2. Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1 and TSEL2 bitfields.
3. Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a trigger arrives, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and
DAC_DOR2, respectively (after three APB1 clock cycles).

Simultaneous trigger with single LFSR generation

1. To configure the DAC in this conversion mode, the following sequence is required:
2. Set the two DAC channel trigger enable bits TEN1 and TEN2.
3. Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1 and TSEL2 bitfields.
4. Configure the two DAC channel WAVEx[1:0] bits as 01 and the same LFSR mask value
in the MAMPx[3:0] bits.
5. Load the dual DAC channel data to the desired DHR register (DHR12RD, DHR12LD or
DHR8RD).
When a trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1
register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The
LFSR1 counter is then updated. At the same time, the LFSR2 counter, with the same mask,
is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1
clock cycles later). The LFSR2 counter is then updated.

Simultaneous trigger with different LFSR generation

To configure the DAC in this conversion mode, the following sequence is required:
1. Set the two DAC channel trigger enable bits TEN1 and TEN2
2. Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1 and TSEL2 bitfields.
3. Configure the two DAC channel WAVEx[1:0] bits as 01 and set different LFSR mask
values using the MAMP1[3:0] and MAMP2[3:0] bits.
4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is
added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock
cycles later). The LFSR1 counter is then updated.
At the same time, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to
the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles
later). The LFSR2 counter is then updated.

Simultaneous trigger with single triangle generation

To configure the DAC in this conversion mode, the following sequence is required:

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RM0432 Digital-to-analog converter (DAC)

1. Set the two DAC channel trigger enable bits TEN1 and TEN2
2. Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1 and TSEL2 bitfields.
3. Configure the two DAC channel WAVEx[1:0] bits as 1x and the same maximum
amplitude value using the MAMPx[3:0] bits.
4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a trigger arrives, the DAC channel1 triangle counter, with the same triangle
amplitude, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three
APB1 clock cycles later). The DAC channel1 triangle counter is then updated.
At the same time, the DAC channel2 triangle counter, with the same triangle amplitude, is
added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock
cycles later). The DAC channel2 triangle counter is then updated.

Simultaneous trigger with different triangle generation

To configure the DAC in this conversion mode, the following sequence is required:
1. Set the two DAC channel trigger enable bits TEN1 and TEN2
2. Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1 and TSEL2 bitfields.
3. Configure the two DAC channel WAVEx[1:0] bits as 1x and set different maximum
amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits.
4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude
configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into
DAC_DOR1 (three APB clock cycles later). Then the DAC channel1 triangle counter is
updated.
At the same time, the DAC channel2 triangle counter, with a triangle amplitude configured
by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2
(three APB1 clock cycles later). Then the DAC channel2 triangle counter is updated.

22.5 DAC low-power modes

Table 149. Effect of low-power modes on DAC
Mode Description

Sleep No effect, DAC used with DMA

Low-power run No effect.
Low-power sleep No effect. DAC used with DMA.
DAC remains active with a static value, if Sample and hold mode is
Stop 0 / Stop 1
selected using LSI clock
The DAC registers content is kept. The DAC must be disabled before
Stop 2
entering Stop 2.

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Table 149. Effect of low-power modes on DAC (continued)

Mode Description

Standby The DAC peripheral is powered down and must be reinitialized after exiting
Shutdown Standby or Shutdown mode.

22.6 DAC interrupts

Table 150. DAC interrupts
Interrupt Interrupt Enable Interrupt clear Exit Sleep Exit Stop Exit Standby
Event flag
acronym event control bit method mode mode mode

DMA DMAUDRI Write

DAC DMAUDRx Yes No No
underrun Ex DMAUDRx = 1

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22.7 DAC registers

Refer to Section 1 on page 84 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32-bit).

22.7.1 DAC control register (DAC_CR)

Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAU DMAE
Res. CEN2 MAMP2[3:0] WAVE2[1:0] TSEL2[3] TSEL2[2] TSEL2[1] TSEL2[0] TEN2 EN2
DRIE2 N2
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAU DMAE
HFSEL CEN1 MAMP1[3:0] WAVE1[1:0] TSEL1[3] TSEL1[2] TSEL1[1] TSEL1[0] TEN1 EN1
DRIE1 N1
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 Reserved, must be kept at reset value.

Bit 30 CEN2: DAC channel2 calibration enable
This bit is set and cleared by software to enable/disable DAC channel2 calibration, it can be
written only if EN2 bit is set to 0 into DAC_CR (the calibration mode can be entered/exit only
when the DAC channel is disabled) Otherwise, the write operation is ignored.
0: DAC channel2 in Normal operating mode
1: DAC channel2 in calibration mode
Note: This bit is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bit 29 DMAUDRIE2: DAC channel2 DMA underrun interrupt enable
This bit is set and cleared by software.
0: DAC channel2 DMA underrun interrupt disabled
1: DAC channel2 DMA underrun interrupt enabled
Note: This bit is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bit 28 DMAEN2: DAC channel2 DMA enable
This bit is set and cleared by software.
0: DAC channel2 DMA mode disabled
1: DAC channel2 DMA mode enabled
Note: This bit is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.

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Bits 27:24 MAMP2[3:0]: DAC channel2 mask/amplitude selector

These bits are written by software to select mask in wave generation mode or amplitude in
triangle generation mode.
0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1
0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
Note: These bits are available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bits 23:22 WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable
These bits are set/reset by software.
00: wave generation disabled
01: Noise wave generation enabled
1x: Triangle wave generation enabled
Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
These bits are available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bits 21:18 TSEL2[3:0]: DAC channel2 trigger selection
These bits select the external event used to trigger DAC channel2
0000: SWTRIG2
0001: dac_ch2_trig1
0010: dac_ch2_trig2
...
1111: dac_ch2_trig15
Refer to the trigger selection tables in Section 22.4.6: DAC trigger selection for details on
trigger configuration and mapping.
Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled).
These bits are available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bit 17 TEN2: DAC channel2 trigger enable
This bit is set and cleared by software to enable/disable DAC channel2 trigger
0: DAC channel2 trigger disabled and data written into the DAC_DHR2 register are
transferred one APB1 clock cycle later to the DAC_DOR2 register
1: DAC channel2 trigger enabled and data from the DAC_DHR2 register are transferred
three APB1 clock cycles later to the DAC_DOR2 register
Note: When software trigger is selected, the transfer from the DAC_DHR2 register to the
DAC_DOR2 register takes only one APB1 clock cycle.
These bits are available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.

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Bit 16 EN2: DAC channel2 enable

This bit is set and cleared by software to enable/disable DAC channel2.
0: DAC channel2 disabled
1: DAC channel2 enabled
Note: These bits are available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bit 15 HFSEL: High frequency interface mode enable
This bit is set and cleared by software to enable/disable DAC interface high speed mode
This bit need to be set when APB1 clock frequency is higher than 80 MHz.
0: High frequency interface mode disabled
1: High frequency interface mode enabled
Bit 14 CEN1: DAC channel1 calibration enable
This bit is set and cleared by software to enable/disable DAC channel1 calibration, it can be
written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when
the DAC channel is disabled) Otherwise, the write operation is ignored.
0: DAC channel1 in Normal operating mode
1: DAC channel1 in calibration mode
Bit 13 DMAUDRIE1: DAC channel1 DMA Underrun Interrupt enable
This bit is set and cleared by software.
0: DAC channel1 DMA Underrun Interrupt disabled
1: DAC channel1 DMA Underrun Interrupt enabled
Bit 12 DMAEN1: DAC channel1 DMA enable
This bit is set and cleared by software.
0: DAC channel1 DMA mode disabled
1: DAC channel1 DMA mode enabled
Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector
These bits are written by software to select mask in wave generation mode or amplitude in
triangle generation mode.
0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1
0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
Bits 7:6 WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable
These bits are set and cleared by software.
00: wave generation disabled
01: Noise wave generation enabled
1x: Triangle wave generation enabled
Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).

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Bits 5:2 TSEL1[3:0]: DAC channel1 trigger selection

These bits select the external event used to trigger DAC channel1
0000: SWTRIG1
0001: dac_ch1_trig1
0010: dac_ch1_trig2
...
1111: dac_ch1_trig15
Refer to the trigger selection tables in Section 22.4.6: DAC trigger selection for details on
trigger configuration and mapping.
Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).
Bit 1 TEN1: DAC channel1 trigger enable
This bit is set and cleared by software to enable/disable DAC channel1 trigger.
0: DAC channel1 trigger disabled and data written into the DAC_DHR1 register are
transferred one APB1 clock cycle later to the DAC_DOR1 register
1: DAC channel1 trigger enabled and data from the DAC_DHR1 register are transferred
three APB1 clock cycles later to the DAC_DOR1 register
Note: When software trigger is selected, the transfer from the DAC_DHR1 register to the
DAC_DOR1 register takes only one APB1 clock cycle.
Bit 0 EN1: DAC channel1 enable
This bit is set and cleared by software to enable/disable DAC channel1.
0: DAC channel1 disabled
1: DAC channel1 enabled

22.7.2 DAC software trigger register (DAC_SWTRGR)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWTRIG2 SWTRIG1
w w

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Bits 31:2 Reserved, must be kept at reset value.

Bit 1 SWTRIG2: DAC channel2 software trigger
This bit is set by software to trigger the DAC in software trigger mode.
0: No trigger
1: Trigger
Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2
register value has been loaded into the DAC_DOR2 register.
This bit is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bit 0 SWTRIG1: DAC channel1 software trigger
This bit is set by software to trigger the DAC in software trigger mode.
0: No trigger
1: Trigger
Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1
register value has been loaded into the DAC_DOR1 register.

22.7.3 DAC channel1 12-bit right-aligned data holding register

(DAC_DHR12R1)
Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. DACC1DHR[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data
These bits are written by software. They specify 12-bit data for DAC channel1.

22.7.4 DAC channel1 12-bit left aligned data holding register

(DAC_DHR12L1)
Address offset: 0x0C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR[11:0] Res. Res. Res. Res.
rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:16 Reserved, must be kept at reset value.

Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data
These bits are written by software.
They specify 12-bit data for DAC channel1.
Bits 3:0 Reserved, must be kept at reset value.

22.7.5 DAC channel1 8-bit right aligned data holding register

(DAC_DHR8R1)
Address offset: 0x10
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. DACC1DHR[7:0]
rw rw rw rw rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data
These bits are written by software. They specify 8-bit data for DAC channel1.

22.7.6 DAC channel2 12-bit right aligned data holding register

(DAC_DHR12R2)
This register is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Address offset: 0x14
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. DACC2DHR[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data
These bits are written by software. They specify 12-bit data for DAC channel2.

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22.7.7 DAC channel2 12-bit left aligned data holding register

(DAC_DHR12L2)
This register is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Address offset: 0x18
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR[11:0] Res. Res. Res. Res.
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:4 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data
These bits are written by software which specify 12-bit data for DAC channel2.
Bits 3:0 Reserved, must be kept at reset value.

22.7.8 DAC channel2 8-bit right-aligned data holding register

(DAC_DHR8R2)
This register is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Address offset: 0x1C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. DACC2DHR[7:0]
rw rw rw rw rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data
These bits are written by software which specifies 8-bit data for DAC channel2.

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22.7.9 Dual DAC 12-bit right-aligned data holding register

(DAC_DHR12RD)
Address offset: 0x20
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. DACC2DHR[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. DACC1DHR[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data
These bits are written by software which specifies 12-bit data for DAC channel2.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data
These bits are written by software which specifies 12-bit data for DAC channel1.

22.7.10 Dual DAC 12-bit left aligned data holding register

(DAC_DHR12LD)
Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR[11:0] Res. Res. Res. Res.
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR[11:0] Res. Res. Res. Res.
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:20 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data

These bits are written by software which specifies 12-bit data for DAC channel2.
Bits 19:16 Reserved, must be kept at reset value.
Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data
These bits are written by software which specifies 12-bit data for DAC channel1.
Bits 3:0 Reserved, must be kept at reset value.

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22.7.11 Dual DAC 8-bit right aligned data holding register

(DAC_DHR8RD)
Address offset: 0x28
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR[7:0] DACC1DHR[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data
These bits are written by software which specifies 8-bit data for DAC channel2.
Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data
These bits are written by software which specifies 8-bit data for DAC channel1.

22.7.12 DAC channel1 data output register (DAC_DOR1)

Address offset: 0x2C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. DACC1DOR[11:0]
r r r r r r r r r r r r

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 DACC1DOR[11:0]: DAC channel1 data output
These bits are read-only, they contain data output for DAC channel1.

RM0432 Rev 6 753/2301

762
Digital-to-analog converter (DAC) RM0432

22.7.13 DAC channel2 data output register (DAC_DOR2)

This register is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Address offset: 0x30
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. DACC2DOR[11:0]
r r r r r r r r r r r r

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 DACC2DOR[11:0]: DAC channel2 data output
These bits are read-only, they contain data output for DAC channel2.

22.7.14 DAC status register (DAC_SR)

Address offset: 0x34
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CAL_ DMAU
BWST2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
FLAG2 DR2
r r rc_w1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAL_ DMAU
BWST1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
FLAG1 DR1
r r rc_w1

754/2301 RM0432 Rev 6

RM0432 Digital-to-analog converter (DAC)

Bit 31 BWST2: DAC channel2 busy writing sample time flag

This bit is systematically set just after Sample and hold mode enable. It is set each time the
software writes the register DAC_SHSR2, It is cleared by hardware when the write operation
of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization).
0:There is no write operation of DAC_SHSR2 ongoing: DAC_SHSR2 can be written
1:There is a write operation of DAC_SHSR2 ongoing: DAC_SHSR2 cannot be written
Note: This bit is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bit 30 CAL_FLAG2: DAC channel2 calibration offset status
This bit is set and cleared by hardware
0: calibration trimming value is lower than the offset correction value
1: calibration trimming value is equal or greater than the offset correction value
Note: This bit is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bit 29 DMAUDR2: DAC channel2 DMA underrun flag
This bit is set by hardware and cleared by software (by writing it to 1).
0: No DMA underrun error condition occurred for DAC channel2
1: DMA underrun error condition occurred for DAC channel2 (the currently selected trigger is
driving DAC channel2 conversion at a frequency higher than the DMA service capability
rate).
Note: This bit is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bit 28 Reserved, must be kept at reset value.
Bit 27 Reserved, must be kept at reset value.
Bits 26:16 Reserved, must be kept at reset value.
Bit 15 BWST1: DAC channel1 busy writing sample time flag
This bit is systematically set just after Sample and hold mode enable and is set each time the
software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of
DAC_SHSR1 is complete. (It takes about 3 LSI periods of synchronization).
0:There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
1:There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written
Bit 14 CAL_FLAG1: DAC channel1 calibration offset status
This bit is set and cleared by hardware
0: calibration trimming value is lower than the offset correction value
1: calibration trimming value is equal or greater than the offset correction value
Bit 13 DMAUDR1: DAC channel1 DMA underrun flag
This bit is set by hardware and cleared by software (by writing it to 1).
0: No DMA underrun error condition occurred for DAC channel1
1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is
driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)
Bit 12 Reserved, must be kept at reset value.
Bit 11 Reserved, must be kept at reset value.
Bits 10:0 Reserved, must be kept at reset value.

RM0432 Rev 6 755/2301

762
Digital-to-analog converter (DAC) RM0432

22.7.15 DAC calibration control register (DAC_CCR)

Address offset: 0x38
Reset value: 0x00XX 00XX

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OTRIM2[4:0]
rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OTRIM1[4:0]
rw rw rw rw rw

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:16 OTRIM2[4:0]: DAC channel2 offset trimming value
These bits are available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bits 15:5 Reserved, must be kept at reset value.
Bits 4:0 OTRIM1[4:0]: DAC channel1 offset trimming value

22.7.16 DAC mode control register (DAC_MCR)

Address offset: 0x3C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MODE2[2:0]

rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MODE1[2:0]

rw rw rw

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 Reserved, must be kept at reset value.
Bit 24 Reserved, must be kept at reset value.
Bits 23:19 Reserved, must be kept at reset value.

756/2301 RM0432 Rev 6

RM0432 Digital-to-analog converter (DAC)

Bits 18:16 MODE2[2:0]: DAC channel2 mode

These bits can be written only when the DAC is disabled and not in the calibration mode
(when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write
operation is ignored.
They can be set and cleared by software to select the DAC channel2 mode:
– DAC channel2 in Normal mode
000: DAC channel2 is connected to external pin with Buffer enabled
001: DAC channel2 is connected to external pin and to on chip peripherals with buffer
enabled
010: DAC channel2 is connected to external pin with buffer disabled
011: DAC channel2 is connected to on chip peripherals with Buffer disabled
– DAC channel2 in Sample and hold mode
100: DAC channel2 is connected to external pin with Buffer enabled
101: DAC channel2 is connected to external pin and to on chip peripherals with Buffer
enabled
110: DAC channel2 is connected to external pin and to on chip peripherals with Buffer
disabled
111: DAC channel2 is connected to on chip peripherals with Buffer disabled
Note: This register can be modified only when EN2=0.
Refer to Section 22.3: DAC implementation for the availability of DAC channel2.
Bits 15:14 Reserved, must be kept at reset value.
Bits 13:10 Reserved, must be kept at reset value.
Bit 9 Reserved, must be kept at reset value.
Bit 8 Reserved, must be kept at reset value.
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 MODE1[2:0]: DAC channel1 mode
These bits can be written only when the DAC is disabled and not in the calibration mode
(when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write
operation is ignored.
They can be set and cleared by software to select the DAC channel1 mode:
– DAC channel1 in Normal mode
000: DAC channel1 is connected to external pin with Buffer enabled
001: DAC channel1 is connected to external pin and to on chip peripherals with Buffer
enabled
010: DAC channel1 is connected to external pin with Buffer disabled
011: DAC channel1 is connected to on chip peripherals with Buffer disabled
– DAC channel1 in sample & hold mode
100: DAC channel1 is connected to external pin with Buffer enabled
101: DAC channel1 is connected to external pin and to on chip peripherals with Buffer
enabled
110: DAC channel1 is connected to external pin and to on chip peripherals with Buffer
disabled
111: DAC channel1 is connected to on chip peripherals with Buffer disabled
Note: This register can be modified only when EN1=0.

RM0432 Rev 6 757/2301

762
Digital-to-analog converter (DAC) RM0432

22.7.17 DAC channel1 sample and hold sample time register

(DAC_SHSR1)
Address offset: 0x40
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. TSAMPLE1[9:0]
rw rw rw rw rw rw rw rw rw rw

Bits 31:10 Reserved, must be kept at reset value.

Bits 9:0 TSAMPLE1[9:0]: DAC channel1 sample time (only valid in Sample and hold mode)
These bits can be written when the DAC channel1 is disabled or also during normal operation.
in the latter case, the write can be done only when BWST1 of DAC_SR register is low, If
BWST1=1, the write operation is ignored.

Note: It represents the number of LSI clocks to perform a sample phase. Sampling time =
(TSAMPLE1[9:0] + 1) x LSI clock period.

22.7.18 DAC channel2 sample and hold sample time register

(DAC_SHSR2)
This register is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Address offset: 0x44
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. TSAMPLE2[9:0]
rw rw rw rw rw rw rw rw rw rw

Bits 31:10 Reserved, must be kept at reset value.

Bits 9:0 TSAMPLE2[9:0]: DAC channel2 sample time (only valid in Sample and hold mode)
These bits can be written when the DAC channel2 is disabled or also during normal
operation. in the latter case, the write can be done only when BWST2 of DAC_SR register is
low, if BWST2=1, the write operation is ignored.

Note: It represents the number of LSI clocks to perform a sample phase. Sampling time =
(TSAMPLE1[9:0] + 1) x LSI clock period.

758/2301 RM0432 Rev 6

RM0432 Digital-to-analog converter (DAC)

22.7.19 DAC sample and hold time register (DAC_SHHR)

Address offset: 0x48
Reset value: 0x0001 0001

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. THOLD2[9:0]
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. THOLD1[9:0]
rw rw rw rw rw rw rw rw rw rw

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:16 THOLD2[9:0]: DAC channel2 hold time (only valid in Sample and hold mode).
Hold time= (THOLD[9:0]) x LSI clock period
Note: This register can be modified only when EN2=0.
These bits are available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:0 THOLD1[9:0]: DAC channel1 hold time (only valid in Sample and hold mode)
Hold time= (THOLD[9:0]) x LSI clock period
Note: This register can be modified only when EN1=0.

Note: These bits can be written only when the DAC channel is disabled and in Normal operating
mode (when bit ENx=0 and bit CENx=0 in the DAC_CR register). If ENx=1 or CENx=1 the
write operation is ignored.

22.7.20 DAC sample and hold refresh time register (DAC_SHRR)

Address offset: 0x4C
Reset value: 0x0001 0001

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. TREFRESH2[7:0]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. TREFRESH1[7:0]
rw rw rw rw rw rw rw rw

RM0432 Rev 6 759/2301

762
Digital-to-analog converter (DAC) RM0432

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 TREFRESH2[7:0]: DAC channel2 refresh time (only valid in Sample and hold mode)
Refresh time= (TREFRESH[7:0]) x LSI clock period
Note: This register can be modified only when EN2=0.
These bits are available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 TREFRESH1[7:0]: DAC channel1 refresh time (only valid in Sample and hold mode)
Refresh time= (TREFRESH[7:0]) x LSI clock period
Note: This register can be modified only when EN1=0.

Note: These bits can be written only when the DAC channel is disabled and in Normal operating
mode (when bit ENx=0 and bit CENx=0 in the DAC_CR register). If ENx=1 or CENx=1 the
write operation is ignored.

760/2301 RM0432 Rev 6

 0x34
0x30
0x28
0x24
0x20
0x18
0x14
0x10
0x08
0x04
0x00

0x2C
0x1C
0x0C
Offset
RM0432

22.7.21

DAC_
DAC_
DAC_
DAC_
DAC_
DAC_
DAC_
DAC_
DAC_
DAC_
DAC_
DAC_

DOR2
DOR1
name

DHR8R2
DHR8R1

DAC_SR
DHR8RD
DAC_CR

SWTRGR

DHR12L2
DHR12L1

DHR12R2
DHR12R1

DHR12LD
DHR12RD
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

0
0
BWST2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31

0
0
0
CAL_FLAG2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CEN2 30

0
0
0
DMAUDR2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMAUDRIE2 29

0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMAEN2 28

0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27

0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
MAMP2[3:0]

0
0
0
DAC register map

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25

0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24

DACC2DHR[11:0]

0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
WAVE2[2:0]

0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22

0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TSEL23 21

0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TSEL22 20

DACC2DHR[11:0]

0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TSEL21 19
Table 151 summarizes the DAC registers.

0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TSEL20 18

0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TEN2 17

RM0432 Rev 6
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EN2 16

0
0
0

0
0
0
BWST1 Res. Res. Res. Res. Res. Res. Res. Res. HFSEL 15

0
0
0

0
0
0
CAL_FLAG1 Res. Res. Res. Res. Res. Res. Res. Res. CEN1 14

0
0
0

0
0
0

DMAUDR1 Res. Res. Res. Res. Res. Res. Res. Res. DMAUDRIE1 13

0
0

0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. DMAEN1 12

0
0

0
0
0
0
0
0
0
0

Res. Res. Res. Res. 11

0
0
0

0
0
0
0
0
0
0
Table 151. DAC register map and reset values

Res. Res. Res. Res. 10

DACC2DHR[7:0]
MAMP1[3:0]

0
0

0
0
0
0
0
0
0
0

Res. Res. Res. Res. 9

0
0
0

0
0
0
0
0
0
0

Res. Res. Res. Res. 8

DACC1DHR[11:0]
DACC2DHR[11:0]
DACC1DHR[11:0]

0
0

0
0
0
0
0

0
0
0

0
0

Res. Res. 7
WAVE1[1:0]

0
0
0

0
0
0
0
0

0
0
0
0

Res. Res. 6

0
0
0

0
0
0
0
0

0
0
0
0

Res. Res. TSEL13 5

0
0
0

0
0
0
0
0
0

0
0
0

Res. Res. TSEL12 4

DACC1DHR[11:0]
DACC2DHR[11:0]
DACC1DHR[11:0]

DACC2DOR[11:0]
DACC1DOR[11:0]
0
0

0
0
0
0
0
0
0

Res. Res. Res. Res. Res. TSEL11 3

0
0

0
0
0
0
0
0
0

Res. Res. Res. Res. Res. TSEL10 2

DACC1DHR[7:0]
DACC2DHR[7:0]
DACC1DHR[7:0]

0
0

0
0
0
0
0
0
0
0

Res. Res. Res. Res. SWTRIG2 TEN1 1

0
0

0
0
0
0
0
0
0
0

Res. Res. Res. Res. SWTRIG1 EN1 0

761/2301
Digital-to-analog converter (DAC)

762
 0x48
0x44
0x40
0x38

0x4C
0x3C
Offset

762/2301
DAC_
DAC_
DAC_
DAC_

SHRR
SHHR
SHSR2
SHSR1
name

DAC_CCR

DAC_MCR
Register

Reset value
Reset value
Reset value
Reset value
Reset value

Reset value
Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. 26

0
Digital-to-analog converter (DAC)

Res. Res. Res. Res. Res. 25

0
Res. Res. Res. Res. Res. 24

0
0
Res. Res. Res. Res. 23

0
0
Res. Res. Res. Res. 22

0
0
Res. Res. Res. Res. 21

0
0
X

Res. Res. Res. 20

THOLD2[9:0]

0
0
X

Res. Res. Res. 19

0
0

0
X

Res. Res. 18
TREFRESH2[7:0]

0
0

0
X

Res. Res. 17
[2:0]
OTRIM2[4:0]

RM0432 Rev 6
MODE2

1
0

1
X

Res. Res. 16
Res. Res. Res. Res. Res. Res. 15
Res. Res. Res. Res. Res. Res. 14
Res. Res. Res. Res. Res. Res. 13
Res. Res. Res. Res. Res. Res. 12
Res. Res. Res. Res. Res. Res. 11
Res. Res. Res. Res. Res. Res. 10
0
0
0

Res. Res. Res. 9

0
0
0

Refer to Section 2.2 on page 91 for the register boundary addresses.

Res. Res. Res. 8

Table 151. DAC register map and reset values (continued)

0
0
0
0

Res. Res. 7
0
0
0
0

Res. Res. 6
0
0
0
0

Res. Res. 5
0
0
0
0
X

Res. 4
0
0
0
0
X

THOLD1[9:0]

Res. 3
TSAMPLE2[9:0]
TSAMPLE1[9:0]

0
0
0

0
0
X

2
TREFRESH1[7:0]

0
0
0

0
0
X

1
[2:0]
OTRIM1[4:0]

MODE1

1
1
0

0
0
X

0
RM0432
RM0432 Voltage reference buffer (VREFBUF)

23 Voltage reference buffer (VREFBUF)

23.1 Introduction
The STM32L4+ Series devices embed a voltage reference buffer which can be used as
voltage reference for ADCs, DACs and also as voltage reference for external components
through the VREF+ pin. When the VREF+ pin is double-bonded with VDDA pin in a
package, the voltage reference buffer is not available and must be kept disabled (refer to
datasheet for packages pinout description).

23.2 VREFBUF functional description

The internal voltage reference buffer supports two voltages(a), which are configured with
VRS bits in the VREFBUF_CSR register:
• VRS = 0: VREF_OUT1 around 2.048 V.
• VRS = 1: VREF_OUT2 around 2.5 V.
The internal voltage reference can be configured in four different modes depending on
ENVR and HIZ bits configuration. These modes are provided in the table below:

Table 152. VREF buffer modes

ENVR HIZ VREF buffer configuration

VREFBUF buffer OFF:

0 0
– VREF+ pin pulled-down to VSSA
External voltage reference mode (default value):
0 1 – VREFBUF buffer OFF
– VREF+ pin input mode
Internal voltage reference mode:
1 0 – VREFBUF buffer ON
– VREF+ pin connected to VREFBUF buffer output
Hold mode:
– VREFBUF buffer OFF
1 1
– VREF+ pin floating. The voltage is held with the external capacitor
– VRR detection disabled and VRR bit keeps last state

After enabling the VREFBUF by setting ENVR bit and clearing HIZ bit in the VREFBUF_CSR register,
the user must wait until VRR bit is set, meaning that the voltage reference output has reached its
expected value.

a. The minimum VDDA voltage depends on VRS setting, refer to the product datasheet.

RM0432 Rev 6 763/2301

765
Voltage reference buffer (VREFBUF) RM0432

23.3 VREFBUF registers

23.3.1 VREFBUF control and status register (VREFBUF_CSR)

Address offset: 0x00
Reset value: 0x0000 0002

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. VRR VRS HIZ ENVR
r rw rw rw

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 VRR: Voltage reference buffer ready
0: the voltage reference buffer output is not ready.
1: the voltage reference buffer output reached the requested level.
Bit 2 VRS: Voltage reference scale
This bit selects the value generated by the voltage reference buffer.
0: Voltage reference set to VREF_OUT1 (around 2.048 V).
1: Voltage reference set to VREF_OUT2 (around 2.5 V).
Bit 1 HIZ: High impedance mode
This bit controls the analog switch to connect or not the VREF+ pin.
0: VREF+ pin is internally connected to the voltage reference buffer output.
1: VREF+ pin is high impedance.
Refer to Table 152: VREF buffer modes for the mode descriptions depending on ENVR bit
configuration.
Bit 0 ENVR: Voltage reference buffer mode enable
This bit is used to enable the voltage reference buffer mode.
0: Internal voltage reference mode disable (external voltage reference mode).
1: Internal voltage reference mode (reference buffer enable or hold mode) enable.

764/2301 RM0432 Rev 6

RM0432 Voltage reference buffer (VREFBUF)

23.3.2 VREFBUF calibration control register (VREFBUF_CCR)

Address offset: 0x04
Reset value: 0x0000 00XX

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TRIM[5:0]
rw rw rw rw rw rw

Bits 31:6 Reserved, must be kept at reset value.

Bits 5:0 TRIM[5:0]: Trimming code
These bits are automatically initialized after reset with the trimming value stored in the Flash
memory during the production test. Writing into these bits allows the tuning of the internal
reference buffer voltage.

23.3.3 VREFBUF register map

The following table gives the VREFBUF register map and the reset values.

Table 153. VREFBUF register map and reset values

Offset Register name

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0 ENVR
VRR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

VRS
HIZ
VREFBUF_CSR
0x00
Reset value 0 0 1 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

VREFBUF_CCR TRIM[5:0]
0x04
Reset value x x x x x x

Refer to Section 2.2 on page 91 for the register boundary addresses.

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24 Digital camera interface (DCMI)

24.1 Introduction
The digital camera is a synchronous parallel interface able to receive a high-speed data flow
from an external 8-, 10-, 12- or 14-bit CMOS camera module. It supports different data
formats: YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG).

24.2 DCMI main features

• 8-, 10-, 12- or 14-bit parallel interface
• Embedded/external line and frame synchronization
• Continuous or snapshot mode
• Crop feature
• Supports the following data formats:
– 8/10/12/14-bit progressive video: either monochrome or raw Bayer
– YCbCr 4:2:2 progressive video
– RGB 565 progressive video
– Compressed data: JPEG

24.3 DCMI functional description

The digital camera interface is a synchronous parallel interface that can receive high-speed
data flows. It consists of up to 14 data lines (DCMI_D[13:0]) and a pixel clock line
(DCMI_PIXCLK). The pixel clock has a programmable polarity, so that data can be captured
on either the rising or the falling edge of the pixel clock.
The data are packed into a 32-bit data register (DCMI_DR) and then transferred through a
general-purpose DMA channel. The image buffer is managed by the DMA, not by the
camera interface.
The data received from the camera can be organized in lines/frames (raw YUB/RGB/Bayer
modes) or can be a sequence of JPEG images. To enable JPEG image reception, the JPEG
bit (bit 3 of DCMI_CR register) must be set.
The data flow is synchronized either by hardware using the optional DCMI_HSYNC
(horizontal synchronization) and DCMI_VSYNC (vertical synchronization) signals or by
synchronization codes embedded in the data flow.

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24.3.1 DCMI block diagram

Figure 167 shows the DCMI block diagram.

Figure 167. DCMI block diagram

DMA
Control/Statusregister
interface

AHB
interface

FIFO
Data Synchronizer DCMI_PIXCLK
Data
extraction
formatter

DCMI_D[13:0], DCMI_HSYNC, DCMI_VSYNC ai5604c

Figure 168. Top-level block diagram

DCMI_D[13:0]

HCLK DCMI_PIXCLK External

DCMI_HSYNC interface
DCMI_VSYNC

Interrupt DCMI_IT DCMI

controller

DMA_REQ
ai15603c

24.3.2 DCMI pins

The following table shows DCMI pins.

Table 154. DCMI input/output pins

Mode Pin name Signal type Description

8 bits DCMI_D[7:0]
10 bits DCMI_D[9:0]
Inputs DCMI data
12 bits DCMI_D[11:0]
14 bits DCMI_D[13:0]
DCMI_PIXCLK Input Pixel clock
DCMI_HSYNC Input Horizontal synchronization / Data valid
DCMI_VSYNC Input Vertical synchronization

24.3.3 DCMI clocks

The digital camera interface uses two clock domains, DCMI_PIXCLK and HCLK. The
signals generated with DCMI_PIXCLK are sampled on the rising edge of HCLK once they
are stable. An enable signal is generated in the HCLK domain, to indicate that data coming

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from the camera are stable and can be sampled. The maximum DCMI_PIXCLK period must
be higher than 2.5 HCLK periods.

24.3.4 DCMI DMA interface

The DMA interface is active when the CAPTURE bit of the DCMI_CR register is set. A DMA
request is generated each time the camera interface receives a complete 32-bit data block
in its register.

24.3.5 DCMI physical interface

The interface is composed of 11/13/15/17 inputs. Only the Slave mode is supported.
The camera interface can capture 8-bit, 10-bit, 12-bit or 14-bit data depending on the
EDM[1:0] bits of the DCMI_CR register. If less than 14 bits are used, the unused input pins
must be connected to ground.
DCMI pins are shown in Table 154.
The data are synchronous with DCMI_PIXCLK and change on the rising/falling edge of the
pixel clock depending on the polarity.
The DCMI_HSYNC signal indicates the start/end of a line.
The DCMI_VSYNC signal indicates the start/end of a frame

Figure 169. DCMI signal waveforms

DCMI_PIXCLK

DCMI_D[13:0]

DCMI_HSYNC

DCMI_VSYNC
ai15606c

1. The capture edge of DCMI_PIXCLK is the falling edge, the active state of DCMI_HSYNC and
DCMI_VSYNC is 1.
2. DCMI_HSYNC and DCMI_VSYNC can change states at the same time.

8-bit data
When EDM[1:0] = 00 in DCMI_CR the interface captures 8 LSBs at its input (DCMI_D[7:0])
and stores them as 8-bit data. The DCMI_D[13:8] inputs are ignored. In this case, to capture
a 32-bit word, the camera interface takes four pixel clock cycles.
The first captured data byte is placed in the LSB position in the 32-bit word and the 4th
captured data byte is placed in the MSB position in the 32-bit word. The table below gives
an example of the positioning of captured data bytes in two 32-bit words.

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Table 155. Positioning of captured data bytes in 32-bit words (8-bit width)
Byte address 31:24 23:16 15:8 7:0

0 Dn+3[7:0] Dn+2[7:0] Dn+1[7:0] Dn[7:0]

4 Dn+7[7:0] Dn+6[7:0] Dn+5[7:0] Dn+4[7:0]

10-bit data
When EDM[1:0] = 01 in DCMI_CR, the camera interface captures 10-bit data at its input
DCMI_D[9:0] and stores them as the 10 least significant bits of a 16-bit word. The remaining
most significant bits of the DCMI_DR register (bits 11 to 15) are cleared to zero. So, in this
case, a 32-bit data word is made up every two pixel clock cycles.
The first captured data are placed in the LSB position in the 32-bit word and the 2nd
captured data are placed in the MSB position in the 32-bit word as shown in the table below.

Table 156. Positioning of captured data bytes in 32-bit words (10-bit width)
Byte address 31:26 25:16 15:10 9:0

0 0 Dn+1[9:0] 0 Dn[9:0]
4 0 Dn+3[9:0] 0 Dn+2[9:0]

12-bit data
When EDM[1:0] = 10 in DCMI_CR, the camera interface captures the 12-bit data at its input
DCMI_D[11:0] and stores them as the 12 least significant bits of a 16-bit word. The
remaining most significant bits are cleared to zero. So, in this case a 32-bit data word is
made up every two pixel clock cycles.
The first captured data are placed in the LSB position in the 32-bit word and the 2nd
captured data are placed in the MSB position in the 32-bit word as shown in the table below.

Table 157. Positioning of captured data bytes in 32-bit words (12-bit width)
Byte address 31:28 27:16 15:12 11:0

0 0 Dn+1[11:0] 0 Dn[11:0]
4 0 Dn+3[11:0] 0 Dn+2[11:0]

14-bit data
When EDM[1:0] = 11 in DCMI_CR, the camera interface captures the 14-bit data at its input
DCMI_D[13:0] and stores them as the 14 least significant bits of a 16-bit word. The
remaining most significant bits are cleared to zero. So, in this case a 32-bit data word is
made up every two pixel clock cycles.
The first captured data are placed in the LSB position in the 32-bit word and the 2nd
captured data are placed in the MSB position in the 32-bit word as shown in the table below.

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Table 158. Positioning of captured data bytes in 32-bit words (14-bit width)
Byte address 31:30 29:16 15:14 13:0

0 0 Dn+1[13:0] 0 Dn[13:0]
4 0 Dn+3[13:0] 0 Dn+2[13:0]

24.3.6 DCMI synchronization

The digital camera interface supports embedded or hardware (DCMI_HSYNC and
DCMI_VSYNC) synchronization. When embedded synchronization is used, it is up to the
digital camera module to make sure that the 0x00 and 0xFF values are used ONLY for
synchronization (not in data). Embedded synchronization codes are supported only for the
8-bit parallel data interface width (that is, in the DCMI_CR register, the EDM[1:0] bits must
be cleared).
For compressed data, the DCMI supports only the hardware synchronization mode. In this
case, DCMI_VSYNC is used as a start/end of the image, and DCMI_HSYNC is used as a
Data Valid signal. Figure 170 shows the corresponding timing diagram.

Figure 170. Timing diagram

Padding data
at the end of the JPEG stream
Beginning of JPEG stream Programmable
JPEG packet size

JPEG data

End of JPEG stream

DCMI_HSYNC

DCMI_VSYNC

Packet dispatching depends on the image content.

This results in a variable blanking duration.

JPEG packet data

ai15944b

Hardware synchronization mode

In hardware synchronization mode, the two synchronization signals
(DCMI_HSYNC/DCMI_VSYNC) are used.
Depending on the camera module/mode, data may be transmitted during horizontal/vertical
synchronization periods. The DCMI_HSYNC/DCMI_VSYNC signals act like blanking
signals since all the data received during DCMI_HSYNC/DCMI_VSYNC active periods are
ignored.
In order to correctly transfer images into the DMA/RAM buffer, data transfer is synchronized
with the DCMI_VSYNC signal. When the hardware synchronization mode is selected, and

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capture is enabled (CAPTURE bit set in DCMI_CR), data transfer is synchronized with the
deactivation of the DCMI_VSYNC signal (next start of frame).
Transfer can then be continuous, with successive frames transferred by DMA to successive
buffers or the same/circular buffer. To allow the DMA management of successive frames, a
VSIF (Vertical synchronization interrupt flag) is activated at the end of each frame.

Embedded data synchronization mode

In this synchronization mode, the data flow is synchronized using 32-bit codes embedded in
the data flow. These codes use the 0x00/0xFF values that are not used in data anymore.
There are 4 types of codes, all with a 0xFF0000XY format. The embedded synchronization
codes are supported only in 8-bit parallel data width capture (in the DCMI_CR register, the
EDM[1:0] bits must be cleared). For other data widths, this mode generates unpredictable
results and must not be used.
Note: Camera modules can have 8 such codes (in interleaved mode). For this reason, the
interleaved mode is not supported by the camera interface (otherwise, every other
half-frame would be discarded).
• Mode 2
Four embedded codes signal the following events
– Frame start (FS)
– Frame end (FE)
– Line start (LS)
– Line end (LE)
The XY values in the 0xFF0000XY format of the four codes are programmable (see
Section 24.5.7: DCMI embedded synchronization code register (DCMI_ESCR)).
A 0xFF value programmed as a “frame end” means that all the unused codes are
interpreted as valid frame end codes.
In this mode, once the camera interface has been enabled, the frame capture starts
after the first occurrence of the frame end (FE) code followed by a frame start (FS)
code.
• Mode 1
An alternative coding is the camera mode 1. This mode is ITU656 compatible.
The codes signal another set of events:
– SAV (active line) - line start
– EAV (active line) - line end
– SAV (blanking) - end of line during interframe blanking period
– EAV (blanking) - end of line during interframe blanking period
This mode can be supported by programming the following codes:
• FS ≤ 0xFF
• FE ≤ 0xFF
• LS ≤ SAV (active)
• LE ≤ EAV (active)
An embedded unmask code is also implemented for frame/line start and frame/line end
codes. Using it, it is possible to compare only the selected unmasked bits with the
programmed code. A bit can therefore be selected to compare in the embedded code and

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detect a frame/line start or frame/line end. This means that there can be different codes for
the frame/line start and frame/line end with the unmasked bit position remaining the same.

Example
FS = 0xA5
Unmask code for FS = 0x10
In this case the frame start code is embedded in the bit 4 of the frame start code.

24.3.7 DCMI capture modes

This interface supports two types of capture: snapshot (single frame) and continuous grab.

Snapshot mode (single frame)

In this mode, a single frame is captured (CM = 1 of the DCMI_CR register). After the
CAPTURE bit is set in DCMI_CR, the interface waits for the detection of a start of frame
before sampling the data. The camera interface is automatically disabled (CAPTURE bit
cleared in DCMI_CR) after receiving the first complete frame. An interrupt is generated
(IT_FRAME) if it is enabled.
In case of an overrun, the frame is lost and the CAPTURE bit is cleared.

Figure 171. Frame capture waveforms in snapshot mode

DCMI_HSYNC

DCMI_VSYNC

Frame 2
Frame 1 captured not captured

ai15832b

1. Here, the active state of DCMI_HSYNC and DCMI_VSYNC is 1.

2. DCMI_HSYNC and DCMI_VSYNC can change states at the same time.

Continuous grab mode

In this mode (CM bit = 0 in DCMI_CR), once the CAPTURE bit has been set in DCMI_CR,
the grabbing process starts on the next DCMI_VSYNC or embedded frame start depending
on the mode. The process continues until the CAPTURE bit is cleared in DCMI_CR. Once
the CAPTURE bit has been cleared, the grabbing process continues until the end of the
current frame.

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Figure 172. Frame capture waveforms in continuous grab mode

DCMI_HSYNC

DCMI_VSYNC

Frame 1 captured Frame 2 captured

ai15833b

1. Here, the active state of DCMI_HSYNC and DCMI_VSYNC is 1.

2. DCMI_HSYNC and DCMI_VSYNC can change states at the same time.
In continuous grab mode, the FCRC[1:0] bits in DCMI_CR can be configured to grab all
pictures, every second picture or one out of four pictures to decrease the frame capture
rate.
Note: In the hardware synchronization mode (ESS = 0 in DCMI_CR), the IT_VSYNC interrupt is
generated (if enabled) even when CAPTURE = 0 in DCMI_CR so, to reduce the frame
capture rate even further, the IT_VSYNC interrupt can be used to count the number of
frames between 2 captures in conjunction with the Snapshot mode. This is not allowed by
embedded data synchronization mode.

24.3.8 DCMI crop feature

With the crop feature, the camera interface can select a rectangular window from the
received image. The start (upper left corner) coordinates and size (horizontal dimension in
number of pixel clocks and vertical dimension in number of lines) are specified using two
32-bit registers (DCMI_CWSTRT and DCMI_CWSIZE). The size of the window is specified
in number of pixel clocks (horizontal dimension) and in number of lines (vertical dimension).

Figure 173. Coordinates and size of the window after cropping

VST[12:0] in DCMI_CWSTRT

VLINE[13:0] in DCMI_CWSIZE
HOFFCNT[13:0]
in
CAPCNT[13:0] in DCMI_CWSIZE
DCMI_CWSTRT
MS35933V3

These registers specify the coordinates of the starting point of the capture window as a line
number (in the frame, starting from 0) and a number of pixel clocks (on the line, starting from
0), and the size of the window as a line number and a number of pixel clocks. The CAPCNT
value can only be a multiple of 4 (two least significant bits are forced to 0) to allow the
correct transfer of data through the DMA.

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If the DCMI_VSYNC signal goes active before the number of lines is specified in the
DCMI_CWSIZE register, then the capture stops and an IT_FRAME interrupt is generated
when enabled.

Figure 174. Data capture waveforms

DCMI_HSYNC

DCMI_VSYNC

HOFFCNT

CAPCNT

Data not captured in this phase

Data captured in this phase

MS35934V2

1. Here, the active state of DCMI_HSYNC and DCMI_VSYNC is 1.

2. DCMI_HSYNC and DCMI_VSYNC can change states at the same time.

24.3.9 DCMI JPEG format

To allow JPEG image reception, it is necessary to set the JPEG bit of the DCMI_CR register.
JPEG images are not stored as lines and frames, so the DCMI_VSYNC signal is used to
start the capture while DCMI_HSYNC serves as a data enable signal. The number of bytes
in a line may not be a multiple of 4. This case must be carefully handled since a DMA
request is generated each time a complete 32-bit word has been constructed from the
captured data. When an end of frame is detected and the 32-bit word to be transferred has
not been completely received, the remaining data are padded with zeros and a DMA
request is generated.
The crop feature and embedded synchronization codes cannot be used in JPEG format.

24.3.10 DCMI FIFO

A 8-word FIFO is implemented to manage data rate transfers on the AHB. The DCMI
features a simple FIFO controller with a read pointer incremented each time the camera
interface reads from the AHB, and a write pointer incremented each time the camera
interface writes to the FIFO. There is no overrun protection to prevent the data from being
overwritten if the AHB interface does not sustain the data transfer rate.
In case of overrun or errors in the synchronization signals, the FIFO is reset and the DCMI
interface waits for a new start of frame.

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24.3.11 DCMI data format description

Data formats
Three types of data are supported:
• 8/10/12/14-bit progressive video: either monochrome or raw Bayer format
• YCbCr 4:2:2 progressive video
• RGB565 progressive video. A pixel coded in 16 bits (5 bits for blue, 5 bits for red, 6 bits
for green) takes two clock cycles to be transferred.
Compressed data: JPEG
For B&W (black and white), YCbCr or RGB data, the maximum input size is 2048 × 2048
pixels. No limit in JPEG compressed mode.
For monochrome, RGB and YCbCr, the frame buffer is stored in raster mode. 32-bit words
are used. Only the little-endian format is supported.

Figure 175. Pixel raster scan order

Monochrome format
Characteristics:
• Raster format
• 8 bits per pixel
The table below shows how the data are stored.

Table 159. Data storage in monochrome progressive video format

Byte address 31:24 23:16 15:8 7:0

0 n+3 n+2 n+1 n

4 n+7 n+6 n+5 n+4

RGB format
Characteristics:
• Raster format
• RGB
• Interleaved: one buffer: R, G and B interleaved (such as BRGBRGBRG)
• Optimized for display output

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The RGB planar format is compatible with standard OS frame buffer display formats.
Only 16 BPP (bits per pixel): RGB565 (2 pixels per 32-bit word) is supported.
The 24 BPP (palletized format) and gray-scale formats are not supported. Pixels are stored
in a raster scan order, that is from top to bottom for pixel rows, and from left to right within a
pixel row. Pixel components are R (red), G (green) and B (blue). All components have the
same spatial resolution (4:4:4 format). A frame is stored in a single part, with the
components interleaved on a pixel basis.
The table below shows how the data are stored.

Table 160. Data storage in RGB progressive video format

Byte address 31:27 26:21 20:16 15:11 10:5 4:0

0 Red n + 1 Green n + 1 Blue n + 1 Red n Green n Blue n

4 Red n + 4 Green n + 3 Blue n + 3 Red n + 2 Green n + 2 Blue n + 2

YCbCr format
Characteristics:
• Raster format
• YCbCr 4:2:2
• Interleaved: one buffer: Y, Cb and Cr interleaved (such as CbYCrYCbYCr)
Pixel components are Y (luminance or “luma”), Cb and Cr (chrominance or “chroma” blue
and red). Each component is encoded in 8 bits. Luma and chroma are stored together
(interleaved) as shown in the table below.

Table 161. Data storage in YCbCr progressive video format

Byte address 31:24 23:16 15:8 7:0

0 Yn+1 Cr n Yn Cb n
4 Yn+3 Cr n + 2 Yn+2 Cb n + 2

YCbCr format - Y only

Characteristics:
• Raster format
• YCbCr 4:2:2
• The buffer only contains Y information - monochrome image
Pixel components are Y (luminance or “luma”), Cb and Cr (chrominance or “chroma” blue
and red). In this mode, the chroma information is dropped. Only the luma component of
each pixel, encoded in 8 bits, is stored as shown in Table 162.
The result is a monochrome image having the same resolution as the original YCbCr data.

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Table 162. Data storage in YCbCr progressive video format - Y extraction mode
Byte address 31:24 23:16 15:8 7:0

0 Yn+3 Yn+2 Yn+1 Yn

4 Yn+7 Yn+6 Yn+5 Yn+4

Half resolution image extraction

This is a modification of the previous reception modes, being applicable to monochrome,
RGB or Y extraction modes.
This mode is used to only store a half resolution image. It is selected through OELS and
LSM control bits.

24.4 DCMI interrupts

Five interrupts are generated. All interrupts are maskable by software. The global interrupt
(DCMI_IT) is the OR of all the individual interrupts. The table below gives the list of all
interrupts.

Table 163. DCMI interrupts

Exists
Exits
Interrupt Enable Interrupt clear Stop and
Interrupt event Event flag Sleep
acronym control bit method Standby
mode
modes

End of line LINE_RIS LINE_IE Set LINE_ISC Yes No

End of frame capture FRAME_RIS FRAME_IE Set FRAME_ISC Yes No
Overrun of data reception OVR_RIS OVR_IE Set OVR_ISC Yes No
DCMI_IT Synchronization frame VSYNC_RIS VSYNC_IE Set VSYNC_ISC Yes No
Detection of an error in the
embedded
ERR_RIS ERR_IE Set ERR_ISC Yes No
synchronization frame
detection

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24.5 DCMI registers

Refer to Section 1.2 on page 84 for list of abbreviations used in register descriptions. All
DCMI registers must be accessed as 32-bit words, otherwise a bus error occurs.

24.5.1 DCMI control register (DCMI_CR)

Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OELS LSM OEBS BSM[1:0]
rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENABL PCKPO CAPTU
Res. Res. Res. EDM[1:0] FCRC[1:0] VSPOL HSPOL ESS JPEG CROP CM
E L RE
rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 OELS: Odd/Even Line Select (Line Select Start)
This bit works in conjunction with the LSM field (LSM = 1).
0: Interface captures first line after the frame start, second one being dropped.
1: Interface captures second line from the frame start, first one being dropped.
Bit 19 LSM: Line Select mode
0: Interface captures all received lines.
1: Interface captures one line out of two.
Bit 18 OEBS: Odd/Even Byte Select (Byte Select Start)
This bit works in conjunction with BSM field (BSM ≠ 00).
0: Interface captures first data (byte or double byte) from the frame/line start, second one
being dropped.
1: Interface captures second data (byte or double byte) from the frame/line start, first one
being dropped.
Bits 17:16 BSM[1:0]: Byte Select mode
00: Interface captures all received data.
01: Interface captures every other byte from the received data.
10: Interface captures one byte out of four.
11: Interface captures two bytes out of four.
Note: This mode only works for EDM[1:0] = 00. For all other EDM values, this field must be
programmed to the reset value.
Bit 15 Reserved, must be kept at reset value.
Bit 14 ENABLE: DCMI enable
0: DCMI disabled
1: DCMI enabled
Note: The DCMI configuration registers must be programmed correctly before enabling this
bit.
Bits 13:12 Reserved, must be kept at reset value.

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Bits 11:10 EDM[1:0]: Extended data mode

00: Interface captures 8-bit data on every pixel clock.
01: Interface captures 10-bit data on every pixel clock.
10: Interface captures 12-bit data on every pixel clock.
11: Interface captures 14-bit data on every pixel clock.
Bits 9:8 FCRC[1:0]: Frame capture rate control
These bits define the frequency of frame capture. They are meaningful only in Continuous
grab mode. They are ignored in snapshot mode.
00: All frames are captured.
01: Every alternate frame captured (50% bandwidth reduction)
10: One frame out of four captured (75% bandwidth reduction)
11: reserved
Bit 7 VSPOL: Vertical synchronization polarity
This bit indicates the level on the DCMI_VSYNC pin when the data are not valid on the
parallel interface.
0: DCMI_VSYNC active low
1: DCMI_VSYNC active high
Bit 6 HSPOL: Horizontal synchronization polarity
This bit indicates the level on the DCMI_HSYNC pin when the data are not valid on the
parallel interface.
0: DCMI_HSYNC active low
1: DCMI_HSYNC active high
Bit 5 PCKPOL: Pixel clock polarity
This bit configures the capture edge of the pixel clock.
0: Falling edge active
1: Rising edge active
Bit 4 ESS: Embedded synchronization select
0: Hardware synchronization data capture (frame/line start/stop) is synchronized with the
DCMI_HSYNC/DCMI_VSYNC signals.
1: Embedded synchronization data capture is synchronized with synchronization codes
embedded in the data flow.
Note: Valid only for 8-bit parallel data. HSPOL/VSPOL are ignored when the ESS bit is set.
This bit is disabled in JPEG mode.
Bit 3 JPEG: JPEG format
0: Uncompressed video format
1: This bit is used for JPEG data transfers. The DCMI_HSYNC signal is used as data enable.
The crop and embedded synchronization features (ESS bit) cannot be used in this mode.
Bit 2 CROP: Crop feature
0: The full image is captured. In this case the total number of bytes in an image frame must
be a multiple of four.
1: Only the data inside the window specified by the crop register is captured. If the size of the
crop window exceeds the picture size, then only the picture size is captured.
Bit 1 CM: Capture mode
0: Continuous grab mode - The received data are transferred into the destination memory
through the DMA. The buffer location and mode (linear or circular buffer) is controlled
through the system DMA.
1: Snapshot mode (single frame) - Once activated, the interface waits for the start of frame
and then transfers a single frame through the DMA. At the end of the frame, the CAPTURE
bit is automatically reset.

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Digital camera interface (DCMI) RM0432

Bit 0 CAPTURE: Capture enable

0: Capture disabled
1: Capture enabled
The camera interface waits for the first start of frame, then a DMA request is generated to
transfer the received data into the destination memory.
In snapshot mode, the CAPTURE bit is automatically cleared at the end of the first frame
received.
In continuous grab mode, if the software clears this bit while a capture is ongoing, the bit is
effectively cleared after the frame end.
Note: The DMA controller and all DCMI configuration registers must be programmed correctly
before enabling this bit.

24.5.2 DCMI status register (DCMI_SR)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FNE VSYNC HSYNC
r r r

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 FNE: FIFO not empty
This bit gives the status of the FIFO.
1: FIFO contains valid data.
0: FIFO empty
Bit 1 VSYNC: Vertical synchronization
This bit gives the state of the DCMI_VSYNC pin with the correct programmed polarity. When
embedded synchronization codes are used, the meaning of this bit is the following:
0: active frame
1: synchronization between frames
In case of embedded synchronization, this bit is meaningful only if the CAPTURE bit in
DCMI_CR is set.
Bit 0 HSYNC: Horizontal synchronization
This bit gives the state of the DCMI_HSYNC pin with the correct programmed polarity. When
embedded synchronization codes are used, the meaning of this bit is the following:
0: active line
1: synchronization between lines
In case of embedded synchronization, this bit is meaningful only if the CAPTURE bit in
DCMI_CR is set.

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RM0432 Digital camera interface (DCMI)

24.5.3 DCMI raw interrupt status register (DCMI_RIS)

DCMI_RIS gives the raw interrupt status and is accessible in read only. When read, this
register returns the status of the corresponding interrupt before masking with the DCMI_IER
register value.
Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINE VSYNC ERR OVR FRAME
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
_RIS _RIS _RIS _RIS _RIS
r r r r r

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 LINE_RIS: Line raw interrupt status
This bit gets set when the DCMI_HSYNC signal changes from the inactive state to the
active state. It goes high even if the line is not valid.
In the case of embedded synchronization, this bit is set only if the CAPTURE bit in
DCMI_CR is set.
It is cleared by setting the LINE_ISC bit of the DCMI_ICR register.
Bit 3 VSYNC_RIS: DCMI_VSYNC raw interrupt status
This bit is set when the DCMI_VSYNC signal changes from the inactive state to the active
state.
In the case of embedded synchronization, this bit is set only if the CAPTURE bit is set in
DCMI_CR.
It is cleared by setting the VSYNC_ISC bit of the DCMI_ICR register.
Bit 2 ERR_RIS: Synchronization error raw interrupt status
0: No synchronization error detected
1: Embedded synchronization characters are not received in the correct order.
This bit is valid only in the embedded synchronization mode. It is cleared by setting the
ERR_ISC bit of the DCMI_ICR register.
Note: This bit is available only in embedded synchronization mode.
Bit 1 OVR_RIS: Overrun raw interrupt status
0: No data buffer overrun occurred
1: A data buffer overrun occurred and the data FIFO is corrupted.
The bit is cleared by setting the OVR_ISC bit of the DCMI_ICR register.
Bit 0 FRAME_RIS: Capture complete raw interrupt status
0: No new capture
1: A frame has been captured.
This bit is set when a frame or window has been captured.
In case of a cropped window, this bit is set at the end of line of the last line in the crop. It is
set even if the captured frame is empty (e.g. window cropped outside the frame).
The bit is cleared by setting the FRAME_ISC bit of the DCMI_ICR register.

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Digital camera interface (DCMI) RM0432

24.5.4 DCMI interrupt enable register (DCMI_IER)

The DCMI_IER register is used to enable interrupts. When one of the DCMI_IER bits is set,
the corresponding interrupt is enabled. This register is accessible in both read and write.
Address offset: 0x0C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINE VSYNC ERR OVR FRAME
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
_IE _IE _IE _IE _IE
rw rw rw rw rw

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 LINE_IE: Line interrupt enable
0: No interrupt generation when the line is received
1: An Interrupt is generated when a line has been completely received.
Bit 3 VSYNC_IE: DCMI_VSYNC interrupt enable
0: No interrupt generation
1: An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active
state.
The active state of the DCMI_VSYNC signal is defined by the VSPOL bit.
Bit 2 ERR_IE: Synchronization error interrupt enable
0: No interrupt generation
1: An interrupt is generated if the embedded synchronization codes are not received in the
correct order.
Note: This bit is available only in embedded synchronization mode.
Bit 1 OVR_IE: Overrun interrupt enable
0: No interrupt generation
1: An interrupt is generated if the DMA was not able to transfer the last data before new data
(32-bit) are received.
Bit 0 FRAME_IE: Capture complete interrupt enable
0: No interrupt generation
1: An interrupt is generated at the end of each received frame/crop window (in crop mode).

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RM0432 Digital camera interface (DCMI)

24.5.5 DCMI masked interrupt status register (DCMI_MIS)

This DCMI_MIS register is a read-only register. When read, it returns the current masked
status value (depending on the value in DCMI_IER) of the corresponding interrupt. A bit in
this register is set if the corresponding enable bit in DCMI_IER is set and the corresponding
bit in DCMI_RIS is set.
Address offset: 0x10
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINE VSYNC ERR OVR FRAME
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
_MIS _MIS _MIS _MIS _MIS
r r r r r

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 LINE_MIS: Line masked interrupt status
This bit gives the status of the masked line interrupt.
0: No interrupt generation when the line is received
1: An Interrupt is generated when a line has been completely received and the LINE_IE bit
is set in DCMI_IER.
Bit 3 VSYNC_MIS: VSYNC masked interrupt status
This bit gives the status of the masked VSYNC interrupt.
0: No interrupt is generated on DCMI_VSYNC transitions.
1: An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active
state and the VSYNC_IE bit is set in DCMI_IER.
The active state of the DCMI_VSYNC signal is defined by the VSPOL bit.
Bit 2 ERR_MIS: Synchronization error masked interrupt status
This bit gives the status of the masked synchronization error interrupt.
0: No interrupt is generated on a synchronization error.
1: An interrupt is generated if the embedded synchronization codes are not received in the
correct order and the ERR_IE bit in DCMI_IER is set.
Note: This bit is available only in embedded synchronization mode.
Bit 1 OVR_MIS: Overrun masked interrupt status
This bit gives the status of the masked overflow interrupt.
0: No interrupt is generated on overrun.
1: An interrupt is generated if the DMA was not able to transfer the last data before new
data (32-bit) are received and the OVR_IE bit is set in DCMI_IER.
Bit 0 FRAME_MIS: Capture complete masked interrupt status
This bit gives the status of the masked capture complete interrupt
0: No interrupt is generated after a complete capture.
1: An interrupt is generated at the end of each received frame/crop window (in crop mode)
and the FRAME_IE bit is set in DCMI_IER.

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Digital camera interface (DCMI) RM0432

24.5.6 DCMI interrupt clear register (DCMI_ICR)

The DCMI_ICR register is write-only. Setting a bit of this register clears the corresponding
flag in the DCMI_RIS and DCMI_MIS registers. Writing 0 has no effect.
Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINE VSYNC ERR OVR FRAME
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
_ISC _ISC _ISC _ISC _ISC
w w w w w

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 LINE_ISC: line interrupt status clear
Setting this bit clears the LINE_RIS flag in the DCMI_RIS register.
Bit 3 VSYNC_ISC: Vertical Synchronization interrupt status clear
Setting this bit clears the VSYNC_RIS flag in the DCMI_RIS register.
Bit 2 ERR_ISC: Synchronization error interrupt status clear
Setting this bit clears the ERR_RIS flag in the DCMI_RIS register.
Note: This bit is available only in embedded synchronization mode.
Bit 1 OVR_ISC: Overrun interrupt status clear
Setting this bit clears the OVR_RIS flag in the DCMI_RIS register.
Bit 0 FRAME_ISC: Capture complete interrupt status clear
Setting this bit clears the FRAME_RIS flag in the DCMI_RIS register.

24.5.7 DCMI embedded synchronization code register (DCMI_ESCR)

Address offset: 0x18
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FEC[7:0] LEC[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSC[7:0] FSC[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

784/2301 RM0432 Rev 6

RM0432 Digital camera interface (DCMI)

Bits 31:24 FEC[7:0]: Frame end delimiter code

This byte specifies the code of the frame end delimiter. The code consists of 4 bytes in the
form of 0xFF, 0x00, 0x00, FEC.
If FEC is programmed to 0xFF, all the unused codes (0xFF0000XY) are interpreted as frame
end delimiters.
Bits 23:16 LEC[7:0]: Line end delimiter code
This byte specifies the code of the line end delimiter. The code consists of 4 bytes in the form
of 0xFF, 0x00, 0x00, LEC.
Bits 15:8 LSC[7:0]: Line start delimiter code
This byte specifies the code of the line start delimiter. The code consists of 4 bytes in the
form of 0xFF, 0x00, 0x00, LSC.
Bits 7:0 FSC[7:0]: Frame start delimiter code
This byte specifies the code of the frame start delimiter. The code consists of 4 bytes in the
form of 0xFF, 0x00, 0x00, FSC.
If FSC is programmed to 0xFF, no frame start delimiter is detected. But, the first occurrence
of LSC after an FEC code is interpreted as a start of frame delimiter.

RM0432 Rev 6 785/2301

789
Digital camera interface (DCMI) RM0432

24.5.8 DCMI embedded synchronization unmask register (DCMI_ESUR)

Address offset: 0x1C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FEU[7:0] LEU[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSU[7:0] FSU[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 FEU[7:0]: Frame end delimiter unmask

This byte specifies the mask to be applied to the code of the frame end delimiter.
0: The corresponding bit in the FEC byte in DCMI_ESCR is masked while comparing the
frame end delimiter with the received data.
1: The corresponding bit in the FEC byte in DCMI_ESCR is compared while comparing the
frame end delimiter with the received data.
Bits 23:16 LEU[7:0]: Line end delimiter unmask
This byte specifies the mask to be applied to the code of the line end delimiter.
0: The corresponding bit in the LEC byte in DCMI_ESCR is masked while comparing the line
end delimiter with the received data.
1: The corresponding bit in the LEC byte in DCMI_ESCR is compared while comparing the
line end delimiter with the received data.
Bits 15:8 LSU[7:0]: Line start delimiter unmask
This byte specifies the mask to be applied to the code of the line start delimiter.
0: The corresponding bit in the LSC byte in DCMI_ESCR is masked while comparing the line
start delimiter with the received data.
1: The corresponding bit in the LSC byte in DCMI_ESCR is compared while comparing the
line start delimiter with the received data.
Bits 7:0 FSU[7:0]: Frame start delimiter unmask
This byte specifies the mask to be applied to the code of the frame start delimiter.
0: The corresponding bit in the FSC byte in DCMI_ESCR is masked while comparing the
frame start delimiter with the received data.
1: The corresponding bit in the FSC byte in DCMI_ESCR is compared while comparing the
frame start delimiter with the received data.

24.5.9 DCMI crop window start (DCMI_CWSTRT)

Address offset: 0x20
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. VST[12:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. HOFFCNT[13:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

786/2301 RM0432 Rev 6

RM0432 Digital camera interface (DCMI)

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:16 VST[12:0]: Vertical start line count
The image capture starts with this line number. Previous line data are ignored.
0x0000: line 1
0x0001: line 2
0x0002: line 3
....
Bits 15:14 Reserved, must be kept at reset value.
Bits 13:0 HOFFCNT[13:0]: Horizontal offset count
This value gives the number of pixel clocks to count before starting a capture.

24.5.10 DCMI crop window size (DCMI_CWSIZE)

Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. VLINE[13:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. CAPCNT[13:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:16 VLINE[13:0]: Vertical line count
This value gives the number of lines to be captured from the starting point.
0x0000: 1 line
0x0001: 2 lines
0x0002: 3 lines
....
Bits 15:14 Reserved, must be kept at reset value.
Bits 13:0 CAPCNT[13:0]: Capture count
This value gives the number of pixel clocks to be captured from the starting point on the
same line. It value must corresponds to word-aligned data for different widths of parallel
interfaces.
0x0000 => 1 pixel
0x0001 => 2 pixels
0x0002 => 3 pixels
....

24.5.11 DCMI data register (DCMI_DR)

Address offset: 0x28
Reset value: 0x0000 0000
The digital camera Interface packages all the received data in 32-bit format before
requesting a DMA transfer. A 8-word deep FIFO is available to leave enough time for DMA
transfers and avoid DMA overrun conditions.

RM0432 Rev 6 787/2301

789
Digital camera interface (DCMI) RM0432

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BYTE3[7:0] BYTE2[7:0]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BYTE1[7:0] BYTE0[7:0]
r r r r r r r r r r r r r r r r

Bits 31:24 BYTE3[7:0]: Data byte 3

Bits 23:16 BYTE2[7:0]: Data byte 2
Bits 15:8 BYTE1[7:0]: Data byte 1
Bits 7:0 BYTE0[7:0]: Data byte 0

788/2301 RM0432 Rev 6

 0x28
0x24
0x20
0x18
0x14
0x10
0x08
0x04
0x00

0x1C
0x0C
Offset
RM0432

24.5.12

name

DCMI_SR
DCMI_CR

DCMI_DR
DCMI_RIS

DCMI_IER

DCMI_ICR
DCMI_MIS
Register

Reset value
Reset value
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

DCMI_ESUR
DCMI_ESCR

DCMI_CWSIZE
DCMI_CWSTRT

0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. 31

0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. 30

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. 29

0
0
0
0
0
Res. Res. Res. Res. Res. Res. 28

0
0
0
0
0
Res. Res. Res. Res. Res. Res. 27

FEU[7:0]
FEC[7:0]

BYTE3[7:0]

0
0
0
0
0
Res. Res. Res. Res. Res. Res. 26
DCMI register map

0
0
0
0
0
Res. Res. Res. Res. Res. Res. 25

0
0
0
0
0
Res. Res. Res. Res. Res. Res. 24

0
0
0
0
0
Res. Res. Res. Res. Res. Res. 23

0
0
0
0
0
Res. Res. Res. Res. Res. Res. 22

VLINE[13:0]

0
0
0
0
0
Res. Res. Res. Res. Res. Res.

VST[12:0]
21

0
0
0
0
0
0

Res. Res. Res. Res. Res. OELS 20

0
0
0
0
0
0

Res. Res. Res. Res. Res. LSM 19

LEU[7:0]
LEC[7:0]

BYTE2[7:0]

0
0
0
0
0
0

Res. Res. Res. Res. Res. OEBS 18

0
0
0
0
0
0

RM0432 Rev 6
Res. Res. Res. Res. Res. 17
BSM[1:0]

0
0
0
0
0
0

Res. Res. Res. Res. Res. 16

0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. 15

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. ENABLE 14

0
0
0
0
0
Res. Res. Res. Res. Res. Res.

Refer to Section 2.2 for the register boundary addresses.

13

0
0
0
0
0
Res. Res. Res. Res. Res. Res. 12

0
0
0
0
0
0

Res. Res. Res. Res. Res. 11

LSU[7:0]
LSC[7:0]
EDM[1:0]
Table 164. DCMI register map and reset values

BYTE1[7:0]

0
0
0
0
0
0

Res. Res. Res. Res. Res. 10

0
0
0
0
0
0

Res. Res. Res. Res. Res. 9

FCRC[1:0]

0
0
0
0
0
0

Res. Res. Res. Res. Res. 8

0
0
0
0
0
0

Res. Res. Res. Res. Res. VSPOL 7

0
0
0
0
0
0

Res. Res. Res. Res. Res. HSPOL 6

0
0
0
0
0
0

Res. Res. Res. Res. Res. PCKPOL

CAPCNT[13:0]
5

HOFFCNT[13:0]

0
0
0
0
0
0

0
0
0
0

LINE_ISC LINE_MIS LINE_IE LINE_RIS Res. ESS 4

0
0
0
0
0
0

0
0
0
0

VSYNC_ISC VSYNC_MIS VSYNC_IE VSYNC_RIS Res. JPEG 3

FSU[7:0]
FSC[7:0]

BYTE0[7:0]

0
0
0
0
0
0

0
0
0
0
0

ERR_ISC ERR_MIS ERR_IE ERR_RIS FNE CROP 2

0
0
0
0
0
0

0
0
0
0
0

OVR_ISC OVR_MIS OVR_IE OVR_RIS VSYNC CM 1

0
0
0
0
0
0

0
0
0
0
0

FRAME_ISC FRAME_MIS FRAME_IE FRAME_RIS HSYNC CAPTURE

Digital camera interface (DCMI)

789/2301
0

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Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx only

25 Parallel synchronous slave interface (PSSI) applied

to STM32L4P5xx and STM32LQ5xx only

The PSSI peripheral and the DCMI (digital camera interface) use the same circuitry. As a
result, these two peripherals cannot be used at the same time: when using the PSSI, the
DCMI registers cannot be accessed, and vice-versa.
In addition, the PSSI and the DCMI share the same alternate functions and interrupt vector
(see Section 25.3.2: PSSI pins and internal signals).

25.1 Introduction
The PSSI is a generic synchronous 8/16-bit parallel data input/output slave interface. It
enables the transmitter to send a data valid signal that indicates when the data is valid, and
the receiver to output a flow control signal that indicates when it is ready to sample the data.

25.2 PSSI main features

The PSSI peripheral main features are the following:
• Slave mode operation
• 8-bit or 16-bit parallel data input or output
• 8-word (32-byte) FIFO
• Data enable (PSSI_DE) alternate function input and Ready (PSSI_RDY) alternate
function output
When selected, these inputs can either enable the transmitter to indicate when the data
is valid, allow the receiver to indicate when it is ready to sample the data, or both.

25.3 PSSI functional description

The PSSI is a synchronous parallel slave interface that can send or receive high-speed data
flows. It consists of up to 16 data lines (PSSI_D[15:0]) plus a clock line (PSSI_PDCK). The
clock polarity can be configured so that data can be captured or transmitted on either the
clock rising or falling edge.
Usually, a general-purpose DMA channel is used to pass 32-bit packed data via the data
register (PSSI_DR).
The data flow can either be continuous or synchronized by hardware using the optional
PSSI_DE (Data enable), and PSSI_RDY (Ready) signals.
Figure 176 shows the PSSI block diagram.

790/2301 RM0432 Rev 6

RM0432 Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx

25.3.1 PSSI block diagram

Figure 176. PSSI block diagram

DMA Control/Status
interface Register
AHB interface

FIFO/ PSSI_PDCK
Data
Data Synchronizer
extraction
formatter

PSSI_D[15:0]
PSSI_DE
PSSI_RDY
MSv48844V2

Figure 177. Top-level block diagram

pssi_hclk

PSSI_D[15:0]

PSSI PSSI_DE External interface

Interrupt pssi_it
PSSI_RDY
controller
PSSI_PDCK

pssi_dma

MSv48845V3

25.3.2 PSSI pins and internal signals

The PSSI interface is composed of 19 pins, though nine signals are enough to transfer
parallel data. Table 165 shows the PSSI pins.
When the PSSI ENABLE bit (bit 14 of PSSI_CR) is set to 1, the alternate functions and the
interrupt vector are associated with the PSSI. Otherwise, they are associated with the
DCMI. The DCMI ENABLE bit (bit 15 of DCMI_CR) and the PSSI ENABLE bit (bit 14 of
PSSI_CR) must not be set to 1 at the same time. As an example, if a GPIO is configured to
use the alternate function PSSI_PDCK/DCMI_PIXCK, it is the PSSI_PDCK function which
becomes active if PSSI_CR/ENABLE is set to 1.

RM0432 Rev 6 791/2301

804
Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx only

Table 165. PSSI input/output pins

PSSI signal DCMI signal it
Signal type Description
name is shared with

PSSI_PDCK DCMI_PIXCK Input Parallel Data clock input

Data output when transmitting, data input when
PSSI_D[15:0] DCMI_D[13:0] Input/output
receiving
Data enable signal: data valid signal when receiving
PSSI_DE DCMI_HSYNC Input
or flow control signal when transmitting
Ready signal: flow control signal when receiving or
PSSI_RDY DCMI_VSYNC Output
data valid signal when transmitting

Table 166 shows the PSSI internal input/output signals.

Table 166. PSSI internal input/output signals

Internal
signal Signal type Description
name

pssi_it Output Interrupt

pssi_dma Output DMA request
pssi_hclk Input AHB clock

25.3.3 PSSI clock

The AHB clock frequency must be at least 2.5 times higher than the PSSI_PDCK frequency.
At frequency ratios lower than 2.5, data might be corrupted or lost during transfers.
Data transfers are synchronous with PSSI_PDCK. The PSSI_PDCK polarity can be
configured as follows, through CKPOL bit (bit 5 of PSSI_CR):
• When CKPOL=0
– Input pins are sampled on PSSI_PDCK falling edge
– Output pins are driven on PSSI_PDCK rising edge
• When CKPOL=1
– Input pins are sampled on PSSI_PDCK rising edge
– Output pins are driven on PSSI_PDCK falling edge

25.3.4 PSSI data management

Data direction
The direction of data transfers is configured through the OUTEN control bit (bit 31 of
PSSI_CR):
• When OUTEN is cleared to 0 (default setting), the PSSI operates in receive mode and
the data is input on the data pins.
• When OUTEN is set to 1, the peripheral operates in transmit mode and the data is
output on the data pins.
OUTEN can be modified only when the ENABLE bit is cleared to 0.

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Data register and DMA

Data are transferred from/to the FIFO using the PSSI_DR data register:
• In receive mode, data must be read from the FIFO by reading PSSI_DR.
• In transmit mode, data must be written to the FIFO by writing into PSSI_DR.
Word (32-bit) accesses to PSSI_DR and half-word (16-bit) accesses to PSSI_DR[15:0] are
permitted in all modes. Byte (8-bit) accesses to PSSI_DR[7:0] are permitted only when the
PSSI is configured to transfer 8 bits at a time (EDM=00 in the PSSI_CR register).
To reduce the load on the CPU, it is recommended to use the DMA to transfer data from/to
the PSSI FIFO. When it is used, the DMA must be configured to transfer data via the
PSSI_DR register. Using 32-bit transfers optimizes bandwidth and reduces the bus load.
However, 8-bit and 16-bit transfers are also permitted.
To use the DMA, set the PSSI DMA enable bit (DMAEN in PSSI_CR) to 1 (default setting).
When DMAEN is set to 1, a DMA transfer is initiated when the FIFO is ready for a 32-bit
transfer (four valid bytes in receive mode or four empty bytes in transmit mode). As a result,
in receive mode, no DMA transfers are initiated if there are three bytes or fewer in the FIFO,
even if the DMA is configured to perform 8-bit transfers.
The RTT4B and RTT1B status bits (PSSI_SR) are useful when the CPU directly perform
transfers to and from the FIFO. RTT4B set to 1 indicates that the FIFO is ready to transfer
four bytes: at least four valid bytes in the FIFO in receive mode or at least four free bytes in
transmit mode. RTT1B set to 1 indicates that the FIFO is ready to transfer one byte: at least
one valid byte in the FIFO in receive mode or at least one free byte in transmit mode.

8-bit data
The PSSI parallel interface can transfer either 8-bit (using D[7:0]) or 16-bit data (using
D[15:0]) depending on the EDM[1:0] control bits (bits 11:10 of PSSI_CR). If the 8-bit
configuration is selected (EDM[1:0] set to 00), the unused D[15:0] pins can be used for
GPIO or other functions.
When EDM[1:0] in PSSI_CR are programmed to 00, the interface transfers 8 bits using the
D[7:0] pins. In this case, D[15:8] are not used and four PSSI_PDCK cycles are required to
transfer a 32-bit word.
The least-significant byte (bits 7:0) correspond to the first byte transferred, and the most-
significant byte (bits 31:28) corresponds to the forth byte transferred. Table 167 illustrates
the positioning of the data bytes in two 32-bit words.

Table 167. Positioning of captured data bytes in 32-bit words (8-bit width)
Byte address 31:24 23:16 15:8 7:0

0 Dn+3[7:0] Dn+2[7:0] Dn+1[7:0] Dn[7:0]

4 Dn+7[7:0] Dn+6[7:0] Dn+5[7:0] Dn+4[7:0]

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16-bit data
When EDM[1:0] in PSSI_CR are programmed to 11, the interface transfers 16 bits using the
D[15:0] pins. In this case, two PSSI_PDCK cycles are required to transfer a 32-bit word.
The least-significant half word (bits 15:0) correspond to the first half word transferred, and
the most-significant half-word (bits 31:16) corresponds to the second half word transferred.
Table 168 illustrates the positioning of the data in two 32-bit words.

Table 168. Positioning of captured data bytes in 32-bit words (16-bit width)
Byte address 31:16 15:0

0 Dn+1[15:0] Dn[15:0]
4 Dn+3[15:0] Dn+2[15:0]

FIFO data buffer and error conditions

A eight-word FIFO helps improving performance and avoids overruns and underruns.
If the ready signal (PSSI_RDY) is disabled in receive mode, an overrun error is generated
when a clock active edge occurs when the FIFO is full. In this case, the input data is lost.
If the data enable signal (PSSI_DE) is disabled in transmit mode, an underrun error is
generated when a clock active edge occurs when the FIFO is empty. In this case,
unpredictable data are output.
The OVR_RIS status bit indicates that either an overrun or an underrun occurred. An
interrupt can be generated when these events occur.

25.3.5 PSSI optional control signals

Data Enable (PSSI_DE) alternate function input
The data enable signal, PSSI_DE, is an optional signal. It is driven by the data
source/transmitter in order to indicate that the data is valid to be transferred during the
current cycle. When PSSI_DE is inactive, it means that the data will not be or should not be
sampled by the receiver at the next clock edge.
This alternate function signal can be enabled using the DERDYCFG (bits 20:18 of
PSSI_CR) control bits. PSSI_DE polarity is configured through DEPOL control bit (bit 6 of
PSSI_CR). PSSI_DE is active low when DEPOL is cleared to 0, and high when DEPOL is et
to 1.
The direction of the PSSI_DE signal is defined by the OUTEN value. It is the same as the
data direction.
If the PSSI_DE alternate function input is enabled (through DERDYCFG) in receive mode
(OUTEN cleared to 0), the PSSI samples PSSI_DE on the same PSSI_PDCK edge as the
one used for sampling the data (D[15:0]). If PSSI_DE is active, the sampled data is saved in
the FIFO. Otherwise, the sampled data is considered invalid and discarded. The
transmitting device can use PSSI_DE as a data valid signal, driving it inactive when the data
in the current cycle is not valid. This flow control function allows avoiding underrun errors.

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Figure 178. Data enable in receive mode waveform diagram (CKPOL=0)

PSSI_PDCK

PSSI_D[15:0]

PSSI_DE

MSv48846V2

If the PSSI_DE alternate output function is enabled (through DERDYCFG) in transmit mode
(OUTEN=1), the PSSI drives PSSI_DE on the same PSSI_PDCK edge that the one used to
drive the data (D[15:0]). If a new 8 or 16-bit data (as programmed in the EDM[1:0] control
bits in PSSI_CR) is available for transmission in the internal FIFO, this data is output on the
data outputs (D[15:0]) and the PSSI_DE output becomes active on the current PSSI_PDCK
edge. Otherwise (if the TX FIFO is empty), the D[15:0] outputs remains unchanged on the
next clock edge and the PSSI_DE output becomes inactive.

Figure 179. Data enable waveform diagram in transmit mode (CKPOL=0)

PSSI_PDCK

PSSI_D[15:0]

PSSI_DE

MSv48847V2

Ready (PSSI_RDY) alternate function output

The ready signal, PSSI_RDY, is an optional signal. It is driven by the receiving device and
indicates whether data is being accepted in the current cycle. When PSSI_RDY is inactive,
it means that the data will not be or should not be sampled by the receiver at the next clock
edge.
This alternate function signal can be enabled using the DERDYCFG control bits (bits 20:18
of PSSI_CR). PSSI_RDY polarity is configured through the RDYPOL control bit (bit 6 of
PSSI_CR). PSSI_RDY is active low when RDYPOL is cleared to 0, and high when RDYPOL
set to 1.
The direction of the PSSI_RDY signal is defined by the OUTEN (bit 31 of PSSI_CR). It is set
in the opposite direction compared to the PSSI_DE and data signals.

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If the PSSI_RDY alternate output function is enabled (through DERDYCFG) in receive

mode (OUTEN=0), the PSSI drives PSSI_RDY one PSSI_PDCK half cycle after it samples
the data (D[15:0]). If the FIFO has enough free space to receive more data, the PSSI drives
the PSSI_RDY signal active. Otherwise, if the FIFO is full and cannot accept more data, the
PSSI drives the PSSI_RDY signal inactive. The transmitting device must repeat the current
data in the next cycle when it detects that PSSI_RDY is inactive. This flow control function
allows the PSSI to avoid overrun errors when the system (via the DMA) is unable to keep up
with the data flow.

Figure 180. Ready in receive mode waveform diagram (CKPOL=0)

PSSI_PDCK

PSSI_D[15:0]

PSSI_DE

PSSI_RDY

MSv48848V2

If the PSSI_RDY alternate input function is enabled (through DERDYCFG) in transmit mode
(OUTEN=1), the PSSI samples the PSSI_RDY signal on the opposite PSSI_PDCK edge to
the one at which D[15:0] are driven. If the PSSI_RDY signal is inactive, the PSSI keeps the
same data (D[15:0]) and PSSI_DE signals that valid data are available during the next
PSSI_PDCK clock cycle. Otherwise, if PSSI_RDY signal is sampled as active, the next data
from the TX FIFO (if available) is output on the data outputs (D[15:0]). If no new data are
available in the TX FIFO, the PSSI keeps the data output values and outputs the PSSI_DE
signal as inactive (if enabled).
The receiving device uses the PSSI_RDY to control the data flow and avoid overrun errors
when the system (via the DMA) is unable to keep up with the data flow.

Bidirectional PSSI_DE/PSSI_RDY signal

A single pin can be used for both data enable (PSSI_DE) and ready (PSSI_RDY) functions
if DEPOL and RDYPOL are both set to 1 and DERDYCFG is set to 111 or 100 in the
PSSI_CR register. In this case, the GPIO corresponding to selected alternate function
(PSSI_DE when DERDYCFG=111 or PSSI_RDY when DERDYCFG=100) must be
configured as open-drain. The other device must also be configured to drive the line as
open-drain, and a weak pull-up must be applied to the line.
The signal thus becomes bidirectional. If either the sender drives the line low (to indicate
that the data is not valid) or the receiver drives the line low (to indicate that it is not sampling
the current data), then both devices will know that the data is not being transferred in the
current cycle.

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Figure 181. Bidirectional PSSI_DE/PSSI_RDY waveform

PSSI_PDCK

PSSI_D[15:0]

PSSI_DE
PSSI_RDY

MSv48849V2

Figure 182. Bidirectional PSSI_DE/PSSI_RDY connection diagram

PSSI_D[15:0]

PSSI_PDCK
PSSI Master transmitter

PSSI_DE_RDY

MSv48850V2

25.4 PSSI interrupts

The PSSI generates only one interrupt (IT_OVR). It is consequently equivalent to the global
interrupt (pssi_it). Refer to Table 169 for the list of interrupts.
The PSSI and the DCMI share the same interrupt vector. When the PSSI ENABLE bit (bit 14
of PSSI_CR) is set to 1, these interrupts are triggered by the PSSI. Otherwise, they are
controlled by the DCMI.
The DCMI ENABLE bit (bit 14 of DCMI_CR) and PSSI ENABLE bit must not be set to 1 at
the same time.

Table 169. PSSI interrupt requests

Shared
Interrupt Interrupt Enable Interrupt Exit from low-
with Event flag
acronym event control bit clear method power mode
DCMI

indicates
overrun in
IT_OVR IT_OVR receive mode OVR_RIS OVR_IE OVR_ISC NA
or underrun in
transmit mode

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25.5 PSSI registers

An 8-bit write or a 16-bit write operation to any PSSI register besides PSSI_DR will result in
a bus error. 32-bit read and write operations are permitted.

25.5.1 PSSI control register (PSSI_CR)

Address offset: 0x00
Reset value: 0x4000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DERDYCFG
DMAEN
OUTEN

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDYPOL
ENABLE

DEPOL

CKPOL
Res. Res. Res. EDM[1:0] Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw

Bit 31 OUTEN: Data direction selection bit

0: Receive mode: data is input synchronously with PSSI_PDCK
1: Transmit mode: data is output synchronously with PSSI_PDCK
Bit 30 DMAEN: DMA enable bit
0: DMA transfers are disabled. The user application can directly access the
PSSI_DR register when DMA transfers are disabled.
1: DMA transfers are enabled (default configuration). A DMA channel in the
general-purpose DMA controller must be configured to perform transfers from/to
PSSI_DR.
Bits 29:21 Reserved, must be kept at reset value.
Bits 20:18 DERDYCFG: Data enable and ready configuration
000: PSSI_DE and PSSI_RDY both disabled
001: Only PSSI_RDY enabled
010: Only PSSI_DE enabled
011: Both PSSI_RDY and PSSI_DE alternate functions enabled
100: Both PSSI_RDY and PSSI_DE features enabled - bidirectional on
PSSI_RDY pin (see Bidirectional PSSI_DE/PSSI_RDY signal on page 796)
101: Only PSSI_RDY function enabled, but mapped to PSSI_DE pin
110: Only PSSI_DE function enabled, but mapped to PSSI_RDY pin
111: Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_DE
pin (see Bidirectional PSSI_DE/PSSI_RDY signal on page 796)
When the PSSI_RDY function is mapped to the PSSI_DE pin (settings 101 or
111), it is still the RDYPOL bit which determines its polarity. Similarly, when the
PSSI_DE function is mapped to the PSSI_RDY pin (settings 110 or 111), it is still
the DEPOL bit which determines its polarity.
Bits 17:15 Reserved, must be kept at reset value.

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Bit 14 ENABLE: PSSI enable

0: PSSI disabled
1: PSSI enabled
The contents of the FIFO are flushed when ENABLE is cleared to 0.
Note: When ENABLE=1, the content of PSSI_CR must not be changed, except
for the ENABLE bit itself. All configuration bits can change as soon as
ENABLE changes from 0 to 1.
The DMA controller and all PSSI configuration registers must be
programmed correctly before setting the ENABLE bit to 1.
The ENABLE bit and the DCMI ENABLE bit (bit 15 of DCMI_CR) must not
be set to 1 at the same time.
Bits 13:12 Reserved, must be kept at reset value.
Bits 11:10 EDM[1:0]: Extended data mode
00: Interface captures 8-bit data on every parallel data clock
01: Reserved, must not be selected
10: Reserved, must not be selected
11: The interface captures 16-bit data on every parallel data clock
Bit 9 Reserved, must be kept at reset value.
Bit 8 RDYPOL: Ready (PSSI_RDY) polarity
This bit indicates the level on the PSSI_RDY pin when the data are not valid on
the parallel interface.
0: PSSI_RDY active low (0 indicates that the receiver is ready to receive)
1: PSSI_RDY active high (1 indicates that the receiver is ready to receive)
Bit 7 Reserved, must be kept at reset value.
Bit 6 DEPOL: Data enable (PSSI_DE) polarity
This bit indicates the level on the PSSI_DE pin when the data are not valid on
the parallel interface.
0: PSSI_DE active low (0 indicates that data is valid)
1: PSSI_DE active high (1 indicates that data is valid)
Bit 5 CKPOL: Parallel data clock polarity
This bit configures the capture edge of the parallel clock or the edge used for
driving outputs, depending on OUTEN.
0: Falling edge active for inputs or rising edge active for outputs
1: Rising edge active for inputs or falling edge active for outputs.
Bits 4:0 Reserved, must be kept at reset value.

25.5.2 PSSI status register (PSSI_SR)

Address offset: 0x04
Reset value: 0x0000 0000

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RTT1B

RTT4B
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

r r

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 RTT1B: FIFO is ready to transfer one byte
1: FIFO is ready for a one byte (32-bit) transfer. In receive mode, this means
that at least one valid data byte is in the FIFO. In transmit mode, this means that
there is at least one byte free in the FIFO.
0: FIFO is not ready for a 1-byte transfer
Bit 2 RTT4B: FIFO is ready to transfer four bytes
1: FIFO is ready for a four-byte (32-bit) transfer. In receive mode, this means
that at least four valid data bytes are in the FIFO. In transmit mode, this means
that there are at least four bytes free in the FIFO.
0: FIFO is not ready for a four-byte transfer
Bits 1:0 Reserved, must be kept at reset value.

25.5.3 PSSI raw interrupt status register (PSSI_RIS)

Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVR_RIS

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

PSSI_RIS gives the raw interrupt status. This register is read-only. When read, it returns the
status of the corresponding interrupt before masking with the PSSI_IER register value.

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 OVR_RIS: Data buffer overrun/underrun raw interrupt status
0: No overrun/underrun occurred
1: An overrun/underrun occurred: overrun in receive mode, underrun in transmit
mode.
This bit is cleared by writing a 1 to the OVR_ISC bit in PSSI_ICR.
Bit 0 Reserved, must be kept at reset value.

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25.5.4 PSSI interrupt enable register (PSSI_IER)

Address offset: 0x0C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OVR_IE
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw

The PSSI_IER register is used to enable interrupts. When one of the PSSI_IER bits is set,
the corresponding interrupt is enabled. This register is accessible both in read and write
modes.

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 OVR_IE: Data buffer overrun/underrun interrupt enable
0: No interrupt generation
1: An interrupt is generated if either an overrun or an underrun error occurred.
Bit 0 Reserved, must be kept at reset value.

25.5.5 PSSI masked interrupt status register (PSSI_MIS)

This PSSI_MIS register is read-only. When read, it returns the current masked status value
of the corresponding interrupt (depending on the value in PSSI_IER). A bit in this register is
set if the corresponding enable bit in PSSI_IER is set and the corresponding bit in
PSSI_RIS is set.
Address offset: 0x10
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVR_MIS

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

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Bits 31:2 Reserved, must be kept at reset value.

Bit 1 OVR_MIS: Data buffer overrun/underrun masked interrupt status
This bit is set to 1 only when PSSI_IER/OVR_IE and PSSI_RIS/OVR_RIS are
both set to 1.
0: No interrupt is generated when an overrun/underrun error occurs
1: An interrupt is generated if there is either an overrun or an underrun error
and the OVR_IE bit is set in PSSI_IER.
Bit 0 Reserved, must be kept at reset value.

25.5.6 PSSI interrupt clear register (PSSI_ICR)

Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OVR_ISC
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

The PSSI_ICR register is write-only. Writing a 1 into a bit of this register clears the
corresponding bit in the PSSI_RIS and PSSI_MIS registers. Writing a 0 has no effect.
Reading this register always gives zeros.

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 OVR_ISC: Data buffer overrun/underrun interrupt status clear
Writing this bit to 1 clears the OVR_RIS bit in PSSI_RIS.
Bit 0 Reserved, must be kept at reset value.

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25.5.7 PSSI data register (PSSI_DR)

Address offset: 0x28
Reset value: 0x0000 0000
In receive mode (OUTEN=0), the DMA controller must read the received data from this
register. Write operations to PSSI_DR result in an error response. When more bytes than
the number of valid bytes are read in the FIFO, the invalid bytes return zeros.
In transmit mode (OUTEN=1), the DMA controller must write the data to be transmitted into
this register. Read operations to PSSI_DR result in an error response.
32-bit, 16-bit, and 8-bit accesses are all supported for PSSI_DR. For instance, 16-bit
read/write operations remove/add two bytes from/to the FIFO. However, 8-bit accesses are
permitted only when the PSSI is configured to transfer 8 data bits at a time (EDM=00 in
PSSI_CR). 8-bit accesses to PSSI_DR when EDM is not set to 0 result in an error response.
All accesses must include byte 0: 8-bit accesses must be performed to bits 7 to 0 and 16-bit
accesses from bits 15 to 0. Accesses that do not include byte 0 results in an error response.
Accessing PSSI_DR when ENABLE bit in PSSI_CR is set to 0 results in an error response.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BYTE3 BYTE2
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BYTE1 BYTE0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 BYTE3: Data byte 3

Bits 23:16 BYTE2: Data byte 2
Bits 15:8 BYTE1: Data byte 1
Bits 7:0 BYTE0: Data byte 0

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804
 to
to

0x28
0x24
0x18
0x14
0x10
0x08
0x04
0x00

0x2C
0x0C
Offset

0x3EC
25.5.8

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Register

PSSI_SR

Reserved
PSSI_DR
PSSI_CR

Reserved
PSSI_RIS

PSSI_IER

PSSI_ICR
PSSI_MIS

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Res. Res. Res. Res. Res. OUTEN 31

0 1
Res. Res. Res. Res. Res. DMAEN 30
Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. 27

BYTE3
Res. Res. Res. Res. Res. Res. 26
PSSI register map

Res. Res. Res. Res. Res. Res. 25

Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. DERDYCFG 19
Table 170 summarizes the PSSI registers.

BYTE2
0 0 0

Res. Res. Res. Res. Res. 18

RM0432 Rev 6
Res. Res. Res. Res. Res. Res. 17
Res. Res. Res. Res. Res. Res. 16

Res.
Res.
Res. Res. Res.am Res. Res. Res. 15
0

Res. Res. Res. Res. Res. ENABLE 14

Res. Res. Res. Res. Res. Res. 13
Res. Res. Res. Res. Res. Res. 12
Res. Res. Res. Res. Res. 11

BYTE1
Table 170. PSSI register map and reset values

0 0

Res. Res. Res. Res. Res.

EDM

10
Res. Res. Res. Res. Res. Res. 9

Refer to Section 2.2 on page 91 for the register boundary addresses.

0

Res. Res. Res. Res. Res. RDYPOL 8

Res. Res. Res. Res. Res. Res. 7
Res. Res. Res. Res. Res. DEPOL 6
0 0

Res. Res. Res. Res. Res. CKPOL 5

Res. Res. Res. Res. Res. Res. 4
Res. Res. Res. Res. RTT1B Res. 3

BYTE0
Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx only

0 0

Res. Res. Res. Res. RTT4B Res. 2

0
0
0
0

OVR_ISC OVR_MIS OVR_IE OVR_RIS Res. Res. 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res. Res. Res. Res. Res. Res. 0
RM0432 Comparator (COMP)

26 Comparator (COMP)

26.1 Introduction
The device embeds two ultra-low-power comparators COMP1, and COMP2
The comparators can be used for a variety of functions including:
• Wakeup from low-power mode triggered by an analog signal,
• Analog signal conditioning,
• Cycle-by-cycle current control loop when combined with a PWM output from a timer.

26.2 COMP main features

• Each comparator has configurable plus and minus inputs used for flexible voltage
selection:
– Multiplexed I/O pins
– DAC Channel1 and Channel2
– Internal reference voltage and three submultiple values (1/4, 1/2, 3/4) provided by
scaler (buffered voltage divider)
• Programmable hysteresis
• Programmable speed / consumption
• The outputs can be redirected to an I/O or to timer inputs for triggering:
– Break events for fast PWM shutdowns
• Comparator outputs with blanking source
• The two comparators can be combined in a window comparator
• Each comparator has interrupt generation capability with wakeup from Sleep and Stop
modes (through the EXTI controller)

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Comparator (COMP) RM0432

26.3 COMP functional description

26.3.1 COMP block diagram

The block diagram of the comparators is shown in Figure 183: Comparator block diagram.

Figure 183. Comparator block diagram

COMPx_INPSEL GPIO
alternate
function
COMPx_POL COMPx_OUT
COMPx_INP
COMPx_INP I/Os +
COMPx
COMPx_ COMPx_INM COMPx_VALUE Wakeup EXTI line
INMSEL - interrupt

COMPx_INM I/Os Polarity selection

DAC_CH1 TIMERS
DAC_CH2
VREFINT
3/4 VREFINT
1/2 VREFINT
1/4 VREFINT
MS34498V1

26.3.2 COMP pins and internal signals

The I/Os used as comparators inputs must be configured in analog mode in the GPIOs
registers.
The comparator output can be connected to the I/Os using the alternate function channel
given in “Alternate function mapping” table in the datasheet.
The output can also be internally redirected to a variety of timer input for the following
purposes:
• Emergency shut-down of PWM signals, using BKIN and BKIN2 inputs
• Cycle-by-cycle current control, using OCREF_CLR inputs
• Input capture for timing measures
It is possible to have the comparator output simultaneously redirected internally and
externally.

Table 171. COMP1 input plus assignment

COMP1_INP COMP1_INPSEL

PC5 0
PB2 1

Table 172. COMP1 input minus assignment

COMP1_INM COMP1_INMSEL[2:0]

¼ VREFINT 000
½ VREFINT 001

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RM0432 Comparator (COMP)

Table 172. COMP1 input minus assignment (continued)

COMP1_INM COMP1_INMSEL[2:0]

¾ VREFINT 010
VREFINT 011
DAC Channel1 100
DAC Channel2 101
PB1 110
PC4 111

Table 173. COMP2 input plus assignment

COMP2_INP COMP2_INPSEL

PB4 0
PB6 1

Table 174. COMP2 input minus assignment

COMP2_INM COMP2_INMSEL[2:0]

¼ VREFINT 000
½ VREFINT 001
¾ VREFINT 010
VREFINT 011
DAC Channel1 100
DAC Channel2 101
PB3 110
PB7 111

26.3.3 COMP reset and clocks

The COMP clock provided by the clock controller is synchronous with the APB2 clock.
There is no clock enable control bit provided in the RCC controller. Reset and clock enable
bits are common for COMP and SYSCFG.
Important: The polarity selection logic and the output redirection to the port works
independently from the APB2 clock. This allows the comparator to work even in Stop mode.

26.3.4 Comparator LOCK mechanism

The comparators can be used for safety purposes, such as over-current or thermal
protection. For applications having specific functional safety requirements, it is necessary to
insure that the comparator programming cannot be altered in case of spurious register
access or program counter corruption.

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For this purpose, the comparator control and status registers can be write-protected (read-
only).
Once the programming is completed, the COMPx LOCK bit can be set to 1. This causes the
whole register to become read-only, including the COMPx LOCK bit.
The write protection can only be reset by a MCU reset.

26.3.5 Window comparator

The purpose of window comparator is to monitor the analog voltage if it is within specified
voltage range defined by lower and upper threshold.
Two embedded comparators can be utilized to create window comparator. The monitored
analog voltage is connected to the non-inverting (plus) inputs of comparators connected
together and the upper and lower threshold voltages are connected to the inverting (minus)
inputs of the comparators. Two non-inverting inputs can be connected internally together by
enabling WINMODE bit to save one IO for other purposes.

Figure 184. Window mode

COMPx_INPSEL

COMPx_INP
COMPx_INP I/Os +
COMPx
COMPx_INM
COMPx_INMSEL -

COMPx_INM I/Os

.
Internal sources .
.

WINMODE
COMPx_INPSEL
COMPy_INP
+
COMPy_INP I/Os
COMPy
COMPy_INM
COMPy_INMSEL -

COMPy_INM I/Os

.
Internal sources .
.
MS35329V1

26.3.6 Hysteresis
The comparator includes a programmable hysteresis to avoid spurious output transitions in
case of noisy signals. The hysteresis can be disabled if it is not needed (for instance when
exiting from low-power mode) to be able to force the hysteresis value using external
components.

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RM0432 Comparator (COMP)

Figure 185. Comparator hysteresis

INP

INM
INM - Vhyst

COMP_OUT

MS19984V1

26.3.7 Comparator output blanking function

The purpose of the blanking function is to prevent the current regulation to trip upon short
current spikes at the beginning of the PWM period (typically the recovery current in power
switches anti parallel diodes).It consists of a selection of a blanking window which is a timer
output compare signal. The selection is done by software (refer to the comparator register
description for possible blanking signals). Then, the complementary of the blanking signal is
ANDed with the comparator output to provide the wanted comparator output. See the
example provided in the figure below.

Figure 186. Comparator output blanking

PWM

Current limit

Current

Raw comp output

Blanking window

Final comp output

Comp out
Comp out (to TIM_BK …)
Blank

MS30964V1

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26.3.8 COMP power and speed modes

COMP1 and COMP2 power consumption versus propagation delay can be adjusted to have
the optimum trade-off for a given application.
The bits PWRMODE[1:0] in COMPx_CSR registers can be programmed as follows:
00: High speed / full power
01 or 10: Medium speed / medium power
11: Low speed / ultra-low-power

26.4 COMP low-power modes

Table 175. Comparator behavior in the low power modes
Mode Description

No effect on the comparators.

Sleep
Comparator interrupts cause the device to exit the Sleep mode.

Low-power run No effect.

Low-power sleep No effect. COMP interrupts cause the device to exit the Low-power sleep mode.

Stop 0
No effect on the comparators.
Stop 1 Comparator interrupts cause the device to exit the Stop mode.

Stop 2

Standby
The COMP registers are powered down and must be reinitialized after exiting
Standby or Shutdown mode.
Shutdown

26.5 COMP interrupts

The comparator outputs are internally connected to the Extended interrupts and events
controller. Each comparator has its own EXTI line and can generate either interrupts or
events. The same mechanism is used to exit from low-power modes.
Refer to Interrupt and events section for more details.
To enable COMPx interrupt, it is required to follow this sequence:
1. Configure and enable the EXTI line corresponding to the COMPx output event in
interrupt mode and select the rising, falling or both edges sensitivity
2. Configure and enable the NVIC IRQ channel mapped to the corresponding EXTI lines
3. Enable COMPx.

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RM0432 Comparator (COMP)

Table 176. Interrupt control bits

Enable control Exit from Sleep Exit from Stop Exit from
Interrupt event Event flag
bit mode modes Standby mode

VALUE in
COMP1 output through EXTI yes yes N/A
COMP1_CSR
VALUE in
COMP2 output through EXTI yes yes N/A
COMP2_CSR

26.6 COMP registers

26.6.1 Comparator 1 control and status register (COMP1_CSR)
The COMP1_CSR is the Comparator 1 control/status register. It contains all the bits /flags
related to comparator1.
Address offset: 0x00
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCAL BRG
LOCK VALUE Res. Res. Res. Res. Res. Res. Res. BLANKING HYST
EN EN
rs r rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POLA INP
Res. Res. Res. Res. Res. Res. Res. INMSEL PWRMODE Res. EN
RITY SEL.
rw rw rw rw rw

Bit 31 LOCK: COMP1_CSR register lock bit

This bit is set by software and cleared by a hardware system reset. It locks the whole
content of the comparator 1 control register, COMP1_CSR[31:0].
0: COMP1_CSR[31:0] for comparator 1 are read/write
1: COMP1_CSR[31:0] for comparator 1 are read-only
Bit 30 VALUE: Comparator 1 output status bit
This bit is read-only. It reflects the current comparator 1 output taking into account
POLARITY bit effect.
Bits 29: Reserved, must be kept at reset value.
Bit 23 SCALEN: Voltage scaler enable bit
This bit is set and cleared by software. This bit enable the outputs of the VREFINT divider
available on the minus input of the Comparator 1.
0: Bandgap scaler disable (if SCALEN bit of COMP2_CSR register is also reset)
1: Bandgap scaler enable

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Bit 22 BRGEN: Scaler bridge enable

This bit is set and cleared by software (only if LOCK not set). This bit enable the bridge of
the scaler.
0: Scaler resistor bridge disable (if BRGEN bit of COMP2_CSR register is also reset)
1: Scaler resistor bridge enable
If SCALEN is set and BRGEN is reset, BG voltage reference is available but not 1/4 BGAP,
1/2 BGAP, 3/4 BGAP. BGAP value is sent instead of 1/4 BGAP, 1/2 BGAP, 3/4 BGAP.
If SCALEN and BRGEN are set, 1/4 BGAP 1/2 BGAP 3/4 BGAP and BGAP voltage
references are available.
Bit 21 Reserved, must be kept at reset value
Bits 20:18 BLANKING[2:0]: Comparator 1 blanking source selection bits
These bits select which timer output controls the comparator 1 output blanking.
000: No blanking
001: TIM1 OC5 selected as blanking source
010: TIM2 OC3 selected as blanking source
All other values: reserved
Bits 17:16 HYST[1:0]: Comparator 1 hysteresis selection bits
These bits are set and cleared by software (only if LOCK not set). They select the
Hysteresis voltage of the comparator 1.
00: No hysteresis
01: Low hysteresis
10: Medium hysteresis
11: High hysteresis
Bit 15 POLARITY: Comparator 1 polarity selection bit
This bit is set and cleared by software (only if LOCK not set). It inverts Comparator 1
polarity.
0: Comparator 1 output value not inverted
1: Comparator 1 output value inverted
Bits 14: Reserved, must be kept at reset value.
Bit 7 INPSEL: Comparator1 input plus selection bit
This bit is set and cleared by software (only if LOCK not set).
0: external IO - PC5
1: PB2
Bits 6:4 INMSEL: Comparator 1 input minus selection bits
These bits are set and cleared by software (only if LOCK not set). They select which input is
connected to the input minus of comparator 1.
000 = 1/4 VREFINT
001 = 1/2 VREFINT
010 = 3/4 VREFINT
011 = VREFINT
100 = DAC Channel1
101 = DAC Channel2
110 = PB1111 = PC4

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RM0432 Comparator (COMP)

Bits 3:2 PWRMODE[1:0]: Power Mode of the comparator 1

These bits are set and cleared by software (only if LOCK not set). They control the
power/speed of the Comparator 1.
00: High speed
01 or 10: Medium speed
11: Ultra low power
Bit 1 Reserved, must be kept cleared.
Bit 0 EN: Comparator 1 enable bit
This bit is set and cleared by software (only if LOCK not set). It switches on Comparator1.
0: Comparator 1 switched OFF
1: Comparator 1 switched ON

26.6.2 Comparator 2 control and status register (COMP2_CSR)

The COMP2_CSR is the Comparator 2 control/status register. It contains all the bits /flags
related to comparator 2.
Address offset: 0x04
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCAL BRG
LOCK VALUE Res. Res. Res. Res. Res. Res. Res. BLANKING HYST
EN EN
rs r rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POLA WIN INP
Res. Res. Res. Res. Res. Res. INMSEL PWRMODE Res. EN
RITY MODE SEL.
rw rw rw rw rw rw

Bit 31 LOCK: CSR register lock bit

This bit is set by software and cleared by a hardware system reset. It locks the whole
content of the comparator 2 control register, COMP2_CSR[31:0].
0: COMP2_CSR[31:0] for comparator 2 are read/write
1: COMP2_CSR[31:0] for comparator 2 are read-only
Bit 30 VALUE: Comparator 2 output status bit
This bit is read-only. It reflects the current comparator 2 output taking into account
POLARITY bit effect.
Bits 29: Reserved, must be kept at reset value
Bit 23 SCALEN: Voltage scaler enable bit
This bit is set and cleared by software. This bit enable the outputs of the VREFINT divider
available on the minus input of the Comparator 2.
0: Bandgap scaler disable (if SCALEN bit of COMP1_CSR register is also reset)
1: Bandgap scaler enable

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Comparator (COMP) RM0432

Bit 22 BRGEN: Scaler bridge enable

This bit is set and cleared by software (only if LOCK not set). This bit enable the bridge of
the scaler.
0: Scaler resistor bridge disable (if BRGEN bit of COMP1_CSR register is also reset)
1: Scaler resistor bridge enable
If SCALEN is set and BRGEN is reset, BG voltage reference is available but not 1/4 BGAP,
1/2 BGAP, 3/4 BGAP. BGAP value is sent instead of 1/4 BGAP, 1/2 BGAP, 3/4 BGAP.
If SCALEN and BRGEN are set, 1/4 BGAP 1/2 BGAP 3/4 BGAP and BGAP voltage
references are available.
Bit 21 Reserved, must be kept at reset value
Bits 20:18 BLANKING[2:0]: Comparator 2 blanking source selection bits
These bits select which timer output controls the comparator 2 output blanking.
000: No blanking
100: TIM15 OC1 selected as blanking source
All other values: reserved
Bits 17:16 HYST[1:0]: Comparator 2 hysteresis selection bits
These bits are set and cleared by software (only if LOCK not set). Select the hysteresis
voltage of the comparator 2.
00: No hysteresis
01: Low hysteresis
10: Medium hysteresis
11: High hysteresis
Bit 15 POLARITY: Comparator 2 polarity selection bit
This bit is set and cleared by software (only if LOCK not set). It inverts Comparator 2
polarity.
0: Comparator 2 output value not inverted
1: Comparator 2 output value inverted
Bits 14:10 Reserved, must be kept at reset value.
Bit 9 WINMODE: Windows mode selection bit
This bit is set and cleared by software (only if LOCK not set). This bit selects the window
mode of the comparators. If set, both positive inputs of comparators will be connected
together.
0: Input plus of Comparator 2 is not connected to Comparator 1
1: Input plus of Comparator 2 is connected with input plus of Comparator 1
Bit 8 Reserved, must be kept at reset value.
Bit 7 INPSEL: Comparator 1 input plus selection bit
This bit is set and cleared by software (only if LOCK not set).
0: PB4
1: PB6

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RM0432 Comparator (COMP)

Bits 6:4 INMSEL: Comparator 2 input minus selection bits

These bits are set and cleared by software (only if LOCK not set). They select which input is
connected to the input minus of comparator 2.
000 = 1/4 VREFINT
001 = 1/2 VREFINT
010 = 3/4 VREFINT
011 = VREFINT
100 = DAC Channel1
101 = DAC Channel2
110 = PB3
111 = PB7
Bits 3:2 PWRMODE[1:0]: Power Mode of the comparator 2
These bits are set and cleared by software (only if LOCK not set). They control the
power/speed of the Comparator 2.
00: High speed
01 or 10: Medium speed
11: Ultra low power
Bit 1 Reserved, must be kept cleared.
Bit 0 EN: Comparator 2 enable bit
This bit is set and cleared by software (only if LOCK not set). It switches oncomparator2.
0: Comparator 2 switched OFF
1: Comparator 2 switched ON

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Comparator (COMP) RM0432

26.6.3 COMP register map

The following table summarizes the comparator registers.

Table 177. COMP register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
PWRMODE
POLARITY.
BLANKING
SCALEN
BRGEN.

INPSEL.

INMSEL
VALUE
LOCK

HYST
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
COMP1_CSR

EN
0x00

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWRMODE
POLARITY.
BLANKING

WINMODE
SCALEN.
BRGEN.

INMSEL
INPSEL
VALUE

HYST.
LOCK

Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
Res.
Res.
Res.
Res.

Res.

Res.
COMP2_CSR

EN
0x04

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 91 for the register boundary addresses.

816/2301 RM0432 Rev 6

RM0432 Operational amplifiers (OPAMP)

27 Operational amplifiers (OPAMP)

27.1 Introduction
The device embeds two operational amplifiers with two inputs and one output each. The
three I/Os can be connected to the external pins, this enables any type of external
interconnections. The operational amplifier can be configured internally as a follower or as
an amplifier with a non-inverting gain ranging from 2 to 16.
The positive input can be connected to the internal DAC.
The output can be connected to the internal ADC.

27.2 OPAMP main features

• Rail-to-rail input and output voltage range
• Low input bias current (down to 1 nA)
• Low input offset voltage (1.5 mV after calibration, 3 mV with factory calibration)
• Low-power mode (current consumption reduced to 30 µA instead of 100 µA)
• Fast wakeup time (10 µs in normal mode, 30 µs in low-power mode)
• Gain bandwidth of 1.6 MHz

27.3 OPAMP functional description

The OPAMP has several modes.
Each OPAMP can be individually enabled, when disabled the output is high-impedance.
When enabled, it can be in calibration mode, all input and output of the OPAMP are then
disconnected, or in functional mode.
There are two functional modes, the low-power mode or the normal mode. In functional
mode the inputs and output of the OPAMP are connected as described in the
Section 27.3.3: Signal routing.

27.3.1 OPAMP reset and clocks

The operational amplifier clock is necessary for accessing the registers. When the
application does not need to have read or write access to those registers, the clock can be
switched off using the peripheral clock enable register (see OPAMPEN bit in Section 6.2.18:
Peripheral clock enable register (RCC_AHBxENR, RCC_APBxENRy)).
The bit OPAEN enables and disables the OPAMP operation. The OPAMP registers
configurations should be changed before enabling the OPAEN bit in order to avoid spurious
effects on the output.
When the output of the operational amplifier is no more needed the operational amplifier can
be disabled to save power. All the configurations previously set (including the calibration)
are maintained while OPAMP is disabled.

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Operational amplifiers (OPAMP) RM0432

27.3.2 Initial configuration

The default configuration of the operational amplifier is a functional mode where the three
IOs are connected to external pins. In the default mode the operational amplifier uses the
factory trimming values. See electrical characteristics section of the datasheet for factory
trimming conditions, usually the temperature is 30 °C and the voltage is 3 V. The trimming
values can be adjusted, see Section 27.3.5: Calibration for changing the trimming values.
The default configuration uses the normal mode, which provides the highest performance.
Bit OPALPM can be set in order to switch the operational amplifier to low-power mode and
reduced performance. Both normal and low-power mode characteristics are defined in the
section “electrical characteristics” of the datasheet. Before utilization, the bit OPA_RANGE
of OPAMP_CSR must be set to 1 if VDDA is above 2.4V, or kept at 0 otherwise.
As soon as the OPAEN bit in OPAMP_CSR register is set, the operational amplifier is
functional. The two input pins and the output pin are connected as defined in Section 27.3.3:
Signal routing and the default connection settings can be changed.
Note: The inputs and output pins must be configured in analog mode (default state) in the
corresponding GPIOx_MODER register.

27.3.3 Signal routing

The routing for the operational amplifier pins is determined by OPAMP_CSR register.
The connections of the two operational amplifiers (OPAMP1 and OPAMP2) are described in
the table below

Table 178. Operational amplifier possible connections

Signal Pin Internal comment

OPAMP1_OUT or Controlled by bits OPAMODE

OPAMP1_VINM PA1 or dedicated pin(1)
PGA and VM_SEL.
OPAMP1_VINP PA0 DAC1_OUT1 Controlled by bit VP_SEL.
The pin is connected when the
OPAMP1_VOUT PA3 ADC1_IN8 OPAMP is enabled. The ADC
input is controlled by ADC.

PA7 or dedicated OPAMP2_OUT or Controlled by bits OPAMODE

OPAMP2_VINM
pinChapter 1. PGA and VM_SEL.
OPAMP2_VINP PA6 DAC1_OUT2 Controlled by bit VP_SEL
The pin is connected when the
OPAMP2_VOUT PB0 ADC1_IN15 OPAMP is enabled. The ADC
input is controlled by ADC.
1. The dedicated pin is only available on BGA132 and BGA169 package. This configuration provides the
lowest input bias current (see datasheet).

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RM0432 Operational amplifiers (OPAMP)

27.3.4 OPAMP modes

The operational amplifier inputs and outputs are all accessible on terminals. The amplifiers
can be used in multiple configuration environments:
• Standalone mode (external gain setting mode)
• Follower configuration mode
• PGA modes
Note: The amplifier output pin is directly connected to the output pad to minimize the output
impedance. It cannot be used as a general purpose I/O, even if the amplifier is configured
as a PGA and only connected to the ADC channel.
Note: The impedance of the signal must be maintained below a level which avoids the input
leakage to create significant artifacts (due to a resistive drop in the source). Please refer to
the electrical characteristics section in the datasheet for further details.

Standalone mode (external gain setting mode)

The procedure to use the OPAMP in standalone mode is presented hereafter.
Starting from the default value of OPAMP_CSR, and the default state of GPIOx_MODER,
configure bit OPA_RANGE according the VDDA voltage. As soon as the OPAEN bit is set,
the two input pins and the output pin are connected to the operational amplifier.
This default configuration uses the factory trimming values and operates in normal mode
(highest performance). The behavior of the OPAMP can be changed as follows:
• OPALPM can be set to “operational amplifier low-power” mode in order to save power.
• USERTRIM can be set to modify the trimming values for the input offset.

Figure 187. Standalone mode: external gain setting mode

STM32

GPIO
+
DAC_OUT
ADC
GPIO

MS35324V1

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Follower configuration mode

The procedure to use the OPAMP in follower mode is presented hereafter.
• configure OPAMODE bits as “internal follower”
• configure VP_SEL bits as “GPIO connected to VINP”.
• As soon as the OPAEN bit is set, the signal on pin OPAMP_VINP is copied to pin
OPAMP_VOUT.
Note: The pin corresponding to OPAMP_VINM is free for another usage.
Note: The signal on the operational amplifier output is also seen as an ADC input. As a
consequence, the OPAMP configured in follower mode can be used to perform impedance
adaptation on input signals before feeding them to the ADC input, assuming the input signal
frequency is compatible with the operational amplifier gain bandwidth specification.

Figure 188. Follower configuration

STM32

GPIO
+
DAC_OUT
ADC

GPIO
-

Always connected to
OPAMP output (can be
used during debug)

MS35325V1

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RM0432 Operational amplifiers (OPAMP)

Programmable Gain Amplifier mode

The procedure to use the OPAMP to amplify the amplitude of an input signal is
presented hereafter.
• configure OPAMODE bits as “internal PGA enabled”,
• configure PGA_GAIN bits as “internal PGA Gain 2, 4, 8 or 16”,
• configure VM_SEL bits as “inverting not externally connected”,
• configure VP_SEL bits as “GPIO connected to VINP”.
As soon as the OPAEN bit is set, the signal on pin OPAMP_VINP is amplified by the
selected gain and visible on pin OPAMP_VOUT.
Note: To avoid saturation, the input voltage should stay below VDDA divided by the selected gain.

Figure 189. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used

STM32

GPIO
+
DAC_OUT
ADC

GPIO
-

Always connected to
OPAMP output (can be
used during debug)

MS35326V1

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Programmable Gain Amplifier mode with external filtering

The procedure to use the OPAMP to amplify the amplitude of an input signal, with an
external filtering, is presented hereafter.
• configure OPAMODE bits as “internal PGA enabled”,
• configure PGA_GAIN bits as “internal PGA Gain 2, 4, 8 or 16”,
• configure VM_SEL bits as “GPIO connected to VINM”,
• configure VP_SEL bits as “GPIO connected to VINP”.
Any external connection on VINP can be used in parallel with the internal PGA, for
example a capacitor can be connected between VOUT and VINM for filtering purpose
(see datasheet for the value of resistors used in the PGA resistor network).

Figure 190. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input used for
filtering

STM32

GPIO
+
DAC_OUT
ADC
GPIO

Allows optional
low-pass
filtering (1)
Equivalent to

MS35327V1

1. The gain depends on the cut-off frequency.

27.3.5 Calibration
At startup, the trimming values are initialized with the preset ‘factory’ trimming value.
Each operational amplifier offset can be trimmed by the user. Specific registers allow to
have different trimming values for normal mode and for low-power mode.
The aim of the calibration is to cancel as much as possible the OPAMP inputs offset voltage.
The calibration circuitry allows to reduce the inputs offset voltage to less than +/-1.5 mV
within stable voltage and temperature conditions.
For each operational amplifier and each mode two trimming values need to be trimmed, one
for N differential pair and one for P differential pair.
There are two registers for trimming the offsets for each operational amplifiers, one for
normal mode (OPAMP_OTR) and one low-power mode (OPAMP_LPOTR). Each register is
composed of five bits for P differential pair trimming and five bits for N differential pair
trimming. These are the ‘user’ values.

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RM0432 Operational amplifiers (OPAMP)

The user is able to switch from ‘factory’ values to ‘user’ trimmed values using the
USERTRIM bit in the OPAMP_CSR register. This bit is reset at startup and so the ‘factory’
value are applied by default to the OPAMP trimming registers.
User is liable to change the trimming values in calibration or in functional mode.

The offset trimming registers are typically configured after the calibration operation is
initialized by setting bit CALON to 1. When CALON = 1 the inputs of the operational
amplifier are disconnected from the functional environment.
• Setting CALSEL to 1 initializes the offset calibration for the P differential pair (low
voltage reference used).
• Resetting CALSEL to 0 initializes the offset calibration for the N differential pair (high
voltage reference used).
When CALON = 1, the bit CALOUT will reflect the influence of the trimming value selected
by CALSEL and OPALPM. When the value of CALOUT switches between two consecutive
trimming values, this means that those two values are the best trimming values. The
CALOUT flag needs up to 1 ms after the trimming value is changed to become steady (see
tOFFTRIMmax delay specification in the electrical characteristics section of the datasheet).
Note: The closer the trimming value is to the optimum trimming value, the longer it takes to
stabilize (with a maximum stabilization time remaining below 1 ms in any case).

Table 179. Operating modes and calibration

Control bits Output
Mode
CALOUT
OPAEN OPALPM CALON CALSEL VOUT
flag

Normal operating
1 0 0 X analog 0
mode
Low-power mode 1 1 0 X analog 0
Power down 0 X X X Z 0
Offset cal high for
1 0 1 0 analog X
normal mode
Offset cal low for
1 0 1 1 analog X
normal mode
Offset cal high for
1 1 1 0 analog X
low-power mode
Offset cal low for
1 1 1 1 analog X
low-power mode

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Calibration procedure
Here are the steps to perform a full calibration of either one of the operational amplifiers:
1. Select correct OPA_RANGE in OPAMP_CSR, then set the OPAEN bit in OPAMP_CSR
to 1 to enable the operational amplifier.
2. Set the USERTRIM bit in the OPAMP_CSR register to 1.
3. Choose a calibration mode (refer to Table 179: Operating modes and calibration). The
steps 3 to 4 will have to be repeated 4 times. For the first iteration select
– Normal mode, offset cal high (N differential pair)
The above calibration mode correspond to OPALPM=0 and CALSEL=0 in the
OPAMP_CSR register.
4. Increment TRIMOFFSETN[4:0] in OPAMP_OTR starting from 00000b until CALOUT
changes to 1 in OPAMP_CSR.
Note: CALOUT will switch from 0 to 1 for offset cal high and from 1 to 0 for offset cal low.
Note: Between the write to the OPAMP_OTR register and the read of the CALOUT value, make
sure to wait for the tOFFTRIMmax delay specified in the electrical characteristics section of
the datasheet, to get the correct CALOUT value.
The commutation means that the offset is correctly compensated and that the
corresponding trim code must be saved in the OPAMP_OTR register.
Repeat steps 3 to 4 for:
– Normal_mode and offset cal low
– Low power mode and offset cal high
– Low power mode and offset cal low
If a mode is not used it is not necessary to perform the corresponding calibration.
All operational amplifier can be calibrated at the same time.
Note: During the whole calibration phase the external connection of the operational amplifier
output must not pull up or down currents higher than 500 µA.
During the calibration procedure, it is necessary to set up OPAMODE bits as 00 or 01 (PGA
disable) or 11 (internal follower).

27.4 OPAMP low-power modes

Table 180. Effect of low-power modes on the OPAMP
Mode Description

Sleep No effect.
Low-power run No effect.
Low-power sleep No effect.
Stop 0 / Stop 1 No effect, OPAMP registers content is kept.
OPAMP registers content is kept. OPAMP must be disabled before entering
Stop 2
Stop 2 mode.

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RM0432 Operational amplifiers (OPAMP)

Table 180. Effect of low-power modes on the OPAMP (continued)

Mode Description

Standby The OPAMP registers are powered down and must be re-initialized after
Shutdown exiting Standby or Shutdown mode.

27.5 OPAMP registers

27.5.1 OPAMP1 control/status register (OPAMP1_CSR)

Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPA_
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RANGE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAL USER CAL VP_ OPA
CALON Res. VM_SEL Res. Res. PGA_GAIN OPAMODE OPAEN
OUT TRIM SEL SEL LPM
r rw rw rw rw rw rw rw rw rw w rw rw

Bit 31 OPA_RANGE: Operational amplifier power supply range for stability

All AOP must be in power down to allow AOP-RANGE bit write. It applies to all AOP
embedded in the product.
0: Low range (VDDA < 2.4V)
1: High range (VDDA > 2.4V)
Bits 30:16 Reserved, must be kept at reset value.
Bit 15 CALOUT: Operational amplifier calibration output
During calibration mode offset is trimmed when this signal toggle.
Bit 14 USERTRIM: allows to switch from ‘factory’ AOP offset trimmed values to AOP offset ‘user’
trimmed values
This bit is active for both mode normal and low-power.
0: ‘factory’ trim code used
1: ‘user’ trim code used
Bit 13 CALSEL: Calibration selection
0: NMOS calibration (200mV applied on OPAMP inputs)
1: PMOS calibration (VDDA-200mV applied on OPAMP inputs)
Bit 12 CALON: Calibration mode enabled
0: Normal mode
1: Calibration mode (all switches opened by HW)
Bit 11 Reserved, must be kept at reset value.
Bit 10 VP_SEL: Non inverted input selection
0: GPIO connected to VINP
1: DAC connected to VINP

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Bits 9:8 VM_SEL: Inverting input selection

These bits are used only when OPAMODE = 00, 01 or 10.
00: GPIO connected to VINM (valid also in PGA mode for filtering
01: Dedicated low leakage input, connected to VINM (valid also in PGA mode for filtering)
1x: Inverting input not externally connected. These configurations are valid only when
OPAMODE = 10 (PGA mode)
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 PGA_GAIN: Operational amplifier Programmable amplifier gain value
00: internal PGA Gain 2
01: internal PGA Gain 4
10: internal PGA Gain 8
11: internal PGA Gain 16
Bits 3:2 OPAMODE: Operational amplifier PGA mode
00: internal PGA disable
01: internal PGA disable
10: internal PGA enable, gain programmed in PGA_GAIN
11: internal follower
Bit 1 OPALPM: Operational amplifier Low Power Mode
The operational amplifier must be disable to change this configuration.
0: operational amplifier in normal mode
1: operational amplifier in low-power mode
Bit 0 OPAEN: Operational amplifier Enable
0: operational amplifier disabled
1: operational amplifier enabled

27.5.2 OPAMP1 offset trimming register in normal mode (OPAMP1_OTR)

Address offset: 0x04
Reset value: 0x0000 XXXX (factory trimmed values)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. TRIMOFFSETP[4:0] Res. Res. Res. TRIMOFFSETN[4:0]
rw rw rw rw rw rw rw rw rw rw

Bits 31:13 Reserved, must be kept at reset value.

Bits 12:8 TRIMOFFSETP[4:0]: Trim for PMOS differential pairs
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 TRIMOFFSETN[4:0]: Trim for NMOS differential pairs

27.5.3 OPAMP1 offset trimming register in low-power mode

(OPAMP1_LPOTR)
Address offset: 0x08

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Reset value: 0x0000 XXXX (factory trimmed values)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. TRIMLPOFFSETP[4:0] Res. Res. Res. TRIMLPOFFSETN[4:0]
rw rw rw rw rw rw rw rw rw rw

Bits 31:13 Reserved, must be kept at reset value.

Bits 12:8 TRIMLPOFFSETP[4:0]: Low-power mode trim for PMOS differential pairs
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 TRIMLPOFFSETN[4:0]: Low-power mode trim for NMOS differential pairs

27.5.4 OPAMP2 control/status register (OPAMP2_CRS)

Address offset: 0x10
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALOU USERT CALSE VP_SE OPALP
CALON Res. VM_SEL Res. Res. PGA_GAIN OPAMODE OPAEN
T RIM L L M
r rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 CALOUT: Operational amplifier calibration output
During calibration mode offset is trimmed when this signal toggle.
Bit 14 USERTRIM: allows to switch from ‘factory’ AOP offset trimmed values to AOP offset ‘user’
trimmed values
This bit is active for both mode normal and low-power.
0: ‘factory’ trim code used
1: ‘user’ trim code used
Bit 13 CALSEL: Calibration selection
0: NMOS calibration (200mV applied on OPAMP inputs)
1: PMOS calibration (VDDA-200mV applied on OPAMP inputs)
Bit 12 CALON: Calibration mode enabled
0: Normal mode
1: Calibration mode (all switches opened by HW)
Bit 11 Reserved, must be kept at reset value.
Bit 10 VP_SEL: Non inverted input selection
0: GPIO connected to VINP
1: DAC connected to VINP

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Bits 9:8 VM_SEL: Inverting input selection

These bits are used only when OPAMODE = 00, 01 or 10.
00:GPIO connected to VINM (valid also in PGA mode for filtering)
01: Dedicated low leakage input, (available only on BGA132) connected to VINM (valid also
in PGA mode for filtering)
1x: Inverting input not externally connected. These configurations are valid only when
OPAMODE = 10 (PGA mode)
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 PGA_GAIN: Operational amplifier Programmable amplifier gain value
00: internal PGA Gain 2
01: internal PGA Gain 4
10: internal PGA Gain 8
11: internal PGA Gain 16
Bits 3:2 OPAMODE: Operational amplifier PGA mode
00: internal PGA disable
01: internal PGA disable
10: internal PGA enable, gain programmed in PGA_GAIN
11: internal follower
Bit 1 OPALPM: Operational amplifier Low Power Mode
The operational amplifier must be disable to change this configuration.
0: operational amplifier in normal mode
1: operational amplifier in low-power mode
Bit 0 OPAEN: Operational amplifier Enable
0: operational amplifier disabled
1: operational amplifier enabled

27.5.5 OPAMP2 offset trimming register in normal mode (OPAMP2_OTR)

Address offset: 0x14
Reset value: 0x0000 XXXX (factory trimmed values)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. TRIMOFFSETP[4:0] Res. Res. Res. TRIMOFFSETN[4:0]
rw rw rw rw rw rw rw rw rw rw

Bits 31:13 Reserved, must be kept at reset value.

Bits 12:8 TRIMOFFSETP[4:0]: Trim for PMOS differential pairs
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 TRIMOFFSETN[4:0]: Trim for NMOS differential pairs

27.5.6 OPAMP2 offset trimming register in low-power mode

(OPAMP2_LPOTR)
Address offset: 0x18

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RM0432 Operational amplifiers (OPAMP)

Reset value: 0x0000 XXXX (factory trimmed values)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. TRIMLPOFFSETP[4:0] Res. Res. Res. TRIMLPOFFSETN[4:0]
rw rw rw rw rw rw rw rw rw rw

Bits 31:13 Reserved, must be kept at reset value.

Bits 12:8 TRIMLPOFFSETP[4:0]: Low-power mode trim for PMOS differential pairs
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 TRIMLPOFFSETN[4:0]: Low-power mode trim for NMOS differential pairs

27.5.7 OPAMP register map

Table 181. OPAMP register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
OPA_RANGE

USERTRIM

PGA_GAIN

OPAMODE

OPALPM
CALOUT

VM_SEL
CALSEL

VP_SEL
CALON

OPAEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
Res.
OPAMP1_CSR
0x00

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TRIM TRIM
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
OPAMP1_OTR
0x04 OFFSETP[4:0] OFFSETN[4:0]

Reset value (1) (1)

OPAMP1_ TRIMLP TRIMLP

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
0x08 LPOTR OFFSETP[4:0] OFFSETN[4:0]

Reset value (1) (1)

USERTRIM

PGA_GAIN

OPAMODE

OPALPM
CALOUT

VM_SEL
CALSEL

VP_SEL
CALON

OPAEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
Res.

OPAMP2_CSR
0x10

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0

TRIM TRIM
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.

OPAMP2_OTR
0x14 OFFSETP[4:0] OFFSETN[4:0]

Reset value (1) (1)

OPAMP2_LPO TRIMLP TRIMLP

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.

0x18 TR OFFSETP[4:0] OFFSETN[4:0]

Reset value (1) (1)

1. Factory trimmed values.

Refer to Section 2.2 on page 91 for the register boundary addresses.

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Digital filter for sigma delta modulators (DFSDM) RM0432

28 Digital filter for sigma delta modulators (DFSDM)

28.1 Introduction
Digital filter for sigma delta modulators (DFSDM) is a high-performance module dedicated to
interface external Σ∆ modulators. It is featuring up to 8 external digital serial interfaces
(channels) and up to 4 digital filters with flexible Sigma Delta stream digital processing
options to offer up to 24-bit final ADC resolution. DFSDM also features optional parallel data
stream input from internal ADC peripherals or from device memory.
An external Σ∆ modulator provides digital data stream of converted analog values from the
external Σ∆ modulator analog input. This digital data stream is sent into a DFSDM input
channel through a serial interface. DFSDM supports several standards to connect various
Σ∆ modulator outputs: SPI interface and Manchester coded 1-wire interface (both with
adjustable parameters). DFSDM module supports the connection of up to 8 multiplexed
input digital serial channels which are shared with up to 4 DFSDM modules. DFSDM
module also supports alternative parallel data inputs from up to 8 internal 16-bit data
channels (from internal ADCs or from device memory).
DFSDM is converting an input data stream into a final digital data word which represents an
analog input value on a Σ∆ modulator analog input. The conversion is based on a
configurable digital process: the digital filtering and decimation of the input serial data
stream.
The conversion speed and resolution are adjustable according to configurable parameters
for digital processing: filter type, filter order, length of filter, integrator length. The maximum
output data resolution is up to 24 bits. There are two conversion modes: single conversion
mode and continuous mode. The data can be automatically stored in a system RAM buffer
through DMA, thus reducing the software overhead.
A flexible timer triggering system can be used to control the start of conversion of DFSDM.
This timing control is capable of triggering simultaneous conversions or inserting a
programmable delay between conversions.
DFSDM features an analog watchdog function. Analog watchdog can be assigned to any of
the input channel data stream or to final output data. Analog watchdog has its own digital
filtering of input data stream to reach the required speed and resolution of watched data.
To detect short-circuit in control applications, there is a short-circuit detector. This block
watches each input channel data stream for occurrence of stable data for a defined time
duration (several 0’s or 1’s in an input data stream).
An extremes detector block watches final output data and stores maximum and minimum
values from the output data values. The extremes values stored can be restarted by
software.
Two power modes are supported: normal mode and stop mode.

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RM0432 Digital filter for sigma delta modulators (DFSDM)

28.2 DFSDM main features

• Up to 8 multiplexed input digital serial channels:
– configurable SPI interface to connect various Σ∆ modulators
– configurable Manchester coded 1 wire interface support
– clock output for Σ∆ modulator(s)
• Alternative inputs from up to 8 internal digital parallel channels:
– inputs with up to 16 bit resolution
– internal sources: ADCs data or memory (CPU/DMA write) data streams
• Adjustable digital signal processing:
– Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
– integrator: oversampling ratio (1..256)
• Up to 24-bit output data resolution:
– right bit-shifter on final data (0..31 bits)
• Signed output data format
• Automatic data offset correction (offset stored in register by user)
• Continuous or single conversion
• Start-of-conversion synchronization with:
– software trigger
– internal timers
– external events
– start-of-conversion synchronously with first DFSDM filter (DFSDM_FLT0)
• Analog watchdog feature:
– low value and high value data threshold registers
– own configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
– input from output data register or from one or more input digital serial channels
– continuous monitoring independently from standard conversion
• Short-circuit detector to detect saturated analog input values (bottom and top ranges):
– up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on input data stream
– monitoring continuously each channel (8 serial channel transceiver outputs)
• Break generation on analog watchdog event or short-circuit detector event
• Extremes detector:
– store minimum and maximum values of output data values
– refreshed by software
• Pulse skipper feature to support beamforming applications (delay line like behavior)
• DMA may be used to read the conversion data
• Interrupts: end of conversion, overrun, analog watchdog, short-circuit, channel clock
absence
• “regular” or “injected” conversions:
– “regular” conversions can be requested at any time or even in continuous mode
without having any impact on the timing of “injected” conversions
– “injected” conversions for precise timing and with high conversion priority

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28.3 DFSDM implementation

This section describes the configuration implemented in DFSDMx.

Table 182. STM32L4Rxxx and STM32L4Sxxx DFSDM1 implementation

DFSDM features DFSDM1

Number of channels 8

Number of filters 4
Input from internal ADC X
Supported trigger sources 32(1)
Pulses skipper X
ID registers support -
1. Refer to Table 186: DFSDM triggers connection for available trigger sources.

Table 183. STM32L4P5xx and STM32L4Q5xx DFSDM1 implementation

DFSDM features DFSDM1

Number of channels 4

Number of filters 2
Input from internal ADC X
Supported trigger sources 32(1)
Pulses skipper X
ID registers support -
1. Refer to Table 186: DFSDM triggers connection for available trigger sources.

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RM0432 Digital filter for sigma delta modulators (DFSDM)

28.4 DFSDM functional description

28.4.1 DFSDM block diagram

Figure 191. Single DFSDM block diagram

APB bus
ADC 0

ADC 7
Sample 1 Sample 0 16
Parallel input data
register 0
Sample 1 Sample 0
16
Parallel input data
register 7

Channel multiplexer
EXTRG[1:0]

Data 0
Filter Oversampling Oversampling
Clock 0 order ratio ratio
CKOUT Clock Mode 16
control control Pulse
DATIN0 skipper Sincx filter 0 Integrator unit 0
Serial transceiver 0 Data 3 Filter Oversampling Oversampling
CKIN0
order ratio ratio
Clock Mode Clock 3
control control Pulse 16
DATIN7 skipper Sincx filter 3 Integrator unit 3
CKIN7 Serial transceiver 7

8 watchdog filters
8 watchdog comparators Right bit-shift
count
Config
Status

Interrupt, Right bit-shift

break Calibration
count data
1's, 0's counter correction unit
threshold Interrupt,
Calibration data
High threshold break DFSDMcorrection
data 0 unit
Short circuit
1's, 0
detector 0's counter Filter 0 Low threshold
threshold config DFSDM data 3
Analog watchdog 0
Short circuit
detector 7 High threshold
Filter 3 Low threshold Data output
config
Analog watchdog 3

APB bus

Control unit Maximum value

Minimum value
Configuration Extremes
Interrupts and events:
registers detector 0
1) end of conversion Maximum value
2) analog watchdog Minimum value
DMA, interrupt, break 3) short circuit detection
control, clock control 4) overrun Extremes
detector 3
MSv43818V2

1. This example shows 4 DFSDM filters and 8 input channels (max. configuration).

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28.4.2 DFSDM pins and internal signals

Table 184. DFSDM external pins

Name Signal Type Remarks

VDD Power supply Digital power supply.

VSS Power supply Digital ground power supply.
CKIN[7:0] Clock input Clock signal provided from external Σ∆ modulator. FT input.
DATIN[7:0] Data input Data signal provided from external Σ∆ modulator. FT input.
Clock output to provide clock signal into external Σ∆
CKOUT Clock output
modulator.
External trigger Input trigger from two EXTI signals to start analog
EXTRG[1:0]
signal conversion (from GPIOs: EXTI11, EXTI15).

Table 185. DFSDM internal signals

Name Signal Type Remarks

Input trigger from internal/external trigger sources in order

Internal/
to start analog conversion (from internal sources:
dfsdm_jtrg[31:0] external trigger
synchronous input, from external sources: asynchronous
signal
input with synchronization). See Table 186 for details.
break signal Break signals event generation from Analog watchdog or
dfsdm_break[3:0]
output short-circuit detector
DMA request DMA request signal from each DFSDM_FLTx (x=0..3):
dfsdm_dma[3:0]
signal end of injected conversion event.
Interrupt
dfsdm_it[3:0] Interrupt signal for each DFSDM_FLTx (x=0..3)
request signal
ADC input
dfsdm_dat_adc[15:0] Up to 4 internal ADC data buses as parallel inputs.
data

Table 186. DFSDM triggers connection

Trigger name Trigger source

dfsdm_jtrg0 TIM1_TRGO
dfsdm_jtrg1 TIM1_TRGO2
dfsdm_jtrg2 TIM8_TRGO
dfsdm_jtrg3 TIM8_TRGO2
dfsdm_jtrg4 TIM3_TRGO
dfsdm_jtrg5 TIM4_TRGO
dfsdm_jtrg6 TIM16_OC1
dfsdm_jtrg7 TIM6_TRGO
dfsdm_jtrg8 TIM7_TRGO
dfsdm_jtrg[23:9] Reserved

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RM0432 Digital filter for sigma delta modulators (DFSDM)

Table 186. DFSDM triggers connection (continued)

Trigger name Trigger source

dfsdm_jtrg24 EXTI11
dfsdm_jtrg25 EXTI15
dfsdm_jtrg26 LTIMER1
dfsdm_jtrg[31:27] Reserved

Table 187. DFSDM break connection

Break name Break destination

dfsdm_break[0] TIM1/TIM15 break

dfsdm_break[1] TIM1 break2 / TIM16 break
dfsdm_break[2] TIM8/TIM17 break
dfsdm_break[3] TIM8 break2

28.4.3 DFSDM reset and clocks

DFSDM on-off control
The DFSDM interface is globally enabled by setting DFSDMEN=1 in the
DFSDM_CH0CFGR1 register. Once DFSDM is globally enabled, all input channels (y=0..7)
and digital filters DFSDM_FLTx (x=0..3) start to work if their enable bits are set (channel
enable bit CHEN in DFSDM_CHyCFGR1 and DFSDM_FLTx enable bit DFEN in
DFSDM_FLTxCR1).
Digital filter x DFSDM_FLTx (x=0..3) is enabled by setting DFEN=1 in the
DFSDM_FLTxCR1 register. Once DFSDM_FLTx is enabled (DFEN=1), both Sincx digital
filter unit and integrator unit are reinitialized.
By clearing DFEN, any conversion which may be in progress is immediately stopped and
DFSDM_FLTx is put into stop mode. All register settings remain unchanged except
DFSDM_FLTxAWSR and DFSDM_FLTxISR (which are reset).
Channel y (y=0..7) is enabled by setting CHEN=1 in the DFSDM_CHyCFGR1 register.
Once the channel is enabled, it receives serial data from the external Σ∆ modulator or
parallel internal data sources (ADCs or CPU/DMA wire from memory).
DFSDM must be globally disabled (by DFSDMEN=0 in DFSDM_CH0CFGR1) before
stopping the system clock to enter in the STOP mode of the device.

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DFSDM clocks
The internal DFSDM clock fDFSDMCLK, which is used to drive the channel transceivers,
digital processing blocks (digital filter, integrator) and next additional blocks (analog
watchdog, short-circuit detector, extremes detector, control block) is generated by the RCC
block and is derived from the system clock SYSCLK or peripheral clock PCLK2 (see
Section 6.4.32: Peripherals independent clock configuration register (RCC_CCIPR2)). The
DFSDM clock is automatically stopped in stop mode (if DFEN = 0 for all DFSDM_FLTx,
x=0..3).
The DFSDM serial channel transceivers can receive an external serial clock to sample an
external serial data stream. The internal DFSDM clock must be at least 4 times faster than
the external serial clock if standard SPI coding is used, and 6 times faster than the external
serial clock if Manchester coding is used.
DFSDM can provide one external output clock signal to drive external Σ∆ modulator(s) clock
input(s). It is provided on CKOUT pin. This output clock signal must be in the range
specified in given device datasheet and is derived from DFSDM clock or from audio clock
(see CKOUTSRC bit in DFSDM_CH0CFGR1 register) by programmable divider in the
range 2 - 256 (CKOUTDIV in DFSDM_CH0CFGR1 register). Audio clock source is SAI1
clock selected by SAI1SEL[1:0] field in RCC configuration (see Section 6.4.32: Peripherals
independent clock configuration register (RCC_CCIPR2)).

28.4.4 Serial channel transceivers

There are 8 multiplexed serial data channels which can be selected for conversion by each
filter or Analog watchdog or Short-circuit detector. Those serial transceivers receive data
stream from external Σ∆ modulator. Data stream can be sent in SPI format or Manchester
coded format (see SITP[1:0] bits in DFSDM_CHyCFGR1 register).
The channel is enabled for operation by setting CHEN=1 in DFSDM_CHyCFGR1 register.

Channel inputs selection

Serial inputs (data and clock signals) from DATINy and CKINy pins can be redirected from
the following channel pins. This serial input channel redirection is set by CHINSEL bit in
DFSDM_CHyCFGR1 register.
Channel redirection can be used to collect audio data from PDM (pulse density modulation)
stereo microphone type. PDM stereo microphone has one data and one clock signal. Data
signal provides information for both left and right audio channel (rising clock edge samples
for left channel and falling clock edge samples for right channel).

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Configuration of serial channels for PDM microphone input:

• PDM microphone signals (data, clock) will be connected to DFSDM input serial channel
y (DATINy, CKOUT) pins.
• Channel y will be configured: CHINSEL = 0 (input from given channel pins: DATINy,
CKINy).
• Channel (y-1) (modulo 8) will be configured: CHINSEL = 1 (input from the following
channel ((y-1)+1) pins: DATINy, CKINy).
• Channel y: SITP[1:0] = 0 (rising edge to strobe data) => left audio channel on channel
y.
• Channel (y-1): SITP[1:0] = 1 (falling edge to strobe data) => right audio channel on
channel y-1.
• Two DFSDM filters will be assigned to channel y and channel (y-1) (to filter left and
right channels from PDM microphone).

Figure 192. Input channel pins redirection

(. . .)

CH(ymax)
Decode
DATIN(ymax)
CKIN(ymax)

. . .
. . .
. . .
FLT(xmax)
.
CHy .
Decode .
DATINy
CKINy FLT(x+1)

FLTx
CH(y-1) .
Decode .
DATIN(y-1)
.
CKIN(y-1)
FLT0
. . .
. . .
. . .

CH0
Decode
DATAIN0
CKIN0

(. . .)
CHINSEL

RCH

MSv41632V1

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Output clock generation

A clock signal can be provided on CKOUT pin to drive external Σ∆ modulator clock inputs.
The frequency of this CKOUT signal is derived from DFSDM clock or from audio clock (see
CKOUTSRC bit in DFSDM_CH0CFGR1 register) divided by a predivider (see CKOUTDIV
bits in DFSDM_CH0CFGR1 register). If the output clock is stopped, then CKOUT signal is
set to low state (output clock can be stopped by CKOUTDIV=0 in DFSDM_CHyCFGR1
register or by DFSDMEN=0 in DFSDM_CH0CFGR1 register). The output clock stopping is
performed:
• 4 system clocks after DFSDMEN is cleared (if CKOUTSRC=0)
• 1 system clock and 3 audio clocks after DFSDMEN is cleared (if CKOUTSRC=1)
Before changing CKOUTSRC the software has to wait for CKOUT being stopped to avoid
glitch on CKOUT pin. The output clock signal frequency must be in the range 0 - 20 MHz.

SPI data input format operation

In SPI format, the data stream is sent in serial format through data and clock signals. Data
signal is always provided from DATINy pin. A clock signal can be provided externally from
CKINy pin or internally from a signal derived from the CKOUT signal source.
In case of external clock source selection (SPICKSEL[1:0]=0) data signal (on DATINy pin) is
sampled on rising or falling clock edge (of CKINy pin) according SITP[1:0] bits setting (in
DFSDM_CHyCFGR1 register).
Internal clock sources - see SPICKSEL[1:0] in DFSDM_CHyCFGR1 register:
• CKOUT signal:
– For connection to external Σ∆ modulator which uses directly its clock input (from
CKOUT) to generate its output serial communication clock.
– Sampling point: on rising/falling edge according SITP[1:0] setting.
• CKOUT/2 signal (generated on CKOUT rising edge):
– For connection to external Σ∆ modulator which divides its clock input (from
CKOUT) by 2 to generate its output serial communication clock (and this output
clock change is active on each clock input rising edge).
– Sampling point: on each second CKOUT falling edge.
• CKOUT/2 signal (generated on CKOUT falling edge):
– For connection to external Σ∆ modulator which divides its clock input (from
CKOUT) by 2 to generate its output serial communication clock (and this output
clock change is active on each clock input falling edge).
– Sampling point: on each second CKOUT rising edge.
Note: An internal clock source can only be used when the external Σ∆ modulator uses CKOUT
signal as a clock input (to have synchronous clock and data operation).
Internal clock source usage can save CKINy pin connection (CKINy pins can be used for
other purpose).
The clock source signal frequency must be in the range 0 - 20 MHz for SPI coding and less
than fDFSDMCLK/4.

Manchester coded data input format operation

In Manchester coded format, the data stream is sent in serial format through DATINy pin
only. Decoded data and clock signal are recovered from serial stream after Manchester

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decoding. There are two possible settings of Manchester codings (see SITP[1:0] bits in
DFSDM_CHyCFGR1 register):
• signal rising edge = log 0; signal falling edge = log 1
• signal rising edge = log 1; signal falling edge = log 0
The recovered clock signal frequency for Manchester coding must be in the range
0 - 10 MHz and less than fDFSDMCLK/6.
To correctly receive Manchester coded data, the CKOUTDIV divider (in
DFSDM_CH0CFGR1 register) must be set with respect to expected Manchester data rate
according formula:

( ( CKOUTDIV + 1 ) × T SYSCLK ) < T Manchester clock < ( 2 × CKOUTDIV × T SYSCLK )

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Figure 193. Channel transceiver timing diagrams

CKINy (SPICKSEL=0)
SPI timing : SPICKSEL = 0

twl twh tr tf
tsu th

SITP = 00
DATINy

tsu th

SITP = 01

SPICKSEL=3
CKOUT

SPICKSEL=2
SPI timing : SPICKSEL = 1, 2, 3

SPICKSEL=1

twl twh tr tf
tsu th

SITP = 0
DATINy

tsu th

SITP = 1

SITP = 2
DATINy
Manchester timing

SITP = 3

recovered clock

recovered data 0 0 1 1 0
MS30766V3

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RM0432 Digital filter for sigma delta modulators (DFSDM)

Clock absence detection

Channels serial clock inputs can be checked for clock absence/presence to ensure the
correct operation of conversion and error reporting. Clock absence detection can be
enabled or disabled on each input channel y by bit CKABEN in DFSDM_CHyCFGR1
register. If enabled, then this clock absence detection is performed continuously on a given
channel. A clock absence flag is set (CKABF[y] = 1) and an interrupt can be invoked (if
CKABIE=1) in case of an input clock error (see CKABF[7:0] in DFSDM_FLT0ISR register
and CKABEN in DFSDM_CHyCFGR1). After a clock absence flag clearing (by CLRCKABF
in DFSDM_FLT0ICR register), the clock absence flag is refreshed. Clock absence status bit
CKABF[y] is set also by hardware when corresponding channel y is disabled (if CHEN[y] = 0
then CKABF[y] is held in set state).
When a clock absence event has occurred, the data conversion (and/or analog watchdog
and short-circuit detector) provides incorrect data. The user should manage this event and
discard given data while a clock absence is reported.
The clock absence feature is available only when the system clock is used for the CKOUT
signal (CKOUTSRC=0 in DFSDM_CH0CFGR1 register).
When the transceiver is not yet synchronized, the clock absence flag is set and cannot be
cleared by CLRCKABF[y] bit (in DFSDM_FLT0ICR register). The software sequence
concerning clock absence detection feature should be:
• Enable given channel by CHEN = 1
• Try to clear the clock absence flag (by CLRCKABF = 1) until the clock absence flag is
really cleared (CKABF = 0). At this time, the transceiver is synchronized (signal clock is
valid) and is able to receive data.
• Enable the clock absence feature CKABEN = 1 and the associated interrupt CKABIE =
1 to detect if the SPI clock is lost or Manchester data edges are missing.
If SPI data format is used, then the clock absence detection is based on the comparison of
an external input clock with an output clock generation (CKOUT signal). The external input
clock signal into the input channel must be changed at least once per 8 signal periods of
CKOUT signal (which is controlled by CKOUTDIV field in DFSDM_CH0CFGR1 register).

Figure 194. Clock absence timing diagram for SPI

max. 8 periods

CKOUT 2 0 1 2 3 4 5 6 7 0
SPI clock presence

restart counting
CKINy
timing

last clock change

CKABF[y]

error reported
MS30767V2

If Manchester data format is used, then the clock absence means that the clock recovery is
unable to perform from Manchester coded signal. For a correct clock recovery, it is first
necessary to receive data with 1 to 0 or 0 to 1 transition (see Figure 196 for Manchester
synchronization).

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The detection of a clock absence in Manchester coding (after a first successful

synchronization) is based on changes comparison of coded serial data input signal with
output clock generation (CKOUT signal). There must be a voltage level change on DATINy
pin during 2 periods of CKOUT signal (which is controlled by CKOUTDIV bits in
DFSDM_CH0CFGR1 register). This condition also defines the minimum data rate to be able
to correctly recover the Manchester coded data and clock signals.
The maximum data rate of Manchester coded data must be less than the CKOUT signal.
So to correctly receive Manchester coded data, the CKOUTDIV divider must be set
according the formula:

( ( CKOUTDIV + 1 ) × T SYSCLK ) < T Manchester clock < ( 2 × CKOUTDIV × T SYSCLK )

A clock absence flag is set (CKABF[y] = 1) and an interrupt can be invoked (if CKABIE=1) in
case of an input clock recovery error (see CKABF[7:0] in DFSDM_FLT0ISR register and
CKABEN in DFSDM_CHyCFGR1). After a clock absence flag clearing (by CLRCKABF in
DFSDM_FLT0ICR register), the clock absence flag is refreshed.

Figure 195. Clock absence timing diagram for Manchester coding

max. 2 periods

CKOUT 0 0 0 1 0

restart counting

SITP = 2
Manchester clock presence

DATINy

last data change

timing

SITP = 3

recovered clock

recovered data 0 0 1 ? ?

CKABF[y]

error reported
MS30768V2

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Manchester/SPI code synchronization

The Manchester coded stream must be synchronized the first time after enabling the
channel (CHEN=1 in DFSDM_CHyCFGR1 register). The synchronization ends when a data
transition from 0 to 1 or from 1 to 0 (to be able to detect valid data edge) is received. The
end of the synchronization can be checked by polling CKABF[y]=0 for a given channel after
it has been cleared by CLRCKABF[y] in DFSDM_FLT0ICR, following the software sequence
detailed hereafter:
CKABF[y] flag is cleared by setting CLRCKABF[y] bit. If channel y is not yet synchronized
the hardware immediately set the CKABF[y] flag. Software is then reading back the
CKABF[y] flag and if it is set then perform again clearing of this flag by setting
CLRCKABF[y] bit. This software sequence (polling of CKABF[y] flag) continues until
CKABF[y] flag is set (signalizing that Manchester stream is synchronized). To be able to
synchronize/receive Manchester coded data the CKOUTDIV divider (in
DFSDM_CH0CFGR1 register) must be set with respect to expected Manchester data rate
according the formula below.

( ( CKOUTDIV + 1 ) × T SYSCLK ) < T Manchester clock < ( 2 × CKOUTDIV × T SYSCLK )

SPI coded stream is synchronized after first detection of clock input signal (valid
rising/falling edge).
Note: When the transceiver is not yet synchronized, the clock absence flag is set and cannot be
cleared by CLRCKABF[y] bit (in DFSDM_FLT0ICR register).

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Figure 196. First conversion for Manchester coding (Manchester synchronization)

SITP = 2
DATINy
Manchester timing

SITP = 3

recovered clock

data from
modulator 0 0 1 1 0

CHEN
real start of first conversion
first conversion
start trigger first data bit toggle - end of Manchester synchronization

recovered data ? ? 1 1 0

CKABF[y]

clearing of CKABF[y] flag by software polling

MS30769V2

External serial clock frequency measurement

The measuring of a channel serial clock input frequency provides a real data rate from an
external Σ∆ modulator, which is important for application purposes.
An external serial clock input frequency can be measured by a timer counting DFSDM
clocks (fDFSDMCLK) during one conversion duration. The counting starts at the first input data
clock after a conversion trigger (regular or injected) and finishes by last input data clock
before conversion ends (end of conversion flag is set). Each conversion duration (time
between first serial sample and last serial sample) is updated in counter CNVCNT[27:0] in
register DFSDM_FLTxCNVTIMR when the conversion finishes (JEOCF=1 or REOCF=1).
The user can then compute the data rate according to the digital filter settings (FORD,
FOSR, IOSR, FAST). The external serial frequency measurement is stopped only if the filter
is bypassed (FOSR=0, only integrator is active, CNVCNT[27:0]=0 in
DFSDM_FLTxCNVTIMR register).
In case of parallel data input (Section 28.4.6: Parallel data inputs) the measured frequency
is the average input data rate during one conversion.

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Note: When conversion is interrupted (e.g. by disabling/enabling the selected channel) the
interruption time is also counted in CNVCNT[27:0]. Therefore it is recommended to not
interrupt the conversion for correct conversion duration result.
Conversion times:
injected conversion or regular conversion with FAST = 0 (or first conversion if
FAST=1):
for Sincx filters (x=1..5):
t = CNVCNT/fDFSDMCLK = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN
for FastSinc filter:
t = CNVCNT/fDFSDMCLK = [FOSR * (IOSR-1 + 4) + 2] / fCKIN
regular conversion with FAST = 1 (except first conversion):
for Sincx and FastSinc filters:
t = CNVCNT/fDFSDMCLK = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
t = IOSR / fCKIN (... but CNVCNT=0)
where:
• fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data
rate (in case of parallel data input)
• FOSR is the filter oversampling ratio: FOSR = FOSR[9:0]+1 (see DFSDM_FLTxFCR
register)
• IOSR is the integrator oversampling ratio: IOSR = IOSR[7:0]+1 (see DFSDM_FLTxFCR
register)
• FORD is the filter order: FORD = FORD[2:0] (see DFSDM_FLTxFCR register)

Channel offset setting

Each channel has its own offset setting (in register) which is finally subtracted from each
conversion result (injected or regular) from a given channel. Offset correction is performed
after the data right bit shift. The offset is stored as a 24-bit signed value in OFFSET[23:0]
field in DFSDM_CHyCFGR2 register.

Data right bit shift

To have the result aligned to a 24-bit value, each channel defines a number of right bit shifts
which will be applied on each conversion result (injected or regular) from a given channel.
The data bit shift number is stored in DTRBS[4:0] bits in DFSDM_CHyCFGR2 register.
The right bit-shift is rounding the result to nearest integer value. The sign of shifted result is
maintained, in order to have valid 24-bit signed format of result data.

Pulses skipper
Purpose of the pulses skipper is to implement delay line like behavior for given input
channel(s). Given number of samples from input serial data stream (serial stream only) can
be discarded before they enter into the filter. This data discarding is performed by skipping
given number of sampling input clock pulses (given serial data samples are then not
sampled by filter). The sampling clock is gated by pulses skipper function for given number
of clock pulses. When given clock pulses are skipped then the filtering continues for
following input data. With comparison to non skipped data stream this operation causes that

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the final output sample (and next samples) from filter will be calculated from later input data.
This final sample then looks a bit in forward - because it is calculated from newer input
samples than the “non-skipped” sample. The final “skipped sample” is converted later
because the skipped input data samples must be replaced by followed input data samples.
The final data buffers behavior (skipped and non-skipped output data buffers comparison)
looks like the non-skipped data stream is a bit delayed - both data buffers will be phase
shifted.
Number of clock pulses to be skipped should be written into PLSSKP[5:0] field in
DFSDM_CHyDLYR register. Once PLSSKP[5:0] field is written the execution of pulses
skipping is started on given channel. PLSSKP[5:0] field can be read in order to check the
progress of pulses skipper. When PLSSKP[5:0]=0 means that pulses skipping has been
executed.
Up to 63 clock pulses can be skip with a single write operation into PLSSKP[5:0]. If more
pulses need to be skipped, then user has to write several times into the PLSSKP[5:0] field.
The application software should handle cumulative skipped clock number per each filter.

28.4.5 Configuring the input serial interface

The following parameters must be configured for the input serial interface:
• Output clock predivider. There is a programmable predivider to generate the output
clock from DFSDM clock (2 - 256). It is defined by CKOUTDIV[7:0] bits in
DFSDM_CH0CFGR1 register.
• Serial interface type and input clock phase. Selection of SPI or Manchester coding
and sampling edge of input clock. It is defined by SITP [1:0] bits in
DFSDM_CHyCFGR1 register.
• Input clock source. External source from CKINy pin or internal from CKOUT pin. It is
defined by SPICKSEL[1:0] field in DFSDM_CHyCFGR1 register.
• Final data right bit-shift. Defines the final data right bit shift to have the result aligned
to a 24-bit value. It is defined by DTRBS[4:0] in DFSDM_CHyCFGR2 register.
• Channel offset per channel. Defines the analog offset of a given serial channel (offset
of connected external Σ∆ modulator). It is defined by OFFSET[23:0] bits in
DFSDM_CHyCFGR2 register.
• short-circuit detector and clock absence per channel enable. To enable or disable
the short-circuit detector (by SCDEN bit) and the clock absence monitoring (by
CKABEN bit) on a given serial channel in register DFSDM_CHyCFGR1.
• Analog watchdog filter and short-circuit detector threshold settings. To configure
channel analog watchdog filter parameters and channel short-circuit detector
parameters. Configurations are defined in DFSDM_CHyAWSCDR register.

28.4.6 Parallel data inputs

Each input channel provides a register for 16-bit parallel data input (besides serial data
input). Each 16-bit parallel input can be sourced from internal data sources only:
• internal ADC results
• direct CPU/DMA writing.
The selection for using serial or parallel data input for a given channel is done by field
DATMPX[1:0] of DFSDM_CHyCFGR1 register. In DATMPX[1:0] is also defined the parallel
data source: internal ADC or direct write by CPU/DMA.

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Each channel contains a 32-bit data input register DFSDM_CHyDATINR in which it can be
written a 16-bit data. Data are in 16-bit signed format. Those data can be used as input to
the digital filter which is accepting 16-bit parallel data.
If serial data input is selected (DATMPX[1:0] = 0), the DFSDM_CHyDATINR register is write
protected.

Input from internal ADC

In case of ADC data parallel input (DATMPX[1:0]=1) the ADC[y+1] result is assigned to
channel y input (ADC1 is filling DFSDM_CHDATIN0R register, ADC2 is filling
DFSDM_CHDATIN1R register, ... , ADC8 is filling DFSDM_CHDATIN7R register). End of
conversion event from ADC[y+1] causes update of channel y data (parallel data from
ADC[y+1] are put as next sample to digital filter). Data from ADC[y+1] is written into
DFSDM_CHyDATINR register (field INDAT0[15:0]) when end of conversion event occurred.
The setting of data packing mode (DATPACK[1:0] in the DFSDM_CHyCFGR1 register) has
no effect in case of ADC data input.

Input from memory (direct CPU/DMA write)

The direct data write into DFSDM_CHyDATINR register by CPU or DMA (DATMPX[1:0]=2)
can be used as data input in order to process digital data streams from memory or
peripherals.
Data can be written by CPU or DMA into DFSDM_CHyDATINR register:
1. CPU data write:
Input data are written directly by CPU into DFSDM_CHyDATINR register.
2. DMA data write:
The DMA should be configured in memory-to-memory transfer mode to transfer data
from memory buffer into DFSDM_CHyDATINR register. The destination memory
address is the address of DFSDM_CHyDATINR register. Data are transferred at DMA
transfer speed from memory to DFSDM parallel input.
This DMA transfer is different from DMA used to read DFSDM conversion results. Both
DMA can be used at the same time - first DMA (configured as memory-to-memory
transfer) for input data writings and second DMA (configured as peripheral-to-memory
transfer) for data results reading.
The accesses to DFSDM_CHyDATINR can be either 16-bit or 32-bit wide, allowing to load
respectively one or two samples in one write operation. 32-bit input data register
(DFSDM_CHyDATINR) can be filled with one or two 16-bit data samples, depending on the
data packing operation mode defined in field DATPACK[1:0] of DFSDM_CHyCFGR1
register:
1. Standard mode (DATPACK[1:0]=0):
Only one sample is stored in field INDAT0[15:0] of DFSDM_CHyDATINR register which
is used as input data for channel y. The upper 16 bits (INDAT1[15:0]) are ignored and
write protected. The digital filter must perform one input sampling (from INDAT0[15:0])
to empty data register after it has been filled by CPU/DMA. This mode is used together
with 16-bit CPU/DMA access to DFSDM_CHyDATINR register to load one sample per
write operation.
2. Interleaved mode (DATPACK[1:0]=1):
DFSDM_CHyDATINR register is used as a two sample buffer. The first sample is
stored in INDAT0[15:0] and the second sample is stored in INDAT1[15:0]. The digital

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filter must perform two input samplings from channel y to empty DFSDM_CHyDATINR
register. This mode is used together with 32-bit CPU/DMA access to
DFSDM_CHyDATINR register to load two samples per write operation.
3. Dual mode (DATPACK[1:0]=2):
Two samples are written into DFSDM_CHyDATINR register. The data INDAT0[15:0] is
for channel y, the data in INDAT1[15:0] is for channel y+1. The data in INDAT1[15:0] is
automatically copied INDAT0[15:0] of the following (y+1) channel data register
DFSDM_CH[y+1]DATINR). The digital filters must perform two samplings - one from
channel y and one from channel (y+1) - in order to empty DFSDM_CHyDATINR
registers.
Dual mode setting (DATPACK[1:0]=2) is available only on even channel numbers (y =
0, 2, 4, 6). If odd channel (y = 1, 3, 5, 7) is set to Dual mode then both INDAT0[15:0]
and INDAT1[15:0] parts are write protected for this channel. If even channel is set to
Dual mode then the following odd channel must be set into Standard mode
(DATPACK[1:0]=0) for correct cooperation with even channels.
See Figure 197 for DFSDM_CHyDATINR registers data modes and assignments of data
samples to channels.

Figure 197. DFSDM_CHyDATINR registers operation modes and assignment

Standard mode Interleaved mode Dual mode

31 16 15 0 31 16 15 0 31 16 15 0
Unused Ch0 (sample 0) Ch0 (sample 1) Ch0 (sample 0) Ch1 (sample 0) Ch0 (sample 0) y=0

Unused Ch1 (sample 0) Ch1 (sample 1) Ch1 (sample 0) Unused Ch1 (sample 0) y=1

Unused Ch2 (sample 0) Ch2 (sample 1) Ch2 (sample 0) Ch3 (sample 0) Ch2 (sample 0) y=2

Unused Ch3 (sample 0) Ch3 (sample 1) Ch3 (sample 0) Unused Ch3 (sample 0) y=3

Unused Ch4 (sample 0) Ch4 (sample 1) Ch4 (sample 0) Ch5 (sample 0) Ch4 (sample 0) y=4

Unused Ch5 (sample 0) Ch5 (sample 1) Ch5 (sample 0) Unused Ch5 (sample 0) y=5

Unused Ch6 (sample 0) Ch6 (sample 1) Ch6 (sample 0) Ch7 (sample 0) Ch6 (sample 0) y=6

Unused Ch7 (sample 0) Ch7 (sample 1) Ch7 (sample 0) Unused Ch7 (sample 0) y=7
MS35354V3

The write into DFSDM_CHyDATINR register to load one or two samples must be performed
after the selected input channel (channel y) is enabled for data collection (starting
conversion for channel y). Otherwise written data are lost for next processing.
For example: for single conversion and interleaved mode, do not start writing pair of data
samples into DFSDM_CHyDATINR before the single conversion is started (any data
present in the DFSDM_CHyDATINR before starting a conversion is discarded).

28.4.7 Channel selection

There are 8 multiplexed channels which can be selected for conversion using the injected
channel group and/or using the regular channel.
The injected channel group is a selection of any or all of the 8 channels. JCHG[7:0] in the
DFSDM_FLTxJCHGR register selects the channels of the injected group, where JCHG[y]=1
means that channel y is selected.

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Injected conversions can operate in scan mode (JSCAN=1) or single mode (JSCAN=0). In
scan mode, each of the selected channels is converted, one after another. The lowest
channel (channel 0, if selected) is converted first, followed immediately by the next higher
channel until all the channels selected by JCHG[7:0] have been converted. In single mode
(JSCAN=0), only one channel from the selected channels is converted, and the channel
selection is moved to the next channel. Writing to JCHG[7:0] if JSCAN=0 resets the channel
selection to the lowest selected channel.
Injected conversions can be launched by software or by a trigger. They are never
interrupted by regular conversions.
The regular channel is a selection of just one of the 8 channels. RCH[2:0] in the
DFSDM_FLTxCR1 register indicates the selected channel.
Regular conversions can be launched only by software (not by a trigger). A sequence of
continuous regular conversions is temporarily interrupted when an injected conversion is
requested.
Performing a conversion on a disabled channel (CHEN=0 in DFSDM_CHyCFGR1 register)
causes that the conversion will never end - because no input data is provided (with no clock
signal). In this case, it is necessary to enable a given channel (CHEN=1 in
DFSDM_CHyCFGR1 register) or to stop the conversion by DFEN=0 in DFSDM_FLTxCR1
register.

28.4.8 Digital filter configuration

DFSDM contains a Sincx type digital filter implementation. This Sincx filter performs an input
digital data stream filtering, which results in decreasing the output data rate (decimation)
and increasing the output data resolution. The Sincx digital filter is configurable in order to
reach the required output data rates and required output data resolution. The configurable
parameters are:
• Filter order/type: (see FORD[2:0] bits in DFSDM_FLTxFCR register):
– FastSinc
– Sinc1
– Sinc2
– Sinc3
– Sinc4
– Sinc5
• Filter oversampling/decimation ratio (see FOSR[9:0] bits in DFSDM_FLTxFCR
register):
– FOSR = 1-1024 - for FastSinc filter and Sincx filter x = FORD = 1..3
– FOSR = 1-215 - for Sincx filter x = FORD = 4
– FOSR = 1-73 - for Sincx filter x = FORD = 5
The filter has the following transfer function (impulse response in H domain):
x
 1 – z – FOSR
• Sincx filter type: H ( z ) =  ----------------------------
-
 1 – z–1 

2
 1 – z – FOSR – ( 2 ⋅ FOSR )
• FastSinc filter type: H ( z ) =  ----------------------------
- ⋅ ( 1 + z )
 1 – z–1 

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Figure 198. Example: Sinc3 filter response

Gain (dB)

Normalized frequency (fIN/fDATA )

MS30770V1

Table 188. Filter maximum output resolution (peak data values from filter output)
for some FOSR values
FOSR Sinc1 Sinc2 FastSinc Sinc3 Sinc4 Sinc5

x +/- x +/- x2 +/- 2x2 +/- x3 +/- x4 +/- x5

4 +/- 4 +/- 16 +/- 32 +/- 64 +/- 256 +/- 1024
8 +/- 8 +/- 64 +/- 128 +/- 512 +/- 4096 -
32 +/- 32 +/- 1024 +/- 2048 +/- 32768 +/- 1048576 +/- 33554432
64 +/- 64 +/- 4096 +/- 8192 +/- 262144 +/- 16777216 +/- 1073741824
128 +/- 128 +/- 16384 +/- 32768 +/- 2097152 +/- 268435456
256 +/- 256 +/- 65536 +/- 131072 +/- 16777216 Result can overflow on full scale
1024 +/- 1024 +/- 1048576 +/- 2097152 +/- 1073741824 input (> 32-bit signed integer)

For more information about Sinc filter type properties and usage, it is recommended to study
the theory about digital filters (more resources can be downloaded from internet).

28.4.9 Integrator unit

The integrator performs additional decimation and a resolution increase of data coming from
the digital filter. The integrator simply performs the sum of data from a digital filter for a given
number of data samples from a filter.
The integrator oversampling ratio parameter defines how many data counts will be summed
to one data output from the integrator. IOSR can be set in the range 1-256 (see IOSR[7:0]
bits description in DFSDM_FLTxFCR register).

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Table 189. Integrator maximum output resolution (peak data values from integrator
output) for some IOSR values and FOSR = 256 and Sinc3 filter type (largest data)
IOSR Sinc1 Sinc2 FastSinc Sinc3 Sinc4 Sinc5

x +/- FOSR. x +/- FOSR2. x +/- 2.FOSR2. x +/- FOSR3. x +/- FOSR4. x +/- FOSR5. x
4 - - - +/- 67 108 864 - -
32 - - - +/- 536 870 912 - -
+/- 2 147 483
128 - - - - -
648
256 - - - +/- 232 - -

28.4.10 Analog watchdog

The analog watchdog purpose is to trigger an external signal (break or interrupt) when an
analog signal reaches or crosses given maximum and minimum threshold values. An
interrupt/event/break generation can then be invoked.
Each analog watchdog will supervise serial data receiver outputs (after the analog watchdog
filter on each channel) or data output register (current injected or regular conversion result)
according to AWFSEL bit setting (in DFSDM_FLTxCR1 register). The input channels to be
monitored or not by the analog watchdog x will be selected by AWDCH[7:0] in
DFSDM_FLTxCR2 register.
Analog watchdog conversions on input channels are independent from standard
conversions. In this case, the analog watchdog uses its own filters and signal processing on
each input channel independently from the main injected or regular conversions. Analog
watchdog conversions are performed in a continuous mode on the selected input channels
in order to watch channels also when main injected or regular conversions are paused
(RCIP = 0, JCIP = 0).
There are high and low threshold registers which are compared with given data values (set
by AWHT[23:0] bits in DFSDM_FLTxAWHTR register and by AWLT[23:0] bits in
DFSDM_FLTxAWLTR register).

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There are 2 options for comparing the threshold registers with the data values
• Option1: in this case, the input data are taken from final output data register
(AWFSEL=0). This option is characterized by:
– high input data resolution (up to 24-bits)
– slow response time - inappropriate for fast response applications like overcurrent
detection
– for the comparison the final data are taken after bit shifting and offset data
correction
– final data are available only after main regular or injected conversions are
performed
– can be used in case of parallel input data source (DATMPX[1:0] ≠ 0 in
DFSDM_CHyCFGR1 register)
• Option2: in this case, the input data are taken from any serial data receivers output
(AWFSEL=1). This option is characterized by:
– input serial data are processed by dedicated analog watchdog Sincx channel
filters with configurable oversampling ratio (1..32) and filter order (1..3) (see
AWFOSR[4:0] and AWFORD[1:0] bits setting in DFSDM_CHyAWSCDR register)
– lower resolution (up to 16-bit)
– fast response time - appropriate for applications which require a fast response like
overcurrent/overvoltage detection)
– data are available in continuous mode independently from main regular or injected
conversions activity
In case of input channels monitoring (AWFSEL=1), the data for comparison to threshold is
taken from channels selected by AWDCH[7:0] field (DFSDM_FLTxCR2 register). Each of
the selected channels filter result is compared to one threshold value pair (AWHT[23:0] /
AWLT[23:0]). In this case, only higher 16 bits (AWHT[23:8] / AWLT[23:8]) define the 16-bit
threshold compared with the analog watchdog filter output because data coming from the
analog watchdog filter is up to a 16-bit resolution. Bits AWHT[7:0] / AWLT[7:0] are not taken
into comparison in this case (AWFSEL=1).
Parameters of the analog watchdog filter configuration for each input channel are set in
DFSDM_CHyAWSCDR register (filter order AWFORD[1:0] and filter oversampling ratio
AWFOSR[4:0]).
Each input channel has its own comparator which compares the analog watchdog data
(from analog watchdog filter) with analog watchdog threshold values (AWHT/AWLT). When
several channels are selected (field AWDCH[7:0] field of DFSDM_FLTxCR2 register),
several comparison requests may be received simultaneously. In this case, the channel
request with the lowest number is managed first and then continuing to higher selected
channels. For each channel, the result can be recorded in a separate flag (fields
AWHTF[7:0], AWLTF[7:0] of DFSDM_FLTxAWSR register). Each channel request is
executed in 8 DFSDM clock cycles. So, the bandwidth from each channel is limited to 8
DFSDM clock cycles (if AWDCH[7:0] = 0xFF). Because the maximum input channel
sampling clock frequency is the DFSDM clock frequency divided by 4, the configuration
AWFOSR = 0 (analog watchdog filter is bypassed) cannot be used for analog watchdog
feature at this input clock speed. Therefore user must properly configure the number of
watched channels and analog watchdog filter parameters with respect to input sampling
clock speed and DFSDM frequency.

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Analog watchdog filter data for given channel y is available for reading by firmware on field
WDATA[15:0] in DFSDM_CHyWDATR register. That analog watchdog filter data is
converted continuously (if CHEN=1 in DFSDM_CHyCFGR1 register) with the data rate
given by the analog watchdog filter setting and the channel input clock frequency.
The analog watchdog filter conversion works like a regular Fast Continuous Conversion
without the intergator. The number of serial samples needed for one result from analog
watchdog filter output (at channel input clock frequency fCKIN):
first conversion:
for Sincx filters (x=1..5): number of samples = [FOSR * FORD + FORD + 1]
for FastSinc filter: number of samples = [FOSR * 4 + 2 + 1]
next conversions:
for Sincx and FastSinc filters: number of samples = [FOSR * IOSR]
where:
FOSR ....... filter oversampling ratio: FOSR = AWFOSR[4:0]+1 (see DFSDM_CHyAWSCDR
register)
FORD ....... the filter order: FORD = AWFORD[1:0] (see DFSDM_CHyAWSCDR register)
In case of output data register monitoring (AWFSEL=0), the comparison is done after a right
bit shift and an offset correction of final data (see OFFSET[23:0] and DTRBS[4:0] fields in
DFSDM_CHyCFGR2 register). A comparison is performed after each injected or regular
end of conversion for the channels selected by AWDCH[7:0] field (in DFSDM_FLTxCR2
register).
The status of an analog watchdog event is signalized in DFSDM_FLTxAWSR register where
a given event is latched. AWHTF[y]=1 flag signalizes crossing AWHT[23:0] value on
channel y. AWLTF[y]=1 flag signalizes crossing AWLT[23:0] value on channel y. Latched
events in DFSDM_FLTxAWSR register are cleared by writing ‘1’ into the corresponding
clearing bit CLRAWHTF[y] or CLRAWLTF[y] in DFSDM_FLTxAWCFR register.
The global status of an analog watchdog is signalized by the AWDF flag bit in
DFSDM_FLTxISR register (it is used for the fast detection of an interrupt source). AWDF=1
signalizes that at least one watchdog occurred (AWHTF[y]=1 or AWLTF[y]=1 for at least one
channel). AWDF bit is cleared when all AWHTF[7:0] and AWLTF[7:0] are cleared.
An analog watchdog event can be assigned to break output signal. There are four break
outputs to be assigned to a high or low threshold crossing event (dfsdm_break[3:0]). The
break signal assignment to a given analog watchdog event is done by BKAWH[3:0] and
BKAWL[3:0] fields in DFSDM_FLTxAWHTR and DFSDM_FLTxAWLTR register.

28.4.11 Short-circuit detector

The purpose of a short-circuit detector is to signalize with a very fast response time if an
analog signal reached saturated values (out of full scale ranges) and remained on this value
given time. This behavior can detect short-circuit or open circuit errors (e.g. overcurrent or
overvoltage). An interrupt/event/break generation can be invoked.
Input data into a short-circuit detector is taken from channel transceiver outputs.
There is an upcounting counter on each input channel which is counting consecutive 0’s or
1’s on serial data receiver outputs. A counter is restarted if there is a change in the data
stream received - 1 to 0 or 0 to 1 change of data signal. If this counter reaches a short-circuit
threshold register value (SCDT[7:0] bits in DFSDM_CHyAWSCDR register), then a short-

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circuit event is invoked. Each input channel has its short-circuit detector. Any channel can
be selected to be continuously monitored by setting the SCDEN bit (in DFSDM_CHyCFGR1
register) and it has its own short-circuit detector settings (threshold value in SCDT[7:0] bits,
status bit SCDF[7:0], status clearing bits CLRSCDF[7:0]). Status flag SCDF[y] is cleared
also by hardware when corresponding channel y is disabled (CHEN[y] = 0).
On each channel, a short-circuit detector event can be assigned to break output signal
dfsdm_break[3:0]. There are four break outputs to be assigned to a short-circuit detector
event. The break signal assignment to a given channel short-circuit detector event is done
by BKSCD[3:0] field in DFSDM_CHyAWSCDR register.
Short circuit detector cannot be used in case of parallel input data channel selection
(DATMPX[1:0] ≠ 0 in DFSDM_CHyCFGR1 register).
Four break outputs are totally available (shared with the analog watchdog function).

28.4.12 Extreme detector

The purpose of an extremes detector is to collect the minimum and maximum values of final
output data words (peak to peak values).
If the output data word is higher than the value stored in the extremes detector maximum
register (EXMAX[23:0] bits in DFSDM_FLTxEXMAX register), then this register is updated
with the current output data word value and the channel from which the data is stored is in
EXMAXCH[2:0] bits (in DFSDM_FLTxEXMAX register) .
If the output data word is lower than the value stored in the extremes detector minimum
register (EXMIN[23:0] bits in DFSDM_FLTxEXMIN register), then this register is updated
with the current output data word value and the channel from which the data is stored is in
EXMINCH[2:0] bits (in DFSDM_FLTxEXMIN register).
The minimum and maximum register values can be refreshed by software (by reading given
DFSDM_FLTxEXMAX or DFSDM_FLTxEXMIN register). After refresh, the extremes
detector minimum data register DFSDM_FLTxEXMIN is filled with 0x7FFFFF (maximum
positive value) and the extremes detector maximum register DFSDM_FLTxEXMAX is filled
with 0x800000 (minimum negative value).
The extremes detector performs a comparison after a right bit shift and an offset data
correction. For each extremes detector, the input channels to be considered into computing
the extremes value are selected in EXCH[7:0] bits (in DFSDM_FLTxCR2 register).

28.4.13 Data unit block

The data unit block is the last block of the whole processing path: External Σ∆ modulators -
Serial transceivers - Sinc filter - Integrator - Data unit block.
The output data rate depends on the serial data stream rate, and filter and integrator
settings. The maximum output data rate is:
f CKIN
Datarate samples ⁄ s = ------------------------------------------------------------------------------------------------------- ...FAST = 0, Sincx filter
F OSR ⋅ ( I OSR – 1 + F ORD ) + ( F ORD + 1 )

f CKIN
Datarate samples ⁄ s = -------------------------------------------------------------------------------- ...FAST = 0, FastSinc filter
F OSR ⋅ ( I OSR – 1 + 4 ) + ( 2 + 1 )

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or
f CKIN
Datarate samples ⁄ s = ------------------------------- ...FAST = 1
F OSR ⋅ I OSR

Maximum output data rate in case of parallel data input:

f DATAIN_RATE
Datarate samples ⁄ s = ------------------------------------------------------------------------------------------------------- ...FAST = 0, Sincx filter
F OSR ⋅ ( I OSR – 1 + F ORD ) + ( F ORD + 1 )

or
f DATAIN_RATE
Datarate samples ⁄ s = -------------------------------------------------------------------------------- ...FAST = 0, FastSinc filter
F OSR ⋅ ( I OSR – 1 + 4 ) + ( 2 + 1 )

or
f DATAIN_RATE
Datarate samples ⁄ s = ------------------------------------ ...FAST=1 or any filter bypass case ( F OSR = 1 )
F OSR ⋅ I OSR

where: f DATAIN_RATE ...input data rate from ADC or from CPU/DMA

The right bit-shift of final data is performed in this module because the final data width is 24-
bit and data coming from the processing path can be up to 32 bits. This right bit-shift is
configurable in the range 0-31 bits for each selected input channel (see DTRBS[4:0] bits in
DFSDM_CHyCFGR2 register). The right bit-shift is rounding the result to nearest integer
value. The sign of shifted result is maintained - to have valid 24-bit signed format of result
data.
In the next step, an offset correction of the result is performed. The offset correction value
(OFFSET[23:0] stored in register DFSDM_CHyCFGR2) is subtracted from the output data
for a given channel. Data in the OFFSET[23:0] field is set by software by the appropriate
calibration routine.
Due to the fact that all operations in digital processing are performed on 32-bit signed
registers, the following conditions must be fulfilled not to overflow the result:
FOSR FORD . IOSR <= 231 ... for Sincx filters, x = 1..5)
2 . FOSR 2 . IOSR <= 231 ... for FastSinc filter)
Note: In case of filter and integrator bypass (IOSR[7:0]=0, FOSR[9:0]=0), the input data rate
(fDATAIN_RATE) must be limited to be able to read all output data:
fDATAIN_RATE ≤ fAPB
where fAPB is the bus frequency to which the DFSDM peripheral is connected.

28.4.14 Signed data format

Each DFSDM input serial channel can be connected to one external Σ∆ modulator. An
external Σ∆ modulator can have 2 differential inputs (positive and negative) which can be
used for a differential or single-ended signal measurement.
A Σ∆ modulator output is always assumed in a signed format (a data stream of zeros and
ones from a Σ∆ modulator represents values -1 and +1).

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Signed data format in registers: Data is in a signed format in registers for final output data,
analog watchdog, extremes detector, offset correction. The msb of output data word
represents the sign of value (two’s complement format).

28.4.15 Launching conversions

Injected conversions can be launched using the following methods:
• Software: writing ‘1’ to JSWSTART in the DFSDM_FLTxCR1 register.
• Trigger: JEXTSEL[4:0] selects the trigger signal while JEXTEN activates the trigger
and selects the active edge at the same time (see the DFSDM_FLTxCR1 register).
• Synchronous with DFSDM_FLT0 if JSYNC=1: for DFSDM_FLTx (x>0), an injected
conversion is automatically launched when in DFSDM_FLT0; the injected conversion is
started by software (JSWSTART=1 in DFSDM_FLT0CR2 register). Each injected
conversion in DFSDM_FLTx (x>0) is always executed according to its local
configuration settings (JSCAN, JCHG, etc.).
If the scan conversion is enabled (bit JSCAN=1) then, each time an injected conversion is
triggered, all of the selected channels in the injected group (JCHG[7:0] bits in
DFSDM_FLTxJCHGR register) are converted sequentially, starting with the lowest channel
(channel 0, if selected).
If the scan conversion is disabled (bit JSCAN=0) then, each time an injected conversion is
triggered, only one of the selected channels in the injected group (JCHG[7:0] bits in
DFSDM_FLTxJCHGR register) is converted and the channel selection is then moved to the
next selected channel. Writing to the JCHG[7:0] bits when JSCAN=0 sets the channel
selection to the lowest selected injected channel.
Only one injected conversion can be ongoing at a given time. Thus, any request to launch
an injected conversion is ignored if another request for an injected conversion has already
been issued but not yet completed.
Regular conversions can be launched using the following methods:
• Software: by writing ‘1’ to RSWSTART in the DFSDM_FLTxCR1 register.
• Synchronous with DFSDM_FLT0 if RSYNC=1: for DFSDM_FLTx (x>0), a regular
conversion is automatically launched when in DFSDM_FLT0; a regular conversion is
started by software (RSWSTART=1 in DFSDM_FLT0CR2 register). Each regular
conversion in DFSDM_FLTx (x>0) is always executed according to its local
configuration settings (RCONT, RCH, etc.).
Only one regular conversion can be pending or ongoing at a given time. Thus, any request
to launch a regular conversion is ignored if another request for a regular conversion has
already been issued but not yet completed. A regular conversion can be pending if it was
interrupted by an injected conversion or if it was started while an injected conversion was in
progress. This pending regular conversion is then delayed and is performed when all
injected conversion are finished. Any delayed regular conversion is signalized by RPEND bit
in DFSDM_FLTxRDATAR register.

28.4.16 Continuous and fast continuous modes

Setting RCONT in the DFSDM_FLTxCR1 register causes regular conversions to execute in
continuous mode. RCONT=1 means that the channel selected by RCH[2:0] is converted
repeatedly after ‘1’ is written to RSWSTART.

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The regular conversions executing in continuous mode can be stopped by writing ‘0’ to
RCONT. After clearing RCONT, the on-going conversion is stopped immediately.
In continuous mode, the data rate can be increased by setting the FAST bit in the
DFSDM_FLTxCR1 register. In this case, the filter does not need to be refilled by new fresh
data if converting continuously from one channel because data inside the filter is valid from
previously sampled continuous data. The speed increase depends on the chosen filter
order. The first conversion in fast mode (FAST=1) after starting a continuous conversion by
RSWSTART=1 takes still full time (as when FAST=0), then each subsequent conversion is
finished in shorter intervals.
Conversion time in continuous mode:
if FAST = 0 (or first conversion if FAST=1):
for Sincx filters:
t = CNVCNT/fDFSDMCLK = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN
for FastSinc filter:
t = CNVCNT/fDFSDMCLK = [FOSR * (IOSR-1 + 4) + 2] / fCKIN
if FAST = 1 (except first conversion):
for Sincx and FastSinc filters:
t = CNVCNT/fDFSDMCLK = [FOSR * IOSR] / fCKIN
in case FOSR = FOSR[9:0]+1 = 1 (filter bypassed, only integrator active):
t = IOSR / fCKIN (... but CNVCNT=0)
Continuous mode is not available for injected conversions. Injected conversions can be
started by timer trigger to emulate the continuous mode with precise timing.
If a regular continuous conversion is in progress (RCONT=1) and if a write access to
DFSDM_FLTxCR1 register requesting regular continuous conversion (RCONT=1) is
performed, then regular continuous conversion is restarted from the next conversion cycle
(like new regular continuous conversion is applied for new channel selection - even if there
is no change in DFSDM_FLTxCR1 register).

28.4.17 Request precedence

An injected conversion has a higher precedence than a regular conversion. A regular
conversion which is already in progress is immediately interrupted by the request of an
injected conversion; this regular conversion is restarted after the injected conversion
finishes.
An injected conversion cannot be launched if another injected conversion is pending or
already in progress: any request to launch an injected conversion (either by JSWSTART or
by a trigger) is ignored as long as bit JCIP is ‘1’ (in the DFSDM_FLTxISR register).
Similarly, a regular conversion cannot be launched if another regular conversion is pending
or already in progress: any request to launch a regular conversion (using RSWSTART) is
ignored as long as bit RCIP is ‘1’ (in the DFSDM_FLTxISR register).
However, if an injected conversion is requested while a regular conversion is already in
progress, the regular conversion is immediately stopped and an injected conversion is
launched. The regular conversion is then restarted and this delayed restart is signalized in
bit RPEND.
Injected conversions have precedence over regular conversions in that a injected
conversion can temporarily interrupt a sequence of continuous regular conversions. When

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the sequence of injected conversions finishes, the continuous regular conversions start
again if RCONT is still set (and RPEND bit will signalize the delayed start on the first regular
conversion result).
Precedence also matters when actions are initiated by the same write to DFSDM, or if
multiple actions are pending at the end of another action. For example, suppose that, while
an injected conversion is in process (JCIP=1), a single write operation to DFSDM_FLTxCR1
writes ‘1’ to RSWSTART, requesting a regular conversion. When the injected sequence
finishes, the precedence dictates that the regular conversion is performed next and its
delayed start is signalized in RPEND bit.

28.4.18 Power optimization in run mode

In order to reduce the consumption, the DFSDM filter and integrator are automatically put
into idle when not used by conversions (RCIP=0, JCIP=0).

28.5 DFSDM interrupts

In order to increase the CPU performance, a set of interrupts related to the CPU event
occurrence has been implemented:
• End of injected conversion interrupt:
– enabled by JEOCIE bit in DFSDM_FLTxCR2 register
– indicated in JEOCF bit in DFSDM_FLTxISR register
– cleared by reading DFSDM_FLTxJDATAR register (injected data)
– indication of which channel end of conversion occurred, reported in JDATACH[2:0]
bits in DFSDM_FLTxJDATAR register
• End of regular conversion interrupt:
– enabled by REOCIE bit in DFSDM_FLTxCR2 register
– indicated in REOCF bit in DFSDM_FLTxISR register
– cleared by reading DFSDM_FLTxRDATAR register (regular data)
– indication of which channel end of conversion occurred, reported in
RDATACH[2:0] bits in DFSDM_FLTxRDATAR register
• Data overrun interrupt for injected conversions:
– occurred when injected converted data were not read from DFSDM_FLTxJDATAR
register (by CPU or DMA) and were overwritten by a new injected conversion
– enabled by JOVRIE bit in DFSDM_FLTxCR2 register
– indicated in JOVRF bit in DFSDM_FLTxISR register
– cleared by writing ‘1’ into CLRJOVRF bit in DFSDM_FLTxICR register
• Data overrun interrupt for regular conversions:
– occurred when regular converted data were not read from DFSDM_FLTxRDATAR
register (by CPU or DMA) and were overwritten by a new regular conversion
– enabled by ROVRIE bit in DFSDM_FLTxCR2 register
– indicated in ROVRF bit in DFSDM_FLTxISR register
– cleared by writing ‘1’ into CLRROVRF bit in DFSDM_FLTxICR register
• Analog watchdog interrupt:

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– occurred when converted data (output data or data from analog watchdog filter -
according to AWFSEL bit setting in DFSDM_FLTxCR1 register) crosses
over/under high/low thresholds in DFSDM_FLTxAWHTR / DFSDM_FLTxAWLTR
registers
– enabled by AWDIE bit in DFSDM_FLTxCR2 register (on selected channels
AWDCH[7:0])
– indicated in AWDF bit in DFSDM_FLTxISR register
– separate indication of high or low analog watchdog threshold error by AWHTF[7:0]
and AWLTF[7:0] fields in DFSDM_FLTxAWSR register
– cleared by writing ‘1’ into corresponding CLRAWHTF[7:0] or CLRAWLTF[7:0] bits
in DFSDM_FLTxAWCFR register
• Short-circuit detector interrupt:
– occurred when the number of stable data crosses over thresholds in
DFSDM_CHyAWSCDR register
– enabled by SCDIE bit in DFSDM_FLTxCR2 register (on channel selected by
SCDEN bi tin DFSDM_CHyCFGR1 register)
– indicated in SCDF[7:0] bits in DFSDM_FLTxISR register (which also reports the
channel on which the short-circuit detector event occurred)
– cleared by writing ‘1’ into the corresponding CLRSCDF[7:0] bit in
DFSDM_FLTxICR register
• Channel clock absence interrupt:
– occurred when there is clock absence on CKINy pin (see Clock absence detection
in Section 28.4.4: Serial channel transceivers)
– enabled by CKABIE bit in DFSDM_FLTxCR2 register (on channels selected by
CKABEN bit in DFSDM_CHyCFGR1 register)
– indicated in CKABF[y] bit in DFSDM_FLTxISR register
– cleared by writing ‘1’ into CLRCKABF[y] bit in DFSDM_FLTxICR register

Table 190. DFSDM interrupt requests

Event/Interrupt clearing Interrupt enable
Interrupt event Event flag
method control bit

End of injected conversion JEOCF reading DFSDM_FLTxJDATAR JEOCIE

End of regular conversion REOCF reading DFSDM_FLTxRDATAR REOCIE
Injected data overrun JOVRF writing CLRJOVRF = 1 JOVRIE
Regular data overrun ROVRF writing CLRROVRF = 1 ROVRIE
AWDF,
writing CLRAWHTF[7:0] = 1 AWDIE,
Analog watchdog AWHTF[7:0],
writing CLRAWLTF[7:0] = 1 (AWDCH[7:0])
AWLTF[7:0]
SCDIE,
short-circuit detector SCDF[7:0] writing CLRSCDF[7:0] = 1
(SCDEN)
CKABIE,
Channel clock absence CKABF[7:0] writing CLRCKABF[7:0] = 1
(CKABEN)

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28.6 DFSDM DMA transfer

To decrease the CPU intervention, conversions can be transferred into memory using a
DMA transfer. A DMA transfer for injected conversions is enabled by setting bit JDMAEN=1
in DFSDM_FLTxCR1 register. A DMA transfer for regular conversions is enabled by setting
bit RDMAEN=1 in DFSDM_FLTxCR1 register.
Note: With a DMA transfer, the interrupt flag is automatically cleared at the end of the injected or
regular conversion (JEOCF or REOCF bit in DFSDM_FLTxISR register) because DMA is
reading DFSDM_FLTxJDATAR or DFSDM_FLTxRDATAR register.

28.7 DFSDM channel y registers (y=0..7)

Word access (32-bit) must be used for registers write access except DFSDM_CHyDATINR
register. Write access to DFSDM_CHyDATINR register can be either word access (32-bit)
or half-word access (16-bit).

28.7.1 DFSDM channel y configuration register (DFSDM_CHyCFGR1)

This register specifies the parameters used by channel y.
Address offset: 0x00 + 0x20 * y, (y = 0 to 7)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM CKOUT
Res. Res. Res. Res. Res. Res. CKOUTDIV[7:0]
EN SRC
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CHIN CKAB
DATPACK[1:0] DATMPX[1:0] Res. Res. Res. CHEN SCDEN Res. SPICKSEL[1:0] SITP[1:0]
SEL EN

rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 DFSDMEN: Global enable for DFSDM interface

0: DFSDM interface disabled
1: DFSDM interface enabled
If DFSDM interface is enabled, then it is started to operate according to enabled y channels and
enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1).
Data cleared by setting DFSDMEN=0:
–all registers DFSDM_FLTxISR are set to reset state (x = 0..3)
–all registers DFSDM_FLTxAWSR are set to reset state (x = 0..3)
Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
Bit 30 CKOUTSRC: Output serial clock source selection
0: Source for output clock is from system clock
1: Source for output clock is from audio clock
–SAI1 clock selected by SAI1SEL[1:0] field in RCC configuration (see Section 6.4.32: Peripherals
independent clock configuration register (RCC_CCIPR2))
This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register).
Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
Bits 29:24 Reserved, must be kept at reset value.

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RM0432 Digital filter for sigma delta modulators (DFSDM)

Bits 23:16 CKOUTDIV[7:0]: Output serial clock divider

0: Output clock generation is disabled (CKOUT signal is set to low state)
1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
256 (Divider = CKOUTDIV+1).
CKOUTDIV also defines the threshold for a clock absence detection.
This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register).
If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is
performed one DFSDM clock cycle after DFSDMEN=0).
Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0)
Bits 15:14 DATPACK[1:0]: Data packing mode in DFSDM_CHyDATINR register.
0: Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty
DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.
1: Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:
–first sample in INDAT0[15:0] (assigned to channel y)
–second sample INDAT1[15:0] (assigned to channel y)
To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from
channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next
sample).
2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples:
–first sample INDAT0[15:0] (assigned to channel y)
–second sample INDAT1[15:0] (assigned to channel y+1)
To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel
y and second sample must be read by another digital filter from channel y+1. Dual mode is
available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7)
DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following
odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even
channel.
3: Reserved
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Bits 13:12 DATMPX[1:0]: Input data multiplexer for channel y
0: Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR
register is write protected.
1: Data to channel y are taken from internal analog to digital converter ADCy+1 output register
update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0]
part of DFSDM_CHyDATINR register.
2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write.
There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting.
3: Reserved
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).

Bits 11:9 Reserved, must be kept at reset value.

Bit 8 CHINSEL: Channel inputs selection
0: Channel inputs are taken from pins of the same channel y.
1: Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Bit 7 CHEN: Channel y enable
0: Channel y disabled
1: Channel y enabled
If channel y is enabled, then serial data receiving is started according to the given channel setting.

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Bit 6 CKABEN: Clock absence detector enable on channel y

0: Clock absence detector disabled on channel y
1: Clock absence detector enabled on channel y
Bit 5 SCDEN: Short-circuit detector enable on channel y
0: Input channel y will not be guarded by the short-circuit detector
1: Input channel y will be continuously guarded by the short-circuit detector
Bit 4 Reserved, must be kept at reset value.
Bits 3:2 SPICKSEL[1:0]: SPI clock select for channel y
0: clock coming from external CKINy input - sampling point according SITP[1:0]
1: clock coming from internal CKOUT output - sampling point according SITP[1:0]
2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge.
For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to
generate its output serial communication clock (and this output clock change is active on each
clock input rising edge).
3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge.
For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to
generate its output serial communication clock (and this output clock change is active on each
clock input falling edge).
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Bits 1:0 SITP[1:0]: Serial interface type for channel y
00: SPI with rising edge to strobe data
01: SPI with falling edge to strobe data
10: Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1
11: Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0
This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).

28.7.2 DFSDM channel y configuration register (DFSDM_CHyCFGR2)

This register specifies the parameters used by channel y.
Address offset: 0x04 + 0x20 * y, (y = 0 to 7)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

OFFSET[23:8]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OFFSET[7:0] DTRBS[4:0] Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw rw

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RM0432 Digital filter for sigma delta modulators (DFSDM)

Bits 31:8 OFFSET[23:0]: 24-bit calibration offset for channel y

For channel y, OFFSET is applied to the results of each conversion from this channel.
This value is set by software.
Bits 7:3 DTRBS[4:0]: Data right bit-shift for channel y
0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
will be performed to have final results. Bit-shift is performed before offset correction. The data shift is
rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid
24-bit signed format of result data).
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Bits 2:0 Reserved, must be kept at reset value.

28.7.3 DFSDM channel y analog watchdog and short-circuit detector register

(DFSDM_CHyAWSCDR)
Short-circuit detector and analog watchdog settings for channel y.
Address offset: 0x08 + 0x20 * y, (y = 0 to 7)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. AWFORD[1:0] Res. AWFOSR[4:0]

rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BKSCD[3:0] Res. Res. Res. Res. SCDT[7:0]

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:22 AWFORD[1:0]: Analog watchdog Sinc filter order on channel y
0: FastSinc filter type
1: Sinc1 filter type
2: Sinc2 filter type
3: Sinc3 filter type x
 1 – z – FOSR
Sincx filter type transfer function: H ( z ) =  ----------------------------
-
 1 – z –1 

2
 1 – z – FOSR – ( 2 ⋅ FOSR )
FastSinc filter type transfer function: H ( z ) =  ----------------------------
- ⋅ ( 1 + z )
 1 – z–1 
This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Bit 21 Reserved, must be kept at reset value.
Bits 20:16 AWFOSR[4:0]: Analog watchdog filter oversampling ratio (decimation rate) on channel y
0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
also the decimation ratio of the analog data rate.
This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Note: If AWFOSR = 0 then the filter has no effect (filter bypass).

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Bits 15:12 BKSCD[3:0]: Break signal assignment for short-circuit detector on channel y
BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y
BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
Bits 11:8 Reserved, must be kept at reset value.
Bits 7:0 SCDT[7:0]: short-circuit detector threshold for channel y
These bits are written by software to define the threshold counter for the short-circuit detector. If this
value is reached, then a short-circuit detector event occurs on a given channel.

28.7.4 DFSDM channel y watchdog filter data register

(DFSDM_CHyWDATR)
This register contains the data resulting from the analog watchdog filter associated to the
input channel y.
Address offset: 0x0C + 0x20 * y, (y = 0 to 7)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WDATA[15:0]

r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 WDATA[15:0]: Input channel y watchdog data
Data converted by the analog watchdog filter for input channel y. This data is continuously converted
(no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).

28.7.5 DFSDM channel y data input register (DFSDM_CHyDATINR)

This register contains 16-bit input data to be processed by DFSDM filter module. Write
access can be either word access (32-bit) or half-word access (16-bit).
Address offset: 0x10 + 0x20 * y, (y = 0 to 7)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

INDAT1[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INDAT0[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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RM0432 Digital filter for sigma delta modulators (DFSDM)

Bits 31:16 INDAT1[15:0]: Input data for channel y or channel y+1

Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2.
Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if
DATMPX[1:0]=1).
If DATPACK[1:0]=0 (standard mode)
INDAT0[15:0] is write protected (not used for input sample).
If DATPACK[1:0]=1 (interleaved mode)
Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored
into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y
data samples.
If DATPACK[1:0]=2 (dual mode).
For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of
channel (y+1).
For odd y channels: INDAT1[15:0] is write protected.
See Section 28.4.6: Parallel data inputs for more details.
INDAT0[15:1] is in the16-bit signed format.
Bits 15:0 INDAT0[15:0]: Input data for channel y
Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2.
Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if
DATMPX[1:0]=1).
If DATPACK[1:0]=0 (standard mode)
Channel y data sample is stored into INDAT0[15:0].
If DATPACK[1:0]=1 (interleaved mode)
First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored
into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y
data samples.
If DATPACK[1:0]=2 (dual mode).
For even y channels: Channel y data sample is stored into INDAT0[15:0].
For odd y channels: INDAT0[15:0] is write protected.
See Section 28.4.6: Parallel data inputs for more details.
INDAT0[15:0] is in the16-bit signed format.

28.7.6 DFSDM channel y delay register (DFSDM_CHyDLYR)

Address offset: 0x14 + 0x20 * y, (y = 0 to 7)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PLSSKP[5:0]

rw rw rw rw rw rw

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Digital filter for sigma delta modulators (DFSDM) RM0432

Bits 31:6 Reserved, must be kept at reset value.

Bits 5:0 PLSSKP[5:0]: Pulses to skip for input data skipping function
0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which
will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped.
Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero.

28.8 DFSDM filter x module registers (x=0..3)

Word access (32-bit) must be used for registers write access except DFSDM_CHyDATINR
register.

28.8.1 DFSDM filter x control register 1 (DFSDM_FLTxCR1)

Address offset: 0x100 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWF RDMA RCON RSW
Res. FAST Res. Res. RCH[2:0] Res. Res. Res. RSYNC Res.
SEL EN T START
rw rw rw rw rw rw rw rw rt_w1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDMA JSW
Res. JEXTEN[1:0] JEXTSEL[4:0] Res. Res. JSCAN JSYNC Res. DFEN
EN START
rw rw rw rw rw rw rw rw rw rw rt_w1 rw

Bit 31 Reserved, must be kept at reset value.

Bit 30 AWFSEL: Analog watchdog fast mode select
0: Analog watchdog on data output value (after the digital filter). The comparison is done after offset
correction and shift
1: Analog watchdog on channel transceivers value (after watchdog filter)
Bit 29 FAST: Fast conversion mode selection for regular conversions
0: Fast conversion mode disabled
1: Fast conversion mode enabled
When converting a regular conversion in continuous mode, having enabled the fast mode causes
each conversion (except the first) to execute faster than in standard mode. This bit has no effect on
conversions which are not continuous.
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN..... for Sincx filters
t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN..... for FastSinc filter
if FAST=1 in continuous mode (except first conversion):
t = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
t = IOSR / fCKIN (... but CNVCNT=0)
where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in
case of parallel data input.
Bits 28:27 Reserved, must be kept at reset value.

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RM0432 Digital filter for sigma delta modulators (DFSDM)

Bits 26:24 RCH[2:0]: Regular channel selection

0: Channel 0 is selected as the regular channel
1: Channel 1 is selected as the regular channel
...
7: Channel 7 is selected as the regular channel
Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is
especially useful in continuous mode (when RCONT=1). It also affects regular conversions which
are pending (due to ongoing injected conversion).
Bits 23:22 Reserved, must be kept at reset value.
Bit 21 RDMAEN: DMA channel enabled to read data for the regular conversion
0: The DMA channel is not enabled to read regular data
1: The DMA channel is enabled to read regular data
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Bit 20 Reserved, must be kept at reset value.
Bit 19 RSYNC: Launch regular conversion synchronously with DFSDM_FLT0
0: Do not launch a regular conversion synchronously with DFSDM_FLT0
1: Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion
is launched in DFSDM_FLT0
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Bit 18 RCONT: Continuous mode selection for regular conversions
0: The regular channel is converted just once for each conversion request
1: The regular channel is converted repeatedly after each conversion request
Writing ‘0’ to this bit while a continuous regular conversion is already in progress stops the
continuous mode immediately.

Bit 17 RSWSTART: Software start of a conversion on the regular channel

0: Writing ‘0’ has no effect
1: Writing ‘1’ makes a request to start a conversion on the regular channel and causes RCIP to
become ‘1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing ‘1’ has no effect if
RSYNC=1.
This bit is always read as ‘0’.
Bits 16:15 Reserved, must be kept at reset value.
Bits 14:13 JEXTEN[1:0]: Trigger enable and trigger edge selection for injected conversions
00: Trigger detection is disabled
01: Each rising edge on the selected trigger makes a request to launch an injected conversion
10: Each falling edge on the selected trigger makes a request to launch an injected conversion
11: Both rising edges and falling edges on the selected trigger make requests to launch injected
conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).

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Bits 12:8 JEXTSEL[4:0]: Trigger signal selection for launching injected conversions
0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter),
asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle).

DFSDM_FLTx
0x00 dfsdm_jtrg0
0x01 dfsdm_jtrg1
...
0x1E dfsdm_jtrg30
0x1F dfsdm_jtrg31
Refer to Table 186: DFSDM triggers connection.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 JDMAEN: DMA channel enabled to read data for the injected channel group
0: The DMA channel is not enabled to read injected data
1: The DMA channel is enabled to read injected data
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Bit 4 JSCAN: Scanning conversion mode for injected conversions
0: One channel conversion is performed from the injected channel group and next the selected
channel from this group is selected.
1: The series of conversions for the injected group channels is executed, starting over with the
lowest selected channel.
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
Bit 3 JSYNC: Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger
0: Do not launch an injected conversion synchronously with DFSDM_FLT0
1: Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected
conversion is launched in DFSDM_FLT0 by its JSWSTART trigger
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Bit 2 Reserved, must be kept at reset value.
Bit 1 JSWSTART: Start a conversion of the injected group of channels
0: Writing ‘0’ has no effect.
1: Writing ‘1’ makes a request to convert the channels in the injected conversion group, causing
JCIP to become ‘1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect.
Writing ‘1’ has no effect if JSYNC=1.
This bit is always read as ‘0’.
Bit 0 DFEN: DFSDM_FLTx enable
0: DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and
all DFSDM_FLTx functions are stopped.
1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating
according to its setting.
Data which are cleared by setting DFEN=0:
–register DFSDM_FLTxISR is set to the reset state
–register DFSDM_FLTxAWSR is set to the reset state

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RM0432 Digital filter for sigma delta modulators (DFSDM)

28.8.2 DFSDM filter x control register 2 (DFSDM_FLTxCR2)

Address offset: 0x104 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. AWDCH[7:0]

rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKAB ROVR JOVRI REOC JEOCI
EXCH[7:0] Res. SCDIE AWDIE
IE IE E IE E
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 AWDCH[7:0]: Analog watchdog channel selection
These bits select the input channel to be guarded continuously by the analog watchdog.
AWDCH[y] = 0: Analog watchdog is disabled on channel y
AWDCH[y] = 1: Analog watchdog is enabled on channel y
Bits 15:8 EXCH[7:0]: Extremes detector channel selection
These bits select the input channels to be taken by the Extremes detector.
EXCH[y] = 0: Extremes detector does not accept data from channel y
EXCH[y] = 1: Extremes detector accepts data from channel y
Bit 7 Reserved, must be kept at reset value.
Bit 6 CKABIE: Clock absence interrupt enable
0: Detection of channel input clock absence interrupt is disabled
1: Detection of channel input clock absence interrupt is enabled
Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR.
Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)
Bit 5 SCDIE: Short-circuit detector interrupt enable
0: short-circuit detector interrupt is disabled
1: short-circuit detector interrupt is enabled
Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR.
Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)
Bit 4 AWDIE: Analog watchdog interrupt enable
0: Analog watchdog interrupt is disabled
1: Analog watchdog interrupt is enabled
Please see the explanation of AWDF in DFSDM_FLTxISR.
Bit 3 ROVRIE: Regular data overrun interrupt enable
0: Regular data overrun interrupt is disabled
1: Regular data overrun interrupt is enabled
Please see the explanation of ROVRF in DFSDM_FLTxISR.

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Bit 2 JOVRIE: Injected data overrun interrupt enable

0: Injected data overrun interrupt is disabled
1: Injected data overrun interrupt is enabled
Please see the explanation of JOVRF in DFSDM_FLTxISR.
Bit 1 REOCIE: Regular end of conversion interrupt enable
0: Regular end of conversion interrupt is disabled
1: Regular end of conversion interrupt is enabled
Please see the explanation of REOCF in DFSDM_FLTxISR.
Bit 0 JEOCIE: Injected end of conversion interrupt enable
0: Injected end of conversion interrupt is disabled
1: Injected end of conversion interrupt is enabled
Please see the explanation of JEOCF in DFSDM_FLTxISR.

28.8.3 DFSDM filter x interrupt and status register (DFSDM_FLTxISR)

Address offset: 0x108 + 0x80 * x, (x = 0 to 3)
Reset value: 0x00FF 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SCDF[7:0] CKABF[7:0]

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. RCIP JCIP Res. Res. Res. Res. Res. Res. Res. Res. AWDF ROVRF JOVRF REOCF JEOCF

r r r r r r r

Bits 31:24 SCDF[7:0]: short-circuit detector flag

SDCF[y]=0: No short-circuit detector event occurred on channel y
SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the
DFSDM_CHyAWSCDR registers
This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in
the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given
channel is disabled).
Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
Bits 23:16 CKABF[7:0]: Clock absence flag
CKABF[y]=0: Clock signal on channel y is present.
CKABF[y]=1: Clock signal on channel y is not present.
Given y bit is set by hardware when clock absence is detected on channel y. It is held at
CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at
CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by
software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register.
Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
Bit 15 Reserved, must be kept at reset value.
Bit 14 RCIP: Regular conversion in progress status
0: No request to convert the regular channel has been issued
1: The conversion of the regular channel is in progress or a request for a regular conversion is
pending
A request to start a regular conversion is ignored when RCIP=1.

870/2301 RM0432 Rev 6

RM0432 Digital filter for sigma delta modulators (DFSDM)

Bit 13 JCIP: Injected conversion in progress status

0: No request to convert the injected channel group (neither by software nor by trigger) has been
issued
1: The conversion of the injected channel group is in progress or a request for a injected conversion
is pending, due either to ‘1’ being written to JSWSTART or to a trigger detection
A request to start an injected conversion is ignored when JCIP=1.
Bits 12:5 Reserved, must be kept at reset value.
Bit 4 AWDF: Analog watchdog
0: No Analog watchdog event occurred
1: The analog watchdog block detected voltage which crosses the value programmed in the
DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers.
This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and
AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing ‘1’ into the clear bits in
DFSDM_FLTxAWCFR register).
Bit 3 ROVRF: Regular conversion overrun flag
0: No regular conversion overrun has occurred
1: A regular conversion overrun has occurred, which means that a regular conversion finished while
REOCF was already ‘1’. RDATAR is not affected by overruns
This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the
DFSDM_FLTxICR register.
Bit 2 JOVRF: Injected conversion overrun flag
0: No injected conversion overrun has occurred
1: An injected conversion overrun has occurred, which means that an injected conversion finished
while JEOCF was already ‘1’. JDATAR is not affected by overruns
This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the
DFSDM_FLTxICR register.
Bit 1 REOCF: End of regular conversion flag
0: No regular conversion has completed
1: A regular conversion has completed and its data may be read
This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.
Bit 0 JEOCF: End of injected conversion flag
0: No injected conversion has completed
1: An injected conversion has completed and its data may be read
This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.

Note: For each of the flag bits, an interrupt can be enabled by setting the corresponding bit in
DFSDM_FLTxCR2. If an interrupt is called, the flag must be cleared before exiting the
interrupt service routine.
All the bits of DFSDM_FLTxISR are automatically reset when DFEN=0.

RM0432 Rev 6 871/2301

889
Digital filter for sigma delta modulators (DFSDM) RM0432

28.8.4 DFSDM filter x interrupt flag clear register (DFSDM_FLTxICR)

Address offset: 0x10C + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CLRSCDF[7:0] CLRCKABF[7:0]

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRR CLRJ
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
OVRF OVRF
rc_w1 rc_w1

Bits 31:24 CLRSCDF[7:0]: Clear the short-circuit detector flag

CLRSCDF[y]=0: Writing ‘0’ has no effect
CLRSCDF[y]=1: Writing ‘1’ to position y clears the corresponding SCDF[y] bit in the
DFSDM_FLTxISR register
Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
Bits 23:16 CLRCKABF[7:0]: Clear the clock absence flag
CLRCKABF[y]=0: Writing ‘0’ has no effect
CLRCKABF[y]=1: Writing ‘1’ to position y clears the corresponding CKABF[y] bit in the
DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is
set and cannot be cleared by CLRCKABF[y].
Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
Bits 15:4 Reserved, must be kept at reset value.
Bit 3 CLRROVRF: Clear the regular conversion overrun flag
0: Writing ‘0’ has no effect
1: Writing ‘1’ clears the ROVRF bit in the DFSDM_FLTxISR register
Bit 2 CLRJOVRF: Clear the injected conversion overrun flag
0: Writing ‘0’ has no effect
1: Writing ‘1’ clears the JOVRF bit in the DFSDM_FLTxISR register
Bits 1:0 Reserved, must be kept at reset value.

Note: The bits of DFSDM_FLTxICR are always read as ‘0’.

872/2301 RM0432 Rev 6

RM0432 Digital filter for sigma delta modulators (DFSDM)

28.8.5 DFSDM filter x injected channel group selection register

(DFSDM_FLTxJCHGR)
Address offset: 0x110 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0001

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. JCHG[7:0]

rw rw rw rw rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 JCHG[7:0]: Injected channel group selection
JCHG[y]=0: channel y is not part of the injected group
JCHG[y]=1: channel y is part of the injected group
If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel
(channel 0, if selected) is converted first and the sequence ends at the highest selected channel.
If JSCAN=0, then only one channel is converted from the selected channels, and the channel
selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to
the lowest selected channel.
At least one channel must always be selected for the injected group. Writes causing all JCHG bits to
be zero are ignored.

28.8.6 DFSDM filter x control register (DFSDM_FLTxFCR)

Address offset: 0x114 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

FORD[2:0] Res. Res. Res. FOSR[9:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. IOSR[7:0]

rw rw rw rw rw rw rw rw

RM0432 Rev 6 873/2301

889
Digital filter for sigma delta modulators (DFSDM) RM0432

Bits 31:29 FORD[2:0]: Sinc filter order

0: FastSinc filter type
1: Sinc1 filter type
2: Sinc2 filter type
3: Sinc3 filter type
4: Sinc4 filter type
5: Sinc5 filter type
6-7: Reserved x
 1 – z –FOSR
Sincx filter type transfer function: H ( z ) =  ----------------------------
-
 1 – z –1 

2
 1 – z –FOSR
FastSinc filter type transfer function: - ⋅ ( 1 + z –( 2 ⋅ FOSR ) )
H ( z ) =  ----------------------------
 1 – z –1 
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).
Bits 28:26 Reserved, must be kept at reset value.
Bits 25:16 FOSR[9:0]: Sinc filter oversampling ratio (decimation rate)
0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This
number is also the decimation ratio of the output data rate from filter.
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If FOSR = 0, then the filter has no effect (filter bypass).
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 IOSR[7:0]: Integrator oversampling ratio (averaging length)
0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples
from Sinc filter will be summed into one output data sample from the integrator. The output data rate
from the integrator will be decreased by this number (additional data decimation ratio).
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass).

28.8.7 DFSDM filter x data register for injected group

(DFSDM_FLTxJDATAR)
Address offset: 0x118 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

JDATA[23:8]

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

JDATA[7:0] Res. Res. Res. Res. Res. JDATACH[2:0]

r r r r r r r r r r r

874/2301 RM0432 Rev 6

RM0432 Digital filter for sigma delta modulators (DFSDM)

Bits 31:8 JDATA[23:0]: Injected group conversion data

When each conversion of a channel in the injected group finishes, its resulting data is stored in this
field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 JDATACH[2:0]: Injected channel most recently converted
When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to
indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the
channel indicated by JDATACH[2:0].

Note: DMA may be used to read the data from this register. Half-word accesses may be used to
read only the MSBs of conversion data.
Reading this register also clears JEOCF in DFSDM_FLTxISR. Thus, the firmware must not
read this register if DMA is activated to read data from this register.

28.8.8 DFSDM filter x data register for the regular channel

(DFSDM_FLTxRDATAR)
Address offset: 0x11C + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RDATA[23:8]

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RDATA[7:0] Res. Res. Res. RPEND Res. RDATACH[2:0]

r r r r r r r r r r r r

Bits 31:8 RDATA[23:0]: Regular channel conversion data

When each regular conversion finishes, its data is stored in this register. The data is valid when
REOCF=1. Reading this register clears the corresponding REOCF.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 RPEND: Regular channel pending data
Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 RDATACH[2:0]: Regular channel most recently converted
When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was
converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be
updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the
channel indicated by RDATACH[2:0].

Note: Half-word accesses may be used to read only the MSBs of conversion data.
Reading this register also clears REOCF in DFSDM_FLTxISR.

RM0432 Rev 6 875/2301

889
Digital filter for sigma delta modulators (DFSDM) RM0432

28.8.9 DFSDM filter x analog watchdog high threshold register

(DFSDM_FLTxAWHTR)
Address offset: 0x120 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

AWHT[23:8]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AWHT[7:0] Res. Res. Res. Res. BKAWH[3:0]

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:8 AWHT[23:0]: Analog watchdog high threshold

These bits are written by software to define the high threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the
16-bit threshold as compared with the analog watchdog filter output (because data coming from
the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into
comparison in this case.
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 BKAWH[3:0]: Break signal assignment to analog watchdog high threshold event
BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event
BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event

28.8.10 DFSDM filter x analog watchdog low threshold register

(DFSDM_FLTxAWLTR)
Address offset: 0x124 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

AWLT[23:8]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AWLT[7:0] Res. Res. Res. Res. BKAWL[3:0]

rw rw rw rw rw rw rw rw rw rw rw rw

876/2301 RM0432 Rev 6

RM0432 Digital filter for sigma delta modulators (DFSDM)

Bits 31:8 AWLT[23:0]: Analog watchdog low threshold

These bits are written by software to define the low threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define
the 16-bit threshold as compared with the analog watchdog filter output (because data coming
from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into
comparison in this case.
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 BKAWL[3:0]: Break signal assignment to analog watchdog low threshold event
BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event
BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event

28.8.11 DFSDM filter x analog watchdog status register

(DFSDM_FLTxAWSR)
Address offset: 0x128 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AWHTF[7:0] AWLTF[7:0]

r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:8 AWHTF[7:0]: Analog watchdog high threshold flag
AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by
software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.
Bits 7:0 AWLTF[7:0]: Analog watchdog low threshold flag
AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by
software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.

Note: All the bits of DFSDM_FLTxAWSR are automatically reset when DFEN=0.

RM0432 Rev 6 877/2301

889
Digital filter for sigma delta modulators (DFSDM) RM0432

28.8.12 DFSDM filter x analog watchdog clear flag register

(DFSDM_FLTxAWCFR)
Address offset: 0x12C + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CLRAWHTF[7:0] CLRAWLTF[7:0]

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:8 CLRAWHTF[7:0]: Clear the analog watchdog high threshold flag
CLRAWHTF[y]=0: Writing ‘0’ has no effect
CLRAWHTF[y]=1: Writing ‘1’ to position y clears the corresponding AWHTF[y] bit in the
DFSDM_FLTxAWSR register
Bits 7:0 CLRAWLTF[7:0]: Clear the analog watchdog low threshold flag
CLRAWLTF[y]=0: Writing ‘0’ has no effect
CLRAWLTF[y]=1: Writing ‘1’ to position y clears the corresponding AWLTF[y] bit in the
DFSDM_FLTxAWSR register

28.8.13 DFSDM filter x extremes detector maximum register

(DFSDM_FLTxEXMAX)
Address offset: 0x130 + 0x80 * x, (x = 0 to 3)
Reset value: 0x8000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

EXMAX[23:8]

rs_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EXMAX[7:0] Res. Res. Res. Res. Res. EXMAXCH[2:0]

rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r r r r

Bits 31:8 EXMAX[23:0]: Extremes detector maximum value

These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx.
EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 EXMAXCH[2:0]: Extremes detector maximum data channel.
These bits contains information about the channel on which the data is stored into EXMAX[23:0].
Bits are cleared by reading of this register.

878/2301 RM0432 Rev 6

RM0432 Digital filter for sigma delta modulators (DFSDM)

28.8.14 DFSDM filter x extremes detector minimum register

(DFSDM_FLTxEXMIN)
Address offset: 0x134 + 0x80 * x, (x = 0 to 3)
Reset value: 0x7FFF FF00

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

EXMIN[23:8]

rc_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EXMIN[7:0] Res. Res. Res. Res. Res. EXMINCH[2:0]

rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r r r r

Bits 31:8 EXMIN[23:0]: Extremes detector minimum value

These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx.
EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 EXMINCH[2:0]: Extremes detector minimum data channel
These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits
are cleared by reading of this register.

28.8.15 DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR)

Address offset: 0x138 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CNVCNT[27:12]

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CNVCNT[11:0] Res. Res. Res. Res.

r r r r r r r r r r r r

RM0432 Rev 6 879/2301

889
Digital filter for sigma delta modulators (DFSDM) RM0432

Bits 31:4 CNVCNT[27:0]: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK
The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time
measurement is started on each conversion start and stopped when conversion finishes (interval
between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion
time measurement stopped and CNVCNT[27:0] = 0. The counted time is:
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN..... for Sincx filters
t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN..... for FastSinc filter
if FAST=1 in continuous mode (except first conversion):
t = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN)
where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in
case of parallel data input (from internal ADC or from CPU/DMA write)
Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also
this interruption time.
Bits 3:0 Reserved, must be kept at reset value.

28.8.16 DFSDM register map

The following table summarizes the DFSDM registers.

Table 191. DFSDM register map and reset values

Register
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name
DATPACK[1:0]

DATMPX[1:0]
CKOUTSRC
DFSDMEN

SPICKSEL
CHINSEL

SITP[1:0]
CKABEN
SCDEN
CHEN
DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.

Res.

[1:0]
CKOUTDIV[7:0]
0x00 CH0CFGR1

reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_

Res.
Res.
Res.
OFFSET[23:0] DTRBS[4:0]
0x04 CH0CFGR2
reset value 0 0
AWFORD

DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
Res.
Res.
Res.
[1:0]

AWFOSR[4:0] BKSCD[3:0] SCDT[7:0]

0x08 CH0AWSCDR

reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

WDATA[15:0]
0x0C CH0WDATR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_
INDAT1[15:0] INDAT0[15:0]
0x10 CH0DATINR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

PLSSKP[5:0]
0x14 CH0DLYR
reset value 0 0 0 0 0 0
0x18 -
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Reserved
0x1C

880/2301 RM0432 Rev 6

 0x54
0x50
0x48
0x44
0x40
0x34
0x30
0x28
0x24
0x20

0x5C
0x4C
0x3C
0x2C

0x58 -
0x38 -
Offset
RM0432

name

DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_

Reserved
Reserved

CH2DLYR
CH1DLYR

reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
Register

CH2CFGR2
CH2CFGR1
CH1CFGR2
CH1CFGR1

CH2WDATR
CH1WDATR

CH2DATINR
CH1DATINR

CH2AWSCDR
CH1AWSCDR

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 23

AWFORD[1:0] AWFORD[1:0]

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res.

INDAT1[15:0]
INDAT1[15:0]
22

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 20

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 19

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res.

OFFSET[23:0]
OFFSET[23:0]

18

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res.

RM0432 Rev 6
17

AWFOSR[4:0]
AWFOSR[4:0]

0
0
0
0
0

0
0

Res. Res. Res. Res. Res. Res. Res. Res. 16

0
0
0
0

0
0
0
0
0
0

Res. Res. Res. Res. 15

DATPACK[1:0] DATPACK[1:0]

0
0
0

0
0
0
0
0
0
0

Res. Res. Res. Res. 14

0
0
0

0
0
0
0
0
0
0

Res. Res. Res. Res. 13

DATMPX[1:0] DATMPX[1:0]

BKSCD[3:0]
BKSCD[3:0]

0
0
0
0

0
0
0
0
0
0

Res. Res. Res. Res. 12

0
0
0
0

0
0

Res. Res. Res. Res. Res. Res. Res. Res. 11

0
0
0
0

0
0

Res. Res. Res. Res. Res. Res. Res. Res. 10

0
0
0
0

0
0

Res. Res. Res. Res. Res. Res. Res. Res. 9

0
0
0
0

0
0
0
0

Res. Res. Res. CHINSEL Res. Res. Res. CHINSEL 8

Table 191. DFSDM register map and reset values (continued)

0
0
0
0

0
0
0
0
0
0

Res. Res. CHEN Res. Res. CHEN 7

0
0
0
0

0
0
0
0
0
0

Res. Res. CKABEN Res. Res. CKABEN

WDATA[15:0]
WDATA[15:0]

INDAT0[15:0]
INDAT0[15:0]

0
0
0
0

0
0
0
0
0
0

0
0

Res. SCDEN Res. SCDEN 5

0
0
0
0

0
0
0
0

0
0

Res. Res. Res. Res. 4

DTRBS[4:0]
DTRBS[4:0]

0
0
0
0

0
0
0
0

0
0
0
0

Res. Res. SPICKSEL 3

SPICKSEL[1:0]

SCDT[7:0]
SCDT[7:0]

[1:0]

0
0

0
0
0
0

0
0
0
0

Res. Res. Res. Res. 2

0
0

0
0
0
0

0
0
0
0

PLSSKP[5:0]
PLSSKP[5:0]

Res. Res. Res. Res. 1

SITP[1:0] SITP[1:0]

0
0

0
0
0
0

0
0
0
0

Res. Res. Res. Res. 0

Digital filter for sigma delta modulators (DFSDM)

881/2301
889
 0x94
0x90
0x88
0x84
0x80
0x74
0x70
0x68
0x64
0x60

0x9C
0x8C
0x7C
0x6C

0x98 -
0x78 -
Offset

882/2301
name

DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_

Reserved
Reserved

CH4DLYR
CH3DLYR

reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
Register

CH4CFGR2
CH4CFGR1
CH3CFGR2
CH3CFGR1

CH4WDATR
CH3WDATR

CH4DATINR
CH3DATINR

CH4AWSCDR
CH3AWSCDR

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 23

AWFORD[1:0] AWFORD[1:0]

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res.

INDAT1[15:0]
INDAT1[15:0]
22

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 20

Digital filter for sigma delta modulators (DFSDM)

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 19

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res.

OFFSET[23:0]
OFFSET[23:0]

18

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res.

RM0432 Rev 6
17

AWFOSR[4:0]
AWFOSR[4:0]

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 16

0
0
0

0
0
0
0
0
0
0

Res. Res. Res. Res. 15

DATPACK[1:0] DATPACK[1:0]

0
0

0
0
0
0
0
0
0
0

Res. Res. Res. Res. 14

0
0
0
0

0
0
0
0
0
0

Res. Res. Res. Res. 13

DATMPX[1:0] DATMPX[1:0]

BKSCD[3:0]
BKSCD[3:0]

0
0
0
0

0
0
0
0
0
0

Res. Res. Res. Res. 12

0
0
0
0

0
0

Res. Res. Res. Res. Res. Res. Res. Res. 11

0
0
0
0

0
0

Res. Res. Res. Res. Res. Res. Res. Res. 10

0
0
0
0

0
0

Res. Res. Res. Res. Res. Res. Res. Res. 9

0
0
0
0

0
0
0
0

Res. Res. Res. CHINSEL Res. Res. Res. CHINSEL 8

Table 191. DFSDM register map and reset values (continued)

0
0
0
0

0
0
0
0
0
0

Res. Res. CHEN Res. Res. CHEN 7

0
0
0
0

0
0
0
0
0
0

Res. Res. CKABEN Res. Res. CKABEN

WDATA[15:0]
WDATA[15:0]

INDAT0[15:0]
INDAT0[15:0]

0
0
0
0

0
0
0
0
0
0

0
0

Res. SCDEN Res. SCDEN 5

0
0
0
0

0
0
0
0

0
0

Res. Res. Res. Res. 4

DTRBS[4:0]
DTRBS[4:0]

0
0
0
0

0
0

0
0
0
0

0
0

Res. Res. 3
SPICKSEL[1:0] SPICKSEL[1:0]

SCDT[7:0]
SCDT[7:0]

0
0

0
0
0
0

0
0
0
0

Res. Res. Res. Res. 2

0
0

0
0
0
0

0
0
0
0

PLSSKP[5:0]
PLSSKP[5:0]

Res. Res. Res. Res. 1

SITP[1:0] SITP[1:0]

0
0

0
0
0
0

0
0
0
0

Res. Res. Res. Res. 0

RM0432
 0xB4
0xB0
0xA8
0xA4
0xA0

0xD4
0xD0
0xC8
0xC4
0xC0
0xBC
0xAC

0xDC
0xCC
0xB8 -

0xD8 -
Offset
RM0432

name

DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_

Reserved
Reserved

CH6DLYR
CH5DLYR

reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
Register

CH6CFGR2
CH6CFGR1
CH5CFGR2
CH5CFGR1

CH6WDATR
CH5WDATR

CH6DATINR
CH5DATINR

CH6AWSCDR
CH5AWSCDR

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 23

AWFORD[1:0] AWFORD[1:0]

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res.

INDAT1[15:0]
INDAT1[15:0]
22

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 20

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 19

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res.

OFFSET[23:0]
OFFSET[23:0]

18

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res.

RM0432 Rev 6
17

AWFOSR[4:0]
AWFOSR[4:0]

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 16

0
0
0
0

0
0
0
0
0
0

Res. Res. Res. Res. 15

DATPACK[1:0] DATPACK[1:0]

0
0
0
0

0
0
0
0
0
0

Res. Res. Res. Res. 14

0
0
0

0
0
0
0
0
0
0

Res. Res. Res. Res. 13

DATMPX[1:0] DATMPX[1:0]

BKSCD[3:0]
BKSCD[3:0]

0
0
0
0

0
0
0
0
0
0

Res. Res. Res. Res. 12

0
0
0
0

0
0

Res. Res. Res. Res. Res. Res. Res. Res. 11

0
0
0
0

0
0

Res. Res. Res. Res. Res. Res. Res. Res. 10

0
0
0
0

0
0

Res. Res. Res. Res. Res. Res. Res. Res. 9

0
0
0
0

0
0
0
0

Res. Res. Res. CHINSEL Res. Res. Res. CHINSEL 8

Table 191. DFSDM register map and reset values (continued)

0
0
0
0

0
0
0
0
0
0

Res. Res. CHEN Res. Res. CHEN 7

0
0
0
0

0
0
0
0
0
0

Res. Res. CKABEN Res. Res. CKABEN

WDATA[15:0]
WDATA[15:0]

INDAT0[15:0]
INDAT0[15:0]

0
0
0
0

0
0
0
0
0
0

0
0

Res. SCDEN Res. SCDEN 5

0
0
0
0

0
0
0
0

0
0

Res. Res. Res. Res. 4

DTRBS[4:0]
DTRBS[4:0]

0
0
0
0

0
0
0

0
0
0

0
0

Res. Res. 3
SPICKSEL[1:0] SPICKSEL[1:0]

SCDT[7:0]
SCDT[7:0]

0
0

0
0
0
0

0
0
0
0

Res. Res. Res. Res. 2

0
0

0
0
0
0

0
0
0
0

PLSSKP[5:0]
PLSSKP[5:0]

Res. Res. Res. Res. 1

SITP[1:0] SITP[1:0]

0
0

0
0
0
0

0
0
0
0

Res. Res. Res. Res. 0

Digital filter for sigma delta modulators (DFSDM)

883/2301
889
 0xF4
0xF0
0xE8
0xE4
0xE0

0xFC
0xEC

0x114
0x110
0x108
0x104
0x100
0xF8 -

0x10C
Offset

884/2301
name

FLT0ISR

FLT0ICR

DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_

Reserved

FLT0CR2
FLT0CR1

FLT0FCR
CH7DLYR

reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
Register

CH7CFGR2
CH7CFGR1

CH7WDATR

CH7DATINR

FLT0JCHGR
CH7AWSCDR

0
0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. 31

0
0
0
0
0
0
FORD[2:0] Res. Res. AWFSEL Res. Res. Res. Res. Res. 30

0
0
0
0
0
0
Res. Res. FAST Res. Res. Res. Res. Res. 29

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. 28

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. 27

SCDF[7:0]

0
0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. 26

CLRSCDF[7:0]

0
0
0
0
0
0
Res. Res. Res. Res. Res. Res. Res. 25

0
0
0
0
0
0

RCH[2:0]
Res. Res. Res. Res. Res. Res. Res. 24

0
0
1
0
0
0
0

Res. Res. Res. Res. Res. Res. 23

AWFORD[1:0]

0
0
1
0
0
0
0

Res. Res. Res. Res. Res. Res.

INDAT1[15:0]
22

0
0
1
0
0
0
0

Res. RDMAEN Res. Res. Res. Res. Res. 21

0
0
1
0
0
0
0

Res. Res. Res. Res. Res. Res. 20

Digital filter for sigma delta modulators (DFSDM)

FOSR[9:0]

0
0
1
0
0
0
0
0

Res. RSYNC Res. Res. Res. Res. 19

CKABF[7:0]

0
0
1
0
0
0
0
0

AWDCH[7:0]
Res. RCONT Res. Res. Res. Res.
OFFSET[23:0]

18

CLRCKABF[7:0]

0
0
1
0
0
0
0
0

Res. RSW START Res. Res. Res. Res.

RM0432 Rev 6
17
AWFOSR[4:0]

0
0
1
0
0
0
0

Res. Res. Res. Res. Res. Res. 16

0
0
0

0
0
0

Res. Res. Res. Res. Res. Res. Res. 15

DATPACK[1:0]

0
0
0
0
0
0
0
0

Res. Res. Res. RCIP Res. Res. 14

JEXTEN[1:0]

0
0
0
0
0
0
0
0

Res. Res. Res. JCIP Res. Res. 13

DATMPX[1:0]
BKSCD[3:0]

0
0
0
0

0
0
0

Res. Res. Res. Res. Res. Res. 12

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 11

EXCH[7:0]

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 10

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 9

JEXTSEL[4:0]

0
0
0
0

0
0

Res. Res. Res. Res. Res. Res. Res. CHINSEL 8

Table 191. DFSDM register map and reset values (continued)

0
0
0

0
0

0
0

Res. Res. Res. Res. Res. Res. CHEN 7

0
0
0
0

0
0

0
0

Res. Res. CKABIE Res. Res. Res. CKABEN

WDATA[15:0]

INDAT0[15:0]

0
0
0
0
0

0
0

0
0

Res. Res. SCDIE JDMAEN Res. SCDEN 5

0
0
0
0
0
0

0
0

0
0

Res. AWDF AWDIE JSCAN Res. Res. 4

DTRBS[4:0]

0
0
0
0
0
0
0

0
0

0
0
0

CLR ROVRF ROVRF ROVRIE JSYNC Res. 3

SPICKSEL[1:0]

IOSR[7:0]
JCHG[7:0]
SCDT[7:0]

0
0
0
0
0
0
0

0
0
0

CLR JOVRF JOVRF JOVRIE Res. Res. Res. 2

0
0
0
0
0
0
0

0
0
0

PLSSKP[5:0]

Res. REOCF REOCIE JSW START Res. Res. 1

SITP[1:0]

0
0
0
0
0
0
0

1
0
0

Res. JEOCF JEOCIE DFEN Res. Res. 0

RM0432
RM0432 Digital filter for sigma delta modulators (DFSDM)

Table 191. DFSDM register map and reset values (continued)

Register
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name

JDATACH [2:0]
DFSDM_

Res.
Res.
Res.
Res.
Res.
JDATA[23:0]
0x118 FLT0JDATAR

reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RDATA

RPEND
DFSDM_

Res.
Res.
Res.

Res.
RDATA[23:0] CH[2:0]
0x11C FLT0RDATAR

reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_

Res.
Res.
Res.
Res.
AWHT[23:0] BKAWH[3:0]
0x120 FLT0AWHTR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_

Res.
Res.
Res.
Res.
AWLT[23:0] BKAWL[3:0]
0x124 FLT0AWLTR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AWHTF[7:0] AWLTF[7:0]
0x128 FLT0AWSR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

CLRAWHTF[7:0] CLRAWLTF[7:0]
0x12C FLT0AWCFR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXMAXCH[2:0]
DFSDM_

Res.
Res.
Res.
Res.
Res.
EXMAX[23:0]
0x130 FLT0EXMAX

reset value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXMINCH[2:0]
DFSDM_
Res.
Res.
Res.
Res.
Res.
FLT0EXMIN EXMIN[23:0]
0x134

reset value 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
DFSDM_
Res.
Res.
Res.

FLT0CNVTIMR
CNVCNT[27:0] Res.
0x138
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x13C -
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RSW START Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Reserved
0x17C
JEXTEN[1:0]

JSW START
RDMAEN

JDMAEN
AWFSEL

RCONT
RSYNC

JSCAN
JSYNC

DFEN

DFSDM_
FAST
Res.

Res.
Res.

Res.
Res.

Res.

Res.
Res.

Res.
Res.

Res.

RCH[2:0] JEXTSEL[4:0]
0x180 FLT1CR1

reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ROVRIE

REOCIE
JEOCIE
JOVRIE
AWDIE

DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.

AWDCH[7:0] EXCH[7:0]
0x184 FLT1CR2

reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ROVRF

REOCF
JOVRF

JEOCF
AWDF

DFSDM_
RCIP
JCIP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

0x188 FLT1ISR

reset value 0 0 0 0 0 0 0

RM0432 Rev 6 885/2301

889
Digital filter for sigma delta modulators (DFSDM) RM0432

Table 191. DFSDM register map and reset values (continued)

Register
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name

CLR ROVRF
CLR JOVRF
DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
0x18C FLT1ICR

reset value 0 0
DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
JCHG[7:0]
0x190 FLT1JCHGR
reset value 0 0 0 0 0 0 0 1
FORD[2:0]

DFSDM_
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FOSR[9:0] IOSR[7:0]
0x194 FLT1FCR

reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

JDATACH[2:0]
DFSDM_

Res.
Res.
Res.
Res.
Res.
JDATA[23:0]
0x198 FLT1JDATAR

reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RDATA

RPEND
DFSDM_

Res.
Res.
Res.

Res.
RDATA[23:0] CH[2:0]
0x19C FLT1RDATAR

reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_

Res.
Res.
Res.
Res.
AWHT[23:0] BKAWH[3:0]
0x1A0 FLT1AWHTR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_
Res.
Res.
Res.
Res.
AWLT[23:0] BKAWL[3:0]
0x1A4 FLT1AWLTR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

AWHTF[7:0] AWLTF[7:0]
0x1A8 FLT1AWSR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

CLRAWHTF[7:0] CLRAWLTF[7:0]
0x1AC FLT1AWCFR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EXMAXCH[2:0]

DFSDM_
Res.
Res.
Res.
Res.
Res.

EXMAX[23:0]
0x1B0 FLT1EXMAX

reset value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EXMINCH[2:0]

DFSDM_
Res.
Res.
Res.
Res.
Res.

FLT1EXMIN EXMIN[23:0]
0x1B4

reset value 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
DFSDM_
Res.
Res.
Res.
Res.

CNVCNT[27:0]
0x1B8 FLT1CNVTIMR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x1BC -
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Reserved
0x1FC

886/2301 RM0432 Rev 6

RM0432 Digital filter for sigma delta modulators (DFSDM)

Table 191. DFSDM register map and reset values (continued)

Register
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name

RSW START

JEXTEN[1:0]

JSW START
RDMAEN

JDMAEN
AWFSEL

RCONT
RSYNC

JSCAN
JSYNC

DFEN
DFSDM_

FAST
Res.

Res.
Res.

Res.
Res.

Res.

Res.
Res.

Res.
Res.

Res.
RCH[2:0] JEXTSEL[4:0]
0x200 FLT2CR1

reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ROVRIE

REOCIE
JOVRIE

JEOCIE
AWDIE
DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
AWDCH[7:0] EXCH[7:0]
0x204 FLT2CR2

reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ROVRF

REOCF
JOVRF

JEOCF
AWDF
DFSDM_

RCIP
JCIP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x208 FLT2ISR

reset value 0 0 0 0 0 0 0

CLR ROVRF
CLR JOVRF
DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
0x20C FLT2ICR

reset value 0 0
DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
JCHG[7:0]
0x210 FLT2JCHGR
reset value 0 0 0 0 0 0 0 1
FORD[2:0]

DFSDM_
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FOSR[9:0] IOSR[7:0]
0x214 FLT2FCR

reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

JDATACH[2:0]
DFSDM_
Res.
Res.
Res.
Res.
Res.
JDATA[23:0]
0x218 FLT2JDATAR

reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RDATA
RPEND

DFSDM_
Res.
Res.
Res.

Res.

RDATA[23:0] CH[2:0]
0x21C FLT2RDATAR

reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_
Res.
Res.
Res.
Res.

AWHT[23:0] BKAWH[3:0]
0x220 FLT2AWHTR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_
Res.
Res.
Res.
Res.

AWLT[23:0] BKAWL[3:0]
0x224 FLT2AWLTR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

AWHTF[7:0] AWLTF[7:0]
0x228 FLT2AWSR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

CLRAWHTF[7:0] CLRAWLTF[7:0]
0x22C FLT2AWCFR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RM0432 Rev 6 887/2301

889
 0x298
0x294
0x290
0x288
0x284
0x280
0x238
0x234
0x230

0x28C
0x27C
0x23C -
Offset

888/2301
name

FLT3ISR

FLT3ICR

DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_

Reserved

FLT3CR2
FLT3CR1

FLT3FCR

reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
Register

FLT2EXMIN

FLT3JCHGR
FLT2EXMAX

FLT3JDATAR
FLT2CNVTIMR

0
0
0
0
1
Res. Res. Res. Res. Res. Res. 31

0
0
0
0
1
0
FORD[2:0] Res. Res. Res. Res. AWFSEL Res. 30

0
0
0
0
1
0
Res. Res. Res. Res. FAST Res. 29

0
0
1
Res. Res. Res. Res. Res. Res. Res. 0
28

0
0
1
0

Res. Res. Res. Res. Res. Res. Res. 27

0
0
0
1
0

Res. Res. Res. Res. Res. Res. 26

0
0
0
0
1
0

Res. Res. Res. Res. Res. 25

0
0
0
0
1
0

RCH[2:0]
Res. Res. Res. Res. Res. 24

0
0
0
0
1
0

Res. Res. Res. Res. Res. 23

0
0
0
0
1
0

Res. Res. Res. Res. Res. 22

0
0
0
0
0
1
0

Res. Res. Res. RDMAEN Res. 21

0
0
0
0
1
0

Res. Res. Res. Res. Res. 20

Digital filter for sigma delta modulators (DFSDM)

FOSR[9:0]

0
0
0
0
0
1
0

Res. Res. Res. RSYNC Res. 19

JDATA[23:0]

0
0
0
0
0
1
0

EXMIN[23:0]

AWDCH[7:0]
Res. Res. Res. RCONT Res.
EXMAX[23:0]

18

0
0
0
0
0
1
0

Res. Res. Res. RSW START Res.

RM0432 Rev 6
17

0
0
0
0
1
0

Res. Res. Res. Res. Res. 16

CNVCNT[27:0]

0
0
0
1
0

Res. Res. Res. Res. Res. Res. 15

0
0
1
0

0
0
0
Res. Res. Res. RCIP Res. 14
JEXTEN[1:0]

0
0
1
0

0
0
Res. Res. Res. JCIP 0 Res. 13

0
0
0
0
1
0

Res. Res. Res. Res. Res. 12

0
0
0
0
1
0

Res. Res. Res. Res. EXCH[7:0] Res. 11

0
0
0
0
1
0

Res. Res. Res. Res. Res. 10

0
0
0
0
1
0

Res. Res. Res. Res. Res. 9

JEXTSEL[4:0]

0
0
0
0
1
0

Res. Res. Res. Res. Res. 8

Table 191. DFSDM register map and reset values (continued)

0
0

0
Res. Res. Res. Res. Res. Res. Res. Res. 7

0
0

0
Res. Res. Res. Res. Res. Res. Res. Res. 6

0
0
0

0
Res. Res. Res. Res. JDMAEN Res. Res. Res. 5

0
0
0
0

0
0
Res. Res. AWDF AWDIE JSCAN Res. Res. Res. 4

0
0
0

0
0
0

Res. CLR ROVRF ROVRF ROVRIE JSYNC Res. Res. Res. Res. 3

IOSR[7:0]
JCHG[7:0]

0
0
0
0
0

0
0
0

CLR JOVRF JOVRF JOVRIE Res. Res. Res. 2

0
0
0
0
0
0

0
0

JDATACH[2:0] Res. REOCF REOCIE JSW START Res. Res. EXMINCH[2:0] EXMAXCH[2:0] 1

0
0
0
0
0
0

1
0

Res. JEOCF JEOCIE DFEN Res. Res. 0

RM0432
RM0432 Digital filter for sigma delta modulators (DFSDM)

Table 191. DFSDM register map and reset values (continued)

Register
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name
RDATA

RPEND
DFSDM_

Res.
Res.
Res.

Res.
RDATA[23:0] CH[2:0]
0x29C FLT3RDATAR

reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_

Res.
Res.
Res.
Res.
AWHT[23:0] BKAWH[3:0]
0x2A0 FLT3AWHTR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_

Res.
Res.
Res.
Res.
AWLT[23:0] BKAWL[3:0]
0x2A4 FLT3AWLTR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AWHTF[7:0] AWLTF[7:0]
0x2A8 FLT3AWSR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CLRAWHTF[7:0] CLRAWLTF[7:0]
0x2AC FLT3AWCFR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXMAXCH[2:0]
DFSDM_

Res.
Res.
Res.
Res.
Res.
EXMAX[23:0]
0x2B0 FLT3EXMAX

reset value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXMINCH[2:0]
DFSDM_

Res.
Res.
Res.
Res.
Res.
FLT3EXMIN EXMIN[23:0]
0x2B4

reset value 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
DFSDM_

Res.
Res.
Res.
Res.
CNVCNT[27:0]
0x2B8 FLT3CNVTIMR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x2BC -
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved
0x3FC

Refer to Section 2.2 on page 91 for the register boundary addresses.

RM0432 Rev 6 889/2301

889
LCD-TFT display controller (LTDC) RM0432

29 LCD-TFT display controller (LTDC)

29.1 Introduction
The LCD-TFT (liquid crystal display - thin film transistor) display controller provides a
parallel digital RGB (red, green, blue) and signals for horizontal, vertical synchronization,
pixel clock and data enable as output to interface directly to a variety of LCD and TFT
panels.

29.2 LTDC main features

• 24-bit RGB parallel pixel output; 8 bits-per-pixel (RGB888)
• 2 display layers with dedicated FIFO (64x32-bit)
• Color look-up table (CLUT) up to 256 color (256x24-bit) per layer
• Programmable timings for different display panels
• Programmable background color
• Programmable polarity for HSYNC, VSYNC and data enable
• Up to 8 input color formats selectable per layer:
– ARGB8888
– RGB888
– RGB565
– ARGB1555
– ARGB4444
– L8 (8-bit luminance or CLUT)
– AL44 (4-bit alpha + 4-bit luminance)
– AL88 (8-bit alpha + 8-bit luminance)
• Pseudo-random dithering output for low bits per channel
– Dither width 2 bits for red, green, blue
• Flexible blending between two layers using alpha value (per pixel or constant)
• Color keying (transparency color)
• Programmable window position and size
• Supports thin film transistor (TFT) color displays
• AHB master interface with burst of 16 words
• Up to 4 programmable interrupt events

29.3 LTDC implementation

Table 192. LTDC implementation
STM32L4R7xx/STM32L4R9xx and STM32L4P5xx and
References
STM32L4S7xx/STM32L4S9xx STM32L4Q5xx

Number of layers 2 1

890/2301 RM0432 Rev 6

RM0432 LCD-TFT display controller (LTDC)

29.4 LTDC functional description

29.4.1 LTDC block diagram

The block diagram of the LTDC is shown in the figure below.

Figure 199. LTDC block diagram

Pixel clock domain
AHB clock domain

Layer1
PFC LCD_HSYNC
FIFO
AHB Blending Dithering LCD_VSYNC
interface unit unit LCD_DE
Layer1 LCD-TFT
PFC LCD_CLK
FIFO panel
LCD_R[7:0]
LCD_G[7:0]
APB2 clock domain

Configuration LCD_B[7:0]
Timing
and status
generator
registers

Interrupts
MSv19675V1

Layer FIFO: One FIFO 64x32-bit per layer.

PFC: pixel format converter, performing the pixel format conversion from the selected input
pixel format of a layer to words.
AHB interface: for data transfer from memories to the FIFO.
Blending, dithering unit and timings generator: Refer to Section 29.5.1 and Section 29.5.2.

29.4.2 LTDC pins and external signal interface

The table below summarizes the LTDC signal interface.

Table 193. LTDC pins and signal interface

LCD-TFT signals I/O Description

LCD_CLK O Clock output

LCD_HSYNC O Horizontal synchronization
LCD_VSYNC O Vertical synchronization
LCD_DE O Not data enable
LCD_R[7:0] O Data: 8-bit red data
LCD_G[7:0] O Data: 8-bit green data
LCD_B[7:0] O Data: 8-bit blue data

RM0432 Rev 6 891/2301

923
LCD-TFT display controller (LTDC) RM0432

The LTDC-TFT controller pins must be configured by the user application. The unused pins
can be used for other purposes.
For LTDC outputs up to 24 bits (RGB888), if less than 8 bpp are used to output for example
RGB565 or RGB666 to interface on 16- or 18-bit displays, the RGB display data lines must
be connected to the MSB of the LCD-TFT controller RGB data lines. As an example, in the
case of an LCD-TFT controller interfacing with a RGB565 16-bit display, the LCD display
R[4:0], G[5:0] and B[4:0] data lines pins must be connected to LCD-TFT controller
LCD_R[7:3], LCD_G[7:2] and LCD_B[7:3].

29.4.3 LTDC reset and clocks

The LCD-TFT controller peripheral uses the following clock domains:
• AHB clock domain (HCLK)
This domain contains the LCD-TFT AHB master interface for data transfer from the
memories to the Layer FIFO and the frame buffer configuration register
• APB2 clock domain (PCLK2):
This domain contains the global configuration registers and the interrupt register.
• Pixel clock domain (LCD_CLK)
This domain contains the pixel data generation, the layer configuration register as well
as the LCD-TFT interface signal generator. The LCD_CLK output should be configured
following the panel requirements. The LCD_CLK is generated from a specific PLL
output (refer to the reset and clock control section).
The table below summarizes the clock domain for each register.

Table 194. Clock domain for each register

LTDC register Clock domain

LTDC_LxCR
LTDC_LxCFBAR
HCLK
LTDC_LxCFBLR
LTDC_LxCFBLNR
LTDC_SRCR
LTDC_IER
PCLK2
LTDC_ISR
LTDC_ICR

892/2301 RM0432 Rev 6

RM0432 LCD-TFT display controller (LTDC)

Table 194. Clock domain for each register (continued)

LTDC register Clock domain

LTDC_SSCR
LTDC_BPCR
LTDC_AWCR
LTDC_TWCR
LTDC_GCR
LTDC_BCCR
LTDC_LIPCR
LTDC_CPSR
LTDC_CDSR Pixel clock (LCD_CLK)
LTDC_LxWHPCR
LTDC_LxWVPCR
LTDC_LxCKCR
LTDC_LxPFCR
LTDC_LxCACR
LTDC_LxDCCR
LTDC_LxBFCR
LTDC_LxCLUTWR

Care must be taken while accessing the LTDC registers, the APB2 bus is stalled during:
• 6 PCKL2 periods + 5 LCD_CLK periods (five HCLK periods for register on AHB clock
domain) for register write access and update
• 7 PCKL2 periods + 5 LCD_CLK periods (five HCLK periods for register on AHB clock
domain) for register read access
For registers on PCLK2 clock domain, APB2 bus is stalled for six PCKL2 periods during the
register write accesses, and for seven PCKL2 periods during read accesses.
The LCD controller can be reset by setting the corresponding bit in the RCC_APB2RSTR
register. It resets the three clock domains.

29.5 LTDC programmable parameters

The LCD-TFT controller provides flexible configurable parameters. It can be enabled or
disabled through the LTDC_GCR register.

29.5.1 LTDC global configuration parameters

Synchronous timings
Figure 200 presents the configurable timing parameters generated by the synchronous
timings generator block presented in the block diagram Figure 199. It generates the

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horizontal and vertical synchronization timings panel signals, the pixel clock and the data
enable signals.

Figure 200. LCD-TFT synchronous timings

Total width
HBP HFP

HSYNC
width
Active width

VSYNC width

VBP

Data1, Line1
Total height

Active display area

Active height

Data(n), Line(n)

VFP

MSv19674V1

Note: The HBP and HFP are respectively the horizontal back porch and front porch period.
The VBP and the VFP are respectively the vertical back porch and front porch period.
The LCD-TFT programmable synchronous timings are the following:
• HSYNC and VSYNC width: horizontal and vertical synchronization width, configured by
programming a value of HSYNC width - 1 and VSYNC width - 1 in the LTDC_SSCR
register
• HBP and VBP: horizontal and vertical synchronization back porch width, configured by
programming the accumulated value HSYNC width + HBP - 1 and the accumulated
value VSYNC width + VBP - 1 in the LTDC_BPCR register.
• Active width and active height: the active width and active height are configured by
programming the accumulated value HSYNC width + HBP + active width - 1 and the
accumulated value VSYNC width + VBP + active height - 1 in the LTDC_AWCR
register.
• Total width: the total width is configured by programming the accumulated value
HSYNC width + HBP + active width + HFP - 1 in the LTDC_TWCR register. The HFP is
the horizontal front porch period.
• Total height: the total height is configured by programming the accumulated value
VSYNC height + VBP + active height + VFP - 1 in the LTDC_TWCR register. The VFP
is the vertical front porch period.

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RM0432 LCD-TFT display controller (LTDC)

Note: When the LTDC is enabled, the timings generated start with X/Y=0/0 position as the first
horizontal synchronization pixel in the vertical synchronization area and following the back
porch, active data display area and the front porch.
When the LTDC is disabled, the timing generator block is reset to X = total width - 1,
Y = total height - 1 and held the last pixel before the vertical synchronization phase and the
FIFO are flushed. Therefore only blanking data is output continuously.

Example of synchronous timings configuration

LCD-TFT timings (must be extracted from panel datasheet):
• horizontal and vertical synchronization width: 0xA pixels and 0x2 lines
• horizontal and vertical back porch: 0x14 pixels and 0x2 lines
• active width and active height: 0x140 pixels, 0xF0 lines (320x240)
• horizontal front porch: 0xA pixels
• vertical front porch: 0x4 lines
The programmed values in the LTDC timings registers are:
• LTDC_BPCR register: to be programmed to 0x001D0003 (AHBP[11:0] is 0x1D(0xA+
0x13) and AVBP[10:0]A is 0x3(0x2 + 0x1)).
• LTDC_AWCR register: to be programmed to 0x015D00F3 (AAW[11:0] is 0x15D(0xA
+0x14 +0x13F) and AAH[10:0] is 0xF3(0x2 +0x2 + 0xEF).
• LTDC_TWCR register: to be programmed to 0x00000167 (TOTALW[11:0] is 0x167(0xA
+0x14 +0x140 + 0x9).
• LTDC_THCR register: to be programmed to 0x000000F7 (TOTALH[10:0]is 0xF7(0x2
+0x2 + 0xF0 + 3)

Programmable polarity
The horizontal and vertical synchronization, data enable and pixel clock output signals
polarity can be programmed to active high or active low through the LTDC_GCR register.

Background color
A constant background color (RGB888) can programmed through the LTDC_BCCR register.
It is used for blending with the bottom layer.

Dithering
The dithering pseudo-random technique using an LFSR is used to add a small random
value (threshold) to each pixel color channel (R, G or B) value, thus rounding up the MSB in
some cases when displaying a 24-bit data on 18-bit display. Thus the dithering technique is
used to round data which is different from one frame to the other.
The dithering pseudo-random technique is the same as comparing LSBs against a
threshold value and adding a 1 to the MSB part only, if the LSB part is ≥ the threshold. The
LSBs are typically dropped once dithering was applied.
The width of the added pseudo-random value is two bits for each color channel: two bits for
red, two bits for green and two bits for blue.
Once the LCD-TFT controller is enabled, the LFSR starts running with the first active pixel
and it is kept running even during blanking periods and when dithering is switched off. If the
LTDC is disabled, the LFSR is reset.

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The dithering can be switched on and off on the fly through the LTDC_GCR register.

Reload shadow registers

Some configuration registers are shadowed. The shadow registers values can be reloaded
immediately to the active registers when writing to these registers or at the beginning of the
vertical blanking period following the configuration in the LTDC_SRCR register. If the
immediate reload configuration is selected, the reload must be activated only when all new
registers have been written.
The shadow registers must not be modified again before the reload is done. Reading from
the shadow registers returns the actual active value. The new written value can only be read
after the reload has taken place.
A register reload interrupt can be generated if enabled in the LTDC_IER register.
The shadowed registers are all layer1 and layer2 registers except LTDC_LxCLUTWR.

Interrupt generation event

Refer to Section 29.6: LTDC interrupts for the interrupt configuration.

29.5.2 Layer programmable parameters

Up to two layers can be enabled, disabled and configured separately. The layer display
order is fixed and it is bottom up. If two layers are enabled, the layer2 is the top displayed
window.

Windowing
Every layer can be positioned and resized and it must be inside the active display area.
The window position and size are configured through the top-left and bottom-right X/Y
positions and the internal timing generator that includes the synchronous, back porch size
and the active data area. Refer to LTDC_LxWHPCR and LTDC_WVPCR registers.

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The programmable layer position and size defines the first/last visible pixel of a line and the
first/last visible line in the window. It allows to display either the full image frame or only a
part of the image frame (see the figure below):
• The first and the last visible pixel in the layer are set by configuring the WHSTPOS[11:0]
and WHSPPOS[11:0] in the LTDC_LxWHPCR register.
• The first and the last visible lines in the layer are set by configuring the WVSTPOS[10:0]
and WVSPPOS[10:0] in the LTDC_LxWVPCR register.

Figure 201. Layer window programmable parameters

Active data area
WVSTPOS bits in
LTDC_LxWVPCR

WVSPPOS bits in
WHSTPOS bits in
LTDC_LxWVPCR
LTDC_LxWHPCR Window

WHSPPOS bits in
LTDC_LxWHPCR

MSv19676V3

Pixel input format

The programmable pixel format is used for the data stored in the frame buffer of a layer.
Up to height input pixel formats can be configured for every layer through the
LTDC_LxPFCR register
The pixel data is read from the frame buffer and then transformed to the internal 8888
(ARGB) format as follows: components having a width of less than 8 bits get expanded to 8
bits by bit replication. The selected bit range is concatenated multiple times until it is longer
than 8 bits. Of the resulting vector, the 8 MSB bits are chosen. Example: 5 bits of an
RGB565 red channel become (bit positions) 43210432 (the three LSBs are filled with the
three MSBs of the five bits)
The table below describes the pixel data mapping depending on the selected format.

Table 195. Pixel data mapping versus color format

ARGB8888
@+3 @+2 @+1 @
Ax[7:0] Rx[7:0] Gx[7:0] Bx[7:0]
@+7 @+6 @+5 @+4
Ax+1[7:0] Rx+1[7:0] Gx+1[7:0] Bx+1[7:0]
RGB888
@+3 @+2 @+1 @
Bx+1[7:0] Rx[7:0] Gx[7:0] Bx[7:0]

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Table 195. Pixel data mapping versus color format (continued)

@+7 @+6 @+5 @+4
Gx+2[7:0] Bx+2[7:0] Rx+1[7:0] Gx+1[7:0]
RGB565
@+3 @+2 @+1 @
Rx+1[4:0] Gx+1[5:3] Gx+1[2:0] Bx+1[4:0] Rx[4:0] Gx[5:3] Gx[2:0] Bx[4:0]
@+7 @+6 @+5 @+4
Rx+3[4:0] Gx+3[5:3] Gx+3[2:0] Bx+3[4:0] Rx+2[4:0] Gx+2[5:3] Gx+2[2:0] Bx+2[4:0]
ARGB1555
@+3
@+2 @+1 @
Ax+1[0]Rx+1[4:0]
Gx+1[2:0] Bx+1[4:0] Ax[0] Rx[4:0] Gx[4:3] Gx[2:0] Bx[4:0]
Gx+1[4:3]
@+7 @+5
@+6 @+4
Ax+3[0]Rx+3[4:0] Ax+2[0]Rx+2[4:0]Gx+2[4:
Gx+3[2:0] Bx+3[4:0] Gx+2[2:0] Bx+2[4:0]
Gx+3[4:3] 3]

ARGB4444
@+3 @+2 @+1 @
Ax+1[3:0]Rx+1[3:0] Gx+1[3:0] Bx+1[3:0] Ax[3:0] Rx[3:0] Gx[3:0] Bx[3:0]
@+7 @+6 @+5 @+4
Ax+3[3:0]Rx+3[3:0] Gx+3[3:0] Bx+3[3:0] Ax+2[3:0]Rx+2[3:0] Gx+2[3:0] Bx+2[3:0]
L8
@+3 @+2 @+1 @
Lx+3[7:0] Lx+2[7:0] Lx+1[7:0] Lx[7:0]
@+7 @+6 @+5 @+4
Lx+7[7:0] Lx+6[7:0] Lx+5[7:0] Lx+4[7:0]
AL44
@+3 @+2 @+1 @
Ax+3[3:0] Lx+3[3:0] Ax+2[3:0] Lx+2[3:0] Ax+1[3:0] Lx+1[3:0] Ax[3:0] Lx[3:0]
@+7 @+6 @+5 @+4
Ax+7[3:0] Lx+7[3:0] Ax+6[3:0] Lx+6[3:0] Ax+5[3:0] Lx+5[3:0] Ax+4[3:0] Lx+4[3:0]
AL88
@+3 @+2 @+1 @
Ax+1[7:0] Lx+1[7:0] Ax[7:0] Lx[7:0]
@+7 @+6 @+5 @+4
Ax+3[7:0] Lx+3[7:0] Ax+2[7:0] Lx+2[7:0]

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RM0432 LCD-TFT display controller (LTDC)

Color look-up table (CLUT)

The CLUT can be enabled at run-time for every layer through the LTDC_LxCR register and
it is only useful in case of indexed color when using the L8, AL44 and AL88 input pixel
format.
First, the CLUT must be loaded with the R, G and B values that replace the original R, G, B
values of that pixel (indexed color). Each color (RGB value) has its own address that is the
position within the CLUT.
The R, G and B values and their own respective address are programmed through the
LTDC_LxCLUTWR register:
• In case of L8 and AL88 input pixel format, the CLUT must be loaded by 256 colors. The
address of each color is configured in the CLUTADD bits in the LTDC_LxCLUTWR
register.
• In case of AL44 input pixel format, the CLUT must be loaded by only16 colors. The
address of each color must be filled by replicating the 4-bit L channel to 8-bit as follows:
– L0 (indexed color 0), at address 0x00
– L1, at address 0x11
– L2, at address 0x22
– .....
– L15, at address 0xFF

Color frame buffer address

Every layer has a start address for the color frame buffer configured through the
LTDC_LxCFBAR register.
When a layer is enabled, the data is fetched from the color frame buffer.

Color frame buffer length

Every layer has a total line length setting for the color frame buffer in bytes and a number of
lines in the frame buffer configurable in the LTDC_LxCFBLR and LTDC_LxCFBLNR register
respectively.
The line length and the number of lines settings are used to stop the prefetching of data to
the layer FIFO at the end of the frame buffer:
• If it is set to less bytes than required, a FIFO underrun interrupt is generated if it has
been previously enabled.
• If it is set to more bytes than actually required, the useless data read from the FIFO is
discarded. The useless data is not displayed.

Color frame buffer pitch

Every layer has a configurable pitch for the color frame buffer, that is the distance between
the start of one line and the beginning of the next line in bytes. It is configured through the
LTDC_LxCFBLR register.

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Layer blending
The blending is always active and the two layers can be blended following the blending
factors configured through the LTDC_LxBFCR register.
The blending order is fixed and it is bottom up. If two layers are enabled, first the Layer1 is
blended with the Background color, then the layer2 is blended with the result of blended
color of layer1 and the background. Refer to the figure below.

Figure 202. Blending two layers with background

Layer2
Layer1 Layer2 Layer2 +
BG Layer1 + BG Layer1 + BG

MSv48123V1

Default color
Every layer can have a default color in the format ARGB which is used outside the defined
layer window or when a layer is disabled.
The default color is configured through the LTDC_LxDCCR register.
The blending is always performed between the two layers even when a layer is disabled. To
avoid displaying the default color when a layer is disabled, keep the blending factors of this
layer in the LTDC_LxBFCR register to their reset value.

Color keying
A color key (RGB) can be configured to be representative for a transparent pixel.
If the color keying is enabled, the current pixels (after format conversion and before CLUT
respectively blending) are compared to the color key. If they match for the programmed
RGB value, all channels (ARGB) of that pixel are set to 0.
The color key value can be configured and used at run-time to replace the pixel RGB value.
The color keying is enabled through the LTDC_LxCKCR register.
The color keying is configured through the LTDC_LxCKCR register. The programmed value
depends on the pixel format as it is compared to current pixel after pixel format conversion
to ARGB888.
Example: if the a mid-yellow color (50 % red + 50 % green) is used as the transparent color
key:
• In RGB565, the mid-yellow color is 0x8400. Set the LTDC_LxCKCR to 0x848200.
• In ARGB8888, the mid-yellow color is 0x808000. Set LTDC_LxCKCR to 0x808000.
• In all CLUT-based color modes (L8, AL88, AL44), set one of the palette entry to the
mid-yellow color 0x808000 and set the LTDC_LxCKCR to 0x808000.

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RM0432 LCD-TFT display controller (LTDC)

29.6 LTDC interrupts

The LTDC provides four maskable interrupts logically ORed to two interrupt vectors.
The interrupt sources can be enabled or disabled separately through the LTDC_IER
register. Setting the appropriate mask bit to 1 enables the corresponding interrupt.
The two interrupts are generated on the following events:
• Line interrupt: generated when a programmed line is reached. The line interrupt
position is programmed in the LTDC_LIPCR register
• Register reload interrupt: generated when the shadow registers reload is performed
during the vertical blanking period
• FIFO underrun interrupt: generated when a pixel is requested from an empty layer
FIFO
• Transfer error interrupt: generated when an AHB bus error occurs during data transfer
Those interrupts events are connected to the NVIC controller as described in the figure
below.

Figure 203. Interrupt events

Line
LTDC global interrupt
Register reload

FIFO underrun
LTDC global error interrupt
Transfer error
MS19678V1

Table 196. LTDC interrupt requests

Interrupt event Event flag Enable control bit

Line LIF LIE

Register reload RRIF RRIEN
FIFO underrun FUDERRIF FUDERRIE
Transfer error TERRIF TERRIE

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29.7 LTDC programming procedure

The steps listed below are needed to program the LTDC:
1. Enable the LTDC clock in the RCC register.
2. Configure the required pixel clock following the panel datasheet.
3. Configure the synchronous timings: VSYNC, HSYNC, vertical and horizontal back
porch, active data area and the front porch timings following the panel datasheet as
described in the Section 29.5.1: LTDC global configuration parameters.
4. Configure the synchronous signals and clock polarity in the LTDC_GCR register.
5. If needed, configure the background color in the LTDC_BCCR register.
6. Configure the needed interrupts in the LTDC_IER and LTDC_LIPCR register.
7. Configure the layer1/2 parameters by:
– programming the layer window horizontal and vertical position in the
LTDC_LxWHPCR and LTDC_WVPCR registers. The layer window must be in the
active data area.
– programming the pixel input format in the LTDC_LxPFCR register
– programming the color frame buffer start address in the LTDC_LxCFBAR register
– programming the line length and pitch of the color frame buffer in the
LTDC_LxCFBLR register
– programming the number of lines of the color frame buffer in the
LTDC_LxCFBLNR register
– if needed, loading the CLUT with the RGB values and its address in the
LTDC_LxCLUTWR register
– If needed, configuring the default color and the blending factors respectively in the
LTDC_LxDCCR and LTDC_LxBFCR registers
8. Enable layer1/2 and if needed the CLUT in the LTDC_LxCR register.
9. If needed, enable dithering and color keying respectively in the LTDC_GCR and
LTDC_LxCKCR registers. They can be also enabled on the fly.
10. Reload the shadow registers to active register through the LTDC_SRCR register.
11. Enable the LCD-TFT controller in the LTDC_GCR register.
12. All layer parameters can be modified on the fly except the CLUT. The new configuration
must be either reloaded immediately or during vertical blanking period by configuring
the LTDC_SRCR register.
Note: All layer’s registers are shadowed. Once a register is written, it must not be modified again
before the reload has been done. Thus, a new write to the same register overrides the
previous configuration if not yet reloaded.

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29.8 LTDC registers

29.8.1 LTDC synchronization size configuration register (LTDC_SSCR)

This register defines the number of horizontal synchronization pixels minus 1 and the
number of vertical synchronization lines minus 1. Refer to Figure 200 and Section 29.5:
LTDC programmable parameters for an example of configuration.
Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. HSW[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. VSH[10:0]

rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 HSW[11:0]: horizontal synchronization width (in units of pixel clock period)
These bits define the number of Horizontal Synchronization pixel minus 1.
Bits 15:11 Reserved, must be kept at reset value.
Bits 10:0 VSH[10:0]: vertical synchronization height (in units of horizontal scan line)
These bits define the vertical Synchronization height minus 1. It represents the number of
horizontal synchronization lines.

29.8.2 LTDC back porch configuration register (LTDC_BPCR)

This register defines the accumulated number of horizontal synchronization and back porch
pixels minus 1 (HSYNC width + HBP - 1) and the accumulated number of vertical
synchronization and back porch lines minus 1 (VSYNC height + VBP - 1). Refer to
Figure 200 and Section 29.5: LTDC programmable parameters for an example of
configuration.
Address offset: 0x0C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. AHBP[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. AVBP[10:0]

rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 AHBP[11:0]: accumulated horizontal back porch (in units of pixel clock period)
These bits define the accumulated horizontal back porch width that includes the horizontal
synchronization and horizontal back porch pixels minus 1.
The horizontal back porch is the period between horizontal synchronization going inactive
and the start of the active display part of the next scan line.
Bits 15:11 Reserved, must be kept at reset value.
Bits 10:0 AVBP[10:0]: accumulated Vertical back porch (in units of horizontal scan line)
These bits define the accumulated vertical back porch width that includes the vertical
synchronization and vertical back porch lines minus 1.
The vertical back porch is the number of horizontal scan lines at a start of frame to the start of
the first active scan line of the next frame.

29.8.3 LTDC active width configuration register (LTDC_AWCR)

This register defines the accumulated number of horizontal synchronization, back porch and
active pixels minus 1 (HSYNC width + HBP + active width - 1) and the accumulated number
of vertical synchronization, back porch lines and active lines minus 1
(VSYNC height + BVBP + active height - 1). Refer to Figure 200 and Section 29.5: LTDC
programmable parameters for an example of configuration.
Address offset: 0x10
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. AAW[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. AAH[10:0]

rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 AAW[11:0]: accumulated active width (in units of pixel clock period)
These bits define the accumulated active width which includes the horizontal
synchronization, horizontal back porch and active pixels minus 1.
The active width is the number of pixels in active display area of the panel scan line.
Refer to device datasheet for maximum active width supported following maximum pixel
clock.
Bits 15:11 Reserved, must be kept at reset value.
Bits 10:0 AAH[10:0]: accumulated active height (in units of horizontal scan line)
These bits define the accumulated height which includes the vertical synchronization, vertical
back porch and the active height lines minus 1. The active height is the number of active
lines in the panel.
Refer to device datasheet for maximum active height supported following maximum pixel
clock.

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RM0432 LCD-TFT display controller (LTDC)

29.8.4 LTDC total width configuration register (LTDC_TWCR)

This register defines the accumulated number of horizontal synchronization, back porch,
active and front porch pixels minus 1 (HSYNC width + HBP + active width + HFP - 1) and
the accumulated number of vertical synchronization, back porch lines, active and front lines
minus 1 (VSYNC height + BVBP + active height + VFP - 1). Refer to Figure 200 and
Section 29.5: LTDC programmable parameters for an example of configuration.
Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. TOTALW[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. TOTALH[10:0]

rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 TOTALW[11:0]: total width (in units of pixel clock period)
These bits defines the accumulated total width which includes the horizontal synchronization,
horizontal back porch, active width and horizontal front porch pixels minus 1.
Bits 15:11 Reserved, must be kept at reset value.
Bits 10:0 TOTALH[10:0]: total height (in units of horizontal scan line)
These bits defines the accumulated height which includes the vertical synchronization,
vertical back porch, the active height and vertical front porch height lines minus 1.

29.8.5 LTDC global control register (LTDC_GCR)

This register defines the global configuration of the LCD-TFT controller.
Address offset: 0x18
Reset value: 0x0000 2220

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

HSPOL VSPOL DEPOL PCPOL Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DEN

rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. DRW[2:0] Res. DGW[2:0] Res. DBW[2:0] Res. Res. Res. LTDCEN

r r r r r r r r r rw

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LCD-TFT display controller (LTDC) RM0432

Bit 31 HSPOL: horizontal synchronization polarity

This bit is set and cleared by software.
0: horizontal synchronization polarity is active low.
1: horizontal synchronization polarity is active high.
Bit 30 VSPOL: vertical synchronization polarity
This bit is set and cleared by software.
0: vertical synchronization is active low.
1: vertical synchronization is active high.
Bit 29 DEPOL: not data enable polarity
This bit is set and cleared by software.
0: not data enable polarity is active low.
1: not data enable polarity is active high.
Bit 28 PCPOL: pixel clock polarity
This bit is set and cleared by software.
0: pixel clock polarity is active low.
1: pixel clock is active high.
Bits 27:17 Reserved, must be kept at reset value.
Bit 16 DEN: dither enable
This bit is set and cleared by software.
0: dither disable
1: dither enable
Bit 15 Reserved, must be kept at reset value.
Bits 14:12 DRW[2:0]: dither red width
These bits return the Dither Red Bits.
Bit 11 Reserved, must be kept at reset value.
Bits 10:8 DGW[2:0]: dither green width
These bits return the dither green bits.
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 DBW[2:0]: dither blue width
These bits return the dither blue bits.
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 LTDCEN: LCD-TFT controller enable
This bit is set and cleared by software.
0: LTDC disable
1: LTDC enable

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29.8.6 LTDC shadow reload configuration register (LTDC_SRCR)

This register allows to reload either immediately or during the vertical blanking period, the
shadow registers values to the active registers. The shadow registers are all Layer1 and
Layer2 registers except the LTDC_L1CLUTWR and the LTDC_L2CLUTWR.
Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. VBR IMR

rw rw

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 VBR: vertical blanking reload
This bit is set by software and cleared only by hardware after reload (it cannot be cleared
through register write once it is set).
0: no effect
1: The shadow registers are reloaded during the vertical blanking period (at the beginning of
the first line after the active display area).
Bit 0 IMR: immediate reload
This bit is set by software and cleared only by hardware after reload.
0: no effect
1: The shadow registers are reloaded immediately.

Note: The shadow registers read back the active values. Until the reload has been done, the 'old'
value is read.

29.8.7 LTDC background color configuration register (LTDC_BCCR)

This register defines the background color (RGB888).
Address offset: 0x2C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. BCRED[7:0]

rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BCGREEN[7:0] BCBLUE[7:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RM0432 Rev 6 907/2301

923
LCD-TFT display controller (LTDC) RM0432

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 BCRED[7:0]: background color red value
These bits configure the background red value.
Bits 15:8 BCGREEN[7:0]: background color green value
These bits configure the background green value.
Bits 7:0 BCBLUE[7:0]: background color blue value
These bits configure the background blue value.

29.8.8 LTDC interrupt enable register (LTDC_IER)

This register determines which status flags generate an interrupt request by setting the
corresponding bit to 1.
Address offset: 0x34
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RRIE TERRIE FUIE LIE

rw rw rw rw

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 RRIE: register reload interrupt enable
This bit is set and cleared by software.
0: register reload interrupt disable
1: register reload interrupt enable
Bit 2 TERRIE: transfer error interrupt enable
This bit is set and cleared by software.
0: transfer error interrupt disable
1: transfer error interrupt enable
Bit 1 FUIE: FIFO underrun interrupt enable
This bit is set and cleared by software.
0: FIFO underrun interrupt disable
1: FIFO underrun Interrupt enable
Bit 0 LIE: line interrupt enable
This bit is set and cleared by software.
0: line interrupt disable
1: line interrupt enable

908/2301 RM0432 Rev 6

RM0432 LCD-TFT display controller (LTDC)

29.8.9 LTDC interrupt status register (LTDC_ISR)

This register returns the interrupt status flag.
Address offset: 0x38
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RRIF TERRIF FUIF LIF

r r r r

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 RRIF: register reload interrupt flag
0: no register reload interrupt generated
1: register reload interrupt generated when a vertical blanking reload occurs (and the first line
after the active area is reached)
Bit 2 TERRIF: transfer error interrupt flag
0: no transfer error interrupt generated
1: transfer error interrupt generated when a bus error occurs
Bit 1 FUIF: FIFO underrun interrupt flag
0: no FIFO underrun interrupt generated.
1: FIFO underrun interrupt generated, if one of the layer FIFOs is empty and pixel data is
read from the FIFO
Bit 0 LIF: line interrupt flag
0: no line interrupt generated
1: line interrupt generated when a programmed line is reached

29.8.10 LTDC Interrupt Clear Register (LTDC_ICR)

Address offset: 0x3C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CRRIF CTERRIF CFUIF CLIF

w w w w

RM0432 Rev 6 909/2301

923
LCD-TFT display controller (LTDC) RM0432

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 CRRIF: clears register reload interrupt flag
0: no effect
1: clears the RRIF flag in the LTDC_ISR register
Bit 2 CTERRIF: clears the transfer error interrupt flag
0: no effect
1: clears the TERRIF flag in the LTDC_ISR register.
Bit 1 CFUIF: clears the FIFO underrun interrupt flag
0: no effect
1: clears the FUDERRIF flag in the LTDC_ISR register.
Bit 0 CLIF: clears the line interrupt flag
0: no effect
1: clears the LIF flag in the LTDC_ISR register.

29.8.11 LTDC line interrupt position configuration register (LTDC_LIPCR)

This register defines the position of the line interrupt. The line value to be programmed
depends on the timings parameters. Refer to Figure 200.
Address offset: 0x40
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. LIPOS[10:0]

rw rw rw rw rw rw rw rw rw rw rw

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:0 LIPOS[10:0]: line interrupt position
These bits configure the line interrupt position.

29.8.12 LTDC current position status register (LTDC_CPSR)

Address offset: 0x44
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CXPOS[15:0]

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CYPOS[15:0]

r r r r r r r r r r r r r r r r

910/2301 RM0432 Rev 6

RM0432 LCD-TFT display controller (LTDC)

Bits 31:16 CXPOS[15:0]: current X position

These bits return the current X position.
Bits 15:0 CYPOS[15:0]: current Y position
These bits return the current Y position.

29.8.13 LTDC current display status register (LTDC_CDSR)

This register returns the status of the current display phase which is controlled by the
HSYNC, VSYNC, and horizontal/vertical DE signals.
Example: if the current display phase is the vertical synchronization, the VSYNCS bit is set
(active high). If the current display phase is the horizontal synchronization, the HSYNCS bit
is active high.
Address offset: 0x48
Reset value: 0x0000 000F

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. HSYNCS VSYNCS HDES VDES

r r r r

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 HSYNCS: horizontal synchronization display status
0: active low
1: active high
Bit 2 VSYNCS: vertical synchronization display status
0: active low
1: active high
Bit 1 HDES: horizontal data enable display status
0: active low
1: active high
Bit 0 VDES: vertical data enable display status
0: active low
1: active high

Note: The returned status does not depend on the configured polarity in the LTDC_GCR register,
instead it returns the current active display phase.

29.8.14 LTDC layer x control register (LTDC_LxCR)

Address offset: 0x84 + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000

RM0432 Rev 6 911/2301

923
LCD-TFT display controller (LTDC) RM0432

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CLUTEN Res. Res. COLKEN LEN

rw rw rw

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 CLUTEN: color look-up table enable
This bit is set and cleared by software.
0: color look-up table disable
1: color look-up table enable
The CLUT is only meaningful for L8, AL44 and AL88 pixel format. Refer to Color look-up
table (CLUT)
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 COLKEN: color keying enable
This bit is set and cleared by software.
0: color keying disable
1: color keying enable
Bit 0 LEN: layer enable
This bit is set and cleared by software.
0: layer disable
1: layer enable

29.8.15 LTDC layer x window horizontal position configuration register

(LTDC_LxWHPCR)
This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window.
The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the
LTDC_BPCR register.
The last visible pixel of a line is the programmed value of AAW[11:0] bits in the
LTDC_AWCR register.
Address offset: 0x88 + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. WHSPPOS[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. WHSTPOS[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw

912/2301 RM0432 Rev 6

RM0432 LCD-TFT display controller (LTDC)

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 WHSPPOS[11:0]: window horizontal stop position
These bits configure the last visible pixel of a line of the layer window.
WHSPPOS[11:0] must be ≥ AHBP[11:0] bits + 1 (programmed in LTDC_BPCR register).
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 WHSTPOS[11:0]: window horizontal start position
These bits configure the first visible pixel of a line of the layer window.
WHSTPOS[11:0] must be ≤ AAW[11:0] bits (programmed in LTDC_AWCR register).

Example:
The LTDC_BPCR register is configured to 0x000E0005 (AHBP[11:0] is 0xE) and the
LTDC_AWCR register is configured to 0x028E01E5 (AAW[11:0] is 0x28E). To configure the
horizontal position of a window size of 630x460, with horizontal start offset of 5 pixels in the
active data area:
1. layer window first pixel, WHSTPOS[11:0], must be programmed to 0x14 (0xE+1+0x5)
2. layer window last pixel, WHSPPOS[11:0], must be programmed to 0x28A.

29.8.16 LTDC layer x window vertical position configuration register

(LTDC_LxWVPCR)
This register defines the vertical position (first and last line) of the layer1 or 2 window.
The first visible line of a frame is the programmed value of AVBP[10:0] bits + 1 in the register
LTDC_BPCR register.
The last visible line of a frame is the programmed value of AAH[10:0] bits in the
LTDC_AWCR register.
Address offset: 0x8C + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. WVSPPOS[10:0]

rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. WVSTPOS[10:0]

rw rw rw rw rw rw rw rw rw rw rw

Bits 31:27 Reserved, must be kept at reset value.

Bits 26:16 WVSPPOS[10:0]: window vertical stop position
These bits configure the last visible line of the layer window.
WVSPPOS[10:0] must be ≥ AVBP[10:0] bits + 1 (programmed in LTDC_BPCR register).
Bits 15:11 Reserved, must be kept at reset value.
Bits 10:0 WVSTPOS[10:0]: window vertical start position
These bits configure the first visible line of the layer window.
WVSTPOS[10:0] must be ≤ AAH[10:0] bits (programmed in LTDC_AWCR register).

RM0432 Rev 6 913/2301

923
LCD-TFT display controller (LTDC) RM0432

Example:
The LTDC_BPCR register is configured to 0x000E0005 (AVBP[10:0] is 0x5) and the
LTDC_AWCR register is configured to 0x028E01E5 (AAH[10:0] is 0x1E5).
To configure the vertical position of a window size of 630x460, with vertical start offset of 8
lines in the active data area:
1. layer window first line: WVSTPOS[10:0] must be programmed to 0xE (0x5 + 1 + 0x8).
2. layer window last line: WVSTPOS[10:0] must be programmed to 0x1DA.

29.8.17 LTDC layer x color keying configuration register

(LTDC_LxCKCR)
This register defines the color key value (RGB), that is used by the color keying.
Address offset: 0x90 + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. CKRED[7:0]

rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CKGREEN[7:0] CKBLUE[7:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 CKRED[7:0]: color key red value
Bits 15:8 CKGREEN[7:0]: color key green value
Bits 7:0 CKBLUE[7:0]: color key blue value

29.8.18 LTDC layer x pixel format configuration register

(LTDC_LxPFCR)
This register defines the pixel format that is used for the stored data in the frame buffer of a
layer. The pixel data is read from the frame buffer and then transformed to the internal
format 8888 (ARGB).
Address offset: 0x94 + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PF[2:0]

rw rw rw

914/2301 RM0432 Rev 6

RM0432 LCD-TFT display controller (LTDC)

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 PF[2:0]: pixel format
These bits configure the pixel format
000: ARGB8888
001: RGB888
010: RGB565
011: ARGB1555
100: ARGB4444
101: L8 (8-bit luminance)
110: AL44 (4-bit alpha, 4-bit luminance)
111: AL88 (8-bit alpha, 8-bit luminance)

29.8.19 LTDC layer x constant alpha configuration register

(LTDC_LxCACR)
This register defines the constant alpha value (divided by 255 by hardware), that is used in
the alpha blending. Refer to LTDC_LxBFCR register.
Address offset: 0x98 + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 00FF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. CONSTA[7:0]

rw rw rw rw rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 CONSTA[7:0]: constant alpha
These bits configure the constant alpha used for blending. The constant alpha is divided by
255 by hardware.
Example: if the programmed constant alpha is 0xFF, the constant alpha value is
255 / 255 = 1.

RM0432 Rev 6 915/2301

923
LCD-TFT display controller (LTDC) RM0432

29.8.20 LTDC layer x default color configuration register

(LTDC_LxDCCR)
This register defines the default color of a layer in the format ARGB. The default color is
used outside the defined layer window or when a layer is disabled. The reset value of
0x00000000 defines a transparent black color.
Address offset: 0x9C + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DCALPHA[7:0] DCRED[7:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DCGREEN[7:0] DCBLUE[7:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 DCALPHA[7:0]: default color alpha

These bits configure the default alpha value.
Bits 23:16 DCRED[7:0]: default color red
These bits configure the default red value.
Bits 15:8 DCGREEN[7:0]: default color green
These bits configure the default green value.
Bits 7:0 DCBLUE[7:0]: default color blue
These bits configure the default blue value.

916/2301 RM0432 Rev 6

RM0432 LCD-TFT display controller (LTDC)

29.8.21 LTDC layer x blending factors configuration register

(LTDC_LxBFCR)
This register defines the blending factors F1 and F2.
The general blending formula is: BC = BF1 x C + BF2 x Cs
• BC = blended color
• BF1 = blend factor 1
• C = current layer color
• BF2 = blend factor 2
• Cs = subjacent layers blended color
Address offset: 0xA0 + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0607

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. BF1[2:0] Res. Res. Res. Res. Res. BF2[2:0]

rw rw rw rw rw rw

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:8 BF1[2:0]: blending factor 1
These bits select the blending factor F1.
000: reserved
001: reserved
010: reserved
011: reserved
100: constant alpha
101: reserved
110: pixel alpha x constant alpha
111: reserved
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 BF2[2:0]: blending factor 2
These bits select the blending factor F2
000: reserved
001: reserved
010: reserved
011: reserved
100: reserved
101: 1 - constant alpha
110: reserved
111: 1 - (pixel alpha x constant alpha)

RM0432 Rev 6 917/2301

923
LCD-TFT display controller (LTDC) RM0432

Note: The constant alpha value, is the programmed value in the LxCACR register divided by 255
by hardware.
Example: Only layer1 is enabled, BF1 configured to constant alpha. BF2 configured to
1 - constant alpha. The constant alpha programmed in the LxCACR register is 240 (0xF0).
Thus, the constant alpha value is 240/255 = 0.94. C: current layer color is 128.
Cs: background color is 48. Layer1 is blended with the background color.
BC = constant alpha x C + (1 - Constant Alpha) x Cs = 0.94 x 128 + (1- 0.94) x 48 = 123.

29.8.22 LTDC layer x color frame buffer address register

(LTDC_LxCFBAR)
This register defines the color frame buffer start address which has to point to the address
where the pixel data of the top left pixel of a layer is stored in the frame buffer.
Address offset: 0xAC + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CFBADD[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CFBADD[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 CFBADD[31:0]: color frame buffer start address

These bits define the color frame buffer start address.

29.8.23 LTDC layer x color frame buffer length register

(LTDC_LxCFBLR)
This register defines the color frame buffer line length and pitch.
Address offset: 0xB0 + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. CFBP[12:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. CFBLL[12:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:16 CFBP[12:0]: color frame buffer pitch in bytes
These bits define the pitch that is the increment from the start of one line of pixels to the start
of the next line in bytes.
Bits 15:13 Reserved, must be kept at reset value.

918/2301 RM0432 Rev 6

RM0432 LCD-TFT display controller (LTDC)

Bits 12:0 CFBLL[12:0]: color frame buffer line length

These bits define the length of one line of pixels in bytes + 3.
The line length is computed as follows:
active high width * number of bytes per pixel + 3.

Example:
• A frame buffer having the format RGB565 (2 bytes per pixel) and a width of 256 pixels
(total number of bytes per line is 256 * 2 = 512), where pitch = line length requires a
value of 0x02000203 to be written into this register.
• A frame buffer having the format RGB888 (3 bytes per pixel) and a width of 320 pixels
(total number of bytes per line is 320 * 3 = 960), where pitch = line length requires a
value of 0x03C003C3 to be written into this register.

29.8.24 LTDC layer x color frame buffer line number register

(LTDC_LxCFBLNR)
This register defines the number of lines in the color frame buffer.
Address offset: 0xB4 + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. CFBLNBR[10:0]

rw rw rw rw rw rw rw rw rw rw rw

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:0 CFBLNBR[10:0]: frame buffer line number
These bits define the number of lines in the frame buffer that corresponds to the active high
width.

Note: The number of lines and line length settings define how much data is fetched per frame for
every layer. If it is configured to less bytes than required, a FIFO underrun interrupt will be
generated if enabled.
The start address and pitch settings on the other hand define the correct start of every line in
memory.

RM0432 Rev 6 919/2301

923
LCD-TFT display controller (LTDC) RM0432

29.8.25 LTDC layer x CLUT write register (LTDC_LxCLUTWR)

This register defines the CLUT address and the RGB value.
Address offset: 0xC4 + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CLUTADD[7:0] RED[7:0]

w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GREEN[7:0] BLUE[7:0]

w w w w w w w w w w w w w w w w

Bits 31:24 CLUTADD[7:0]: CLUT address

These bits configure the CLUT address (color position within the CLUT) of each RGB value.
Bits 23:16 RED[7:0]: red value
These bits configure the red value.
Bits 15:8 GREEN[7:0]: green value
These bits configure the green value.
Bits 7:0 BLUE[7:0]: blue value
These bits configure the blue value.

Note: The CLUT write register must be configured only during blanking period or if the layer is
disabled. The CLUT can be enabled or disabled in the LTDC_LxCR register.
The CLUT is only meaningful for L8, AL44 and AL88 pixel format.

920/2301 RM0432 Rev 6

 Offset

0x0048
0x0044
0x0040
0x0038
0x0034
0x0024
0x0018
0x0014
0x0010
0x0008

0x003C
0x002C
0x000C
RM0432

29.8.26

LTDC_ISR
LTDC_IER

LTDC_ICR

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

LTDC_GCR
LTDC_BPCR
LTDC_SSCR

LTDC_CPSR

LTDC_CDSR
LTDC_BCCR
LTDC_SRCR

LTDC_LIPCR
LTDC_TWCR
LTDC_AWCR
Register name

0
0
Res. Res. Res. Res. Res. Res. Res. HSPOL Res. Res. Res. Res. 31

0
0
Res. Res. Res. Res. Res. Res. Res. VSPOL Res. Res. Res. Res. 30

0
0
Res. Res. Res. Res. Res. Res. Res. DEPOL Res. Res. Res. Res. 29

0
0
Res. Res. Res. Res. Res. Res. Res. PCPOL Res. Res. Res. Res. 28

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. 0 27

0
0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. 26
LTDC register map

0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 25

0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 24

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 23

0
0
0
0
0
0

CXPOS[15:0]
Res. Res. Res. Res. Res. Res. Res. 22

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 21

AAW[11:0]
HSW[11:0]

AHBP[11:0]

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res.

TOTALW[11:0]
20

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 19

BCRED[7:0]

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 18

RM0432 Rev 6
0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 17

0
0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. DEN 16

0
0
The following table summarizes the LTDC registers.

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15

0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 14

0
0
1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 13

0
0
0
DRW[2:0]

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 12

0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11
Table 197. LTDC register map and reset values

0
0
0
0
0
0
0

0
Res. Res. Res. Res. Res. 10

BCGREEN[7:0]

0
0
1
0
0
0
0

0
Res. Res. Res. Res. Res. 9

0
0
0
0
0
0
0

0
Res. Res. Res. Res. Res.
DGW[2:0]

0
0
0
0
0
0

0
Res. Res. Res. Res. Res. Res. 7

0
0
0
0
0
0
0

0
Res. Res. Res. Res. Res.

CYPOS[15:0]
6

0
0
1
0
0
0
0

0
Res. Res. Res. Res. Res. 5

0
0
0
0
0
0
0

0
DBW[2:0]

Res. Res. Res. Res. Res.

AAH[10:0]
VSH[10:0]

4
AVBP[10:0]

LIPOS10:0]
TOTALH[10:0]

0
0
0
0
0
0

1
0
0
0
0
HSYNCS CRRIF RRIF RRIE Res. Res. 3

0
0
0
0
0
0

1
0
0
0
0
BCBLUE[7:0]

VSYNCS CTERRIF TERRIF TERRIE Res. Res. 2

0
0
0
0
0
0

1
0
0
0
0
0

HDES CFUIF FUIF FUIE VBR Res. 1

0
0
0
0

1
0
0
0
0

0
0
0
0

VDES CLIF LIF LIE IMR LTDCEN 0

921/2301
LCD-TFT display controller (LTDC)

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LCD-TFT display controller (LTDC) RM0432

Table 197. LTDC register map and reset values (continued)

Offset Register name

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
COLKEN
CLUTEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

LEN
LTDC_L1CR
0x0084

Reset value Res. 0 0 0

Res.
Res.
Res.

Res.
Res.
Res.
Res.
LTDC_L1WHPCR WHSPPOS[11:0] WHSTPOS[11:0]
0x0088

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
LTDC_L1WVPCR WVSPPOS[10:0] WVSTPOS[10:0]
0x008C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

LTDC_L1CKCR CKRED[7:0] CKGREEN[7:0] CKBLUE[7:0]

0x0090

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LTDC_L1PFCR PF[2:0]
0x0094
Reset value 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LTDC_L1CACR CONSTA[7:0]
0x0098
Reset value 1 1 1 1 1 1 1 1

LTDC_L1DCCR DCALPHA[7:0] DCRED[7:0] DCGREEN[7:0] DCBLUE[7:0]

0x009C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
LTDC_L1BFCR BF1[2:0] BF2[2:0]
0x00A0

Reset value 1 1 0 1 1 1

LTDC_L1CFBAR CFBADD[31:0]
0x00AC

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.

Res.
Res.
Res.

LTDC_L1CFBLR CFBP[12:0] CFBLL[12:0]

0x00B0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

LTDC_L1CFBLNR CFBLNBR[10:0]
0x00B4

Reset value 0 0 0 0 0 0 0 0 0 0 0

LTDC_L1CLUTWR CLUTADD[7:0] RED[7:0] GREEN[7:0] BLUE[7:0]

0x00C4

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
COLKEN
CLUTEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

LEN

LTDC_L2CR
0x0104

Reset value 0 0 0
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.

LTDC_L2WHPCR WHSPPOS[11:0] WHSTPOS[11:0]

0x0108

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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RM0432 LCD-TFT display controller (LTDC)

Table 197. LTDC register map and reset values (continued)

Offset Register name

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
LTDC_L2WVPCR WVSPPOS[10:0] WVSTPOS[10:0]
0x010C

Reset value Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Res.
Res.
Res.
Res.
Res.
Res.
Res.
LTDC_L2CKCR CKRED[7:0] CKGREEN[7:0] CKBLUE[7:0]
0x0110

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LTDC_L2PFCR PF[2:0]
0x0114

Reset value 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LTDC_L2CACR CONSTA[7:0]
0x0118

Reset value 1 1 1 1 1 1 1 1

LTDC_L2DCCR DCALPHA[7:0] DCRED[7:0] DCGREEN[7:0] DCBLUE[7:0]

0x011C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
LTDC_L2BFCR BF1[2:0] BF2[2:0]
0x0120
Reset value 1 1 0 1 1 1

LTDC_L2CFBAR CFBADD[31:0]
0x012C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.

Res.
Res.
Res.

LTDC_L2CFBLR CFBP[12:0] CFBLL[12:0]

0x0130

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

LTDC_L2CFBLNR CFBLNBR[10:0]
0x0134

Reset value 0 0 0 0 0 0 0 0 0 0 0

LTDC_L2CLUTWR CLUTADD[7:0] RED[7:0] GREEN[7:0] BLUE[7:0]

0x0144

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 91 for the register boundary addresses.

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30 DSI Host (DSIHOST) applied to

STM32L4R9xx and STM32L4S9xx only

30.1 Introduction
The Display Serial Interface (DSI) is part of a group of communication protocols defined by
the MIPI® Alliance. The MIPI® DSI Host Controller is a digital core that implements all
protocol functions defined in the MIPI® DSI Specification.
It provides an interface between the system and the MIPI® D-PHY, allowing the
communication with a DSI-compliant display.

30.2 Standard and references

• MIPI® Alliance Specification for Display Serial Interface (DSI)
v1.1 - 22 November 2011
• MIPI® Alliance Specification for Display Bus Interface (DBI-2)
v2.00 - 16 November 2005
• MIPI® Alliance Specification for Display Command Set (DCS)
v1.1 - 22 November 2011
• MIPI® Alliance Specification for Display Pixel Interface (DPI-2)
v2.00 - 15 September 2005
• MIPI® Alliance Specification for Stereoscopic Display Formats (SDF)
v1.0 - 22 November 2011
• MIPI® Alliance Specification for D-PHY
v1.1 - 7 November 2011

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30.3 DSI Host main features

• Compliant with MIPI® Alliance standards (see Section 30.2: Standard and references)
• Interface with MIPI® D-PHY
• Supports all commands defined in the MIPI® Alliance specification for DCS:
– Transmission of all Command mode packets through the APB interface
– Transmission of commands in Low-Power and High-Speed during Video mode
• Supports up to two D-PHY data lanes
• Bidirectional communication and escape mode support through data lane 0
• Supports non-continuous clock in D-PHY clock lane for additional power saving
• Supports Ultra Low-Power mode with PLL disabled
• ECC and Checksum capabilities
• Support for End of Transmission Packet (EoTp)
• Fault recovery schemes
• Configurable selection of system interfaces:
– AMBA APB for control and optional support for Generic and DCS commands
– Video mode interface through LTDC
– Adapted Command mode interface through LTDC
– Independently programmable virtual channel Id in Video mode, Adapted
Command mode and APB slave
• Video mode interfaces features:
– LTDC interface color coding mappings into 24-bit interface:
•16-bit RGB, configurations 1, 2, and 3
•18-bit RGB, configurations 1 and 2
•24-bit RGB
– Programmable polarity of all LTDC interface signals
– Extended resolutions beyond the DPI standard maximum resolution of 800x480
pixels:
– Maximum resolution is limited by available DSI physical link bandwidth:
•Number of lanes:2
•Maximum speed per lane: 500 Mbps
•See examples in Section 30.4.2: Supported resolutions and frame rates
• Adapted interface features:
– Support for sending large amounts of data through the memory_write_start (WMS)
and memory_write_continue (WMC) DCS commands
– LTDC interface color coding mappings into 24-bit interface:
•16-bit RGB, configurations 1, 2, and 3
•18-bit RGB, configurations 1 and 2
•24-bit RGB
• Video mode pattern generator:
– Vertical and horizontal color bar generation without LTDC stimuli
– BER pattern without LTDC stimuli

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30.4 DSI Host functional description

30.4.1 General description

The MIPI® DSI Host includes dedicated video interfaces internally connected to the LTDC
and a generic APB interface that can be used to transmit information to the display. More in
detail:
• LTDC interface:
– Used to transmit information in Video mode, in which the transfers from the host
processor to the peripheral take the form of a real-time pixel stream (DPI).
– Through a customized mode, this interface can be used to transmit information in
full bandwidth in the Adapted Command mode (DBI).
• APB slave interface: This interface allows the transmission of generic information in
Command mode, and follows a proprietary register interface. This interface can
operate concurrently with either LTDC interface in either Video mode or Adapted
Command mode.
• Video mode pattern generator: This interface allows the transmission of
horizontal/vertical color bar and D-PHY BER testing pattern without any kind of stimuli.
The block diagram of the DSI Host is shown in Figure 204.

Figure 204. DSI Host block diagram

DSI Host
LTDC
Ctrl FIFO DATAP1
LTDC
RGB
Interface LTDC DATAN1
Pixel FIFO DATAP0
D-PHY PPI
Packet DATAN0
APB to Interface D-PHY
Generic FIFO Handler
Generic Control CLKP
CLKN
Video Mode
Pattern
Generator

APB Register Bank Error Management

MS35899V1

30.4.2 Supported resolutions and frame rates

The DSI specification does not define supported standard resolutions or frame rates.
Display resolution, blanking periods, synchronization events duration, frame rates, and pixel
color depth play a fundamental role in the required bandwidth. In addition, other link related
attributes can influence the ability of the link to support a DSI-specific device. These
attributes can be: display input buffering capabilities, video transmission mode (Burst or
Non-Burst), Bus Turn-Around (BTA) time, concurrent command mode traffic in a video mode
transmission, or display device specifics. All these variables make it difficult to define a

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RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only

standard procedure to estimate the minimum lane rate and the minimum number of lanes
that support a specific display device.
The basic assumptions for estimates are:
• clock lane frequency is 250 MHz, resulting in a bandwidth of 500 Mbps for each data
lane;
• the display should be capable of buffering the pixel data at the speed at which it is
delivered in the DSI link;
• no significant control traffic is present on the link when the pixel data is being
transmitted.

30.4.3 System level architecture

Figure 205 shows the architecture of the DSI Host

Figure 205. DSI Host architecture

Regulator

PLL

Ctrl DSI Host

DATAP1
LTDC RGB LTDC
RGB DSI DATAN1
Wrapper I/F PPI
Packet D-PHY DATAP0
Handler I/F D-PHY
APB to DATAN0
APB Generic
CLKP
Register Error CLKN
APB
Bank Management

MSv37300V1

The different parts have the following functions:

• The DSI Wrapper ensures the interfacing between the LTDC and the DSI Host kernel.
It can adapt the color mode, the signal polarity and manages the Tearing Effect (TE)
management for automatic frame buffer update in Adapted Command mode. The DSI
Wrapper also control the DSI Regulator, the DSI PLL and specific functions of the
MIPI® D-PHY.
• The LTDC interface captures the data and control signals from the LTDC and conveys
them to a FIFO for video control signals and another one for the pixel data. This data is
then used to build one of the following:
– Video packets, when in Video mode (see Section 30.5)
– The memory_write_start and memory_write_continue DCS commands, when in
Adapted Command mode (see Section 30.6)
• The Register Bank is accessible through a standard AMBA-APB slave interface,
providing access to the DSI Host registers for configuration and control. There is also a
fully programmable interrupt generator to inform the system about certain events.
• The PHY Interface Control is responsible for managing the D-PHY interface. It
acknowledges the current operation and enables Low-Power transmission/reception or

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a High-Speed transmission. It also performs data splitting between available D-PHY

lanes for High-Speed transmission.
• The Packet Handler schedules the activities inside the link. It performs several
functions based on the interfaces that are currently operational and the video
transmission mode that is used (burst mode or non-burst mode with sync pulses or
sync events). It builds long or short packet generating correspondent ECC and CRC
codes. This block also performs the following functions:
– packet reception
– validation of packet header by checking the ECC
– header correction and notification for single-bit errors
– termination of reception
– multiple header error notification
– depending on the virtual channel of the incoming packet, the handler routes the
output data to the respective port.
• The APB-to-Generic block bridges the APB operations into FIFOs holding the Generic
commands. The block interfaces with the following FIFOS:
– Command FIFO
– Write payload FIFO
– Read payload FIFO
• The Error Management notifies and monitors the error conditions on the DSI link. It
controls the timers used to determine if a timeout condition occurred, performing an
internal soft reset and triggering an interruption notification.

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30.5 Functional description: Video mode on LTDC interface

The LTDC interface captures the data and control signals and conveys them to the FIFO
interfaces that transmit them to the DSI link.
Two different streams of data are present at the interface, namely video control signals and
pixel data. Depending on the interface color coding, the pixel data is disposed differently
throughout the LTDC bus.
Interface pixel color coding is summarized in Table 198.

Table 198. Location of color components in the LTDC interface

16 bits 18 bits
Location 24 bits
Configuration Configuration Configuration Configuration Configuration
1 2 3 1 2

D23 - - - - - R[7]

D22 - - - - - R[6]

D21 - - R[4] - R[5] R[5]

D20 - R[4] R[3] - R[4] R[4]

D19 - R[3] R[2] - R[3] R[3]

D18 - R[2] R[1] - R[2] R[2]

D17 - R[1] R[0] R[5] R[1] R[1]

D16 - R[0] - R[4] R[0] R[0]

D15 R[4] - - R[3] - G[7]

D14 R[3] - - R[2] - G[6]

D13 R[2] G[5] G[5] R[1] G[5] G[5]

D12 R[1] G[4] G[4] R[0] G[4] G[4]

D11 R[0] G[3] G[3] G[5] G[3] G[3]

D10 G[5] G[2] G[2] G[4] G[2] G[2]

D9 G[4] G[1] G[1] G[3] G[1] G[1]

D8 G[3] G[0] G[0] G[2] G[0] G[0]

D7 G[2] - - G[1] - B[7]

D6 G[1] - - G[0] - B[6]

D5 G[0] - B[4] B[5] B[5] B[5]

D4 B[4] B[4] B[3] B[4] B[4] B[4]

D3 B[3] B[3] B[2] B[3] B[3] B[3]

D2 B[2] B[2] B[1] B[2] B[2] B[2]

D1 B[1] B[1] B[0] B[1] B[1] B[1]

D0 B[0] B[0] - B[0] B[0] B[0]

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The LTDC interface can be configured to increase flexibility and promote correct use of this
interface for several systems. The following configuration options are available:
• Polarity control: All the control signals are programmable to change the polarity
depending on the LTDC configuration.
• After the core reset, DSI Host waits for the first VSYNC active transition to start signal
sampling, including pixel data, thus avoiding starting the transmission of the image data
in the middle of a frame.
• If interface pixel color coding is 18 bits and the 18-bit loosely packed stream is
disabled, the number of pixels programmed in the VPSIZE field must be a multiple of
four. This means that in this mode, the two LSBs in the configuration are always
inferred as zero. The specification states that in this mode, the pixel line size should be
a multiple of four.
• To avoid FIFO underflows and overflows, the configured number of pixels is assumed
to be received from the LTDC at all times.
• To keep the memory organized with respect to the packet scheduling, the number of
pixels per packet parameter is used to separate the memory space of different video
packets.
For SHTDN and COLM sampling and transmission, the video streaming from the LTDC
must be active. This means that if the LTDC is not actively generating the video signals like
VSYNC and HSYNC, these signals are not transmitted through the DSI link. Because of
such constraints and for commands to be correctly transmitted, the first VSYNC active pulse
should occur for the command sampling and transmission. When shutting down the display,
it is necessary for the LTDC to be kept active for one frame after the command being issued.
This ensures that the commands are correctly transmitted before actually disabling the
video generation at the LTDC interface.
The SHTDN and COLM values can be programmed in the DSI Wrapper Control Register
(DSI_WCR).
For all of the data types, one entire pixel is received per each clock cycle. The number of
pixels of payload is restricted to a multiple of a value, as shown in Table 199.

Table 199. Multiplicity of the payload size in pixels for each data type
Value Data Types

16-bit
1 18-bit loosely packed
24-bit
2 Loosely packed pixel stream
4 18-bit non-loosely packed

30.5.1 Video transmission mode

There are different video transmission modes, namely:
• Burst mode
• Non-Burst mode
– Non-Burst mode with sync pulse
– Non-Burst mode with sync event.

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Burst mode
In this mode, the entire active pixel line is buffered into a FIFO and transmitted in a single
packet with no interruptions. This transmission mode requires that the DPI Pixel FIFO has
the capacity to store a full line of active pixel data inside it. This mode is optimally used
when the difference between the pixel required bandwidth and DSI link bandwidth is
significant, it enables the DSI Host to quickly dispatch the entire active video line in a single
burst of data and then return to Low-power mode.

Non-Burst mode
In this mode, the processor uses the partitioning properties of the DSI Host to divide the
video line transmission into several DSI packets. This is done to match the pixel required
bandwidth with the DSI link bandwidth. With this mode, the controller configuration does not
require a full line of pixel data to be stored inside the LTDC interface pixel FIFO. It requires
only the content of one video packet.

Guidelines for selecting the Burst or Non-Burst mode

Selecting the Burst and Non-Burst mode is mainly dependent on the system configuration
and the device requirements. Choose the video transmission mode that suits the application
scenario. The Burst mode is more beneficial because it increases the probability of the link
spending more time in the Low-Power mode, decreasing power consumption. However, the
following conditions should be met for availing the maximum benefits from the Burst mode
of operation:
• The DSI Host core should have sufficient pixel memory to store an entire pixel line to
avoid the overflow of the internal FIFOs.
• The display device should support receiving a full pixel line in a single packet burst to
avoid the overflow on the reception buffer.
• The DSI output bandwidth should be higher than the LTDC interface input bandwidth in
a relation that enables the link to go to Low-Power once per line.
If the system cannot meet these requirements, it is likely that the pixel data will be lost
causing the malfunctioning of the display device while using the Burst mode. These errors
are related to the capabilities of the system to store the temporary pixel data.
If all the conditions for using the Burst mode cannot be met, use the Non-Burst mode to
avoid the errors caused by the Burst mode. The Non-Burst mode provides a better matching
of rates for pixel transmission, enabling:
• Only a certain amount of pixels to be stored in the memory and not requiring a full pixel
line (lesser LTDC interface RAM requirements in the DSI Host).
• Operation with devices that support only a small amount of pixel buffering (less than a
full pixel line).
The DSI Non-Burst mode should be configured in such way that the DSI output pixel ratio
matches with the LTDC interface input pixel ratio, reducing the memory requirements on
both host and/or device side. This is achieved by dividing a pixel line into several chunks of
pixels and optionally interleaving them with null packets.
The following equations show how the DSI Host core transmission parameters should be
programmed in Non-Burst mode to match the DSI link pixel output ratio (left hand side of the
"=" sign) and LTDC interface pixel input (right hand side of the "=" sign).

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When the null packets are enabled:

lanebyteclkperiod * NUMC (VPSIZE * bytes_per_pixel + 12 + NPSIZE) / number_of_lanes
= pixels_per_line * LTDC_Clock_period
When the null packets are disabled:
lanebyteclkperiod * NUMC (VPSIZE * bytes_per_pixel + 6) / number_of_lanes
= pixels_per_line * LTDC_Clock_period

30.5.2 Updating the LTDC interface configuration in video mode

It is possible to update the LTDC interface configuration on the fly without impacting the
current frame. It is done with the help of shadow registers. This feature is controlled by the
DSI Host Video Shadow Control Register (DSI_VSCR).
The new configuration is only used when the system requests for it. To update the Video
configuration during the transmission of a video frame, the configuration of that frame needs
to be stored in the auxiliary registers. This way, the new frame configurations can be set
through the APB interface without corrupting the current frame.
By default, this feature is disabled. To enable this feature, set the Enable (EN) bit of the DSI
Host Video Shadow Control Register (DSI_VSCR) to 1.
When this feature is enabled, the system supplies the configuration stored in the auxiliary
registers.
Figure 206 shows the necessary steps to update the LTDC interface configuration.

Figure 206. Flow to update the LTDC interface configuration using shadow registers

Configure the LTDC interface

Request update New resolution

Read DSI Host LTDC

Start video engine
shadow control register

Active Accepted
UR
MSv35855V1

Immediate update
When the shadow register feature is active, the auxiliary registers requires the LTDC
configuration before the video engine starts. This means that, after a reset, Update Register
(UR) bit is immediately granted.

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In situations when it is required to immediately update the active registers without the reset
(as illustrated in Figure 207), ensure that the Enable (EN) and Update Register (UR) bits of
the DSI Host Video Shadow Control Register (DSI_VSCR) are set to 0.

Figure 207. Immediate update procedure

DSI Host DSI Host

Default DPI Config DPI Config 1

DPI CONFIG 1 Video Shadow Update
EN=0 EN=1

UR=0 UR=1

MSv35856V2

Updating the configuration during the transmission of a frame using APB

To update the LTDC interface configuration, follow the steps shown in Figure 208:
1. Ensure that the Enable (EN) bit of the DSI Host Video Shadow Control Register
(DSI_VSCR) register is set to 1.
2. Set the Update Register (UR) bit of DSI Host Video Shadow Control Register
(DSI_VSCR) to 1.
3. Monitor the Update Register (UR) bit. This bit is set to 0 when the update is complete.

Figure 208. Configuration update during the trasmission of a frame

DSI Host DSI Host

Default DPI Config DPI Config 1

DPI CONFIG 1 Video Shadow Request
EN=1 EN=1

UR=0 UR=1

MSv35857V2

Requesting a configuration update

It is possible to request for the LTDC interface configuration update at any part of the frame.
DSI Host waits until the end of the frame to change the configuration. However, avoid
sending the update request during the first line of the frame because the data must
propagate between clock domains.

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30.6 Functional description: adapted command mode on LTDC

interface
The Adapted Command mode, enables the system to input a stream of pixel from the LTDC
that is conveyed by DSI Host using the Command mode transmission (using the DCS
packets). The Adapted Command mode also supports pixel input control rate signaling and
Tearing Effect report mechanism.
The Adapted Command mode allows to send large amounts of data through the
memory_write_start (WMS) and memory_write_continue (WMC) DCS commands. It helps
in delivering a wider data bandwidth for the memory write operations sent in Command
mode to MIPI® displays and to refresh large areas of pixels in high resolution displays. If
additional commands such as display configuration commands, read back commands, and
tearing effect initialization are to be transferred, then the APB slave generic interface should
be used to complement the Adapted Command mode functionality.
Adapted Command mode of operation supports 16 bpp, 18 bpp, and 24 bpp RGB.
To transmit the image data in Adapted Command mode:
• Set Command mode (CMDM) bit of the DSI Host mode Configuration Register
(DSI_MCR) to 1.
• Set DSI mode (DSIM) bit in the DSI Wrapper Configuration Register (DSI_WCFGR) to
1.
To transmit the image data, follow these steps:
• Define the image area to be refreshed, by using the set_column_address and
set_page_address DCS commands. The image area needs to be defined only once
and remains effective until different values are defined.
• Define the pixel color coding to be used by using the Color Coding (COLC) field in the
DSI Host LTDC Color Coding Register (DSI_LCOLCR).
• Define the Virtual Channel ID of the LTDC interface generated packets using the Virtual
Channel ID (VCID) field in the DSI Host LTDC VCID Register (DSI_LVCIDR). These
also need to be defined only once.
• Start transmitting the data from the LTDC setting the LTDC Enable (LTDCEN) bit of the
DSI_WCR register.
Figure 209 shows the adapted command mode usage flow.

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Figure 209. Adapted command mode usage flow

Video engine DSI controller Display

genIF:
set_co
lumn_a
ddress
DCS: s
et_colu
mn_ad
genIF: dress
set_pa
ge_add
ress
DCS: s
et_pag
e_addre
LTDCIF ss
: vsync
= 1, dp
idataen
=1

DCS: w
rite_me
mory_s
tart
DCS: w
rite_me
mory_c
ontinue
1
DCS: w
rite_me
mory_c
ontinue
LTDCIF 2
: vsync DCS: w
= 0, dp rite_me
idataen mory_c
=0 ontinue
3

MSv35860V1

When the Command mode (CMDM) bit of the DSI Host mode Configuration Register
(DSI_CFGR) is set to 1, the LTDC interface assume the behavior corresponding to the
Adapted Command mode.
In this mode, the host processor can use the LTDC interface to transmit a continuous
stream of pixels to be written in the local frame buffer of the peripheral. It uses a pixel input
bus to receive the pixels and controls the flow automatically to limit the stream of continuous
pixels. When the first pixel is received, the current value of the Command Size (CMDSIZE)
field of the DSI Host LTDC Command Configuration Register (DSI_LCCR), is shadowed to
the internal interface function. The interface increments a counter on every valid pixel that is
input through the interface. When this pixel counter reaches Command Size (CMDSIZE), a
command is written into the command FIFO and the packet is ready to be transmitted
through the DSI link.
If the last pixel arrives before the counter reaches the value of shadowed Command Size
(CMDSIZE), a WMS command is issued to the command FIFO with Word Count (WC) set to
the amount of bytes that correspond to the value of the counter. If more than CMDSIZE
number of pixels are received (shadowed value), a WMS command is sent to the command
FIFO with WC set to the number of bytes that correspond to Command Size (CMDSIZE)
and the counter is restarted.
After the first WMS command has been written to the FIFO, the circuit behaves in a similar
way, but issues WMC commands instead of WMS commands. The process is repeated until
the last pixel of the image is received. The core automatically starts sending a new packet

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when the last pixel of the image is received falls or Command Size (CMDSIZE) limit is
reached.

Synchronization with the LTDC

The DSI wrapper performs the synchronization of the transfer process by :
• controlling the start/halt of the LTDC.
• making the data flow control between LTDC and DSI Host.
The transfer to refresh the display frame buffer can be trigged
• manually, setting the LTDC Enable (LTDCEN) bit of the DSI Wapper Control Register
(DSI_WCR).
• automatically when a Tearing Effect (TEIF) event occurs and Automatic Refresh (AR) is
enabled.
The selection between manual and automatic mode is done through the Automatic Refresh
(AR) bit of the DSI Wapper Configuration Register (DSI_WCFGR). In automatic refresh
mode, the LTDC Enable (LTDCEN) bit of the DSI Wapper Control Register (DSI_WCR) is
set automatically by a Tearing Effect (TEIF) event.
Once the transfer of one frame is done whatever in manual or automatic refresh mode, the
DSI Wrapper is halting the TFT Display Controller (LTDC) resetting the LTDC Enable
(LTDCEN) bit of the DSI Wapper Control Register (DSI_WCR) and set the End of Refresh
Interrupt Flag (ERIF) flag of the DSI Wrapper Status Register (DSI_WSR). If the End of
Refresh Interrupt Enable (ERIE) bit of the DSI Wapper Configuration Register
(DSI_WCFGR) is set, an interrupt is generated.
The End of Refresh Interrupt Flag (ERIF) flag of the DSI Wrapper Status Register
(DSI_WSR) can be reset setting the Clear End of Refresh Interrupt Flag (CERIF) bit of the
DSI Wrapper Clear Interrupt Flag Register (DSI_WCIFR).
The halting of the TFT Display Controller (LTDC) by the DSI Wrapper is done synchronously
on a rising edge or a falling edge of VSync according to the VSync Polarity (VSPOL) bit of
the DSI Wapper Configuration Register (DSI_WCFGR).

Support of tearing effect

The DSI specification supports tearing effect function in Command mode displays. It
enables the Host Processor to receive timing accurate information about where the display
peripheral is in the process of reading the content of its frame buffer.
The Tearing effect can be managed through
• a separate pin which is not covered in the DSI specification
• the DSI tearing effect functionality: a set_tear_on DCS command should be issued
through the APB interface using the Generic interface registers.

Tearing effect through a GPIO

When the Tearing Effect Source (TESRC) bit of the DSI Wrapper Configuration Register
(DSI_WCFGR) is set, the Tearing effect is signaled through a GPIO.
The polarity of the input signal can be configured by the Tearing Effect Polarity (TEPOL) bit
of the DSI Wrapper Configuration Register (DSI_WCFGR).
When the programmed edge is detected, the Tearing Effect Interrupt Flag (TEIF) bit of the
DSI Wrapper Interrupt and Status Register (DSI_WISR) is set.

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If the Tearing Effect Interrupt Enable (TEIE) bit of the DSI Wrapper Interrupt Enable Register
(DSI_WIER) is set, an interrupt is generated.

Tearing effect through DSI link

When the TESRC bit of the DSI Wrapper Configuration Register (DSI_WCFGR) is reset, the
Tearing effect is managed through the DSI link:
The DSI Host performs a double Bus-Turn-Around (BTA) after sending the set_tear_on
command granting the ownership of the link to the DSI display. The Display holds the
ownership of the bus until the tear event occurs, which is indicated to the DSI Host by a D-
PHY trigger event. The DSI Host then decodes the trigger and reports the event setting the
Tearing Effect Interrupt Flag (TEIF) bit of the DSI Wrapper Interrupt and Status Register
(DSI_WISR).
If the Tearing Effect Interrupt Enable (TEIE )bit of the DSI Wrapper Interrupt Enable Register
(DSI_WIER) is set, an interrupt is generated.
To use this function, it is necessary to issue a set_tear_on command after the update of the
display using the WMS and WMC DCS commands. This procedure halts the DSI link until
the display is ready to receive a new frame update.
The DSI Host does not automatically generate the tearing effect request (double BTA) after
a WMS/WMC sequence for flexibility purposes. This way several regions of the display can
be updated improving DSI bandwidth usage. Tearing effect request must always be
triggered by a set_tear_on command in the DSI Host implementation.
Configure the following registers to activate the tearing effect:
• DSI Host Command mode Configuration Register (DSI_CMCR): TEARE;
• DSI Host Protocol Configuration Register (DSI_PCR): BTAE.

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30.7 Functional description: APB slave generic interface

The APB slave interface allows the transmission of generic information in Command mode,
and follows a proprietary register interface. Commands sent through this interface are not
constrained to comply with the DCS specification, and can include generic commands
described in the DSI specification as manufacturer-specific.
The DSI Host supports the transmission of write and read Command mode packets as
described in the DSI specification. These packets are built using the APB register access.
The DSI Host Generic Payload Data Register (DSI_GPDR) has two distinct functions based
on the operation. Writing to this register sends the data as payload when sending a
Command mode packet. Reading this register returns the payload of a read back operation.
The DSI Host Generic Header Configuration Register (DSI_GHCR) contains the Command
mode packet header type and header data. Writing to this register triggers the transmission
of the packet implying that for a long Command mode packet, the packet's payload needs to
be written in advance in the DSI Host Generic Payload Data Register (DSI_GPDR).
The valid packets that can be transmitted through the Generic interface are the following
ones:
• Generic Write Short Packet 0 Parameters
• Generic Write Short Packet 1 Parameters
• Generic Write Short Packet 2 Parameters
• Generic Read Short Packet 0 Parameters
• Generic Read Short Packet 1 Parameters
• Generic Read Short Packet 2 Parameters
• Maximum Read Packet Configuration
• Generic Long Write Packet
• DCS Write Short Packet 0 Parameters
• DCS Write Short Packet 1 Parameters
• DCS Read Short Packet 0 Parameters
• DCS Write Long Packet.
A set of bits in the DSI Host Generic Packet Status Register (DSI_GPSR) reports the status
of the FIFO associated with APB interface support.
Generic interface packets are always transported using one of the DSI transmission modes,
i.e. Video mode or Command mode. If neither of these modes is selected, the packets are
not transmitted through the link and the related FIFO eventually becomes overflown.

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30.7.1 Packet transmission using the generic interface

The transfer of packets through the APB bus is based on the following conditions:
• The APB protocol defines that the write and read procedure takes two clock cycles
each to be executed. This means that the maximum input data rate through the APB
interface is always half the speed of the APB clock.
• The data input bus has a maximum width of 32 bits. This allows for a relation to be
defined between the input APB clock frequency and the maximum bit rate achievable
by the APB interface.
• The DSI link pixel bit rate when using solely APB is (APB clock frequency) * 16 Mbps.
• When using only the APB interface, the theoretical DSI link maximum bit rate can be
expressed as DSI link maximum bit rate = APB clock frequency (in MHz) * 32 / 2 Mbps.
In this formula, the number 32 represents the APB data bus width, and the division by
two is present because each APB write procedure takes two clock cycles to be
executed.
• The bandwidth is dependent on the APB clock frequency; the available bandwidth
increases with the clock frequency.
To drive the APB interface to achieve high bandwidth Command mode traffic transported by
the DSI link, the DSI Host should operate in the Command mode only and the APB interface
should be the only data source that is currently in use. Thus, the APB interface has the
entire bandwidth of the DSI link and does not share it with any another input interface
source.
The memory write commands require maximum throughput from the APB interface,
because they contain the most amount of data conveyed by the DSI link. While writing the
packet information, first write the payload of a given packet into the payload FIFO using the
DSI Host Generic Payload Data Register (DSI_GPDR). When the payload data is for the
command parameters, place the first byte to be transmitted in the least significant byte
position of the APB data bus.
After writing the payload, write the packet header into the command FIFO. For more
information about the packet header organization on the 32-bit APB data bus, so that it is
correctly stored inside the Command FIFO.
When the payload data is for a memory write command, it contains pixel information and it
should follow the pixel to byte conversion organization referred in the Annexe A of the DCS
specification.
Figures 210 to 214 show how the pixel data should be organized in the APB data write bus.
The memory write commands are conveyed in DCS long packets, encapsulated in a DSI
packet. The DSI specifies that the DCS command should be present in the first payload byte
of the packet. This is also included in the diagrams. In figures 210 to 214, the Write Memory
Command can be replaced by the DCS command Write Memory Start and Write Memory
Continue.

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Figure 210. 24 bpp APB pixel to byte organization

[31 …………………. 0]
8 bit 8 bit 8 bit 8 bit

Write_mem
pwdata(0) B0[7:0] G0[7:0] R0[7:0]
Command

Pixel
pwdata(1) R2[7:0] B1[7:0] G1[7:0] R1[7:0] 24 bpp
R0
[7:0]
pwdata(2) G3[7:0] R3[7:0] B2[7:0] G2[7:0]
G0
[7:0]

pwdata(3) B4[7:0] G4[7:0] R4[7:0] B3[7:0] B0

[7:0]

pwdata(4) R6[7:0] B5[7:0] G5[7:0] R5[7:0]

MSv35861V1

Figure 211. 18 bpp APB pixel to byte organization

[31 ………………….0]
8 bit 8 bit 8 bit 8 bit

Write_mem
pwdata(0) B0[5:0] 2'd0 G0[5:0] 2'd0 R0[5:0] 2'd0
Command

Pixel
pwdata(1) R2[5:0] 2'd0 B1[5:0] 2'd0 G1[5:0] 2'd0 R1[5:0] 2'd0 18 bpp
R0
[5:0]
pwdata(2) G3[5:0] 2'd0 R3[5:0] 2'd0 B2[5:0] 2'd0 G2[5:0] 2'd0
G0
[5:0]

pwdata(3) B4[5:0] 2'd0 G4[5:0] 2'd0 R4[5:0] 2'd0 B3[5:0] 2'd0 B0

[5:0]

pwdata(4) R6[5:0] 2'd0 B5[5:0] 2'd0 G5[5:0] 2'd0 R5[5:0] 2'd0

MSv35862V1

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Figure 212. 16 bpp APB pixel to byte organization

[31 …………………. 0]
8 bit 8 bit 8 bit 8 bit

Write_mem
pwdata(0) R1[4:0] G1[5:3] G0[2:0] B0[4:0] R0[4:0] G0[5:3]
Command Pixel
16 bpp
pwdata(1) R3[4:0] G3[5:3] G2[2:0] B2[4:0] R2[4:0] G2[5:3] G1[2:0] B1[4:0] R0
[4:0]

G0
pwdata(2) R5[4:0] G5[5:3] G4[2:0] B4[4:0] R4[4:0] G4[5:3] G3[2:0] B3[4:0] [5:0]

B0
[4:0]
pwdata(3) R7[4:0] G7[5:3] G6[2:0] B6[4:0] R6[4:0] G6[5:3] G5[2:0] B5[4:0]

MSv35863V1

Figure 213. 12 bpp APB pixel to byte organization

[31 …………………. 0]
8 bit 8 bit 8 bit 8 bit

G1 B1 B0 R1 R0 G0 Write_mem
pwdata(0) [3:0] [3:0] [3:0] [3:0] [3:0] [3:0] Command Pixel
12 bpp
R4 G4 G3 B3 B2 R3 R2 G2
pwdata(1) [3:0] [3:0] [3:0] [3:0] [3:0] [3:0] [3:0] [3:0]
R0
[3:0]

B6 R7 R6 G6 G5 B5 B4 R5 G0
pwdata(2) [3:0] [3:0] [3:0] [3:0] [3:0] [3:0] [3:0] [3:0] [3:0]

B0
G9 B9 B8 R9 R8 G8 G7 B7 [3:0]
pwdata(3) [3:0] [3:0] [3:0] [3:0] [3:0] [3:0] [3:0] [3:0]

MSv35864V1

Figure 214. 8 bpp APB pixel to byte organization

[31 …………………. 0]
8 bit 8 bit 8 bit 8 bit
Pixel
8 bpp
R2 G2 B2 R1 G1 B1 R0 G0 B0 Write_mem R0
pwdata(0) [2:0] [2:0] [1:0] [2:0] [2:0] [1:0] [2:0] [2:0] [1:0] Command [2:0]

G0
R6 G6 B6 R5 G5 B5 R4 G4 B4 R3 G3 B3
pwdata(1) [2:0] [2:0] [1:0] [2:0] [2:0] [1:0] [2:0] [2:0] [1:0] [2:0] [2:0] [1:0]
[2:0]

B0
R10 G10 B10 R9 G9 B9 R8 G8 B8 R7 G7 B7 [1:0]
pwdata(2) [2:0] [2:0] [1:0] [2:0] [2:0] [1:0] [2:0] [2:0] [1:0] [2:0] [2:0] [1:0]

MSv35865V1

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30.8 Functional description: Timeout counters

The DSI Host includes counters to manage timeout during the various communication
phases. The duration of each timeout can be configured by the 6 DSI Host Timeout Counter
Configuration Register (DSI_TCCR0..5).
There are two types of counters:
• contention error detection timeout counters (Section 30.8.1);
• peripheral response timeout counters (Section 30.8.2).

30.8.1 Contention error detection timeout counters

The DSI Host implements a set of counters and conditions to notify the errors. It features a
set of registers to control the timers used to determine if a timeout has occurred, and also
contains a set of interruption status registers that are cleared upon a read operation
(detailed in Table 200). Optionally, these registers also trigger an interrupt signal that can be
used by the system to be activated when an error occurs within the DSI connection.

Table 200. Contention detection timeout counters configuration

Timeout counter Value Register Value Field Flag Register Flag Field

High-speed transmission DSI_TCCR0 TOHSTX DSI_ISR1 TOHSTX

Low-power reception DSI_TCCR0 TOLPRX DSI_ISR1 TOLPRX

Time units for these 16-bit counters are configured in cycles defined in the Timeout Clock
Division (TOCKDIV) field in the DSI Host Clock Control Register (DSI_CCR).
The value written to the Timeout Clock Division (TOCKDIV) field in the DSI Host Clock
Control Register (DSI_CCR) defines the time unit for the timeout limits using the Lane byte
clock as input.
This mechanism increases the range to define these limits.

High-speed transmission contention detection

The timeout duration is configured in the High-Speed Transmission Timeout Count
(HSTX_TOCNT) field of the DSI Host Timeout Counter Configuration Register 1
(DSI_TCCR0). A 16-bit counter measures the time during which the High-Speed mode is
active.
If that counter reaches the value defined by the High-Speed Transmission Timeout Count
(HSTX_TOCNT) field of the DSI Host Timeout Counter Configuration Register 1
(DSI_TCCR0), the Timeout High-Speed Transmission (TOHSTX) bit in the DSI Host
Interrupt and Status Register 1 (DSI_ISR1) is asserted and an internal soft reset is
generated to the DSI Host.
If the Timeout High-Speed Transmission Interrupt Enable (TOHSTXIE) bit of the DSI Host
Interrupt Enable Register 1 (DSI_IER1) is set, an interrupt is generated.

Low-power reception contention detection

The timeout is configured in the Low-Power Reception Timeout Counter (LPRX_TOCNT)
field of the DSI Host Timeout Counter Configuration Register 1 (DSI_TCCR1). A 16-bit
counter measures the time during which the Low-Power reception is active.

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If that counter reaches the value defined by the Low-Power Reception Timeout Counter
(LPRX_TOCNT) field of the DSI Host Timeout Counter Configuration Register 1
(DSI_TCCR0), the Timeout Low-Power Reception (TOLPRX) bit in the DSI Host Interrupt
and Status Register 1 (DSI_ISR1) is asserted and an internal soft reset is generated to the
DSI Host.
If the Timeout Low-Power Reception Interrupt Enable (TOLPRXIE) bit of the DSI Host
Interrupt Enable Register 1 (DSI_IER1) is set, an interrupt is generated. Once the software
gets notified by the interrupt, it must reset the D-PHY by de-asserting and asserting the
Digital Enable (DEN) bit of the DSI Host PHY Control Register (DSI_PCTLR).

30.8.2 Peripheral response timeout counters

A peripheral may not immediately respond correctly to some received packets. For
example, a peripheral receives a read request, but due to its architecture cannot access the
RAM for a while. It may be because the panel is being refreshed and takes some time to
respond. In this case, set a timeout to ensure that the host waits long enough so that the
device is able to process the previous data before receiving the new data or responding
correctly to new requests.
Table 201 lists the events belonging to various categories having an associated timeout for
peripheral response.

Table 201. List of events of different categories of the PRESP_TO counter

Category Event

Items implying a BTA PRESP_TO Bus Turn-Around

(0x04) Generic read, no parameters short
READ requests indicating a PRESP_TO (0x14) Generic read, 1 parameter short
(replicated for HS and LP) (0x24) Generic read, 2 parameters short
(0x06) DCS read, no parameters short
(0x03) Generic short write, no parameters short
(0x13) Generic short write, 1 parameter short
(0x23) Generic short write, 2 parameters short
WRITE requests indicating a PRESP_TO (0x29) Generic long write long
(replicated for HS and LP) (0x05) DCS short write, no parameters short
(0x15) DCS short write, 1 parameter short
(0x39) DCS long write/write_LUT, Command packet long
(0x37) Set maximum return packet size

The DSI Host ensures that, on sending an event that triggers a timeout, the D-PHY switches
to the Stop state and a counter starts running until it reaches the value of that timeout. The
link remains in the LP-11 state and unused until the timeout ends, even if there are other
events ready to be transmitted.
Figures 215 to 217 illustrate the flow of counting in the PRESP_TO counter for the three
categories listed in Table 201.

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Figure 215. Timing of PRESP_TO after a bus turn-around

Host Device

BTA

pt
ror R
ck & Er
rigg er | A
Ack T

BTA

PRESP_TO
Timer < PRESP_TO

LP-11
Device Ready

Arbitra
ry even
t after B
TA

MSv35866V1

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Figure 216. Timing of PRESP_TO after a Read Request (HS or LP)

Host Device

READ
Reque
st

LP-11
Timer < PRESP_TO

PRESP_TO
Device Ready
BTA

pt
ror R
& Er
Ack
DR esp |
REA

BTA

MSv35867V1

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Figure 217. Timing of PRESP_TO after a Write Request (HS or LP)

Host Device

WRITE
Reque
st

LP-11
Timer < PRESP_TO

PRESP_TO
Arbitra Device Ready
ry even
t after W
RITE R
eq.

MSv35868V1

Table 202 describes the fields used for the configuration of the PRESP_TO counter.

Table 202. PRESP_TO counter configuration

Description Register Field

After sending a
DSI_TCCR1 HSRD_TOCNT
High-Speed read operation
Period for which the DSI Host After sending a
DSI_TCCR2 LPRD_TOCNT
keeps the link still Low-Power read operation
After completing a
DSI_TCCR5 BTA_TOCNT
Bus-Turn-Around (BTA)
After sending a
DSI_TCCR3 HSWR_TOCNT
Period for which the DSI Host High-Speed write operation
keeps the link inactive After sending a
DSI_TCCR4 LPWR_TOCNT
Low-Power write operation

The values in these registers are measured in number of cycles of the Lane byte clock.
These registers are only used in Command mode because in Video mode, there is a rigid
timing schedule to be met to keep the display properly refreshed and it must not be broken
by these or any other timeouts. Setting a given timeout to 0 disables going into LP-11 state
and timeout for events of that category.
The read and the write requests in High-Speed mode are distinct from the read and the write
requests in Low-Power mode. For example, if HSRD_TOCNT is set to zero and
LPRD_TOCNT is set to a non-zero value, a generic read with no parameters does not
activate the PRESP_TO counter in High-Speed, but it activates the PRESP_TO in Low-
Power.
The DSI Host Timeout Counter Configuration Register 4 (DSI_TCCR3) includes a special
Presp mode (PM) bit to change the normal behavior of PRESP_TO in Adaptive Command

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mode for High-Speed write operation timeout. When set to 1, this bit allows the PRESP_TO
from HSWR_TOCNT to be used only once, when both of the following conditions are met:
• the LTDC VSYNC signal rises and falls;
• the packets originated from the LTDC interface in Adapted Command mode are
transmitted and its FIFO is empty again.
In this scenario, non-Adapted Command mode requests are not sent to the D-PHY, even if
there is traffic from the Generic interface ready to be sent, returning them to the Stop state.
When it happens, the PRESP_TO counter is activated and only when it is completed, the
DSI Host sends any other traffic that is ready, as illustrated in Figure 218.

Figure 218. Effect of Prep mode at 1

dpivsync_edpiwms

dpidataen
dpidata[29:0] A10 A20 A30

edpi_fifo_empty
gen_wr_en

gen_data[31:0] B3

link_state[1:0] LP HS LP HS LP

link_data[31:0]

PRESP_TO_active
MSv35880V1

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30.9 Functional description: transmission of commands

30.9.1 Transmission of commands in Video mode

The DSI Host supports the transmission of commands, both in High-Speed and Low-Power,
while in Video mode. The DSI Host uses Blanking or Low-Power (BLLP) periods to transmit
commands inserted through the APB Generic interface. Those periods correspond to the
gray areas of Figure 219.

Figure 219. Command transmission periods within the image area

VSS
VSA and
or BLLP
VBP lines
HSS

BLLP in
HSS+HBP RGB burst HFP VACT lines
mode

HSS BLLP VFP lines

MSv35869V1

Commands are transmitted in the blanking periods after the following packets/states:
• Vertical Sync Start (VSS) packets, if the Video Sync pulses are not enabled
• Horizontal Sync End (HSE) packets, in the VSA, VBP, and VFP regions
• Horizontal Sync Start (HSS) packets, if the Video Sync pulses are not enabled in the
VSA, VBP, and VFP regions
• Horizontal Active (HACT) state
Besides the areas corresponding to BLLP, large commands can also be sent during the last
line of a frame. In that case, the line time for the Video mode is violated and the edpihalt
signal is set to request the DPI video timing signals to remain inactive. Only if a command
does not fit into any BLLP area, it is postponed to the last line, causing the violation of the
line time for the Video mode, as illustrated in Figure 220.

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Figure 220. Transmission of commands on the last line of a frame

Where vsync would have
asserted if dpihalt stayed low

frame time frame time

dpivsync

dpihsync
dpidataen

edpihalt

vsync can assert immediately

after dpihalt de-asserts
MSv35881V1

Only one command is transmitted per line, even in the case of the last line of a frame but
one command is possible for each line.
There can be only one command sent in Low-Power per line. However, one Low-Power
command is possible for each line. In High-Speed, the DSI Host can send more than one
command, as many as it determines to fit in the available time.
The DSI Host avoids sending commands in the last line because it is possible that the last
line is shorter than the other ones. For instance, the line time (tL) could be half a cycle longer
than the tL on the LTDC interface, that is, each line in the frame taking half a cycle from time
for the last line. This results in the last line being (½ cycle) x (number of lines -1) shorter
than tL.
The COLM and SHTDN bits of the DSI Wrapper Control Register (DSI_WCR) are also able
to trigger the sending of command packets. The commands are:
• Color mode ON
• Color mode OFF
• Shut Down Peripheral
• Turn On Peripheral
These commands are not sent in the VACT region. If the Low-Power Command Enable
(LPCE) bit of the DSI Host Video mode Configuration Register (DSI_VMCR) is set, these
commands are sent in Low-Power mode.
In Low-Power mode, the Largest Packet Size (LPSIZE) field of the DSI Host Low-power
mode Configuration Register (DSI_LPMCR) is used to determine if these commands can be
transmitted. It is assumed that Largest Packet Size (LPSIZE) is greater than or equal to four
bytes (number of bytes in a short packet), because the DSI Host does not transmit these
commands on the last line.
If the Frame Bus-Turn-Around Acknoledge Enable (FBTAAE) bit is set in the DSI Host Low-
power mode Configuration Register (DSI_LPMCR), a BTA is generated by DSI Host after
the last line of a frame. This may coincide with a write command or a read command. In
either case, the LTDC interface is halted until an acknowledge is received (control of the DSI
bus is returned to the host).

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30.9.2 Transmission of commands in Low-power mode

DSI Host can be configured to send the Low-Power commands during the High-Speed
Video mode transmission.
To enable this feature, set the Low Power Command Enable (LPCE) bit of the DSI Host
Video mode Configuration Register (DSI_VMCR) to 1. In this case, it is necessary to
calculate the time available, in bytes, to transmit a command in Low-Power mode to
Horizontal Front Porch (HFP), Vertical Sync Active (VSA), Vertical Back Porch (VBP), and
Vertical Front Porch (VFP) regions.
Bits 8 to 13 of the Video mode configuration register (DSI_VMCR) register indicates if DSI
Host can go to LP when in idle. If the Low-Power Command Enable (LPCE) bit is set and
non-video packets are in queue, DSI Host ignores the Low-Power configuration and
transmits Low-Power commands, even if it is not allowed to enter Low-Power mode in a
specific region. After the Low-Power commands transmission, DSI Host remains in Low-
Power until a sync event occurs.
For example, consider that the VFP is selected as High-Speed region (LPVFPE = 1'b0) with
LPCE set as a command to transmit in Low-Power in the VPF region. This command is
transmitted in Low-Power, and the line stays in Low-Power mode until a new HSS arrives.

Calculating the time to transmit commands in LP mode in the VSA, VBP, and
VFP regions
The Largest Packet Size (LPSIZE) field of the DSI Host Low-Power mode Configuration
Register (DSI_LPMCR) indicates the time available (in bytes) to transmit a command in
Low-Power mode (based on the escape clock) on a line during the VSA, VBP, and the VFP
regions.
Calculation of Largest Packet Size (LPSIZE) depends on the used Video mode.
Figure 221 illustrates the timing intervals for the Video mode in Non-Burst with sync pulses,
while Figure 222 refers to Video mode in Burst and Non-Burst with sync events.

Figure 221. LPSIZE for Non-Burst with sync pulses

tL
tH1 tHS -> LP tLPDT tLPDT tLPS -> HS
command
EscEntry

2 tESCCLK
EscExit
LPDT
HSS

HSE

HSA HSÆLP outvact_lpcmd_time LPÆHS

MSv35870V1

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Figure 222. LPSIZE for Burst or Non-Burst with sync events

tL
tH1 tHS -> LP tLPDT tLPDT tLPS -> HS

command
EscEntry

2 tESCCLK
EscExit
LPDT
HSS
HSÆLP outvact_lpcmd_time LPÆHS

MSv35871V1

This time is calculated as follows:

LPSIZE = (tL - (tH1 + tHS->LP + tLPHS + tLPDT + 2 tESCCLK)) / (2 × 8 × tESCCLK), where
• tL = line time;
• tH1 = time of the HSA pulse for sync pulses mode (Figure 221) or time to send the HSS
packet, including EoTp (Figure 222);
• tHS->LP = time to enter the Low-Power mode;
• tLP->HS = time to leave the Low-Power mode;
• tLPDT = D-PHY timing related with Escape mode Entry, LPDT Command, and Escape
Exit. According to the D-PHY specification, this value is always 11 bits in LP (or 22 TX
escape clock cycles);
• tESCCLK = escape clock period as programmed in the TXECKDIV field of the DSI_CCR
register;
• tESCCLK = delay imposed by the DSI Host implementation.
In the above equation, division by eight is done to convert the available time to bytes.
Division by two is done because one bit is transmitted every two escape clock cycles. The
Largest Packet Size (LPSIZE) field can be compared directly with the size of the command
to be transmitted to determine if there is enough time to transmit the command. The
maximum size of a command that can be transmitted in Low-Power mode is limited to 255
bytes by this field. You must program this register to a value greater than or equal to 4 bytes
for the transmission of the DCTRL commands, such as shutdown and color in Low-Power
mode.
Consider an example of a frame with 12.4 μs per line and assume an escape clock
frequency of 20 MHz and a lane bit rate of 800 Mbits. In this case, it is possible to send 124
bits in escape mode (that is, 124 bit = 12.4 μs * 20 MHz / 2). Still, you need to take into
consideration the D-PHY protocol and PHY timings.
The following assumptions are made:
• lane byte clock period is 10 ns (800 Mbits per Lane);
• escape clock period is 50 ns (DSI_CCR.TXECKDIV = 5);
• video is transmitted in Non-Burst mode with sync pulses bounded by HSS and HSE
packets;
• DSI is configured for two lanes;
• D-PHY takes 180 ns to transit from Low-Power to High-Speed mode
(DSI_DLTCR.LS2HS_TIME = 18);
• D-PHY takes 200 ns to transit from High-Speed to Low-Power mode
(DSI_DLTCR.HS2LP_TIME = 20);
• tHSA = 420 ns.

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In this example, a 13-byte command can be transmitted as follows:

LPSIZE = (12.4 μs - (420 ns + 180 ns +200 ns + (22 × 50 ns + 2 × 50 ns))) / (2 × 8 × 50 ns)
= 13 bytes.

Calculating the Time to Transmit Commands in Low-Power mode in HFP

region
The VACT Largest Packet Size (VLPSIZE) field of the DSIHOST Low-Power mode
Configuration Register (DSI_LPMCR) indicates the time available (in bytes) to transmit a
command in Low-Power mode (based on the escape clock) in the Vertical Active (VACT)
region.
To calculate the value of VACT Largest Packet Size (VLPSIZE), consider the Video mode
being used. Figure 223 shows the timing intervals for Video mode in Non-Burst with sync
pulses, Figure 224 those for Video mode in Non-Burst with sync events, and Figure 225
refers to the Burst Video mode.

Figure 223. VLPSIZE for Non-Burst with sync pulses

tL
tHSA tHBP tHACT tHS -> LP tLPDT tLPDT tLPS -> HS

command
EscEntry

2 tESCCLK
EscExit
LPDT
HSS

HSE

HACT with
HSA HBP HSÆLP invact_lpcmd_time LPÆHS
Blanking Non-Burst

MSv35872V1

Figure 224. VLPSIZE for Non-Burst with sync events

tL
tHSA tHBP tHACT tHS -> LP tLPDT tLPDT tLPS -> HS
command
EscEntry

2 tESCCLK
EscExit
LPDT
HSS

HACT with
HSA HBP HSÆLP invact_lpcmd_time LPÆHS
Blanking Non-Burst

MSv35890V1

Figure 225. VLPSIZE for Burst mode

tL
tHSA tHBP tHACT tHS -> LP tLPDT tLPDT tLPS -> HS
command
EscEntry

2 tESCCLK
EscExit
LPDT
HSS

HSA HBP HACT Burst HSÆLP invact_lpcmd_time LPÆHS

MSv35873V1

This time is calculated as follows:

VLPSIZE = (tL - (tHSA + tHBP + tHACT + tHS->LP + tLP->HS + tLPDT + 2 tESCCLK)) /
(2 × 8 × tESCCLK)

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where
• tL = line time;
• tHSA = time of the HSA pulse (DSI_VHSACR.HSA);
• tHBP = time of Horizontal back porch (DSI_VHBPCR.HBP);
• tHACT = time of Video active. For Burst mode, the Video active is time compressed and
is calculated as tHACT = VPSIZE * Bytes_per_Pixel /Number_Lanes * tLane_byte_clk;
• tESCCLK = escape clock period as programmed in TXECKDIV field of the DSI_CCR
register.
The VLPSIZE field can be compared directly with the size of the command to be transmitted
to determine if there is time to transmit the command.
Consider an example of a frame with 16.4 μs per line and assume an escape clock
frequency of 20 MHz and a Lane bit rate of 800 Mbits/s. In this case, it is possible to send
420 bits in escape mode (that is, 164 bits = 16.4 μs * 20 MHz / 2). Still, since it is the Vertical
Active region of the frame, take into consideration the HSA, HBP, and HACT timings apart
from the D-PHY protocol and PHY timings. The following assumptions are made:
• number of active lanes is 4;
• Lane byte clock period (lanebyteclkperiod) is 10 ns (800 Mbits per Lane);
• escape clock period is 50 ns (DSI_CCR.TXECKDIV = 5);
• D-PHY takes 180 ns to pass from Low-Power to High-Speed mode
(DSI_DLTCR.LP2HS_TIME = 18);
• D-PHY takes 200 ns to pass from High-Speed to Low-Power mode
(DSI_DLTCR.HS2LP_TIME = 20);
• tHSA = 420 ns;
• tHBP = 800 ns;
• tHACT = 12800 ns to send 1280 pixel at 24 bpp;
• video is transmitted in Non-Burst mode;
• DSI Host is configured for four lanes.
In this example, consider that you send video in Non-Burst mode. The VLPSIZE is
calculated as follows:
VLPSIZE = (16.4 µs -(420 ns + 800 ns + 12.8 µs + 180 ns +200 ns +
(22 × 50 ns + 2 × 50 ns)) / (2 × 8 × 50 ns) = 1 byte
Only one byte can be transmitted in this period. A short packet (for example, generic short
write) requires a minimum of four bytes. Therefore, in this example, commands are not sent
in the VACT region.
If Burst mode is enabled, more time is available to transmit the commands in the VACT
region, because HACT is time compressed.
VLPSIZE = (16.4 µs - (420 ns + 800 ns + (1280 × 3 / 4 × 10 ns) + 180 ns + 200 ns +
(22 × 50 ns + 2 × 50 ns) / (2 × 8 × 50 ns) = 5 bytes
For Burst mode, the VLPSIZE is 5 bytes and then a 4-byte short packet can be sent.

Transmission of commands in different periods

The LPSIZE and VLPSIZE fields allow a simple comparison to determine if a command can
be transmitted in any of the BLLP periods.

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Figure 226 illustrates the meaning of VLPSIZE and LPSIZE, matching them with the shaded
areas and the VACT region.

Figure 226. Location of LPSIZE and VLPSIZE in the image area

VSS
VSA and
or BLLP
VBP lines
HSS

BLLP in
HSS+HBP RGB burst HFP VACT lines
mode

HSS BLLP VFP lines

DSI_LPMCR.LPSIZE

DSI_LPMCR.VLPSIZE
MSv35874V1

30.9.3 Transmission of commands in High-speed

If the LPCE bit of the DSI_VMCR register is 0, the commands are sent in High-Speed in
Video mode. In this case, the DSI Host automatically determines the area where each
command can be sent and no programming or calculation is required.

30.9.4 Read command transmission

The MRD_TIME field of the DSI_DLTCR register configures the maximum amount of time
required to perform a read command in lane byte clock cycles, it is calculated as:
MRD_TIME = Time to transmit the read command in Low-Power mode + Time to enter and
leave Low-Power mode + Time to return the read data packet from the peripheral device.
The time to return the read data packet from the peripheral depends on the number of bytes
read and the escape clock frequency of the peripheral, not the escape clock of the host. The
MRD_TIME field is used in both High-Speed and Low-Power mode to determine if there is
time to complete a read command in a BLLP period.
In High-Speed mode (LPCE = 0), MRD_TIME is calculated as follows:
MRD_TIME = (tHS->LP + tLP->HS + tread + 2 x tBTA) / lanebyteclkperiod
In Low-Power mode (LPCE = 1), MRD_TIME is calculated as follows:

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MRD_TIME = (tHS->LP + tLP->HS + tLPDT + tlprd + tread + 2 x tBTA) / lanebyteclkperiod, where:

• tHS->LP = Time to enter the Low-Power mode;
• tLP->HS = Time to leave the Low-Power mode;
• tLPDT = D-PHY timing related to Escape mode entry, LPDT command, and Escape
mode exit (according to the D-PHY specification, this value is always 11 bits in LP, or
22 TX escape clock cycles);
• tlprd = Read command time in Low-Power mode (64 * TX esc clock);
• tread = Time to return the read data packet from the peripheral;
• tBTA = time to perform a bus turnaround (D-PHY dependent).
It is recommended to keep the maximum number of bytes read from the peripheral to a
minimum to have sufficient time available to issue the read commands in a line time. Ensure
that MRD_TIME x Lane byte clock period is less than LPSIZE x 16 x escape clock period of
the host, otherwise, the read commands are dispatched on the last line of a frame. If it is
necessary to read a large number of parameters (> 16), increase the MRD_TIME while the
read command is being executed. When the read has completed, decrease the MRD_TIME
to a lower value.
If a read command is issued on the last line of a frame, the LTDC interface is halted and
stays halted until the read command is in progress. The video transmission should be
stopped during this period.

30.9.5 Clock lane in Low-power mode

To reduce the power consumption of the D-PHY, the DSI Host, when not transmitting in the
High-Speed mode, allows the clock lane to enter into the Low-power mode. The controller
automatically handles the transition of the clock lane from HS (Clock lane active sending
clock) to LP state without direct intervention by the software. This feature can be enabled by
configuring the DPCC and the ACR bits of the DSI_CLCR register.
In the Command mode, the DSI Host can place the clock lane in the Low-Power mode when
it does not have any HS packets to transmit.
In the Video mode (LTDC interface), the DSI Host controller uses its internal video and PHY
timing configurations to determine if there is time available for the clock line to enter the
Low-Power mode and not compromise the video data transmission of pixel data and sync
events.
Along with a correct configuration of the Video mode (see Section 30.5: Functional
description: Video mode on LTDC interface), the DSI Host needs to know the time required
by the clock lane to go from High-Speed to Low-Power mode and viceversa. The values
required can be obtained from the D-PHY specification: program the DSI_CLTCR register
with the following values:
• HS2LP_TIME = Time from HS to LP in clock lane / Byte clock period in HS
(lanebyteclk)
• LP2HS_TIME = Time from LP to HS in clock lane / Byte clock period in HS
(lanebyteclk)
Based on the programmed values, the DSI Host calculates if there is enough time for the
clock lane to enter the Low-Power mode during inactive regions of the video frame.

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The DSI Host decides the best approach to follow regarding power saving out of the three
possible scenarios:
• there is no enough time to go to the Low-Power mode. Therefore, blanking period is
added as shown in Figure 227;
• there is enough time for the data lanes to go to the Low-Power mode but not enough
time for the clock lane to enter the Low-Power mode, see Figure 228.
• there is enough time for both data lanes and clock lane to go to the Low-Power mode,
as in Figure 229.

Figure 227. Clock lane and data lanes in HS

Figure 228. Clock lane in HS and data lanes in LP

Figure 229. Clock lane and data lanes in LP

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30.10 Functional description: virtual channels

The DSI Host supports choosing the Virtual Channel (VC) for use for each interface. Using
multiple Virtual Channels, the system can address multiples displays at the same time,
when each display has a different Virtual Channel identifier.
When the LTDC interface is configured for a particular Virtual Channel, it is possible to use
the APB slave generic interface to issue the commands while the video stream is being
transmitted. With this, it is possible to send the commands through the ongoing video
stream, addressing different virtual channels and thus enable the interface with multiple
displays. During the Video mode, the video stream transmission has the maximum priority.
Therefore, the transmission of sideband packets such as the ones from the Generic
interface are only transported when there is time available within the video stream
transmission. The DSI Host identifies the available time periods and uses them to transport
the Generic interface packets. Figure 230 illustrates where the DSI Host inserts the packets
from the APB Generic interface within the video stream transmitted by the LTDC interface.

Figure 230. Command transmission by the generic interface

It is also possible to address the multiple displays with only the Generic interface using
different Virtual Channels. Because the Generic interface is not restricted to any particular
Virtual Channel through configuration, it is possible to issue the packets with different Virtual
Channels. This enables the interface to time multiplex the packets to be provided to the
displays with different Virtual Channels.
You can use the following configuration registers to select the Virtual Channel ID associated
with transmissions over the LTDC and APB slave generic interfaces:
• DSI_LVCID.VCID field configures the Virtual Channel ID that is indexed to the Video
mode packets using the LTDC interface.
• DSI_GHCR register configures the Packet Header (which includes the Virtual Channel
ID to be used) for transmissions using APB slave generic interface.
• DSI_GVIDR.VCID field configures the Virtual Channel ID of the read responses to
store and return to the Generic interface.

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30.11 Functional description: video mode pattern generator

The Video mode pattern generator allows the transmission of horizontal/vertical color bar
and D-PHY BER testing pattern without any stimuli.
The frame requirements must be defined in video registers that are listed in Table 203.

Table 203. Frame requirement configuration registers

Register Name Description

DSI Host Video mode Configuration Register Video mode configuration

DSI Host Video Packet Configuration Register Video packet size
DSI Host Video Chunks Configuration Register Number of chunks
DSI Host Video Null Packet Configuration Register Null packet size
DSI Host Video HSA Configuration Register Horizontal sync active time
DSI Host Video HBP Configuration Register Horizontal back porch time
DSI Host Video Line Configuration Register Line time
DSI Host Video VSA Configuration Register Vertical sync active period
DSI Host Video VBP Configuration Register Vertical back porch period
DSI Host Video VFP Configuration Register Vertical front porch period
DSI Host Video VA Configuration Register Vertical resolution

30.11.1 Color bar pattern

The color bar pattern comprises eight bars for white, yellow, cyan, green, magenta, red,
blue, and black colors.
Each color width is calculated by dividing the line pixel size (vertical pattern) or the number
of lines (horizontal pattern) by eight. In the vertical color bar mode (Figure 231), each single
color bar has a width of the number of pixels in a line divided by eight. In case the number of
pixels in a line is not divisible by eight, the last color (black) contains the remaining.
In the horizontal color bar mode (Figure 232), each color line has a color width of the
number of lines in a frame divided by eight. In case the number of lines in a frame is not
divisible by eight, the last color (black) contains the remaining lines.

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Figure 231. Vertical color bar mode

Figure 232. Horizontal color bar mode

30.11.2 Color coding

Table 204 shows the RGB components used.

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Table 204. RGB components

White Yellow Cyan Green Magenta Red Blue Black

R High High Low Low High High Low Low

G High High High High Low Low Low Low

B High Low High Low High Low High Low

30.11.3 BER testing pattern

The BER testing pattern simplifies conformance testing. This pattern tests the RX D-PHY
capability to receive the data correctly. The following data patterns are required:
• X bytes of 0xAA (high-frequency pattern, inverted);
• X bytes of 0x33 (mid-frequency pattern);
• X bytes of 0xF0 (low-frequency pattern, inverted);
• X bytes of 0x7F (lone 0 pattern);
• X bytes of 0x55 (high-frequency pattern);
• X bytes of 0xCC (mid-frequency pattern, inverted);
• X bytes of 0x0F (low-frequency pattern);
• Y bytes of 0x80 (lone 1 pattern).
In most cases, Y is equal to X. However, depending on line length and the color coding
used, Y may be different from X. With RGB888 color coding and horizontal resolution in
multiples of eight, the pattern shown in Figure 233 appears on the DSI display.

Figure 233. RGB888 BER testing pattern

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30.11.4 Video mode pattern generator resolution

Depending on the orientation, BER mode, and color coding, the smallest resolutions
accepted by the Video mode pattern generator are:
• BER mode: 8x8;
• horizontal color bar mode: 8x8;
• vertical color bar mode: 8x8.

Vertical pattern
The width of each color bar is determined by the division of horizontal resolution (pixels) for
eight test pattern colors. If the horizontal resolution is not divisible by eight, the last color
(black) is extended to fill the resolution.
In the example in Figure 234, the horizontal resolution is 103.

Figure 234. Vertical pattern (103x15)

Horizontal pattern
The width of each color bar is determined by the division of the number of vertical resolution
(lines) for eight test pattern colors. If the vertical resolution is not divisible by eight, the last
color (black) will be extended to fill the resolution, as shown in Figure 235.

Figure 235. Horizontal pattern (103x15)

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30.12 Functional description: D-PHY management

The embedded MIPI® D-PHY is control directly by the DSI Host and is configured through
the DSI Wrapper.
A dedicated PLL and a dedicated 1.2 V regulator are also embedded to supply the clock
and the power supply to the DSI Host and D-PHY.

30.12.1 D-PHY configuration

The D-PHY configuration is carried out through the DSI Wrapper thanks to the DSI_WPCRx
registers.

Timing definition
The MIPI® D-PHY manages all the communication timing with dedicated timers. As all the
timings are specified in nanoseconds (ns), it’s mandatory to configure the Unit Interval Field
to ensure the good duration of all the timings.
Unit Interval is configure through the DSI_WPCR0.UIX4 field. This value defines the bit
period in High-Speed mode in unit of 0.25ns. If this period is not a multiple of 0.25 ns, the
value driven should be rounded down.
As an example, for a 300 Mbit/s link, the unit interval is 3.33 ns, so UIX4 shall be 13.33. In
this case a value of 13 (0x0D) should be written.

Slew-rate and delay tuning on pins

To fine tune DSI communication, slew-rates and delays be fine tuned:
• slew-rate in High-Speed transmission on data lane and clock lane
• slew-rate in Low-Power transmission on data lane and clock lane
• transmission delay in High-Speed transmission on data land and clock lane

Table 205. Slew-rate and delay tuning

Function Lane(s) Value field in DSI_WPCR1

Clock lane HSTXSRCCL

Slew-rate in High-Speed transmission
Data lanes HSTXSRCDL
Clock lanes LPSRCCL
Slew-rate in Low-Power transmission
Data lanes LPSRCDL
Clock lane HSTXDCL
High-speed transmission delay
Data lanes HSTXDDL

The default values for all this parameters is 2’h00. All this values can be programmed only
when the DSI is stopped (DSI_WCR.DSIEN = 0 and CR.EN = 0).

Low-power reception filter tuning

The cut-off frequency of the low-pass on Low-Power receiver can be fine tuned through the
LPRXFT field of the DSI_WPCR1 register. The default values is 2’h00 and it can be
programmed only when the DSI is stopped (CR.DSIEN = 0 and CR.EN = 0).

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Special Sdd Control

An additional current path can be activated on both clock lane and data lane to meet the
SddTX parameter defined in the MIPI® D-PHY Specification.
This activation is done setting the SDDC bit of the DSI_WPCR1 register.

Custom lane configuration

To ease DSI integration, lane pins can be swapped and/or High-Speed signal can be
inverted on a lane as described in Table 206.

Table 206. Custom lane configuration

Function Lane Enable bit in DSI_WPCR0

Clock lane SWCL

Swap lane pins Data lane 0 SWDL0
Data lane 1 SWDL1
Clock lane HSICL
Invert High-Speed signal on lane Data lane 0 HSIDL0
Data lane 1 HSIDL1

Custom timing configuration

Some of the MIPI® D-PHY timing can be tuned for specific purpose as described in
Table 207.

Table 207. Custom timing parameters

Enable bit in Configuration Default Default
MIPI® timing Field
DSI_WPCR0 register value duration

tCLK-POST TCLKPOSTEN DSI_WPCR4 TCLKPOST 200 100 ns + 120*UI

tLPX (Clock lane) TLPXCEN TLPXC 100 50 ns
tHS_EXIT THSEXITEN THSEXIT 200 100 ns + 40*UI
DSI_WPCR3
tLPX (Data lane) TLPXDEN TLPXD 100 50 ns
tHS-ZERO THSZEROEN THSZERO 175 175 ns + 8*UI
tHS-TRAIL THSTRAIL THSTRAIL 140 70 ns + 8*UI
tHS-PREPARE THSPREPEN THSPREP 126 63 ns + 12*UI
DSI_WPCR2
tCLK-ZERO TCLKZEROEN TCLKZERO 195 390 ns
tCLK-PREPARE TCLKPREPEN TCLKPREP 120 60 ns + 20*UI

All this values can be programmed only when the DSI is stopped (CR.DSIEN = 0 and
CR.EN = 0).

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30.12.2 Special D-PHY operations

The DSI Wrapper have some control bit to force the D-PHY in some particular state and/or
behavior.

Forcing lane state

It’s possible to force the data lane and/or the clock lane in TX Stop mode through the bits
FTXSMDL and FTXSMCL of the DSI_WPCR1 register.
Setting this bits causes the respective lane module to immediately jump in transmit control
mode and to begin transmitting a stop state (LP-11).
This feature can be used to go back in TX ode after a wrong BTA sequence.

Forcing Low-Power receiver in Low-Power mode

The FLPRXLPM bit of the DSI_WPCR1 register enables the Low-Power mode of the low
power receiver (LPRX). When set, the LPRX operates in Low-Power mode all the time.
When not set, the LPRX operates in Low-Power mode during ULPS only.

Disabling turn of data lane

When set, the TDDL bit of the DSI_WPCR0 register forces the data lane to remain in
reception mode even if a Bus Turn Around request (BTA) is received from the other side.

30.12.3 Special Low-power D-PHY functions

The embedded D-PHY offers two specific features to optimize consumption.

Pull-down on lanes
The D-PHY embedded pull-down on each lane to prevent from floating states when the
lanes are unused.
When set, the PDEN bit of the DSI_WPCR0 register enables the pull-down on the lanes.

Disabling contention detection on data lanes

The contention detector on the data lane can be turned off to lower the overall D-PHY
consumption.
When set, the CDOFFDL bit of the DSI_WPCR0 register disables the contention detection
on data lanes.
This can be used in forward Escape mode to reduce the static power consumption.

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30.12.4 DSI PLL control

The dedicated DSI PLL is controlled through the DSI Wrapper, as shown in Figure 236
(analog blocks and signals in pink, digital signals in black, digital blocks in light blue).

Figure 236. PLL block diagram

avddpll1v2 agndpll1v2 dvddpll1v2 dgndpll1v2

CLKIN Input Frequency Divider INFIN Lock

3 3 bit divider (IDF) LOCKP
IDF<2:0> FBCLK Detect
ENABLE
INFIN
INFOUT CPUMP
Buffer PFD VCO
REFOUT and LF
LS 2 ODF<1:0>

Loop Frequency Divider

ODF
DIV 2 PHI
1,2,4,8
FBCLK 7 bit Divider
(LDF)

7
NDIV<6:0>
MSv35895V1

The PLL output frequency is configured through the DSI_WRPCR register fields. The VCO
frequency and the PLL output frequency are calculated as follows:
FVCO = (CLKIN / IDF) * 2 * NDIV,
PHI = FVCO / (2 *ODF)
where:
• CLKIN is in the range of 4 to 100 MHz;
• DSI_WRPCR.NDIV is in the range of 10 to 125;
• DSI_WRPCR.IDF is in the range of 1 to 7;
• INFIN is in the range of 4 to 25 MHz;
• FVCO is in the range of 500 MHz to 1 GHz;
• DSI_WRPCR.ODF can be 1, 2, 4 or 8;
• PHI is in the range of 31.25 to 500 MHz.
The PLL is enabled setting the PLLEN bit in the DSI_WRPCR register.
Once the PLL is locked, the PLLLIF bit is set in the DSI_WISR. If the PLLLIE bit is set in the
DSI_WIER, an interrupt is generated.
The PLL status (lock or unlock) can be monitored with the PLLLS flag in the DSI_WISR
register.

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If the PLL gets unlocked, the PLLUIF bit of the DSI_WISR is set. If the PLLUIE bit of the
DSI_WIER register is set, an interrupt is generated.
The DSI PLL setting can be changed only when the PLL is disabled.

30.12.5 Regulator control

The DSI regulator providing the 1.2 V is controlled through the DSI Wrapper.
The regulator is enabled setting the REGEN bit of the DSI_WRPCR register.
Once the regulator is ready, the RRIF bit of the DSI_WISR register is set. If the RRIE bit of
the DSI_WIER register is set, an interrupt is generated.
The regulator status (ready or not) can be monitored with the RRS flag in the DSI_WISR
register.
Note that the D-PHY has no separated Power ON control bit. The power ON/OFF of the D-
PHY is done directly enabling the 1.2 V regulator.
When the 1.2 V regulator is disabled, the 3.3 V part of the D-PHY is automatically powered
OFF.

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30.13 Functional description: interrupts and errors

The interrupts can be generated either by the DSI Host or by the DSI Wrapper.
All the interrupts are merged in one interrupt lane going to the Interrupt Controller.

30.13.1 DSI wrapper interrupts

An interrupt can be produced on the following events:
• tearing effect event;
• end of refresh;
• PLL locked;
• PLL unlocked;
• regulator ready.
Separate interrupt enable bits are available for flexibility.

Table 208. DSI wrapper interrupt requests

Interrupt event Event flag in DSI_WISR Enable control bit in DSI_WIER

Tearing effect TEIF TEIE

End of refresh ERIF ERIE
PLL locked PLLLIF PLLLIE
PLL unlocked PLLUIF PLLUIE
Regulator ready RRIF RRIE

30.13.2 DSI host interrupts and errors

The DSI_ISR0 and DSI_ISR1 registers are associated with error condition reporting. These
registers can trigger an interrupt to inform the system about the occurrence of errors.
The DSI Host has one interrupt line that is set high when an error occurs in either the
DSI_ISR0 or the DSI_ISR1 register.
The triggering of the interrupt can be masked by programming the mask registers DSI_IER0
and DSI_IER1. By default all errors are masked. When any bit of these registers is set to 1,
it enables the interrupt for a specific error. The error bit is always set in the respective
DSI_ISR register. The DSI_ISR0 and DSI_ISR1 registers are always cleared after a read
operation. The interrupt line is cleared if all registers that caused the interrupt are read.
The interrupt force registers (DSI_FIR0 and DSI_FIR1) are used for test purposes, and they
allow triggering the interrupt events individually without the need to activate the conditions
that trigger the interrupt sources; this is because it is extremely complex to generate the
stimuli for that purpose. This feature also facilitates the development and testing of the
software associated with the interrupt events. Setting any bit of these registers to 1 triggers
the corresponding interrupt.

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The light yellow boxes in Figure 237 illustrate the location of some of the errors.

Figure 237. Error sources

DPI_PAYLOAD_WR_ERR
Packet Handler

LTDC
ctrl FIFO
LTDC
LTDC Video Mode FSM
Interface
LTDC
pixel FIFO

Command Mode FSM

GEN_PAYLOAD_SEND_ERR

GEN_PAYLOAD_RECV_ERR
GEN_COMMAND_WR_ERR
GEN Comm
FIFOs

GEN GEN Pld

APB
Interface Send FIFOs

GEN Pld
RCV FIFOs

GEN_PAYLOAD_WR_ERR
ECC_SINGLE_ERR
Packet Analyzer
GEN Pld ECC_MULTI_ERR

GEN_PAYLOAD_RD_ERR
Send FIFOs
VC ECC/CRC CRC_ERR
GEN Pld Router Analysis
RCV FIFOs PKT_SIZE_ERR

EOTP_ERR

ACK_WITH_ERR
MSv35896V2

Table 209 explains the reasons that set off these interrupts and also explains how to recover
from these interrupts.

Table 209. Error causes and recovery

DSI host interrupt Recommended method
Bit Name Cause of the error
& Status register of handling the error

The D-PHY reports the LP1 Recover the D-PHY from contention.
contention error. Reset the DSI Host and transmit the
0 20 PE4 The D-PHY host detects the packets again. If this error is recurrent,
contention while trying to drive carefully analyze the connectivity between
the line high. the Host and the Device.
D-PHY reports the LP0 Recover the D-PHY from contention.
contention error. Reset the DSI Host and transmit the
0 19 PE3 The D-PHY Host detects the packets again. If this error is recurrent,
contention while trying to drive carefully analyze the connectivity between
the line low. the Host and the Device.

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Table 209. Error causes and recovery (continued)

DSI host interrupt Recommended method
Bit Name Cause of the error
& Status register of handling the error

Device does not behave as expected,

The D-PHY reports the False communication with the Device is not
Control Error. properly established. This is an
0 18 PE2 The D-PHY detects an incorrect unrecoverable error.
line state sequence in lane 0 Reset the DSI Host and the D-PHY. If this
lines. error is recurrent, analyze the behavior of
the Device.
The D-PHY reports the LPDT The data reception is not reliable. The D-
Error. PHY recovers but the received data from
0 17 PE1 The D-PHY detects that the the Device might not be reliable.
LDPT did not match a multiple It is recommended to reset the DSI Host
of 8 bits. and repeat the RX transmission.
The D-PHY reports the Escape
The D-PHY Host does not recognize the
Entry Error.
Escape Entry Code. The Transmission is
0 16 PE0 The D-PHY does not recognize
ignored. The D-PHY Host recovers but the
the received Escape Entry
system should repeat the RX reception.
Code.
Refer to the display documentation. When
This error is directly retrieved
this error is active, the Device should have
from Acknowledge with Error
another read-back command that reports
0 15 AE15 packet.
additional information about this error.
The Device detected a protocol
Read the additional information and take
violation in the reception.
appropriate actions.
The Acknowledge with Error
Refer to the Device documentation
packet contains this error.
0 14 AE14 regarding possible reasons for this error
The Device chooses to use this
and take appropriate actions.
bit for error report.
Possible reason for this is multiple errors
present in the packet header (more than 2),
The Acknowledge with Error so the error detection fails and the Device
packet contains this error. does not discard the packet. In this case,
0 13 AE13 The Device reports that the the packet header is corrupt and can cause
transmission length does not decoding mismatches.
match the packet length. Transmit the packets again. If this error is
recurrent, carefully analyze the connectivity
between the Host and the Device.
Possible reason for this is multiple errors
present in the packet header (more than 2),
The Acknowledge with Error so the error detection fails and the Device
packet contains this error. does not discard the packet. In this case,
0 12 AE12 The Device does not recognize the packet header is corrupt and can cause
the VC ID in at least one of the decoding mismatches.
received packets. Transmit the packets again. If this error is
recurrent, carefully analyze the connectivity
between the Host and the Device.

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Table 209. Error causes and recovery (continued)

DSI host interrupt Recommended method
Bit Name Cause of the error
& Status register of handling the error

The Acknowledge with Error

Check the Device capabilities. It is possible
packet contains this error.
that there are some packets not supported
0 11 AE11 The Device does not recognize
by the Device.
the data type of at least one of
Repeat the transmission.
the received packets.
Some of the long packets, transmitted after
the last Acknowledge request, might
The Acknowledge with Error
contain the CRC errors in the payload.
packet contains this error.
If the payload content is critical, transmit
0 10 AE10 The Device detects the CRC
the packets again.
errors in at least one of the
If this error is recurrent, carefully analyze
received packets.
the connectivity between the Host and the
Device.
The Device does not interpret the packets
transmitted after the last Acknowledge
The Acknowledge with Error
request.
packet contains this error.
If the packets are critical, transmit the
0 9 AE9 The Device detects multi-bit
packets again.
ECC errors in at least one of
If this error is recurrent, carefully analyze
the received packets.
the connectivity between the Host and the
Device.
The Acknowledge with Error
packet contains this error. No action is required.
The Device detects and The Device acknowledges the packet.
0 8 AE8
corrects the 1 bit ECC error in If this error is recurrent, analyze the signal
at least one of the received integrity or the noise conditions of the link.
packets.
This error might corrupt the Low-Power
data reception and transmission.
The Acknowledge with Error Ignore the packets and transmit them
packet contains this error. again. The Device recovers automatically.
0 7 AE7 The Device detects the Line If this error is recurrent, check the Device
Contention through LP0/LP1 capabilities and the connectivity between
detection. the Host and Device.
Refer to.section 7.2.1 of the DSI
Specification 1.1.
The device detects one of the following:
– The LP-10 (LP request) is not followed
by the remainder of a valid escape or
turnaround sequence.
The Acknowledge with Error
packet contains this error. – The LP-01 (HS request) is not followed
0 6 AE6 by a bridge state (LP-00).
The Device detects the False
Control Error. The D-PHY communications are corrupted.
This error is unrecoverable.
Reset the DSI Host and the D-PHY.
Refer to the section 7.1.6 of the DSI
Specification 1.1.

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Table 209. Error causes and recovery (continued)

DSI host interrupt Recommended method
Bit Name Cause of the error
& Status register of handling the error

It is possible that the Host and Device

timeout counters are not correctly
configured. The Device HS_TX timeout
should be shorter than the Host HS_RX
timeout. Host LP_RX timeout should be
The Acknowledge with Error
longer than the Device LP_TX timeout.
packet contains this error.
Check and confirm that the Host
0 5 AE5 The display timeout counters
configuration is consistent with the Device
for a HS reception and LP
specifications. This error is automatically
transmission expire.
recovered, although there is no guarantee
that all the packets in the transmission or
reception are complete. For additional
information about this error, see section
7.2.2 of the DSI Specification 1.1.
The Acknowledge with Error There is no guarantee that the Device
packet contains this error. properly receives the packets.
0 4 AE4 The Device reports that the Transmit the packets again. For additional
LPDT is not aligned in an 8-bit information about this error, see section
boundary 7.1.5 of the DSI Specification.
The Device does not recognize the Escape
The Acknowledge with Error
mode Entry code.
packet contains this error.
Check the Device capability. For additional
0 3 AE3 The Device does not recognize
information about this error, see section
the Escape mode Entry
7.1.4 of the DSI Specification.
command.
Repeat the transmission to the Device.
The Acknowledge with Error There is no guarantee that the Device
packet contains this error. properly received the packets. Re-
The Device detects the HS transmission should be performed.
0 2 AE2
transmission did not end in an Transmit the packets again. For additional
8-bit boundary when the EoT information about this error, see section
seq