LCTI–SS: Low-Clock-Tree-Impact Scan Segmentation

LCTI–SS:
Low-Clock-Tree-Impact
Scan Segmentation for
Avoiding Shift Timing
Failures in Scan Testing
Yuta Yamato Kohei Miyase and Seiji Kajihara
Nara Institute of Science and Technology Kyushu Institute of Technology

Xiaoqing Wen Laung-Terng Wang

Kyushu Institute of Technology SynTest Technologies, Inc.

Michael A. Kochte
University of Stuttgart

IR-drop-induced delay increase on a

Editor’s notes: portion of the clock tree. This paper
In this contribution, the authors describe a method for ensuring that false proposes a novel layout-aware scan
failures do not occur when shifting scan chains for testing. Their approach segmentation design scheme called
identifies an optimal combination of scan segments for simultaneous clock- low-clock-tree-impact scan segmen-
ing that reduces the switching activity near clock trees while maintaining the tation (LCTI–SS) for avoiding shift tim-
average power reduction for conventional scan segmentation. Experiments ing failures. The proposed scheme
using various benchmark circuits demonstrate the overall utility of their searches for an optimal combination
approach. of scan segments for simultaneous
VShawn Blanton, Carnegie Mellon University clocking so as to reduce the switching
activity in the proximities of clock trees
while maintaining the average power
h MOVING FURTHER INTO the deep-submicrometer reduction effect of the conventional scan segmen-
(DSM) era, the problem of test-induced yield loss tation. Experimental results on benchmark circuits
due to high power consumption has increasingly have demonstrated the advantage of the LCTI–SS
worsened. One of the major causes of this problem scheme.
is shift timing failure, which arises from excessive Continuous shrinking in process feature sizes has
switching activity in the proximities of clock paths led in an era of high-speed and low-supply-voltage
that tends to introduce severe clock skew due to VLSI designs. At the same time, the DSM process
technology has posed serious design and test chal-
lenges. One major issue is test-induced yield loss
Digital Object Identifier 10.1109/MDT.2012.2221152 due to excessive power consumption in scan testing.
Date of publication: 02 October 2013; date of current version: In recent years, at-speed scan testing has become
07 November 2013. crucial for DSM VLSI circuits in guaranteeing

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 sufficient circuit quality levels. This is because
timing-related defects have become dominant in
such circuits [1].
In practice, a launch-on-capture (LOC) clocking
scheme has been widely used in scan testing be-
cause its scan enable (SE) signal has lower physical
design complexity than other clocking schemes. A
basic LOC clocking scheme is shown in Figure 1. In
the shift mode (SE ¼ 1), scan chains are operated as
shift registers with multiple clock pulses (S1 to SL )
for loading a new test vector and unloading the test
response to the previous test vector. Then, in the
capture mode (SE ¼ 0), a first capture pulse C1 is
applied for launching transitions and, subsequently,
a second capture pulse C2 is applied at system clock
cycle T for capturing the response to the launched
transitions. After that, SE is set to 1 again for un-
loading the test response and loading the next test
vector.
Figure 1. Test power safety issues.

Test power safety in at-speed scan testing

At-speed scan testing is indispensable for DSM the main cause, the mechanism of timing failures
VLSI circuits. However, despite its importance, scan differs in different scan test modes. In the shift mode,
testing is facing a serious challenge of test-induced IR-drop-induced delay increase along clock paths
yield loss due to excessive power consumption [2]. may lead to severe clock skew, and shift timing
Test power caused by switching activity which failures may occur due to hold time violations. In
attributes to power dissipation in scan testing has contrast, in the capture mode, excessive launch
known to be much higher than functional power switching activity (LSA), as caused by C1 in Figure 1,
because of the need to test in the shortest time pos- results in IR-drop-induced delay increase along sen-
sible. High test power may cause various problems, sitized paths. Capture timing failures may thus occur
threatening test power safety. Figure 1 illustrates the in the capture cycle due to setup time violations.
test power safety issues in at-speed scan testing. Therefore, test power safetyVthe combination of
There are two types of issues in scan testing: both shift safety and launch safetyVmust be gua-
thermal overheating and timing failures. The ther- ranteed for at-speed scan testing to avoid chip and
mal issue is closely related to average power since it package damage, reliability and performance deg-
is the accumulative impact of excessive shift switch- radation, and undue yield loss. The thermal issue
ing activity (SSA) as most of the test application time has been addressed in the past years and various
is spent in the shift mode. This may result in over- techniques have been proposed to reduce average
heating of the die or chip packages, leading to yield SSA. Typical techniques include scan clock gating
loss or performance degradation. On the other [3], scan chain disabling [4], toggle suppression
hand, timing failures can occur in both shift mode [5], scan cell ordering [6], and scan segmentation
and capture mode since they are caused by the in- [7]. For timing failures, effective techniques exist for
stantaneous impact of excessive switching activity at reducing LSA [9], [10], which are helpful in achiev-
individual clock cycles. Excessive switching activity ing launch safety. However, these techniques do not
causes large switching current flow through the target shift timing failures and, thus, cannot guaran-
power and ground network, resulting in the IR drop tee shift safety.
that reduces the switching speed of each affected This paper addresses this shift safety problem
gate. As a result, timing failures may occur due to IR- caused by excessive SSA around clock paths with
drop-induced delay increase, and thus yield loss a novel layout-aware scheme based on scan
occurs [2]. While IR-drop-induced delay increase is segmentation, called LCTI–SS. The basic idea is to

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 LCTI–SS: Low-Clock-Tree-Impact Scan Segmentation

optimize the combination of

scan segments for simultaneous
clocking since SSA depends on
which segments are simulta-
neously clocked. LCTI–SS deals
with the real cause of excessive-
SSA-induced yield loss by re-
ducing SSA in the proximities of
active clock paths while preserv-
ing the benefits of conventional
scan segmentation in reducing
average whole-circuit shift pow-
er without performance degra-
dation. A segment regrouping
algorithm is proposed to directly
reduce SSA in impact areas
(IAs) by optimally grouping
scan segments for simultaneous
clocking. LCTI–SS improves the
shift safety since the reduction
of instantaneous SSA is directly
focused on IAs to significantly
reduce IR-drop-induced shift
timing failures.

Background

Conventional scan
segmentation
The basic concept of scan
segmentation [7] is to split a
scan chain into multiple seg-
ments, and shift just one seg-
ment of the scan chain at a time
while keeping all other seg-
ments deactivated. Figure 2
shows an example of a scan
segmentation design for a cir-
cuit with three scan chains. The
original scan chains with length
L (Figure 2a) are split into three
shorter segments with length
L=3, resulting in a total of nine
segments S11 to S33 (Figure 2b).
Three gated clocks GCLK 1 ,
GCLK2 , and GCLK3 are con-
nected to all scan FFs in three
Figure 2. Conventional scan segmentation. (a) Basic scan architecture segment groups G1 ¼ fS11 ; S21 ;
with three scan chains. (b) Scan segmentation architecture. (c) Clock S31 g, G2 ¼ fS12 ; S22 ; S32 g, and
timing diagram for scan segmentation. G3 ¼ fS13 ; S23 ; S33 g, respectively.

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 The shift operation is conducted for G1, G2 , and G3 , Basics
one at a time. As shown in Figure 2c, gated clocks In conventional scan segmentation, once a scan
GCLK1 , GCLK2 , and GCLK3 are exclusively applied segment configuration is fixed, the same groups of
during a shift operation. The test response to a test segments are always simultaneously shifted at a
vector is captured by applying all gated clock signals time. However, there may be a better combination of
after a test vector has been shifted into all segments. segments for simultaneous clocking with low SSA in
Since the number of simultaneously switching FFs the proximities of clock paths. The LCTI–SS scheme
becomes smaller, global average SSA is effectively tries to find such a combination. Figure 3a shows the
reduced. Note that no modification is required on general flow of the proposed LCTI–SS scheme. It
functional paths, thus avoiding any performance consists of two major steps: IA identification ( 1)

degradation. In addition, test application time re- and segment regrouping ( 2 ), as described below.
mains the same as that of the standard scan archi- Given a circuit netlist N with standard full-scan
tecture. It has been reported in [7] that the average design, conventional scan segmentation (as illus-
shift power reduction ratio is approximately 50% for trated in Figure 2b) is first designed. The result is a
a two-segment configuration and 66% for a three- new netlist N 0 , for which place-and-route is con-
segment configuration. ducted to produce a layout design L and a clock-tree
design C. Based on these two types of information,
Shift timing failures IA identification ( 1 ) is conducted to identify nodes

Conventional scan segmentation can effectively (gates and FFs) whose transitions have significant
and predictably address the accumulative impact of impact on IR-drop-induced delay increase on clock
excessive SSA, thus solving the overheat problem paths. After that, segment regrouping ( 2 ) is con-

caused by high average SSA. However, it is unable to ducted to minimize the number of nodes in IAs
mitigate the instantaneous impact of excessive SSA. which may affect active clock paths. To illustrate the
As a result, IR-drop-induced delay increase may still LCTI–SS scheme, let us revisit the case shown in
occur along clock paths from a clock pin to scan Figure 2b. Here, the initial segment groups provided
FFs, which may cause clock skew and shift timing by conventional scan segmentation are G1 ¼ fS11 ;
failures and severely reduce shift safety and test S21 ; S31 g, G2 ¼ fS12 ; S22 ; S32 g, and G3 ¼ fS13 ; S23 ; S33 g.
yield. By applying the LCTI–SS scheme, scan segments are
Circuit level experiments show that even local IR regrouped, for example, into G10 ¼ fS13 ; S22 ; S31 g,
drop affecting only a single clock buffer may already G20 ¼ fS11 ; S21 ; S33 g, a n d G30 ¼ fS12 ; S23 ; S32 g, a s
cause an increase of the propagation delay of the shown in Figure 3a.
driven clock paths in the order of the designed
maximum clock skew. Reconfigurable scan segmentation architecture
In consequence, excessive SSA around clock Since clock trees are timing critical and have to
paths threatens shift safety by causing shift timing be perfectly balanced, it is objectionable to regroup
failures at scan FFs, resulting in undue yield loss. scan segments by modifying the clock trees after
With regard to scan segmentation, shift safety is not physical design and timing closure. This may lead to
guaranteed by reducing only global average SSA. clock-tree resynthesis, which in turn may change
There is a strong need for effectively reducing local other parts of the layout. As a result, the IAs may also
SSA around clock paths as well. change. To realize scan segment regrouping without
changing the layout, a programmable clock control
The LCTI–SS scheme is preferable [11]. Figure 3c shows an architecture of
This section describes LCTI–SS, for reducing a reconfigurable scan segmentation scheme with
the instantaneous SSA in the proximities of clock programmable clock control. It consists of clock
trees to reduce the risk of timing failures in scan control logic for scan chains, address registers, and
chains. Together with the intrinsic benefit of scan shadow registers. The inputs of the clock control
segmentation for reducing global average SSA to logic are CLK, SE, and the address representing
mitigate the overheat problem, the proposed which segment to activate. Each output is fed into
LCTI–SS significantly improves the overall shift the corresponding clock tree of a segment. At the
safety. beginning of scan testing, address data for the first

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 LCTI–SS: Low-Clock-Tree-Impact Scan Segmentation

segment group are loaded into shadow registers.

When all the control data are loaded, the load clock
of the address registers is applied and SE is set to 1
for scan shift. This selects the AND-gated clock paths
according to the mask in the address registers. Be-
cause of the one hot decoder, only the segments of
the first group are activated. Address data for the
next segment group are loaded into shadow regis-
ters while shifting. After shifting the first segment, the
load clock is applied again to switch the active seg-
ment group. This is repeated until shifting of the last
segment group is completed. Note that, while shift-
ing the last segment group, address data for the first
segment group are loaded into the shadow registers.
SE is then set to 0 for launching transitions and
capturing the response. In the capture mode, paths
from the original clock are selected to activate all
segments at a time. After that, SE is set to 1 again for
shifting out the response and shifting in the next test
vector.
This way, any grouping of scan segments can be
chosen for simultaneous clocking for each scan
chain without layout modification. This flexibility
requires a slight increase in test data volume.
For each scan chain with m segments, the addi-
tional control circuit needs m 2-to-1 MUXs, m AND
gates, one ðlog2 mÞ-to-m decoder, and 2dlog2 me re-
gisters. Then, n of these control circuits are needed
for n scan chains in a circuit. Let us assume the
number of segments is at most four, since average
power reduction effect diminishes beyond four
segments, as shown in [8]. Then, the overhead
per a scan chain is approximately 50 gates in two-
input NAND gate equivalent, when using the SAED
90-nm EDK digital standard cell library. This is suffi-
ciently small even for a circuit with a high number
of scan chains.

Impact area identification

To identify the nodes whose transitions have sig-
nificant impact on clock skew, the LCTI–SS scheme
uses circuit layout information, e.g., a design ex-
change format (DEF) file. The clock aggressors,
defined as the nodes (gates and FFs) placed near a
clock buffer and sharing power rails with the clock
buffer, are extracted from the layout using clock-tree
information. Then, the elements of IAs, i.e., the set
Figure 3. Concept of LCTI–SS. (a) General flow. of nodes which potentially causes transitions in the
(b) Example of segment regrouping. (c) Reconfigurable proximity of active clock paths, are computed based
scan segmentation architecture. on the following definitions. This information is

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 necessary in the subsequent segment regrouping
step.

Definition 1. Let CAðBÞ be a set of clock aggressors

of a clock buffer B, let P be a path consisting of all
clock buffers fB1 ; B2 ; . . . ; Bm g from a gated clock pin
to the clock input of a scan FF, and let S be a set of
all clock paths to all FFs in a scan segment fP1 ;
P2 ; . . . ; Pn g. A set of clock aggressors of a path P,
called the path aggressor set, denoted by PAðPÞ, and
a set of clock aggressors of a segment S, called the
segment aggressor set, denoted by SAðSÞ, are de-
fined as follows:
m
PAðPÞ ¼ [ ðCAðBi ÞÞ
i¼1

n
SAðSÞ ¼ [ ðPAðPi ÞÞ:
i¼1

An example is shown in Figure 4a, where two

scan FFs, FF1 and FF2, are assumed to form the scan
segment S11 . Here, PAðP1 Þ ¼ CAðB1 Þ [ CAðB2 Þ [
CAðB3 Þ and PAðP2 Þ ¼ CAðB1 Þ [ CAðB2 Þ [ CAðB4 Þ. As
a result, SAðS11 Þ ¼ PAðP1 Þ [ PAðP2 Þ.
Path aggressor sets and segment aggressor sets
can be statically identified based on the physical
locations of circuit nodes, thus, each segment is as-
signed a fixed set of clock aggressors. However, not
all clock aggressors in a segment aggressor set nec-
essarily affect the propagation delay of clock paths.
This is because only a part of the segments is sim-
ultaneously activated in scan segmentation. Even
though a clock aggressor belongs to a segment ag-
gressor set of the active segments, transitions may
only occur when connected from active segments.
Otherwise, the clock aggressor has no impact on IR-
drop-induced delay increase on the active clock Figure 4. Impact area identification. (a) Clock
path, and it is not necessary to take it into consid- aggressors. (b) Impact area.
eration any more. A clock aggressor impacting
active clock buffers, called the impact aggressor,
ments S1 ; S2 ; . . ., and Sn to be clocked simulta-
satisfies the following two conditions:
neously. The IA of G, denoted by IAðGÞ, is defined as

h Condition A: the node belongs to at least one n n

IAðGÞ ¼ [ ð SAðSi ÞÞ \ [ ðRAðSi ÞÞ:
segment aggressor set of active segments; i¼1 i¼1

h Condition B: the node is structurally reachable

Thus, the IA of G contains only impact aggressors
from at least one scan FF in active segments.
that may affect active clock paths, i.e., clock aggres-
sors satisfying both condition A and condition B. An
Definition 2. Let RAðSÞ be a set of clock aggressors example is shown in Figure 4b. Here, two scan
structurally reachable from all FFs in a segment S, segments S11 and S21 are assumed to belong to G1.
and let G be a segment group composed of seg- SAðS11 Þ ¼ fN1 ; N2 ; N3 ; N5 ; N7 ; N6 g, SAðS21 Þ ¼ fN4 ; N5 ;

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 LCTI–SS: Low-Clock-Tree-Impact Scan Segmentation

N6 ; N7 ; N8 ; N9 g, RAðS11 Þ ¼ fN1 ; N2 ; N3 ; N5 ; N7 g, and Theorem 1. For a scan segmentation design with

RAðS21 Þ ¼ fN3 ; N5 ; N6 ; N8 g. In this case, IAðG1 Þ ¼ m scan chains and n segments for each scan
ðSAðS11 Þ [ SAðS21 ÞÞ \ ðRAðS11 Þ [ RAðS21 ÞÞ ¼ fN1 ; N2 ; chain, the total number of segment group combi-
N3 ; N5 ; N6 ; N8 g. nations is ðn!Þm .
From above definitions, the IA of a segment
group with arbitrary combinations of scan segments Proof. For the first segment group, n segments can
can be derived. This information is used to estimate be selected from each of the m scan chains, which
the risk of shift timing failures. results in nm possible combinations. Then, repeating
this until the nth segment group results in ðn  1Þm
possible combinations for the second segment
Segment regrouping group, ðn  2Þm possible combinations for the third
Generally, the number of impact aggressors de- segment group, etc., and one combination for the
pends on the combination of segments to be simul- nth segment group. Therefore, the total number of
taneously clocked. The smaller is the number of segment group combinations is as follows:
impact aggressors, the lower the probability of sim-
ultaneous transitions at impact aggressors. This Y
n1
indicates that it is possible to regroup segments ðn  kÞm ¼ ðn!Þm :
k¼0
optimally so that each segment group has a smaller
number of impact aggressors. This section presents
Theorem 1 indicates that it is impractical to
an effective algorithm for segment regrouping,
check all possible segment group combinations to
which is another critical step in the LCTI–SS scheme.
find the best one for large industrial circuits with a
The proposed algorithm for segment regrouping
large number of scan chains. Therefore, we propose
uses the weighted switching activity (WSA) metric
a heuristic two-phase algorithm to efficiently find an
for SSA estimation since this metric has good corre-
optimal segment group combination with low SSA at
lation with power dissipation and IR drop at low
clock aggressors.
computational effort [12].
The proposed segment regrouping algorithm is
shown in Figure 5. In phase 1, a segment group Gtmp
Definition 3. The weighted impact (WI) of an IA, with the maximum WI is identified. Segments in
denoted by WI(IA), is defined as Gtmp are placed into separate groups G1 ; G2 ; . . . ; Gn
in order to divide the segments in the worst case
X
n
WI(IA) ¼ wi segment group into discrete groups. Then, in
i¼1 phase 2, a segment Smin is selected such that the
union ðGi [ Smin Þ has the minimum WI, and Smin is
where n is the number of impact aggressors in IA,
added to Gi . This process is repeated until all seg-
and wi is the weight of node i ði ¼ 1; 2; . . . ; nÞ, which
ments are selected. This algorithm tries to reduce
can be approximated by the number of its fanout
SSA at clock aggressors by minimizing the WI for
branches.
each segment group. This way, the clock aggressors
To find an optimal combination of segments for
of this particular segment group in the affected area
simultaneous clocking with low WI, we formalized
can be reduced.
the problem of segment regrouping as follows.
As shown in Figure 5, in phase 1 and phase 2
of the algorithm, segments are selected one at a
Segment Regrouping Problem. Given a scan time and added to a particular segment group. In
segmentation design with m scan chains and n phase 1, the segment which maximizes the WI of
segments for each scan chain, find n segment impact aggressors IA for group Gtmp is selected. In
groups G1 ; G2 ; . . . ; Gn such that the WI of the IA phase 2, the segment which results in the minimum
for each segment group Gi ði ¼ 1; 2; . . . ; nÞ, namely WI of IA of a particular group G is selected for
WI(IA(Gi )), is minimized. addition to G.
Theoretically, the total number of segment group To find and select the segment with minimum or
combinations can be expressed by the following maximum WI, we compute the resulting WI for the
theorem. considered group and all yet unselected segments.

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 Each segment is selected ex-
actly once and, before the
selection, WI is computed with
respect to each yet unselected
segment. Thus, the number of
WI computations is

X
NS
NSðNS þ 1Þ
i¼
i¼1
2

where NS is the total number of

segments. To compute WI, we
use optimized set operations
(union and intersection) on
the precomputed sets of seg-
ment aggressors SA and reach-
able aggressors RA to reduce
runtime.

Experimental results
Th e p r o p o s e d L C T I – S S
scheme was implemented in
the C language for evaluation.
Six largest ITC’99 benchmark
circuits (b17 to b22) and one
industrial circuit (ck1) were
used in the experiments. The lay-
out was designed using the SAED
90-nm EDK digital standard cell
library with 1.2-V power supply
voltage under typical operating
conditions. Transition delay fault
test sets were generated to eval-
uate SSA at IAs. The profile of Figure 5. Segment regrouping algorithm.
the circuits and corresponding
test sets is shown in Table 1.
For each circuit, various scan configurations with
Table 1 Profile of circuits and test sets.
different numbers of scan chains and segments were
prepared according to the size of the circuit. For b17,
b20, b21, and b22, configurations with three, four,
and five scan chains were used. For b18 and b19,
configurations with ten, 30, and 50 scan chains were
used. For ck1, configurations with 100, 200, and
300 scan chains were used. Conventional scan seg-
mentation with three, four, and five segments were
applied, and LCTI–SS is then performed for each
configuration. Since our objective is to reduce IR
drop on clock paths by reducing switching activity at
IAs, ideally, a dynamic IR-drop analysis for all in-
dividual shift cycles should be performed for exact

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 LCTI–SS: Low-Clock-Tree-Impact Scan Segmentation

evaluation. However, this is computationally too

Table 2 Experimental results.
expensive due to the large number of shift cycles in
the entire test sequence. Therefore, we computed
WSA at IAs for every shift cycle and then picked the
100 cycles with highest WSA at an IA for a dynamic
IR-drop analysis using a commercial tool. For each
cycle, the average IR drop at clock buffers along clock
paths to an active segment group was extracted. We
compared the proposed LCTI–SS scheme with con-
ventional scan segmentation in terms of the WI, WSA
at IA, and average IR drop at active clock buffers.
Table 2 summarizes the experimental results.
The reduction ratio of the maximum and the aver-
age WI, the maximum and the average WSA at IAs,
and the maximum and the average of the average IR
drop at active clock buffers (Avg. IR drop at clock
buffers) among segment groups are shown in col-
umns four to nine. Central processing unit (CPU)
runtime for segment regrouping [CPU (s)] is shown
in column ten.
As can be seen in the table, the WI, our direct
objective for reduction in segment regrouping, was
reduced, on average, by 6.5% and 3.1% for maxi-
mum WI and average WI, respectively. This indicates
that the probability of signal transitions on the nodes
in IA is effectively reduced. The WSA at IA was also
reduced on average 6.1% for maximum WSA and
1.1% for average WSA. The correlation coefficient
between WI and WSA was computed as a measure
of the strength and direction of the linear relation-
ship. The correlation coefficient gives the value
between 1 and þ1 inclusive. The result was 0.6,
which shows a good correlation. As to the average IR
drop at active clock buffers for the worst 100 cycles
of the WSA at IA, while the correlation with WI was
very low, both maximum and average of the average
IR drop among cycles were effectively reduced. The
maximum reduction exceeded 36% in the case of
b18 with ten scan chains and four segment groups.
In addition, effective IR-drop reductions at clock
buffers can be seen for the largest circuit ck1. More-
over, the runtime of the proposed segment regroup-
ing algorithm was relatively short, even for the large
industrial circuit with a high number of scan chains
and FFs. This indicates that this algorithm is appli-
cable for large industrial designs with millions of
gates.

THIS PAPER PROPOSED a novel layout-aware scan

segmentation design scheme called LCTI–SS to

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Acknowledgment I. Pomeranz, and J. Rajski, ‘‘Preferred fill: A scalable
This work was supported in part by JSPS method to reduce capture power for scan based
KAKENHI Grant-in-Aid for Scientific Research (B) designs,’’ in Proc. IEEE Int. Test Conf., 2006,
22300017 and Challenging Exploratory Research DOI: 10.1109/TEST.2006.297694.
24650022. M. Kochte was a Visiting Researcher at [11] A. Al-Yamani, E. Chmelar, and G. Grinchuck,
Kyushu Institute of Technology in 2010, supported ‘‘Segmented addressable scan architecture,’’ in
by the German Academic Exchange Service Proc. IEEE Very Large Scale Integr. (VLSI) Test
(DAAD). This paper is an extension of the paper ‘‘A Symp., 2005, pp. 405–411.
novel scan segmentation design method for avoid- [12] K. Noda, H. Ito, K. Hatayama, and T. Aikyo, ‘‘Power
ing shift timing failures in scan testing,’’ presented at and noise aware test using preliminary estimation,’’ in
the International Test Conference, Anaheim, CA, Proc. Int. Symp. Very Large Scale Integr. (VLSI) Design
USA, in September 2011. Autom. Test, 2009, pp. 323–326.

Yuta Yamato is currently an Assistant Professor

h References at the Nara Institute of Science and Technology,
[1] L.-T. Wang, C.-W. Wu, and X. Wen, Eds., VLSI Test Nara, Japan. His research interests include low
Principles and Architectures: Design for Testability. power test, fault diagnosis, and dependable system.
San Francisco, CA, USA: Morgan Kaufmann, 2006. Yamato has a PhD from Kyushu Institute of Tech-
[2] P. Girard, N. Nicolici, and X. Wen, Eds., Power-Aware nology, Fukuoka, Japan (2010). He is a Member of
Testing and Test Strategies for Low Power Devices. the IEEE.
New York, NY, USA: Springer-Verlag, 2009.
[3] J. Saxena, K. M. Butler, V. B. Jayaram, S. Kundu, Xiaoqing Wen is a Professor and Director of De-
N. V. Arvind, P. Sreeprakash, and M. Hachinger, ‘‘A pendable Integrated Systems Research Center,
case study of IR-drop in structured at-speed testing,’’ in Kyushu Institute of Technology, Fukuoka, Japan.
Proc. IEEE Int. Test Conf., 2003, pp. 1098–1104. His research interests include power-aware testing,
[4] S. Gerstendorfer and H.-J. Wunderlich, ‘‘Minimized design for testability, and fault diagnosis of very
power consumption for scan-based BIST,’’ in Proc. large scale integration (VLSI) circuits. Wen has a
IEEE Int. Test Conf., 1999, pp. 77–84. PhD in applied physics from Osaka University,
[5] R. Sankaralingam and N. A. Touba, ‘‘Reducing test Osaka, Japan. He is a Fellow of the IEEE.
power during test using programmable scan chain
disable,’’ in Proc. Int. Workshop Electron. Design Michael A. Kochte is a Research Assistant at
Test Appl., 2002, pp. 159–163. the Institute for Computer Architecture and Com-

July/August 2013 69
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 LCTI–SS: Low-Clock-Tree-Impact Scan Segmentation

puter Engineering, University of Stuttgart, Stuttgart, Kajihara has a PhD from Osaka University, Osaka,
Germany. His research interests include test gener- Japan (1992). He is a Member of the IEEE, the Insti-
ation, fault simulation, and fault tolerance. Kochte tute of Electronics, Information and Communication
has a Diploma in computer science from University of Engineers (IEICE), and the Information Processing
Stuttgart. He is a Student Member of the IEEE. Society of Japan (IPSJ).

Kohei Miyase is an Assistant Professor at Kyushu Laung-Terng Wang is a Founder and CEO of
Institute of Technology, Fukuoka, Japan, where he SynTest Technologies, Sunnyvale, CA, USA. His re-
has been since 2007. His research interests include search interests include DFT, ATPG, logic and mem-
design for testability, low power test, and fault diag- ory BIST, scan compression, fault diagnosis, and
nosis. Miyase has a PhD from Kyushu Institute of soft-error resilience. Wang has a PhD in electrical
Technology (2005). He is a Member of the IEEE. engineering from Stanford University, Stanford, CA,
USA. He is a Fellow of the IEEE.
Seiji Kajihara is a Professor at Kyushu Institute of
Technology, Fukuoka, Japan, where he has been h Direct questions and comments about this article
since 1996. His research interests include test to Yuta Yamato, Nara Institute of Science and Tech-
generation, delay testing, and design for testability. nology, Nara 630-0192, Japan; [email protected].

70 IEEE Design & Test

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