Prof. Ashwini V.

Urade

Subject:- Computer Architecture and Organization

Unit 2: ARM and x86
Addressing Modes of x86
The addressing modes help us specify the way in which an operand’s effective address is
represented in any given instruction. The addressing mode specifies a rule for interpreting or
modifying the address field of the instruction before the operand is actually executed.
Some addressing modes allow referring to a large range of areas efficiently, like some linear array
of addresses along with a list of addresses. The addressing modes describe an efficient and flexible
way to define complex effective addresses.
The programs are generally written in high-level languages, as it’s a convenient way in which one
can define the variables along with the operations that a programmer performs on the variables.
This program is later compiled so as to generate the actual machine code. A machine code includes
low-level instructions.
A set of low-level instructions has operands and opcodes. An addressing mode has no relation with
the opcode part. It basically focuses on presenting the address of the operand in the instructions.

Addressing Modes Types

The addressing modes refer to how someone can address any given memory location. Five
different addressing modes or five ways exist using which this can be done.
You can find the list below, showing the various kind of addressing modes:

 Implied Mode
 Immediate Mode
 Register Mode
 Register Indirect Mode
 Autodecrement Mode
 Autoincrement Mode
 Direct Address Mode
 Indirect Address Mode
 Indexed Addressing Mode
Effective Address (EA)
The effective address refers to the address of an exact memory location in which an operand’s
value is actually present. Let us now explain all of the addressing modes.
Prof. Ashwini V. Urade

1. Implied Mode
In the implied mode, the operands are implicitly specified in the definition of instruction. Implied

addressing refers to instructions that comprise only an opcode without an operand;

for example,
INCA (“increment accumulator”) instruction.
CMA ( “complement accumulator” )instruction refers to an implied-mode instruction.
It is because, in the definition of the instruction, the operand is implied in the accumulator register.
All the register reference instructions are implied-mode instructions that use an accumulator.

2. Immediate Mode
In the immediate mode, we specify the operand in the instruction itself. Or, in simpler words,
instead of an address field, the immediate-mode instruction consists of an operand field. An
operand field contains the actual operand that is to be used in conjunction with an operation that
is determined in the given instruction. The immediate-mode instructions help initialize registers to
a certain constant value.

Immediate addressing modes

Ex:- LOAD R1, #100 R1 <--- 100

(# represents the value is of operand that to be loaded in R1)
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3. Register Mode
In the register mode, the operands exist in those registers that reside within a CPU. In this case,
we select a specific register from a certain register field in the given instruction. The k-bit field is
capable of determining one 2k register.
Ex:- ADD R1,R2 (R1 <---R1+R2)

4. Register Indirect Mode

In the register indirect mode, the instruction available to us defines that particular register in the
CPU whose contents provides the operand’s address in the memory. In simpler words, any selected
register would include the address of an operand instead of the operand itself.
The reference to a register is equivalent to specifying any memory address. The pros of using this
type of instruction are that an instruction’s address field would make use of fewer bits to select a
register than would be require when someone wants to directly specify a memory address.
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5. Autodecrement or the Autoincrement Mode

The Autodecrement or Autoincrement mode is very similar to the register indirect mode. The only
exception is that the register is decremented or incremented before or after its value is used to
access memory. When the address stored in the register defines a data table in memory, it is very
crucial to decrement or increment the register after accessing the table every time. It can be
obtained using the decrement or increment instruction.

Ex:-Add R1, (R2)+ // OR

R1 = R1 +M[R2] R2 = R2 + d

6. Direct Address Mode

In the direct address mode, the address part of the instruction is equal to the effective address. The
operand would reside in memory, and the address here is given directly by the instruction’s address
field. The address field would specify the actual branch address in a branch-type instruction.

Ex:- ADD A

7. Indirect Address Mode

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In an indirect address mode, the address field of an available instruction gives that address in which
the effective address gets stored in memory. The control fetches the instruction available in the
memory and then uses its address part in order to (again) access memory to read its effective
address.

Indirect addressing mode

8. Displacement addressing mode

Displacement Addressing A very powerful mode of addressing combines the capabilities of direct
addressing and register indirect addressing. It is known by a variety of names depending on the
context of its use, but the basic mechanism is the same. We will refer to this as displacement
addressing: Displacement addressing requires that the instruction have two address fields, at least
one of which is explicit. The value contained in one address field (value = A) EA = A + (R) EA =
(R) is used directly. The other address field, or an implicit reference based on opcode, refers to a
register whose contents are added to A to produce the effective address. We will describe three of
the most common uses of displacement addressing:
• Relative addressing
• Base-register addressing
• Indexing
RELATIVE ADDRESSING For relative addressing, also called PC-relative addressing, the
implicitly referenced register is the program counter (PC). That is, the next instruction address is
added to the address field to produce the EA. Typically, the address field is treated as a twos
complement number for this operation.. If most memory references are relatively near to the
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instruction being executed, then the use of relative addressing saves address bits in the instruction.

Relative Displacement Addressing Mode

BASE-REGISTER ADDRESSING For base-register addressing, the interpretation is the

following: The referenced register contains a main memory address, and the address field contains
a displacement (usually an unsigned integer representation) from that address. The register
reference may be explicit or implicit. Base-register addressing also exploits the locality of memory
references In some implementations, a single segment-base register is employed and is used
implicitly. In others, the programmer may choose a register to hold the base address of a segment,
and the instruction must reference it explicitly. In this latter case, if the length of the address field
is K and the number of possible registers is N, then one instruction can reference any one of N
areas of words.
Indexed Addressing Mode
In the indexed addressing mode, the content of a given index register gets added to an instruction’s
address part so as to obtain the effective address. Here, the index register refers to a special CPU
register that consists of an index value. An instruction’s address field defines the beginning address
of any data array present in memory.

9. Stack Addressing Mode

The stack pointer is maintained in a register. Thus, references to stack locations in memory are in
fact register indirect addresses. The stack mode of addressing is a form of implied addressing. The
machine instructions need not include a memory reference but implicitly operate on the top of the
Prof. Ashwini V. Urade

stackA stack is a linear array of locations. It is sometimes referred to as a pushdown list or last-in-
first-out queue..

Instruction format of x86

Def:-A collection of operation codes, as well as operands that handle the operation codes, are
included in the instruction. The bit design in an instruction is supported by the instruction format.
The operands, opcode, and addressing mode are among the fields.
The following factors can be used to interpret the function of the allocating bits in the
instruction:

 The number of different addressing modes

 Count of operands
 The total number of address lines
 The total number of register sets
 The total number of CPU registers
The Intel Architecture – 32 bits (or IA-32) instruction format was shown in the diagram. Intel’s
most advanced microprocessors use the IA-32 instruction format. The addressing mode field,
opcode field, displacement field, and immediate field are all included in this instruction structure.
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The opcode field consists of 1 or 2 bytes. 1 or 2 bytes are also included in the addressing mode
field. If an instruction uses just one register for generating the effective address of an operand, it
only needs one byte in the addressing mode field.
The displacement field is the field that comes after the addressing mode field. If the displacement
value is used to compute an effective address for a memory operand, one or four bytes are used
to encode. When an operand is just an immediate value, it will show in the immediate field and
will be 1 or 4 bytes long.

x86 Instruction Formats

The x86 is equipped with a variety of instruction formats. Of the elements described in this
subsection, only the opcode field is always present.
Following figure shows the general instruction format. Instructions are made up of from zero to
four optional instruction prefixes, a 1- or 2-byte opcode, an optional address specifier (which
consists of the ModR/m byte and the Scale Index byte) an optional displacement, and an optional
immediate field. Let us first consider the prefix bytes

Fig:- x86 Instruction Format

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• Instruction prefixes: The instruction prefix, if present, consists of the LOCK prefix or one of
the repeat prefixes. The LOCK prefix is used to ensure exclusive use of shared memory in
multiprocessor environments. The repeat prefixes specify repeated operation of a string, which
enables the x86 to process strings much faster than with a regular software loop. There are five
different repeat prefixes: REP, REPE, REPZ, REPNE, and REPNZ. When the absolute REP
prefix is present, the operation specified in the instruction is executed repeatedly on successive
elements of the string; the number of repetitions is specified in register CX. The conditional REP
prefix causes the instruction to repeat until the count in CX goes to zero or until the condition is
met.
• Segment override: Explicitly specifies which segment register an instruction should use,
overriding the default segment-register selection generated by the x86 for that instruction.
• Operand size: An instruction has a default operand size of 16 or 32 bits, and the operand
prefix switches between 32-bit and 16-bit operands.
• Address size: The processor can address memory using either 16- or 32-bit addresses. The
address size determines the displacement size in instructions and the size of address offsets
generated during effective address calculation. One of these sizes is designated as default, and
the address size prefix switches between 32-bit and 16-bit address generation.
The instruction itself includes the following fields:
• Opcode: The opcode field is 1, 2, or 3 bytes in length. The opcode may also include bits that
specify if data is byte- or full-size (16 or 32 bits depending on context), direction of data
operation (to or from memory), and whether an immediate data field must be sign extended.
• ModR/m: This byte, and the next, provide addressing information.The ModR/m byte specifies
whether an operand is in a register or in memory; if it is in memory, then fields within the byte
specify the addressing mode to be used. The ModR/m byte consists of three fields: The Mod
field (2 bits) combines with the r/m field to form 32 possible values: 8 registers and 24 indexing
modes; the Reg/Opcode field (3 bits) specifies either a register number or three more bits of
opcode information; the r/m field (3 bits) can specify a register as the location of an operand, or
it can form part of the addressing-mode encoding in combination with the Mod field
• SIB: Certain encoding of the ModR/m byte specifies the inclusion of the SIB byte to specify
fully the addressing mode.The SIB byte consists of three fields: The Scale field (2 bits) specifies
the scale factor for scaled indexing; the Index field (3 bits) specifies the index register; the Base
field (3 bits) specifies the base register.
• Displacement: When the addressing-mode specifier indicates that a displacement is used, an 8-
, 16-, or 32-bit signed integer displacement field is added.
• Immediate: Provides the value of an 8-, 16-, or 32-bit operand.
Prof. Ashwini V. Urade

Q-) Explain 3-address, 2- address, 1-address and zero- address instruction

format with example
A instruction is of various length depending upon the number of addresses it contain. Generally
CPU organization are of three types on the basis of number of address fields:
Single Accumulator organization
General register organization
Stack organization
In first organization operation is done involving a special register called accumulator. In second
on multiple registers are used for the computation purpose. In third organization the work on stack
basis operation due to which it does not contain any address field. It is not necessary that only a
single organization is is applied a blend of various organization is mostly what we see generally.
On the basis of number of address instruction are classified as:
Note that we will use X = (A+B)*(C+D) expression to showcase the procedure.

ZERO ADDRESS INSTRUCTION

A stack based computer do not use address field in instruction.To evaluate a expression first it is
converted to revere Polish Notation i.e. Post fix Notation.. The PUSH and POP instructions,
however, need an address field to specify the operand that communicates with the stack.

Example:- Expression: X = (A+B)*(C+D)

Postfixed : X = AB+CD+*

TOP means top of stack

M[X] is any memory location

PUSH A TOP = A
PUSH B TOP = B
ADD TOP = A+B
PUSH C TOP = C
PUSH D TOP = D
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ADD TOP = C+D

MUL TOP = (C+D)*(A+B)
POP X M[X] = TOP

One Address instruction

This use a implied ACCUMULATOR register for data manipulation.One operand is in

accumulator and other is in register or memory location.Implied means that the CPU already know
that one operand is in accumulator so there is no need to specify it.

Opcode Operand/Address Mode

of Operand

Example:- Expression: X = (A+B)*(C+D)

AC is accumulator
M[] is any memory location
M[T] is temporary location

AC = M[A]
LOAD A
AC = AC + M[B]
ADD B
M[T] = AC
STORE T
AC = M[C]
LOAD C
AC = AC + M[D]
ADD D
AC = AC * M[T]
MUL T
M[X] = AC
STORE X

TWO ADDRESS INSTRUCTION

This is common in commercial computers. Here two address can be specified in the instruction.
Unlike earlier in one address instruction the result was stored in accumulator here result can be
stored at different location rather than just accumulator, but require more number of bit to
represent address.

Opcode Destination Source address Mode

Example: Expression: X = (A+B)*(C+D)

Prof. Ashwini V. Urade

MOV R1, A R1 = M[A]

ADD R1, B R1 = R1 + M[B]
MOV R2, C R2 = C
ADD R2, D R2 = R2 + D
MUL R1, R2 R1 = R1 * R2
MOV X, R1 M[X] = R1

THREE-ADDRESS INSTRUCTIONS Computers with three-address instruction formats can

use each address field to specify either a processor register or a memory operand.
Three Address Instruction format as follows:--
Opcode Destination Source address 1 Source address 2 Mode

The program in assembly language that evaluates X = (A + B) * (C + D) is together with comments

that explain the register transfer operation of each instruction.
Expression: X = (A+B)*(C+D)
R1, R2 are registers, M[] is any memory location

ADD R1, A, B R1 = M[A] + M[B]

ADD R2, C, D R2 = M[C] + M[D]
MUL X, R1, R2 M[X] = R1 * R2

It is assumed that the computer has two processor registers, R1 and R2. The symbol M [A] denotes
the operand at memory address symbolized by A. The advantage of the three-address format is
that it results in short programs when evaluating arithmetic expressions. The disadvantage is that
the binary-coded instructions require too many bits to specify three addresses.
Prof. Ashwini V. Urade

ARM Addressing Modes

ARM Addressing Modes
Typically, a RISC machine uses a simple and relatively straightforward set of addressing modes.
The ARM architecture departs somewhat from this tradition by providing a relatively rich set of
addressing modes. These modes are most conveniently classified with respect to the type of
instruction
A. LOAD/STORE ADDRESSING
Load and store instructions are the only instructions that reference memory. This is always done
indirectly through a base register plus offset. There are three alternatives with respect to indexing
Offset , Preindex, Postindex
• Offset: For this addressing method, indexing is not used. An offset value is added to or subtracted
from the value in the base register to form the memory address. As an example Figure illustrates
this method with the assembly language instruction STRB r0, [r1, #12]. This is the store byte
instruction. In this case the base address is in register r1 and the displacement is an immediate
value of decimal 12. The resulting address (base plus offset) is the location where the least
significant byte from r0 is to be stored.

Offset Load/Store addressing mode

• Preindex: The memory address is formed in the same way as for offset addressing.The memory
address is also written back to the base register. In other words, the base register value is
incremented or decremented by the offset value. Figure illustrates this method with the assembly
language instruction STRB r0, [r1, #12]! ! -The exclamation point signifies preindexing.
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• Postindex:The memory address is the base register value.An offset is added to or subtracted
from the base register value and the result is written back to the base register. Figure c illustrates
this method with the assembly language instruction STRBv r0, [r1], #12.

B. LOAD/STORE MULTIPLE ADDRESSING MODE

Load Multiple instructions load a subset (possibly all) of the general-purpose registers from
memory. Store Multiple instructions store a subset (possibly all) of the general-purpose registers
to memory. The list of registers for the load or store is specified in a 16-bit field in the instruction
with each bit corresponding to one of the 16 registers. Load and Store Multiple addressing modes
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produce a sequential range of memory addresses. The lowestnumbered register is stored at the
lowest memory address and the highest numbered register at the highest memory address. Four
addressing modes are used in figure .increment after, increment before, decrement after, and
decrement before. A base register specifies a main memory address where register values are
stored in or loaded from in ascending (increment) or descending (decrement) word locations.
Incrementing or decrementing starts either before or after the first memory access.
These instructions are useful for block loads or stores, stack operations, and procedure exit
sequences.

Fig:- ARM Load/Store Multiple Addressing Mode

C. DATA PROCESSING INSTRUCTION ADDRESSING

Data processing instructions use either register addressing of a mixture of register and immediate
addressing. For register addressing, the value in one of the register operands may be scaled using
one of the five shift operators defined in the preceding paragraph.

 Standard data-processing instructions.

These instructions perform basic data-processing operations, and share a common format
with some variations.

 Shift instructions.
 Multiply instructions.
 Saturating instructions.
 Saturating addition and subtraction instructions.
 Packing and unpacking instructions.
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 Parallel addition and subtraction instructions.

 Divide instructions.
 Miscellaneous data-processing instructions.

EX:- Move R1,R2

ADD A,#899

D. BRANCH INSTRUCTIONS
The only form of addressing for branch instructions is immediate addressing. The branch
instruction contains a 24-bit value. For address calculation, this value is shifted left 2 bits, so that
the address is on a word boundary. Thus the effective address range is MB from the program
counter
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Instruction Format of ARM

Explain Instruction format of ARM?
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--------------------------------------32 bits---------------------------------------------------------------

OP Code Rn Rd Other Rm
Condition Information
4bit 8bit 4bit 4bit 8bit 4bit

Condition Flag:- N-Negative, C- Carry, V- Overflow , Z- Zero

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ASSEMBLY LANGUAGE
A processor can understand and execute machine instructions. Such instructions are simply binary
numbers stored in the computer. If a programmer wished to program directly in machine language,
then it would be necessary to enter the program as binary data.
Consider the simple BASIC statement
N=I+J+K
Suppose we wished to program this statement in machine language and to initialize I, J, and K to
2, 3, and 4, respectively.The program starts in location 101 (hexadecimal). Memory is reserved for
the four variables starting at location 201. The program consists of four instructions:
1. Load the contents of location 201 into the AC
2. Add the contents of location 202 to the AC.
3. Add the contents of location 203 to the AC.
4. Store the contents of the AC in location 204.
This is clearly a tedious and very error-prone process. A slight improvement is to write the
program in hexadecimal rather than binary notation We could write the program as a series of
lines. Each line contains the address of a memory location and the hexadecimal code of the
binary value to be stored in that location.Then we need a program that will accept this input,
translate each line into a binary number, and store it in the specified location.
For more improvement, we can make use of the symbolic name or mnemonic of each
instruction. This results in the symbolic program shown in Figure 10.11c. Each line of input
still represents one memory location. Each line consists of three fields, separated by spaces.
The first field contains the address of a location.