Department: Comm. and Elect.

Engineering Misr Higher Institute for Engineering & Technology

Subject: Computer Org.&Arch. Year: Second

Revision

1. The memory size for SAP-1 architecture is

A. 16 word
B. 12 word
C. 8 word
D. 32 word

2. The chip which is used to implement SAP-1 memory is

A. 74289
B. 74189
C. 75189
D. 74389

3. The chip which is used to implement SAP-1 ALU is

A. 74283
B. 74183
C. 75183
D. 7483

4. The chip which is used to implement SAP-1 instruction register is

A. 74LS273
B. 74LS373
C. 74LS73
D. 74LS173

5. The address bus size of SAP-1 architecture is

A. 16 bits
B. 8 bits
C. 32 bits
D. 4 bits

6. The timing diagram for the fetch and ADD routines is shown in the following figure

A. true
B. false

Page 1 of 1
Department: Comm. and Elect. Engineering Misr Higher Institute for Engineering & Technology
Subject: Computer Org.&Arch. Year: Second

7. The timing diagram for the fetch and SUB routines is shown in the following figure

A. true
B. false

8. The block diagram for SAP-1 architecture is shown in the following figure

A. true
B. false

Page 2 of 1
Department: Comm. and Elect. Engineering Misr Higher Institute for Engineering & Technology
Subject: Computer Org.&Arch. Year: Second

9. The machine code shown in the following figure is used to calculate …………….

A. 16 + 24 - 24 – 32
B. 16 - 24 + 20 – 32
C. 16 + 20 + 24 – 32
D. 20 + 24 + 23 – 32

10. The control word generated during the address state is

A. true
B. false

11. The control word generated during the Memory state is

A. true
B. false

12. The control word generated during the increment state is

A. true
B. false

13. The control word generated during the address state is

A. true
B. false

Page 3 of 1
Department: Comm. and Elect. Engineering Misr Higher Institute for Engineering & Technology
Subject: Computer Org.&Arch. Year: Second

14. The contents of the control ROM of SAP-1 for the LDA routine is shown in the following figure

A. true
B. false

15. The contents of the control ROM of SAP-1 for the FETCH routine is shown in the following figure

A. true
B. false

16. When the IR contains IR = 1111 XXXX the instruction field signals the controller-sequencer to.
E. Clear the accumulator
F. Complement the accumulator
G. stop processing data
H. Complement the B register

17. The SAP-1 clock has a frequency of 1 kHz, equivalent to a period of

A. 10 ms
B. 1 ms
C. 1000 ms
D. 100 ms

18. The SAP-1 clock has a frequency of 1 kHz, Therefore, it takes ................. for a SAP-1 machine cycle.
A. 60 ms
B. 6 ms
C. 12 ms
D. 16 ms

Page 4 of 1
Department: Comm. and Elect. Engineering Misr Higher Institute for Engineering & Technology
Subject: Computer Org.&Arch. Year: Second

19. The block diagram for SAP-2 architecture is shown in the following figure

C. true
D. false

Page 5 of 1
Department: Comm. and Elect. Engineering Misr Higher Institute for Engineering & Technology
Subject: Computer Org.&Arch. Year: Second

20. For the hypothetical machine shown in the following figure, show the contents of registers and
memory during the execution of three consecutive instructions.

If PC=300 and the memory contents is as shown

in the figure, show the contents of the
21. Draw the design of BCD 4-bit parrallel adder/ subtractor circuit.

22. Draw Only the SAP-1 Control unit with address memory and control memory in the case of variable
machine cycle.
23. Draw the state diagram for the complete instruction execution cycle.

24. Draw the timing diagram for the OUT fetch and execute routines.

25. Draw the timing diagram for the SUB fetch and execute routines.

26. Draw the circuit digram of Controlled buffer register with parallel load.

27. Draw the circuit digram of Controlled shift Left register.

28. Draw the circuit digram of Controlled buffer register with parallel load and Enable terminals.

29. The following circuit is designed to implement the ..... circuit.

Best wishes
Page 6 of 1
"T2"
"T4" for "Add"
 ‫وزارة التعليم العالى‬
‫معهد مصر العالي للهندسة والتكنولوجيا بالمنصورة‬
‫ الثانى‬2024-2023 ‫نموذج امتحان نهاية الفصل الدراسي الثانى لعام‬

)1( ‫ تنظيم حاسبات‬: ‫المادة‬ ‫ هندسة االتصاالت‬: ‫القسم‬

] 2423 ‫ ] [ هكح‬ELC 2423 [: ‫كود المادة‬ ‫ عام‬: ‫الشعبة‬ ]‫ [الثانية‬:‫الفرقة‬
‫ درجة‬37.00 / ‫ سؤال‬15 : ‫االسئلة االلكترونى‬ 2/6/2024 : ‫تاريخ االمتحان‬
‫ درجة‬38.00 / ‫ سؤال‬5 : ‫االسئلة المقالى‬ ‫ثالث ســاعات‬: ‫زمن االمتحان‬

‫المهدى مرعى أمين الشوبكى؛‬.‫ د‬: ‫القائمين بتدريس المادة‬

)MCQ(‫االسئلة االختيارى‬

Question No 1 ( 2.00 Points )

When the IR in SAP-I contains IR = 1101 1001 the instruction field
signals the controller-sequencer to

A. Clear the accumulator

B. Complement the accumulator
C. stop processing data
D. None of the above

Question No 2 ( 2.00 Points )

The contents of SAP-I control ROM for the ..... routine is shown in the
following figure.

A. LDA
B. Fetch
C. ADD
D. None of the above

Question No 3 ( 3.00 Points )

The timing diagram for the "SUB" instruction executed in SAP-I is shown in the
following figure
 A. True
B. False

Question No 4 ( 3.00 Points )

During the increment state of SAP I, the controller-sequencer will produce a control
word of

A.

B.

C. None of the above

Question No 5 ( 3.00 Points )

The machine code for SAP-I shown in the following figure is used to calculate the
output of the arithmetic operation …………….

A. 16 + 24 - 20 - 32
 B. 16 - 24 + 20 - 32
C. 16 - 44 + 20 - 32
D. None of the above

Question No 6 ( 2.00 Points )

The following circuit is designed to implement the ..... circuit.

A. MAR
B. PC
C. IR
D. None of the above

Question No 7 ( 2.00 Points )

The following circuit is designed to implement the ..... circuit.

A. MAR
B. PC
C. IR
D. None of the above

Question No 8 ( 2.00 Points )

The contents of SAP-I control ROM for the ..... routine is shown in the following
figure.

A. LDA
B. Fetch
 C. ADD
D. None of the above

Question No 9 ( 3.00 Points )

The following figure represents the state ....

A. "T5" for "LDA" execution cycle

B. "T4" for "LDA" execution cycle
C. "T5" for "ADD" execution cycle
D. None of the above

Question No 10 ( 2.00 Points )

The SAP-1 clock has a frequency of 60 kHz, so it can perform ......

A. 1000 instruction per second

B. 6000 instruction per second
C. 10000 instruction per second
D. None of the above

Question No 11 ( 2.00 Points )

The memory size for SAP-1 architecture is .....

A. 16 x 8 word
B. 8 x 8 word
C. 16 x 4 word
D. None of the above

Question No 12 ( 2.00 Points )

The instruction "LDA 02H" means to ......

A. transfer the data in port 2 to the accumulator.

B. transfer the data in port 1 to the accumulator
C. transfer the data in the accumulator to port 2.
D. None of the above

Question No 13 ( 3.00 Points )

In ..... policy all write operations are made to the main memory as well as to the cache, ensuring that
main memory is always valid.
 A. write through
B. write back
C. None of the above

Question No 14 ( 3.00 Points )

.... is the replacement algorithm which replaces that block in the set and has been in the cache longest
with no reference to it

A. Least recently used (LRU)

B. First- In- First- Out (FIFO)
C. Random
D. None of the above

Question No 15 ( 3.00 Points )

DRAM has lower access time, so it is slower than SRAM.

A. True
B. False
 ‫وزارة التعليم العالى‬
‫معهد مصر العالي للهندسة والتكنولوجيا بالمنصورة‬
‫ الثانى‬2024-2023 ‫نموذج امتحان نهاية الفصل الدراسي الثانى لعام‬

)1( ‫ تنظيم حاسبات‬: ‫المادة‬ ‫ هندسة االتصاالت‬: ‫القسم‬

] 2423 ‫ ] [ هكح‬ELC 2423 [: ‫كود المادة‬ ‫ عام‬: ‫الشعبة‬ ]‫ [الثانية‬:‫الفرقة‬
‫ درجة‬37.00 / ‫ سؤال‬15 : ‫االسئلة االلكترونى‬ 2/6/2024 : ‫تاريخ االمتحان‬
‫ درجة‬38.00 / ‫ سؤال‬5 : ‫االسئلة المقالى‬ ‫ثالث ســاعات‬: ‫زمن االمتحان‬

‫المهدى مرعى أمين الشوبكى؛‬.‫ د‬: ‫القائمين بتدريس المادة‬

‫االسئلة المقالى‬

Question No 1 ( 10.00 Points )

Draw the design of SAP 1 architecture with the following specifications. Accordingly, write down the
generated control word in the Address state of the instruction execution cycle

Question No 2 ( 10.00 Points )

Design the Control Unit of SAP 1 architecture using control matrix and decoder .

Question No 3 ( 8.00 Points )

Write down the steps which are required to multiply (7 * 3) using Booth’s Algorithm, also draw the flowchart
which describes the Booth’s Algorithm

Question No 4 ( 5.00 Points )

Compare between SRAM and DRAM

Question No 5 ( 5.00 Points )

Represent (-6.25) in IEEE-754 32 bit binary format.